Integrated circuit device and oscillator

Abstract

To downsize an integrated circuit device.SOLUTION: The present invention relates to an integrated circuit device with a scan test mode, the device having a combination logic circuit test mode for testing an operation of a combination logic circuit and a reset operation test mode for testing a reset operation of a plurality of flip-flop circuits. A common pad is assigned to pads for different purposes in the combination logic circuit test mode and in the reset operation test mode.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to an integrated circuit device and an oscillator. [Background technology]

[0002] Conventionally, scan testing has been known as a method for testing combinational logic circuits. For example, Patent Document 1 discloses a configuration in which flip-flop circuits are arranged at least on one of the input and output of a combinational logic circuit, and in a scan test mode, a scan chain is formed by connecting these flip-flop circuits in series. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-190961 A Summary of the Invention [Problem to be solved by the invention]

[0004] When performing a scan test, five terminals are required: in addition to high and low potential power supply terminals, a clock signal input terminal, an input terminal for test data to the scan chain, an output terminal for the test results from the scan chain, an input terminal for a signal that instructs the flip-flop circuit to be reset, and an input terminal for a signal that instructs the scan chain to be enabled. Conventionally, these terminals were provided on the integrated circuit device, making it difficult to miniaturize the integrated circuit device. [Means for solving the problem]

[0005] An integrated circuit for solving the above problem is an integrated circuit device having a scan test mode, comprising first to fourth pads, a combinational logic circuit, and a plurality of flip-flop circuits, the plurality of flip-flop circuits being switchable between a first state in which they hold an input signal to the combinational logic circuit and hold an output signal from the combinational logic circuit, and a second state in which they configure a scan chain in which the plurality of flip-flop circuits are connected in series, the scan test mode including a combinational logic circuit test mode for testing the operation of the combinational logic circuit, and a reset operation test mode for testing the reset operation of the plurality of flip-flop circuits, and in the combinational logic circuit test mode, the first to fourth pads are used as data input pads for inputting data used for testing the operation of the combinational logic circuit to the scan chain. In the reset operation test mode, the first to fourth pads are assigned to data input pads for inputting data used in testing the reset operation to the scan chain, data output pads for outputting data held in the scan chain, clock input pads for inputting a clock signal to the plurality of flip-flop circuits, and setting signal input pads for inputting a setting signal that sets the plurality of flip-flop circuits to either a first state or a second state, and in the reset operation test mode, the first to fourth pads are assigned to data input pads for inputting data used in testing the reset operation to the scan chain, data output pads for outputting data held in the scan chain, clock input pads for inputting a clock signal to the plurality of flip-flop circuits, and reset signal input pads for inputting a reset signal to the plurality of flip-flop circuits. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of an oscillator according to an embodiment of the present invention. [Diagram 2] 2A and 2B are diagrams illustrating an example of the configuration of an oscillator circuit and an example of the configuration of a control circuit. [Diagram 3] 11 is a timing chart for setting a mode. [Figure 4] FIG. 4 is a diagram illustrating an operation of a control circuit according to a mode setting. [Diagram 5]FIG. 4 is a diagram illustrating an operation of a control circuit according to a mode setting. [Figure 6] FIG. 2 is a diagram showing a scan chain. [Figure 7] 11 is a timing chart of a combinational logic circuit test mode. [Figure 8] 11 is a timing chart of a reset operation test mode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Here, the embodiments of the present invention will be described in the following order. (1) Oscillator configuration: (1-1) Configuration for scan testing: (1-2) Operation in combinational logic circuit test mode: (1-3) Reset operation test mode operation: (2) Other embodiments:

[0008] (1) Oscillator configuration: 1 is a configuration diagram of an oscillator 1 according to one embodiment of the present invention. The oscillator 1 includes a package 4 that houses an integrated circuit device 2 and a resonator 3. The package 4 has a space therein, and the interior is hermetically sealed in a reduced pressure atmosphere such as a vacuum, or in an inert gas atmosphere such as nitrogen, argon, or helium.

[0009] External terminals are provided on the outer surface of the package. In Fig. 1, the external terminals are diagrammatically shown by white circles superimposed on a rectangular line indicating the package 4. Specifically, the package 4 is provided with a high-potential power supply external terminal, a low-potential power supply external terminal, an OE external terminal for controlling whether or not to output from the oscillator 1, and an output external terminal for outputting an oscillation signal from the oscillator 1.

[0010] In this embodiment, a power supply voltage Vcc is applied to the high potential power supply external terminal, and the low potential power supply external terminal is grounded. Hereinafter, the high potential power supply external terminal is referred to as a Vcc external terminal, the low potential power supply external terminal is referred to as a GND external terminal, and the output external terminal is referred to as an OUT external terminal.

[0011] In this embodiment, the vibrator 3 is a quartz crystal vibrator using quartz crystal as a substrate material, for example, an AT-cut or SC-cut quartz crystal vibrator. The vibrator 3 may be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) vibrator. In addition to quartz crystal, the substrate material of the vibrator 3 may be a piezoelectric material such as a piezoelectric single crystal such as lithium tantalate or lithium niobate, or a piezoelectric ceramic such as lead zirconate titanate, or a silicon semiconductor material. The vibrator 3 may be excited by a piezoelectric effect or by electrostatic driving using Coulomb force.

[0012] The integrated circuit device 2 includes a pad electrically connected to an external terminal and a pad electrically connected to the vibrator 3. Specifically, the integrated circuit device 2 includes two pads electrically connected to a Vcc external terminal and a GNC external terminal, respectively. Here, the former is called a Vcc pad and the latter is called a GND pad.

[0013] Furthermore, the integrated circuit device 2 includes first to fourth pads in addition to the Vcc pad and the GND pad. In this embodiment, an OE external terminal is electrically connected to one of the first to fourth pads, and an OUT external terminal is electrically connected to another one of the first to fourth pads. Here, the former is called an OE pad, and the latter is called an OUT pad. Furthermore, the remaining two pads among the first to fourth pads are vibrator pads. That is, the vibrator 3 is electrically connected to a vibrator pad provided on the integrated circuit device 2, and here, one of the vibrator pads is called an XI pad, and the other is called an XO pad. In FIG. 1, the pads are typically shown by white circles superimposed on a rectangular line showing the integrated circuit device 2. In addition, the white circles that typically show the external terminals and pads are also shown with their roles Vcc, GND, OE, OUT, XI, and XO.

[0014] In this embodiment, the integrated circuit device 2 includes an oscillator circuit 10, a fractional PLL circuit 20, an output buffer 30, a power-on detection unit 40, a temperature compensation circuit 50, and a control circuit 60. Note that the integrated circuit device 2 of this embodiment may be configured by omitting or modifying some of these elements, or by adding other elements. In this embodiment, the integrated circuit device 2 is a single-chip semiconductor integrated circuit (IC).

[0015] The oscillator circuit 10 is a circuit for oscillating the oscillator 3, amplifying the output signal of the oscillator 3 and feeding it back to the oscillator 3. The oscillator circuit 10 outputs an oscillation signal REFCLK based on the oscillation of the oscillator 3. For example, the oscillator circuit formed by the oscillator 3 and the oscillator circuit 10 may be any of various types of oscillator circuits, such as a Pierce oscillator circuit, an inverter type oscillator circuit, a Colpitts oscillator circuit, or a Hartley oscillator circuit. Note that FIG. 2, which will be described later, shows an example of the configuration of the oscillator circuit 10.

[0016] The fractional PLL circuit 20 generates an oscillation signal in which the frequency (reference frequency) of the oscillation signal REFCLK is multiplied by an integer or (integer+fraction) in accordance with the division ratio input from the control circuit 60. In this embodiment, the fractional PLL circuit 20 includes a frequency divider circuit (not shown), which divides the oscillation signal by the output division ratio input from the control circuit 60 to generate an oscillation signal CLKO. The output buffer 30 buffers the oscillation signal CLKO output by the frequency divider circuit, and outputs the oscillation signal from the OUT pad to the outside. This oscillation signal becomes the oscillation signal output from the OUT external terminal of the oscillator 1.

[0017] The power-on detection unit 40 includes a regulator (not shown). The regulator converts the voltage of the power source connected to the Vcc external terminal into a predetermined voltage and supplies it to each circuit in the integrated circuit device 2. The power-on detection unit 40 also includes a circuit that detects whether the output voltage of the regulator exceeds a threshold value in the process of rising from 0 to the predetermined voltage. That is, the power-on detection unit 40 can detect that the power is turned on. When the power-on is detected, a signal indicating the power-on is output from the power-on detection unit 40 to the control circuit 60. The power-on detection unit 40 only needs to be able to detect the power-on, and may be configured to include, for example, a comparator that compares the potential of the Vcc pad with a reference potential, or may be any of various known power-on reset circuits.

[0018] The temperature compensation circuit 50 temperature compensates the frequency of the oscillation signal output by the oscillation circuit 10 based on a temperature detection value detected by a temperature sensor (not shown). In this embodiment, the temperature compensation circuit 50 generates a temperature compensation value based on the temperature detection value for temperature compensation so that the frequency of the oscillation signal output by the oscillation circuit 10 becomes a desired frequency. The temperature compensation value is converted into an analog signal and supplied to the oscillation circuit 10. The oscillation circuit 10 oscillates the resonator 3 at a frequency corresponding to the temperature compensation voltage.

[0019] The control circuit 60 has a control register (not shown) and controls the operations of the fractional PLL circuit 20, temperature compensation circuit 50, etc., according to the setting value of the control register. In the control register, it is possible to set the magnitude of the current in the current source of the charge pump circuit, the frequency adjustment value of the oscillator circuit 10, the integer division ratio N and fractional division ratio F / M of the fractional PLL circuit 20, the output division ratio P of the divider circuit, etc.

[0020] In this embodiment, the oscillator 1 can operate in a plurality of modes. Specifically, the oscillator 1 according to this embodiment can be set to a normal operation mode and a scan test mode. The normal operation mode is a mode for outputting an oscillation signal from the oscillator 1, and is a mode in which the user uses the oscillator 1 after the oscillator 1 is shipped. If the oscillator 1 is powered on and a specific signal is not input from the OE pad after the power is turned on to the Vcc pad, the integrated circuit device 2 operates in the normal mode.

[0021] The scan test mode is a mode for inspecting the integrated circuit device 2, and is a mode for performing a scan test before shipping the oscillator 1. In this embodiment, the scan test mode is performed before the integrated circuit device 2 is attached to the package 4. The scan test may be performed in a state in which a predetermined signal can be input to the pads of the integrated circuit device 2. In this embodiment, the scan test is performed in the state of a wafer on which each circuit and pad of the integrated circuit device 2 is formed.

[0022] In this embodiment, in order to reduce the number of pads used in the scan test mode compared to the conventional method, the scan test mode is subdivided into a combinational logic circuit test mode and a reset operation test mode. That is, a reset operation test is not performed in the combinational logic circuit test mode, and a combinational logic circuit test is not performed in the reset operation test mode. Therefore, a pad for inputting a signal for performing a reset operation is not required in the combinational logic circuit test mode, and a pad for inputting a signal for switching between a state in which data is input to the combinational logic circuit and a state in which a scan chain is configured is not required in the reset operation test mode.

[0023] (1-1) Configuration for scan testing: The configuration for performing a scan test in the scan test mode will be described below. First, the configuration for setting the mode will be described. Fig. 2 is a diagram showing a circuit related to mode setting provided in the control circuit 60, and the oscillator circuit 10. In this embodiment, the oscillator circuit 10 is an oscillator circuit using the CMOS gate shown in Fig. 2, and includes an inverter In, a feedback resistor Rf, a limiting resistor Rd, and capacitors Cg and Cd.

[0024] That is, a feedback resistor Rf is connected to each of the input node and the output node of the inverter In, and a capacitor Cg is connected between the input node of the inverter In and the GND pad. Meanwhile, a limiting resistor Rd and a capacitor Cd connected in series are connected between the output node of the inverter In and the GND pad. The input node of the inverter In is electrically connected to the XI pad, and the node between the limiting resistor Rd and the capacitor Cd is electrically connected to the XO pad. With the above configuration, in the oscillation circuit 10, the resonator 3 connected to the XI pad and the XO pad is oscillated, and the oscillation signal REFCLK can be output from the oscillation circuit 10. Also, for example, the frequency of the oscillation signal REFCLK can be changed by changing the capacitance of the capacitors Cg and Cd.

[0025] In this embodiment, a pad for inputting a clock signal in a scan test mode (combinational logic circuit test mode, reset operation test mode) is assigned to the XI pad to which the oscillator 3 is connected in the normal operation mode. That is, the XI pad becomes a pad for inputting a clock signal CLK to a plurality of flip-flop circuits in the scan test mode. In FIG. 2, the symbol CLK indicating a pad for inputting a clock signal is written in parentheses next to the symbol indicating the XI pad. Hereinafter, the pad in the scan test mode is called a CLK pad.

[0026] An amplifier circuit Bu is connected to the CLK pad. Specifically, the input node of the amplifier circuit Bu is electrically connected to the input node of the inverter In, and the output node of the amplifier circuit Bu is input to a control circuit 60. The control circuit 60 includes a plurality of flip-flop circuits, which will be described later, and the signal input to the control circuit 60 becomes a clock signal CLK for these flip-flop circuits.

[0027] The amplifier circuit Bu amplifies the clock signal CLK input from the CLK pad and supplies it to a flip-flop circuit in the control circuit 60, and in this embodiment, it functions as a buffer for shaping the waveform of the clock signal CLK. With the above configuration, the waveform of the clock signal CLK input from outside the integrated circuit device 2 can be adjusted and input to the control circuit 60. Therefore, it is possible to prevent malfunctions caused by poor waveforms of the clock signal CLK. In this embodiment, the output terminal of the oscillation signal REFCLK output from the oscillation circuit 10 is shared with the output terminal of the clock signal CLK. In other words, the oscillation signal REFCLK is an output signal of the amplifier circuit Bu.

[0028] On the other hand, in this embodiment, the XO pad to which the vibrator 3 is connected in the normal operation mode is assigned as a setting signal input pad in the combinational logic circuit test mode. The setting signal input pad is a pad for inputting a setting signal that sets the state of a plurality of flip-flop circuits. The states of the plurality of flip-flop circuits will be described in detail later. In FIG. 2, the symbol MODE indicating the pad for inputting the setting signal is written in parentheses next to the symbol indicating the XO pad. Hereinafter, the pad in the combinational logic circuit test mode will be referred to as the MODE pad.

[0029] In the reset operation test mode, the XO pad is assigned as a pad for inputting a reset signal. The pad for inputting a reset signal is a pad for inputting a reset signal to multiple flip-flop circuits. In FIG. 2, the symbol for the XO pad is followed by the symbol RESET in parentheses, which is a symbol for a pad for inputting a reset signal. Hereinafter, this pad in the reset operation test mode will be called the RESET pad.

[0030] The integrated circuit device 2 according to the present embodiment includes a Vcc pad, a GND pad, an OUT pad, and an OE pad in addition to the XI pad and the XO pad. The Vcc pad and the GND pad are assigned as pads used for connecting a high potential power supply and a low potential power supply during a scan test.

[0031] On the other hand, the OE pad is assigned as a data output pad for outputting data held in a scan chain (to be described later) that is composed of a plurality of flip-flop circuits. In this embodiment, the OE pad is used as a data output pad in both a combinational logic circuit test mode and a reset operation test mode. That is, in the combinational logic circuit test mode, data including the result of an operation test of the combinational logic circuit is output from the data output pad. In the reset operation test mode, data including the result of a test of the reset operation is output from the data output pad. Hereinafter, the data output pad in the combinational logic circuit test mode and the reset operation test mode is referred to as a DATAOUT pad.

[0032] Furthermore, the OUT pad is assigned as a data input pad for inputting data to a scan chain (to be described later) that is configured by a plurality of flip-flop circuits. In this embodiment, the OUT pad is used as a data input pad in both the combinational logic circuit test mode and the reset operation test mode. That is, in the combinational logic circuit test mode, data used in the operation test of the combinational logic circuit is input from the data input pad. In the reset operation test mode, data used in the reset operation test is input from the data input pad. Hereinafter, the data input pad in the combinational logic circuit test mode and the reset operation test mode is referred to as a DATAIN pad.

[0033] As described above, in this embodiment, the power supply pads (Vcc pad and GND pad) have the same role in both the scan test mode and the normal operation mode, but the other four pads (XI pad, XO pad, DATAIN pad, DATAOUT pad) are assigned different roles. And, neither the XI pad nor the XO pad to which the oscillator 3 is connected in the normal operation mode is assigned as the DATAOUT pad.

[0034] As described above, data including the results of the operation test is output from the DATAOUT pad, and the data needs to be analyzed outside the integrated circuit device 2. Therefore, the signal voltage level of the data needs to be at a level that can be handled outside the integrated circuit device 2. For this reason, the data is amplified in advance inside the integrated circuit device 2 before being output from the DATAOUT pad. The amplifier circuit for this amplification is a circuit for amplifying the signal output from the flip-flop circuit of the integrated circuit device 2 to a level that allows the data to be analyzed outside the integrated circuit device 2.

[0035] On the other hand, pads other than the DATAOUT pad, i.e., the CLK pad, the DATAIN pad, the MODE pad, and the RESET pad, are pads for inputting signals from the outside to the inside of the integrated circuit device 2. Signals input to these pads may be amplified by, for example, an amplifier circuit Bu, but the amplification rate is smaller than that of amplification performed in the preceding stage of the DATAOUT pad to enable external analysis. Therefore, the amplification in the DATAOUT pad has a larger circuit scale than that of the other pads. For this reason, the parasitic capacitance that may be generated by the amplification in the DATAOUT pad is larger than that of the other pads.

[0036] When a circuit with a large parasitic capacitance is connected to the XI pad and XO pad to which the resonator 3 is connected, the effect on the oscillation characteristics of the resonator 3 is large, but if the parasitic capacitance is small, the effect on the oscillation characteristics is small. For this reason, in this embodiment, the DATAOUT pad, which is a pad for outputting a signal to the outside, is not assigned to either the XI pad or the XO pad. As a result, the effect on the oscillation characteristics of the resonator 3 can be reduced.

[0037] In order to reduce the influence on the vibration characteristics of the vibrator 3, it is sufficient that neither the XI pad nor the XO pad is assigned as a DATAOUT pad. Therefore, either the XI pad or the XO pad may be configured as a DATAIN pad, which is a data input pad.

[0038] As described above, in the integrated circuit device 2 of this embodiment, each pad is assigned a role different from the role of the pad in the normal operation mode. The pad assignment is predetermined, and when a mode setting is instructed to the integrated circuit device 2, each pad functions as a predetermined pad. Table 1 shows the pad assignment for each mode. [Table 1]

[0039] As shown in Table 1, the Vcc pad and the GND pad are the same pad in all modes. Also, the DATAOUT pad, DATAIN pad, and CLK pad are the same pad in the combinational logic circuit test mode and the reset operation test mode. On the other hand, the pad that is the XO pad in the normal operation mode is assigned as the MODE pad in the combinational logic circuit test mode and as the RESET pad in the reset operation test mode.

[0040] As described above, in this embodiment, the DATAOUT pad, DATAIN pad, and CLK pad do not need to switch roles in the combinational logic circuit test mode and the reset operation test mode. The pad that is an XO pad in the normal operation mode needs to be assigned as a MODE pad or a RESET pad in the combinational logic circuit test mode and the reset operation test mode.

[0041] 2 shows a configuration for changing the assignment of the pads. In this embodiment, the mode is set using the OE pad. Therefore, the OE pad also functions as a pad for mode setting. In this embodiment, the mode is set by serial data.

[0042] Fig. 2 shows a circuit for changing the allocation, which is provided inside the control circuit 60. As shown in Fig. 2, a judgment unit 61 is connected to the OE pad. The judgment unit 61 is also connected to a flip-flop circuit FFs for setting the combinational logic circuit test mode and a flip-flop circuit FFr for setting the reset operation test mode.

[0043] The determination unit 61 is a circuit for determining whether or not a predetermined signal has been input to the OE pad. In this embodiment, when the power-on detection unit 40 detects power-on in the integrated circuit device 2 and a signal indicating power-on is input to the control circuit 60, the determination unit 61 performs a determination.

[0044] That is, the judgment unit 61 judges whether or not a predetermined signal is input within a predetermined period after power-on, and accepts the input of serial data when the predetermined signal is input. In this case, the judgment unit 61 further judges whether or not predetermined serial data is input to the OE pad, and when the predetermined serial data is data indicating the setting of the combinational logic circuit test mode, the judgment unit 61 sets the combinational logic circuit test mode. In this case, the judgment unit 61 changes the setting signal FS to a high level (the setting signal FR is at a low level). As a result, the flip-flop circuit FFs latches the setting signal FS in response to the clock signal, and changes the state of the Q terminal to a high level. In this embodiment, this state is the combinational logic circuit test mode.

[0045] On the other hand, if the predetermined serial data indicates the setting of the reset operation test mode, the judgment unit 61 sets the reset operation test mode. In this case, the judgment unit 61 changes the setting signal FR to a high level (the setting signal FS is at a low level). As a result, the flip-flop circuit FFr latches the setting signal FR in response to the clock signal and changes the state of the Q terminal to a high level. In this embodiment, this state is the reset operation test mode.

[0046] FIG. 3 is a timing chart showing the above operation. In FIG. 3, the operation after power-on to the Vcc pad is detected at time T1 is shown for each of three types of modes. The top row is an example of the normal operation mode. When the power-on detection unit 40 detects power-on, the determination unit 61 determines whether or not a predetermined signal is input to the OE pad during a predetermined period. Ex.A shown in the top row is an example of a case where a predetermined signal is not input to the OE pad during the predetermined period from time T1 to T4. In this case, the determination unit 61 does not output the setting signals FS and FR. After the predetermined period has elapsed, the integrated circuit device 2 enters the normal operation mode. In this embodiment, the normal operation mode is set when there is no input to the OE pad during the predetermined period, but of course, a predetermined signal for indicating the normal operation mode may be defined, and the normal operation mode may be set when the predetermined signal is input to the OE pad.

[0047] Ex.B shown in the middle is an example of a case where a predetermined signal "010110" is input to the OE pad during the period from time T2 to T3 during the predetermined period. In this case, the determination unit 61 further enters the serial communication mode and determines whether or not serial data indicating the combinational logic circuit test mode or the reset operation test mode has been input. Ex.B is an example of a case where serial data "101010" indicating the combinational logic circuit test mode is input to the OE pad during the period from time T5 to T6. In this case, the determination unit 61 does not output the setting signal FR, but outputs the setting signal FS. As a result, the flip-flop circuit FFs latches the setting signal FS and outputs a high level to the Q terminal in synchronization with the clock signal. Through the above operations, the integrated circuit device 2 enters the combinational logic circuit test mode.

[0048] Ex.C shown in the lower part is an example of a case where a predetermined signal "010110" is input to the OE pad during the period from time T2 to T3 during the predetermined period. In this case, the judgment unit 61 further enters the serial communication mode and judges whether or not serial data indicating the combinational logic circuit test mode or the reset operation test mode has been input. Ex.C is an example of a case where serial data "100101" indicating the reset operation test mode is input to the OE pad during the period from time T5 to T6. In this case, the judgment unit 61 does not output the setting signal FS, but outputs the setting signal FR. As a result, the flip-flop circuit FFr latches the setting signal FR and outputs a high level to the Q terminal in synchronization with the clock signal. Through the above operations, the integrated circuit device 2 enters the reset operation test mode.

[0049] As described above, when the combinational logic circuit test mode or the reset operation test mode is set, the allocation of the XO pad in the normal operation mode is changed. In this embodiment, the circuit to which the signal is transmitted to the XO pad is switched depending on the mode. The control circuit 60 includes an AND circuit, an OR circuit, three selector circuits, and a power-on reset circuit. In FIG. 2, the inputs of the AND circuit, the OR circuit, and the selector circuit are distinguished by assigning the symbols 1 and 2 to them.

[0050] Fig. 4 is the same as Fig. 2, but the signal lines that go to high level in the combinational logic circuit test mode are shown by thick solid lines. Fig. 5 is the same as Fig. 2, but the signal lines that go to high level in the reset operation test mode are shown by thick solid lines. Note that the level of the XO pad may vary in the combinational logic circuit test mode and the reset operation test mode, but in Figs. 4 and 5, the signal lines that go to the same signal as the input signal are shown by thick dashed lines.

[0051] 2, 4 and 5, the control circuit 60 includes a gate XOG which is an AND circuit, and the XO pads (MODE pad, RESET pad) are electrically connected to input 1 of the gate XOG. The output of a gate MG which is an OR circuit is electrically connected to input 2 of the gate XOG. Therefore, if the output of the gate MG is at a high level, the output signal of the gate XOG will be the same as the input signal to the XO pad.

[0052] The Q terminal of the flip-flop circuit FFs is electrically connected to the input 1 of the gate MG, and the Q terminal of the flip-flop circuit FFr is electrically connected to the input 2 of the gate MG. Therefore, when the Q terminal of one of the flip-flop circuits FFs, FFr is at a high level, that is, when the mode is either the combinational logic circuit test mode or the reset operation test mode, the output of the gate MG becomes a high level, as shown in Figures 4 and 5. Therefore, when the mode is either the combinational logic circuit test mode or the reset operation test mode, the output signal of the gate XOG becomes the same as the input signal to the XO pad. On the other hand, when the mode is the normal operation mode, the output signal of the gate MG is at a low level, and the output of the gate XOG becomes a low level regardless of the input signal to the XO pad.

[0053] Furthermore, the Q terminal of the flip-flop circuit FFs is electrically connected to the input 3 of the selector circuit SL1, and the Q terminal of the flip-flop circuit FFr is electrically connected to the input 3 of the selector circuit SL2. The selector circuit SL3 is a circuit that outputs the input signal to the input 1 when the signal input to the input 3 is at a high level, and outputs the input signal to the input 2 when the signal input to the input 3 is at a low level.

[0054] The output of the gate XOG is connected to input 1 of the selector circuit SL1 and input 1 of the selector circuit SL2. Input 2 of the selector circuit SL1 is electrically connected to the GND pad and fixed at a low level. Input 2 of the selector circuit SL2 is electrically connected to a power-on reset circuit. The power-on reset circuit is a circuit that is indefinite immediately after power is applied to the integrated circuit device 2, then becomes a low-level signal, and outputs a high-level signal when the voltage stabilizes.

[0055] The output of the selector circuit SL1 is electrically connected to the input 2 of the selector circuit SL3. The input 1 of the selector circuit SL3 is fixed to a high level. The output of the selector circuit SL3 is connected to the SE terminals of a plurality of flip-flop circuits FF1 to FF6, which will be described later. In this embodiment, the output from the selector circuit SL3 is called an SE (scan enable) signal. The output of the selector circuit SL2 is connected to the R terminals of a plurality of flip-flop circuits FF1 to FF6, which will be described later. In this embodiment, the output from the selector circuit SL2 is called an SR (scan reset) signal.

[0056] In the combinational logic circuit test mode, as described above, the signal input to the gate XOG and the output of the gate XOG are the same. In the combinational logic circuit test mode, the Q terminal of the flip-flop circuit FFs becomes high level as shown in FIG. 4, so the output of the selector circuit SL1 is the same as the input 1 and the same as the output of the gate XOG. In the combinational logic circuit test mode, the Q terminal of the flip-flop circuit FFr becomes low level as shown in FIG. 4, so the output of the selector circuit SL3 is the same as the input 2 and the same as the output of the power-on reset circuit. Since the output of the selector circuit SL3 is an SE signal, in the combinational logic circuit test mode, the SE signal becomes the same as the input signal input to the XO pad.

[0057] As described above, in the reset operation test mode, the signal input to the gate XOG and the output of the gate XOG are the same. In the reset operation test mode, the Q terminal of the flip-flop circuit FFr becomes high level as shown in FIG. 5, so the output of the selector circuit SL2 is the same as the input 1, and is the same as the output of the gate XOG. Since the output of the selector circuit SL2 is the SR signal, in the reset operation test mode, the SR signal becomes the same as the input signal input to the XO pad. In FIG. 2, a timing chart of the SR signal is also shown, which shows that the SR signal is electrically equivalent to the input signal input to the XO pad after time t7 in the reset operation test mode.

[0058] In the reset operation test mode, since the Q terminal of the flip-flop circuit FFr is at a high level as shown in Fig. 5, the output of the selector circuit SL3 is at a high level, which is the same as the input 1. Therefore, in the reset operation test mode, the SE signal is always at a high level as shown in Fig. 5.

[0059] As described above, in this embodiment, the signal input to the XO pad in combinational logic circuit test mode is the SE signal, and the signal input to the XO pad in reset operation test mode is the SR signal. As such, since the destination of the signal input to the XO pad differs depending on the mode, in this embodiment, when specifying the destination of the signal, the name of the pad is changed from the XO pad depending on the mode, and is called a MODE pad in combinational logic circuit test mode and a RESET pad in reset operation test mode.

[0060] Note that before the reset operation test mode is determined, or in the normal operation mode or combinational logic circuit test mode, the Q terminal of the flip-flop circuit FFr is at a low level. In this case, the output of the selector circuit SL2 becomes the same as the input signal to the input 2. Therefore, before the reset operation test mode is set, or in the normal operation mode or combinational logic circuit test mode, the output signal of the selector circuit SL2 becomes the same as the output signal of the power-on reset circuit.

[0061] That is, before the reset operation test mode is set, in the normal operation mode, and in the combinational logic circuit test mode, when the voltage stabilizes after power-on, the output of the selector circuit SL2 changes from low level to high level. The SR signal that is the output of the selector circuit SL2 is inverted and input to the reset terminals (R terminals) of the flip-flop circuits FF1 to FF6 described below. Therefore, before the reset operation test mode is set, in the normal operation mode, and in the combinational logic circuit test mode, when the power is turned on, the power-on reset circuit is at low level, so that the flip-flop circuits are once reset. Then, when the voltage stabilizes after power-on, the power-on reset circuit goes to high level, and the reset of the flip-flop circuits is released.

[0062] Next, the relationship between the scan chain and the combinational logic circuit will be described. FIG. 6 shows a plurality of flip-flop circuits FF1 to FF6 constituting a scan chain, and combinational logic circuits CL1 to CL3 which are the targets of a test of the operation of the combinational logic circuit. A scan test is performed by arranging a flip-flop circuit at least on one of the input and output of the combinational circuit to be scanned. That is, desired data is input to the combinational circuit from the flip-flop circuit arranged at the input of the combinational logic circuit. An output indicating the result of the operation by the combinational circuit is held in the flip-flop circuit arranged at the output of the combinational circuit.

[0063] Therefore, when making it possible to carry out a scan test, a flip-flop circuit is arranged on the input side of a combinational logic circuit to be tested by inputting a desired value, and a flip-flop circuit is arranged on the output side of a combinational logic circuit to be tested, whose output result is the object of testing. In Fig. 6, it is assumed that a desired value is input to all of the combinational logic circuits CL1 to CL3, and the output result is the object of testing. Of course, the configuration for the scan test is not limited to the configuration shown in Fig. 6, and the number of combinational logic circuits to be tested, the circuit size to be tested, the arrangement of the flip-flop circuits, and the like may be various.

[0064] 6, the flip-flop circuits FF1 to FF6 include a data input terminal (D terminal), a clock input terminal, a scan data input terminal (SD terminal), a scan enable input terminal (SE terminal), a reset terminal (R terminal), a data output terminal (Q terminal), and an inverted data output terminal (QN terminal). In this embodiment, the inverted data output terminal is not used for a scan test, but a configuration in which it is used may be adopted.

[0065] In this embodiment, the flip-flop circuits FF1 to FF6 operate at the rising edge of a clock signal input to the clock terminal. The SE terminal is a terminal for designating an input terminal to be enabled, and when the signal input to the SE terminal is at a low level, the flip-flop circuits FF1 to FF6 hold a signal input to the D terminal and output it from the Q terminal. When the signal input to the SE terminal is at a high level, the flip-flop circuits FF1 to FF6 hold a signal input to the SD terminal and output it from the Q terminal. Furthermore, when the signal input to the R terminal is at a high level, the flip-flop circuits FF1 to FF6 are asynchronously reset, and the signal output from the Q terminal becomes low level.

[0066] In this embodiment, the flip-flop circuits FF1 to FF3 are configured to latch input signals to the combinational logic circuits CL1 to CL3 and output them to the combinational logic circuits CL1 to CL3. That is, the D terminals of the flip-flop circuits FF1 to FF3 are electrically connected to the signal lines IL1 to IL3 that supply input signals to the combinational logic circuits CL1 to CL3, and the outputs of the Q terminals are supplied to the combinational logic circuits CL1 to CL3.

[0067] In this embodiment, the flip-flop circuits FF4 to FF6 are configured to latch and output the output signals from the combinational logic circuits CL1 to CL3. That is, the D terminals of the flip-flop circuits FF4 to FF6 are electrically connected to the signal lines OL1 to OL3 that output the output signals of the combinational logic circuits CL1 to CL3, and the output of the Q terminal is transmitted to the subsequent circuit.

[0068] As described above, the flip-flop circuits FF1 to FF3 are configured to be able to hold input signals to the combinational logic circuits CL1 to CL3 via terminals D. In addition, the flip-flop circuits FF4 to FF6 are configured to be able to hold output signals from the combinational logic circuits CL1 to CL3.

[0069] The flip-flop circuits FF1 to FF6 according to this embodiment are further configured to be capable of forming a scan chain in which a plurality of these flip-flop circuits are connected in series. Specifically, the Q terminal of the flip-flop circuit FF1 is electrically connected to the SD terminal of the flip-flop circuit FF2. According to this connection, the output of the Q terminal of the flip-flop circuit FF1 is input to the SD terminal of the flip-flop circuit FF2. Here, such a connection is called a series connection in which a signal is transmitted from the flip-flop circuit FF1 to the flip-flop circuit FF2. And, the flip-flop circuits FF1 to FF6 according to this embodiment are serial connections in which a signal is transmitted in the order of the flip-flop circuits FF1, FF2, FF3, FF4, FF5, and FF6, as shown in FIG. 6. Such a connection relationship is a scan chain.

[0070] In the above configuration, the CLK pad is electrically connected to the clock terminals of the flip-flop circuits FF1 to FF6. Therefore, when a clock signal CLK is input to the XI pad shown in Fig. 2, the flip-flop circuits FF1 to FF6 latch in synchronization with the clock signal CLK. In the scan test mode, the clock signal CLK is thus supplied to the XI pad, and is supplied to each flip-flop circuit via the amplifier circuit Bu. In this sense, the XI pad becomes a CLK pad in the scan test mode.

[0071] Also, when the flip-flop circuits FF1 to FF6 connected in series are considered to be arranged in the order of the flip-flop circuits FF1 to FF6, the OUT pad is electrically connected to the SD terminal of the first flip-flop circuit FF1. In the scan mode, data held in the scan chain is supplied to the OUT pad. In this sense, in the scan test mode, the OUT pad becomes a DATAIN pad.

[0072] Furthermore, when the series-connected flip-flop circuits FF1 to FF6 are considered to be arranged in the order of the flip-flop circuits FF1 to FF6, the OE pad is electrically connected to the Q terminal of the last flip-flop circuit FF6. In the scan mode, data held in the scan chain is output to the OE pad. In this sense, in the scan test mode, the OE pad becomes a DATAOUT pad.

[0073] Furthermore, the output terminal of the selector circuit SL3 shown in Fig. 2 is electrically connected to the SE terminals of the flip-flop circuits FF1 to FF6. The SE terminal is a terminal for setting the input terminal to be enabled in the flip-flop circuits FF1 to FF6 to either the D terminal or the SD terminal. Therefore, as shown in Fig. 4, when the input signal to the XO pad becomes the output signal of the selector circuit SL3 in the combinational logic circuit test mode, the input terminal to be enabled in the flip-flop circuits FF1 to FF6 can be set by the input signal to the XO pad. Therefore, in the combinational logic circuit test mode, the XO pad becomes a MODE pad.

[0074] Furthermore, the R terminals of the flip-flop circuits FF1 to FF6 are electrically connected to the output terminal of the selector circuit SL2 shown in Fig. 2. The R terminal is a terminal for resetting the flip-flop circuits FF1 to FF6. Therefore, as shown in Fig. 5, when the input signal to the XO pad in the reset operation test mode is the output signal of the selector circuit SL2, it is possible to reset the flip-flop circuits FF1 to FF6 by the input signal to the XO pad. Therefore, in the reset operation test mode, the XO pad becomes a RESET pad.

[0075] (1-2) Operation in combinational logic circuit test mode: Next, the operation in the combinational logic circuit test mode will be described in detail. The combinational logic circuit test mode is a mode for testing the operation of a combinational logic circuit, in which data input to the scan chain, signal input to the combinational logic circuit, signal output from the combinational logic circuit, and data output from the scan chain are executed.

[0076] FIG. 7 is a diagram showing an example of signals at the CLK pad, the MODE pad, the DATAIN pad, and the DATAOUT pad in the combinational logic circuit test mode, and a signal that is latched by the flip-flop circuits FF1 to FF6 and output from the Q terminal by the signals. In this example, first, after power is turned on, the power-on reset circuit goes to low level, and the output from the selector circuit SL2 goes to low level. As a result, the SR signal goes to low level, but since an inverted signal of the SR signal is input to the R terminals of the flip-flop circuits FF1 to FF6, a high level is input to the R terminals. As a result, the flip-flop circuits FF1 to FF6 are reset. In addition, the Q terminal of the flip-flop circuit FF6 goes to low level, and the output signal of the DATAOUT pad goes to low level. When the power supply becomes stable, the power-on reset circuit goes to high level, and the output from the selector circuit SL2 goes to high level. As a result, the SR signal goes to high level, but since an inverted signal of the SR signal is input to the R terminals of the flip-flop circuits FF1 to FF6, a low level is input to the R terminals. As a result, the reset of the flip-flop circuits FF1 to FF6 is released.

[0077] When the combinational logic circuit test mode is set, a predetermined signal is input to the OE pad during a predetermined period shown in Fig. 3, and the combinational logic circuit test mode is set. In Fig. 7, the timing at which the combinational logic circuit test mode is set is timing t0. At timing t0, the outputs of the Q terminals of the flip-flop circuits FF1 to FF6 and the output of the DATAOUT pad are set to low level L by the above-mentioned reset.

[0078] In the combinational logic circuit test mode, the clock signal input to the CLK pad and the setting signal input to the MODE pad are both initially set to low level. This state is a first state in which the flip-flop circuits FF1 to FF3 hold (latch) the signals to the D terminals which are input signals to the combinational logic circuits CL1 to CL3, and the flip-flop circuits FF4 to FF6 hold (latch) the signals to the D terminals which are output signals from the combinational logic circuits CL1 to CL3.

[0079] Next, the setting signal input to the MODE pad is set to high level, and a clock signal CLK for 6 clocks, which corresponds to the number of flip-flop circuits FF1 to FF6, is input. When the MODE pad is at high level, the signal input to the SE terminals of the flip-flop circuits FF1 to FF6 is at high level, which is the second state in which a scan chain is formed by connecting the flip-flop circuits FF1 to FF6 in series.

[0080] In the combinational logic circuit test mode, the flip-flop circuits FF1 to FF6 are reset at the initial stage, so that the low level L, which is the output of the Q terminal, is sequentially transmitted to the flip-flop circuits FF1 to FF6 in synchronization with the clock signal CLK for the six clocks. As a result, in the period from timing t0 to timing t6, low level signals, which are the data of the flip-flop circuits FF6, FF5, FF4, FF3, FF2, and FF1, are sequentially output from the DATAOUT pad. Figure 7 shows how the low level L is sequentially transmitted to the flip-flop circuits FF1 to FF6, and the signal at the DATAOUT pad from timing t0 to t6 is low level L.

[0081] Furthermore, in synchronization with the six-clock clock signal CLK, high-level or low-level signals a1 to a6 are input to the DATAIN pad in this order as data for the scan test. In Fig. 7, signals a1 to a6 are shown as signals input to the DATAIN pad at each of the timings t1 to t6. For example, signal a1 is latched by flip-flop circuit FF1 at the first timing t1, and as a result of being sequentially transmitted by the scan chain after timing t1, at timing t6 it is latched by flip-flop circuit FF6.

[0082] The signal a1 latched in the flip-flop circuit FF6 is output from the Q terminal, and the output of the DATAOUT pad becomes the signal a1. As a result of this signal transmission, the signals a1 to a6 are transmitted in sequence through the flip-flop circuits FF1 to FF6, and after timing t6 when the input of six clock signals CLK is completed, the signals a1 to a6 are held in the flip-flop circuits FF6, FF5, FF4, FF3, FF2, and FF1, respectively.

[0083] Next, when the MODE pad is set to a low level, the first state is entered and the scan chain is released. In this state, the signals a6, a5, and a4 that are latched in the flip-flop circuits FF1, FF2, and FF3 and output from the Q terminals are input to the combinational logic circuits CL1, Cl2, and CL3, respectively. Furthermore, in this state, the clock signal CLK is input (timing t7 shown in FIG. 7). As a result, the flip-flop circuits FF1 to FF6 perform a latch operation in response to the clock signal CLK. Therefore, the output signals output from the combinational logic circuits CL1, Cl2, and CL3 in response to the input signals a6, a5, and a4 are latched in the flip-flop circuits FF6, FF5, and FF4 and output from the Q terminals. Here, the signals output from the Q terminals of the flip-flop circuits FF6, FF5, and FF4 are called signals b1, b2, and b3.

[0084] Since the flip-flop circuits FF3, FF2, and FF1 also perform latch operations due to the clock signal CLK, the signal at the D terminal is latched and output from the Q terminals of the flip-flop circuits FF3, FF2, and FF1. Here, the signals output from the Q terminals of the flip-flop circuits FF3, FF2, and FF1 are called signals b4, b5, and b6. In this state, the signal b1 latched in the flip-flop circuit FF6 is output from the DATAOUT pad.

[0085] Next, the MODE pad is set to a high level again, and a second state is established in which a scan chain is formed. Then, in synchronization with five clocks of the clock signal CLK from timing t8 onwards, the signals b2, b3, b4, b5, and b6 latched in the flip-flop circuit are sequentially output from the DATAOUT pad. At least a part of the output signals b1 to b6 from the DATAOUT pad has a value corresponding to the input signals a1 to a6 to the DATAIN pad. Therefore, by comparing the input signals a1 to a6 with the output signals b1 to b6, it is possible to test whether the combinational logic circuits CL1 to CL3 are operating as expected.

[0086] After the output signals b1 to b6 are output, the scan test may be continued. In Fig. 7, the signals a8 to a13 are input to the DATAIN pad at timings t8 to t9, which is the second state, and the signals a8 to a13 are latched in the flip-flop circuits FF6 to FF1 at timing t9, and then the state is switched to the first state and a test is performed. Of course, the scan test may be continued after this.

[0087] In the above configuration, the reset operations of the flip-flop circuits FF1 to FF6 are not tested in the combinational logic circuit test mode. Therefore, there is no need to provide pads in the integrated circuit device 2 that are used for the reset operations and are not used in the combinational logic circuit test mode. Therefore, it is possible to reduce the size of the integrated circuit device 2.

[0088] (1-3) Reset operation test mode operation: Next, the operation in the reset operation test mode will be described in detail. The reset operation test mode is a mode for testing the reset operations of the flip-flop circuits FF1 to FF6, in which data input to the scan chain, a reset operation, and data output from the scan chain are executed.

[0089] FIG. 8 is a diagram showing an example of signals at the CLK pad, the SE terminal, the RESET pad, the DATAIN pad, and the DATAOUT pad in the reset operation test mode, and a signal latched by the flip-flop circuits FF1 to FF6 and output from the Q terminal by the signals. In this example, first, after power is turned on, the power-on reset circuit goes to low level, and the output from the selector circuit SL2 goes to low level. As a result, the SR signal goes to low level, but since an inverted signal of the SR signal is input to the R terminals of the flip-flop circuits FF1 to FF6, a high level is input to the R terminals. As a result, the flip-flop circuits FF1 to FF6 are reset, the Q terminal of the flip-flop circuit FF6 goes to low level, and the output signal of the DATAOUT pad goes to low level. When the power supply becomes stable, the power-on reset circuit goes to high level, and the output from the selector circuit SL2 goes to high level. As a result, the SR signal goes to high level, but since an inverted signal of the SR signal is input to the R terminals of the flip-flop circuits FF1 to FF6, a low level is input to the R terminals. As a result, the reset of the flip-flop circuits FF1 to FF6 is released.

[0090] When the reset operation test mode is set, a predetermined signal is input to the OE pad during a predetermined period shown in Fig. 3, and the reset operation test mode is set. In Fig. 8, the timing at which the reset operation test mode is set is timing t0. Note that at timing t0, the outputs of the Q terminals of the flip-flop circuits FF1 to FF6 and the output of the DATAOUT pad are set to low level L by the above-mentioned reset.

[0091] In the reset operation test mode, the clock signal input to the CLK pad is initially set to low level. When the power-on reset circuit outputs a high level, the above-mentioned reset and reset release are performed, and then the reset operation test mode is set, as shown in Figure 5, the Q terminal of the flip-flop circuit FFr goes to high level, so the reset signal SR becomes the same as the signal input to the RESET pad. In the reset operation test mode, the RESET pad is initially set to high level.

[0092] Furthermore, when the reset operation test mode is set, the Q terminal of the flip-flop circuit FFr becomes high level as shown in Figure 5, so that the output of the selector circuit SL3 is fixed at high level. Therefore, the signals input to the SE terminals of the flip-flop circuits FF1 to FF6 become high level. Timing t0 shown in Figure 8 shows this state.

[0093] At timing t0, the signal input to the SE terminal is at a high level, so the flip-flop circuits FF1 to FF6 are in the second state in which a series-connected scan chain is configured. In the reset operation test mode, the signal input to the SE terminal is fixed to a high level, so the second state is maintained in the reset operation test mode.

[0094] Thereafter, a clock signal CLK for six clocks corresponding to the number of flip-flop circuits FF1 to FF6 is input. In the reset operation test mode, since the flip-flop circuits FF1 to FF6 are reset at the initial stage, the output of the Q terminal is sequentially transmitted to the flip-flop circuits FF1 to FF6 in synchronization with the clock signal CLK for six clocks. As a result, during the period from timing t0 to timing t6, low-level signals which are data of the flip-flop circuits FF6, FF5, FF4, FF3, FF2, and FF1 are sequentially output from the DATAOUT pad. FIG. 8 shows how a low level L is sequentially transmitted to the flip-flop circuits FF1 to FF6, and the signal of the DATAOUT pad is low level L from timing t0 to t6.

[0095] Furthermore, in synchronization with the six-clock clock signal CLK, high-level or low-level signals a1 to a6 are input to the DATAIN pad in this order as data for the scan test. As a result, the signals a1 to a6 are transmitted sequentially through the flip-flop circuits FF1 to FF6, and after timing t6 when the input of the six-clock clock signal CLK ends, the signals a1 to a6 are held in the flip-flop circuits FF6, FF5, FF4, FF3, FF2, and FF1, respectively.

[0096] 8, signals a1 to a6 are shown as being input to the DATAIN pad at timings t1 to t6, respectively. For example, signal a1 is latched by flip-flop circuit FF1 at the first timing t1, and as a result of being sequentially transmitted by the scan chain, it is in a state latched by flip-flop circuit FF6 at timing t6. The signal a1 latched by flip-flop circuit FF6 is output from the Q terminal, and the output of the DATAOUT pad becomes signal a1.

[0097] Next, when a pulse signal that changes from high to low and then from low to high is input to the RESET pad at timing t7, the flip-flop circuits FF1 to FF6 are reset, and the Q terminals of the flip-flop circuits FF1 to FF6 become low level L. In this state, when a clock signal CLK is input after timing t8, the low level L latched in the flip-flop circuits is output from the DATAOUT pad in sequence in synchronization with the clock signal CLK. Therefore, by determining whether all of the outputs are low level L, it is possible to test whether the flip-flop circuits FF1 to FF6 are reset normally and whether the paths of the scan chain and the signal lines to each of the flip-flop circuits FF1 to FF6 are appropriate.

[0098] After the series of low level L signals are output, the scan test may be continued. In Fig. 8, signals a8 to a13 are input to the DATAIN pad at timings t8 to t9, and the signals a8 to a13 are latched in the flip-flop circuits FF6 to FF1 at timing t9, after which a reset is performed and the test is performed. Of course, the scan test may be continued after this.

[0099] In the above configuration, the operations of the combinational logic circuits CL1 to CL3 are not tested in the reset operation test mode. Therefore, there is no need to provide pads in the integrated circuit device 2 that are used to release the scan chain and are not used in the reset operation test mode. Therefore, it is possible to reduce the size of the integrated circuit device 2.

[0100] In this embodiment, as described above, the reset operation is not tested in the combinational logic circuit test mode, and the operation of the combinational logic circuit is not tested in the reset operation test mode, so that the number of pads can be reduced. Therefore, in order to test the reset operation after the combinational logic circuit test mode, or to test the operation of the combinational logic circuit after the reset operation test mode, the power supply to the integrated circuit device 2 is stopped once. In other words, by stopping the power supply and turning the power on again to set the mode, any test mode can be set.

[0101] (2) Other embodiments: The above-mentioned embodiment is an example for carrying out the present invention, and various other embodiments can be adopted. In addition, the application target of the integrated circuit device according to one embodiment of the present invention is not limited, and it can be used in various devices, for example, various electronic devices, electrical equipment of a vehicle, etc. Furthermore, the operation by the combinational logic circuit included in the integrated circuit is not limited to the operation used in the PLL circuit, and may be used for various other operations. Furthermore, the sequence for executing the test is not limited to Fig. 7 and Fig. 8, and for example, the clock signal CLK may be input multiple times at the timing t7 in Fig. 7. In addition, the sequence for switching the mode is not limited to Fig. 3.

[0102] Furthermore, various modifications may be made to the elements and circuits constituting the above-mentioned embodiment. For example, the configuration for electrically connecting the same pad to different circuits is not limited to the configuration shown in FIG. 2, and can be realized in various configurations. Specifically, the configuration may be such that the output of the power-on reset circuit is electrically connected to the input 1 of the selector circuit SL3, or a configuration in which an equivalent function is realized by using an AND circuit instead of a selector circuit. Furthermore, although the above-mentioned embodiment is an SPXO (Simple Packaged Crystal Oscillator), other types of oscillators, such as a TCXO (Temperature Compensated Crystal Oscillator) or a VCXO (Voltage Controlled Crystal Oscillator), may also be used. [Explanation of symbols]

[0103] 1...oscillator, 2...oscillating circuit, 3...resonator, 10...oscillating circuit, 20...fractional N-PLL circuit, 30...frequency divider circuit, 40...output circuit, 50...regulator, 60...regulator, 70...control circuit, 80...serial interface circuit, 90...non-volatile memory, D...input signal node, G1...first gate circuit, G2...second gate circuit, G3...third gate circuit, Inv...CMOS inverter circuit

Claims

1. 1. An integrated circuit device having a normal operation mode and a scan test mode, First to fourth pads; A combinational logic circuit; a plurality of flip-flop circuits; The plurality of flip-flop circuits include a first state that holds an input signal to the combinational logic circuit and holds an output signal from the combinational logic circuit; a second state in which a scan chain is configured by connecting a plurality of the flip-flop circuits in series; The scan test mode includes: a combinational logic circuit test mode for testing an operation of the combinational logic circuit, and a reset operation test mode for testing reset operations of a plurality of the flip-flop circuits, In the combinational logic circuit test mode, the first to fourth pads are a data input pad for inputting data used for testing the operation of the combinational logic circuit to the scan chain; a data output pad for outputting data held in the scan chain; a clock input pad for inputting a clock signal to the plurality of flip-flop circuits; a setting signal input pad for inputting a setting signal for setting the plurality of flip-flop circuits to either the first state or the second state; Assign to In the reset operation test mode, the first to fourth pads are a data input pad for inputting data used in testing the reset operation to the scan chain; a data output pad for outputting data held in the scan chain; a clock input pad for inputting a clock signal to the plurality of flip-flop circuits; a reset signal input pad for inputting a reset signal to the plurality of flip-flop circuits; Assign to the first to fourth pads include a transducer pad that is connected to a transducer in the normal operation mode; In the combinational logic circuit test mode, the oscillator pad is assigned to the setting signal input pad; In the reset operation test mode, the transducer pad is assigned to the reset signal input pad. Integrated circuit device.

2. the first to fourth pads include other transducer pads connected to the transducer in the normal operation mode; In the combinational logic circuit test mode, the other oscillator pad is assigned to the data input pad or the clock input pad; In the reset operation test mode, the other oscillator pad is assigned to the data input pad or the clock input pad; an amplifier circuit for amplifying a signal input from the other resonator pad in the combinational logic circuit test mode and the reset operation test mode; 2. The integrated circuit device of claim 1.

3. The amplifier circuit is a buffer for shaping the waveform of the input signal.

3. The integrated circuit device of claim 2.

4. an oscillation circuit for oscillating the oscillator; a fractional PLL circuit to which an oscillation signal from the oscillation circuit is input; A control circuit for controlling the fractional PLL circuit, the control circuit includes the combinational logic circuit and a plurality of the flip-flop circuits; 4. The integrated circuit device according to claim 1.

5. When a predetermined signal is input to any one of the first to fourth pads within a predetermined period of time after the integrated circuit device is powered on, a circuit for receiving serial data input to any one of the first to fourth pads, and setting the normal operation mode, the combinational logic circuit test mode, or the reset operation test mode in accordance with the serial data; 5. The integrated circuit device according to claim 1.

6. An oscillator comprising the integrated circuit device according to any one of claims 1 to 4, the resonator, and a package that houses the integrated circuit device and the resonator, The outer surface of the package is A high-potential power supply external terminal; A low potential power supply external terminal; an OE external terminal for controlling whether or not an output is made from the oscillator; an external output terminal for outputting an oscillation signal from the oscillator; the integrated circuit device includes two pads electrically connected to the high potential power supply external terminal and the low potential power supply external terminal, two pads among the first to fourth pads of the integrated circuit device are electrically connected to the OE external terminal and the output external terminal, respectively; The remaining two pads among the first to fourth pads included in the integrated circuit device, that is, the vibrator pad and another vibrator pad, are each electrically connected to the vibrator. Oscillator.

Images