Photodetector element and electronic device

Abstract

To ensure stable overflow from a PD and to prevent Qs degradation and color mixing.SOLUTION: A solid-state image sensor of an aspect of the present disclosure comprises a charge retention portion that generates and retains a charge in response to incident light, an OFD portion from which the charge saturated in the charge retention portion is discharged, and a potential barrier portion that serves as a barrier to the charge flowing out from the charge retention portion to the OFD portion, on the photosensitive surface side within the semiconductor substrate, and the OFD portion comprises a low-concentration OFD portion and a high-concentration OFD portion having different concentrations of impurities of the same type, and the high-concentration OFD portion and the potential barrier portion are formed with a gap between them. This technology can be applied to CMOS image sensors, for example.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present technology relates to a photodetector element and an electronic device, and more particularly to a photodetector element and an electronic device that enable stable overflow from a photodiode. [Background technology]

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors are known as solid-state imaging devices mounted on digital still cameras, digital video cameras, etc. In a CMOS image sensor (hereafter referred to as CIS), charges corresponding to incident light are generated by photoelectric conversion using a PD (Photodiode) formed for each pixel, and the generated charges are transferred to a FD (Floating Diffusion) via a transfer transistor, where the charges are converted into electrical signals (pixel signals) and read out.

[0003] Conventionally, a configuration has been proposed in which PDs are formed deep inside (on the back side) of a Si (silicon) substrate in order to improve the Qs (saturation charge) of the CIS, form a vertical spectroscopic CIS by stacking multiple PDs vertically, etc. The charge generated and accumulated in the PD is read out and transferred to an FD provided on the front side of the Si substrate via a vertical transistor provided vertically (vertically) to the Si substrate.

[0004] In the above-mentioned configuration, the distance between the PD and the FD is long, and the vertical transistor is fixed to a low voltage during charge storage in the PD, making it difficult to design an overflow. For this reason, a structure has been proposed in which an overflow drain (hereinafter referred to as OFD) is provided on the back side of the Si substrate (for example, Patent Document 1).

[0005] Figure 1 shows an example of the configuration of a CMOS image sensor with a PD and OFD on the back side of a Si substrate. Figure 1A shows a cross-sectional view, and Figure 1B shows the potential of each part of the CIS.

[0006] In this CIS 10, a PD 12 is formed on the back side (deep part) of a Si substrate 11, and an FD 14 is formed on the front side. A vertical transistor 13 is formed in a direction perpendicular to the Si substrate 11. Furthermore, an OFD 16 is formed on the back side (deep part) of the Si substrate 11, and is connected to the PD 12 via a potential barrier part 15. The OFD 16 is made of a high-concentration diffusion layer that is set to the power supply voltage.

[0007] The potential heights of PD 12, potential barrier section 15, and OFD 16 are as shown in FIG. B. When the charge generated and accumulated in PD 12 becomes saturated, the saturated charge will cross potential barrier section 15 and be discharged to OFD 16. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2013-38118 A Summary of the Invention [Problem to be solved by the invention]

[0009] In the case of the configuration shown in A of Fig. 1, the potential heights of the PD 12, the potential barrier section 15, and the OFD 16 are theoretically as shown in B of Fig. 1. However, since the OFD 16 is a high-concentration diffusion layer and is close to the potential barrier section 15, if the arrangement of the PD 12, the potential barrier section 15, and the OFD 16 is shifted or the impurity concentrations of each are varied when forming the PD 12, the potential barrier section 15, and the OFD 16, the potential height of the potential barrier section 15 is likely to change significantly. In that case, Qs may decrease or color mixing with adjacent pixels may occur.

[0010] This technology was developed in light of these circumstances, and aims to enable stable overflow from the PD, thereby preventing a decrease in Qs and the occurrence of color mixing. [Means for solving the problem]

[0011] A photodetector according to a first aspect of the present technology includes, in a semiconductor substrate, a charge retention portion that generates and retains charge in response to incident light, an OFD portion from which the charge saturated in the charge retention portion is discharged, and a potential barrier portion that serves as a barrier for the charge flowing from the charge retention portion to the OFD portion, and a first vertical transistor that is formed on a surface of the semiconductor substrate opposite to a light receiving surface and overlaps the OFD portion in a plan view. a first vertical transistor for discharging the charge from the OFD section; It further comprises:

[0012] An electronic device according to a second aspect of the present technology is an electronic device equipped with a photodetector, the photodetector comprising: a charge retention section that generates and retains charge in response to incident light; an OFD section from which the charge saturated in the charge retention section is discharged; and a potential barrier section that serves as a barrier for the charge flowing from the charge retention section to the OFD section, within a semiconductor substrate; and a first vertical transistor that is formed from a surface of the semiconductor substrate opposite to a light receiving surface and overlaps the OFD section in a plan view. a first vertical transistor for discharging the charge from the OFD section; It further comprises: Effect of the Invention

[0013] According to the first aspect of the present technology, it is possible to stably perform overflow from a charge storage portion and prevent a decrease in Qs and the occurrence of color mixing.

[0014] According to the second aspect of the present technology, it is possible to prevent a decrease in Qs of a solid-state imaging element and the occurrence of color mixing. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a conventional CIS. [Diagram 2] 1 is a cross-sectional view showing a first configuration example of a solid-state imaging element to which the present technology is applied. [Diagram 3] FIG. 13 is a diagram illustrating the potential around the PD in the first configuration example. [Figure 4]2A to 2C are diagrams for explaining a manufacturing method of the first configuration example of the solid-state imaging element. [Diagram 5] 11 is a cross-sectional view showing a second configuration example of a solid-state imaging element to which the present technology is applied. [Figure 6] FIG. 13 is a diagram illustrating the potential around the PD in the second configuration example. [Figure 7] 10A to 10C are diagrams for explaining a manufacturing method of the second configuration example of the solid-state imaging element. [Figure 8] 11 is a cross-sectional view showing a third configuration example of a solid-state imaging element to which the present technology is applied. [Figure 9] 11 is a cross-sectional view showing a configuration example in which a through electrode is provided for each pixel. FIG. [Figure 10] 11 is a cross-sectional view showing a configuration example in which a through electrode is shared by a plurality of pixels. FIG. [Figure 11] FIG. 11 is a top view corresponding to the configuration example shown in FIG. [Figure 12] 11 is a cross-sectional view showing a configuration example for controlling the potential of a potential barrier portion. FIG. [Figure 13] FIG. 11 is a cross-sectional view of a configuration example in which a high-density OFD is shared by a plurality of pixels. [Figure 14] FIG. 14 is a top view corresponding to the configuration example shown in FIG. [Figure 15] FIG. 11 is a cross-sectional view showing a modification in which a PD is additionally laminated in the first configuration example. [Figure 16] FIG. 11 is a cross-sectional view showing a modified example in which a photoelectric conversion film is added to the first configuration example. [Figure 17] FIG. 11 is a cross-sectional view showing a modification in which a drain layer is added to the second configuration example. [Figure 18] FIG. 11 is a cross-sectional view showing a modification in which a well isolation layer is added to the second configuration example. [Figure 19] FIG. 11 is a cross-sectional view showing a configuration example having a well isolation layer. [Figure 20] FIG. 11 is a cross-sectional view showing a configuration example having a well isolation layer. [Figure 21] FIG. 11 is a cross-sectional view showing a configuration example having a well isolation layer. [Figure 22]11 is a cross-sectional view showing a configuration example in which the same effect can be obtained without using a well isolation layer. FIG. [Diagram 23] FIG. 11 is a cross-sectional view showing a modification in which a drain layer and a well isolation layer are added to the second configuration example. [Figure 24] FIG. 24 is a top view of the modification shown in FIG. 23. [Diagram 25] 11 is a top view showing a configuration example in which a vertical transistor is shared by a plurality of pixels. FIG. [Figure 26] 1A to 1C are diagrams illustrating examples of use of a solid-state imaging device according to an embodiment of the present technology; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, the best mode for carrying out the present technology (hereinafter, referred to as an embodiment) will be described in detail with reference to the drawings.

[0017] <First configuration example of a solid-state imaging device according to an embodiment of the present technology> Fig. 2 is a block cross-sectional view showing a first configuration example of a solid-state imaging device according to an embodiment of the present technology. Note that Fig. 2 shows one pixel, and components common to the conventional CIS shown in Fig. 1 are given the same reference numerals, and therefore the description thereof will be omitted as appropriate.

[0018] The first configuration example of this solid-state imaging element 30 is a so-called back-illuminated CIS that has a PD (charge storage unit) 31 formed near the back surface of the Si substrate 11 and outputs a pixel signal in response to light irradiated from the back surface side.

[0019] In a first configuration example of the solid-state imaging element 30, a vertical transistor 13 is formed in a direction perpendicular to (vertical direction) the Si substrate 11, and an FD 14 is formed on the front surface side. The electric charge converted and accumulated in the PD 31 is transferred to the FD 14 via the vertical transistor 13.

[0020] The PD 31 is, for example, an N+ region (with an N-type impurity concentration of 1E16 to 1E18 / cm) formed in a P-type well of the Si substrate 11. 3) and is formed inside the Si substrate 11 at a predetermined distance from the rear surface of the Si substrate 11 so as not to come into contact with the rear surface of the Si substrate 11.

[0021] In addition, the solid-state imaging device 30 includes an N-region (P-type impurity concentration 1E16 to 1E18 / cm 3 ) formed adjacent to the PD 31 in the lateral direction. 3 ) and an N+ region (N-type impurity concentration 1E16 to 1E18 / cm 3 ) having the same concentration as the PD 31 formed adjacent to the potential barrier portion 32 in the lateral direction. 3 ) is formed. The potential control of the potential barrier portion 32 will be described later with reference to FIG.

[0022] Furthermore, in the solid-state imaging element 30, an N+ region (N-type impurity concentration 1E18 to 1E20 / cm) having a higher concentration than the low-concentration OFD 33 is provided at a position overlapping the low-concentration OFD 33 and spaced from the potential barrier portion 32 so as to be in contact with the rear surface side of the Si substrate 11. 3 ) is formed. The high-concentration OFD 34 is fixed to a voltage higher than the potential generated in the PD 31 when charge is accumulated in the PD 31 (details will be described later with reference to FIGS. 9 to 11).

[0023] 3 shows the potential around the PD 31 in the first configuration example of the solid-state imaging device 30. As shown in the figure, the charge saturated during the charge accumulation time in the PD 31 flows over the potential barrier portion 32 into the low-density OFD 33, and is further discharged into the high-density OFD 34.

[0024] <Manufacturing Method of the First Configuration Example of the Solid-State Imaging Device 30> Next, a description will be given of a manufacturing method for the first configuration example of the solid-state imaging element 30. Fig. 4 shows a manufacturing process for the first configuration example of the solid-state imaging element 30.

[0025] First, as shown in FIG. 1A, N-type ions are implanted into a thin silicon film (SOI) 41 to form a PD (charge retention portion) 31 and a low-concentration OFD 33. However, the PD 31 and the low-concentration OFD 33 are made of the same material, and at this stage the two are not distinguished but formed integrally. Next, as shown in FIG. 1B, P-type ions are implanted between the PD 31 and the low-concentration OFD 33 to form a potential barrier portion 32. The formation of the potential barrier portion 32 distinguishes the PD 31 from the low-concentration OFD 33.

[0026] Next, as shown in Fig. 1C, N-type ions are implanted so as to overlap the Si thin film 41 and the low-concentration OFD to form the high-concentration OFD 34. At this time, the high-concentration OFD 34 is formed so as to overlap the low-concentration OFD 33 and to contact the back surface side of the Si thin film 41 at a position spaced apart from the potential barrier portion 32. Note that the high-concentration OFD 34 may be formed before the potential barrier portion 32, and the potential barrier portion 32 may be formed after the high-concentration OFD 34 is formed.

[0027] Finally, as shown in D of the figure, Si is epitaxially grown from the Si thin film 41 to form a Si portion 42, and the vertical transistor 13, the FD 14, etc. are formed in the Si portion 42. Note that P-type ions may be implanted between the PD 31 and the rear surface of the Si thin film 41.

[0028] In the first configuration example of the solid-state imaging device 30 thus generated, when the charge generated in the PD 31 is read out, the charge is transferred to the FD 14 via the vertical transistor 13. Moreover, when the charge generated in the PD 31 is saturated, the saturated charge exceeds the potential barrier portion 32, flows into the low-density OFD 33, and is discharged to the high-density OFD 34.

[0029] In this way, in the first configuration example of the solid-state imaging element 30, the paths used when reading out charge and when discharging saturated charge are different, so that charge can be discharged more stably compared to, for example, a configuration in which charge is also discharged using the path used when reading charge from PD31.

[0030] Furthermore, in the first configuration example of the solid-state imaging element 30, the high-density OFD 34 is formed without being in direct contact with the potential barrier portion 32, and therefore it is possible to prevent the high-density OFD 34 from affecting the level of the potential of the potential barrier portion 32. This makes it possible to prevent a decrease in Qs and the occurrence of color mixing with adjacent pixels.

[0031] <Second configuration example of solid-state imaging device according to an embodiment of the present technology> Fig. 5 is a block cross-sectional view showing a second configuration example of a solid-state imaging device according to an embodiment of the present technology. Note that Fig. 5 shows one pixel, and components common to the first configuration example shown in Fig. 2 are given the same reference numerals, and therefore descriptions thereof will be omitted as appropriate.

[0032] The second configuration example of the solid-state imaging element 30 is a back-illuminated CIS like the first configuration example, but the high-concentration OFD 34 in the first configuration example is removed and instead a vertical transistor (VG) 51 and an OFD 52 are provided.

[0033] The vertical transistor 51 is formed in a position that is in contact with the low-concentration OFD 33 but is not in contact with the potential barrier portion 32, in a direction perpendicular to the Si substrate 11 (vertical direction). The vertical transistor 51 is fixed to a voltage higher than the potential generated in the PD 31 when charge is accumulated in the PD 31. The OFD 52 is formed on the front surface side of the Si substrate 11.

[0034] FIG. 6 shows the potential around the PD 31 in the second configuration example of the solid-state imaging device 30.

[0035] As shown in the figure, charges saturated during charge accumulation time in the PD 31 flow over the potential barrier portion 32 into the low-concentration OFD 33 and are further discharged to the OFD 52 via the vertical transistor 51 .

[0036] <Manufacturing Method of the Second Configuration Example of the Solid-State Imaging Device 30> Next, a description will be given of a manufacturing method for the second configuration example of the solid-state imaging element 30. Fig. 7 shows a manufacturing process for the second configuration example of the solid-state imaging element 30.

[0037] First, as shown in FIG. 1A, N-type ions are implanted into a thin silicon film (SOI) 41 to form a PD (charge retention portion) 31 and a low-concentration OFD 33. However, the PD 31 and the low-concentration OFD 33 are made of the same material, and at this stage the two are not distinguished but formed integrally. Next, as shown in FIG. 1B, P-type ions are implanted between the PD 31 and the low-concentration OFD 33 to form a potential barrier portion 32. The formation of the potential barrier portion 32 distinguishes the PD 31 from the low-concentration OFD 33.

[0038] Finally, as shown in Fig. 1C, Si is epitaxially grown from the Si thin film 41 to form the Si portion 42, and the vertical transistor 51, OFD 52, vertical transistor 13, FD 14, etc. are formed in the Si portion 42. Note that P-type ions may be implanted between the PD 31 and the rear surface of the Si thin film 41.

[0039] As described above, the second configuration example of the solid-state imaging device 30 can be manufactured with fewer steps than the first configuration example.

[0040] In the second configuration example of the solid-state imaging device 30 thus produced, when the charge generated in the PD 31 is read out, the charge is transferred to the FD 14 via the vertical transistor 13. When the charge generated in the PD 31 is saturated, the saturated charge exceeds the potential barrier portion 32, flows into the low-density OFD 33, and is discharged to the OFD 52 via the vertical transistor 51.

[0041] In this way, in the second configuration example of the solid-state imaging element 30, the paths used when reading out charge and when discharging saturated charge are different, so that charge can be discharged more stably compared to, for example, a configuration in which charge is also discharged using the path used when reading charge from PD31.

[0042] In the second configuration example of the solid-state imaging device 30, the vertical transistor 51 is formed without being in direct contact with the potential barrier portion 32, so that it is possible to prevent the voltage applied to the vertical transistor 51 from affecting the potential level of the potential barrier portion 32. This makes it possible to prevent a decrease in Qs and the occurrence of color mixing with adjacent pixels.

[0043] <Third configuration example of solid-state imaging device according to an embodiment of the present technology> Fig. 8 is a block cross-sectional view showing a third configuration example of a solid-state imaging device according to an embodiment of the present technology. Note that Fig. 8 shows one pixel, and components common to the first configuration example shown in Fig. 2 or the second configuration example shown in Fig. 5 are given the same reference numerals, and therefore descriptions thereof will be omitted as appropriate.

[0044] The third configuration example of the solid-state imaging device 30 is obtained by adding the vertical transistor 51 and OFD 52 of the second configuration example to the first configuration example. The vertical transistor 51 is connected to the high-density OFD .

[0045] In the third configuration example of the solid-state imaging device 30, when the charge generated in the PD 31 is read out, the charge is transferred to the FD 14 via the vertical transistor 13. Moreover, when the charge generated in the PD 31 is saturated, the saturated charge flows over the potential barrier portion 32 into the low-density OFD 33 and is discharged to the high-density OFD 34 or is discharged to the OFD 52 via the vertical transistor 51.

[0046] In this way, in the third configuration example of the solid-state imaging element 30, the paths used when reading out charge and when discharging saturated charge are different, so that charge can be discharged more stably compared to, for example, a configuration in which charge is also discharged using the path used when reading charge from PD31.

[0047] In addition, in the third configuration example of the solid-state imaging element 30, the high-concentration OFD 34 and the vertical transistor 51 are formed without being in direct contact with the potential barrier portion 32, so that it is possible to prevent them from affecting the potential level of the potential barrier portion 32. This makes it possible to prevent a decrease in Qs and the occurrence of color mixing with adjacent pixels.

[0048] <Method of fixing the potential of high-concentration OFD34> As described above, the high-concentration OFD 34, which is the destination of the saturated charge from PD 31, needs to be fixed at a voltage higher than the potential generated in PD 31 when charge is accumulated in PD 31. Therefore, when the electrode of the high-concentration OFD 34 is present on the back surface side of the Si substrate 11, a through electrode may be provided in the Si substrate 11 to electrically connect the power supply on the front surface side to the high-concentration OFD 34.

[0049] 9 shows a configuration example in which a through electrode is provided for each pixel. In this case, a high-voltage power supply 71 and the high-concentration OFD 34 are connected via a wiring 72, a through electrode 73, and a wiring 74, and the high-concentration OFD 34 is fixed to a high voltage.

[0050] 10 and 11 show configuration examples in which a through electrode is shared by multiple pixels, with Fig. 10 showing a cross-sectional view and Fig. 11 showing a top view. In this case, the area occupied by each pixel can be reduced by the area of ​​the through electrode 73, compared to the case in which a through electrode 73 is provided for each pixel.

[0051] <Potential Control of Potential Barrier Section 32> 12 shows an example of a configuration for controlling the potential of the potential barrier section 32. FIG. 12A shows an example of a configuration in which a gate electrode 81 is provided on the back side of the Si substrate 11 and connected to the potential barrier section 32. In this case, the potential of the potential barrier section 32 can be controlled by applying a predetermined voltage from the gate electrode 81. FIG. 12B shows an example of a configuration in which the Si substrate 11 is connected to the potential barrier section 32 provided with a vertical transistor 82 from the front side. In this case, the potential of the potential barrier section 32 can be controlled by applying a predetermined voltage from the vertical transistor 82.

[0052] <Modification of the first configuration example of the solid-state imaging device according to the embodiment of the present technology> Next, Fig. 13 and Fig. 14 show a configuration example in which the high-density OFD 34 is shared by a plurality of pixels as a modification (first modification) of the first configuration example of the solid-state imaging element shown in Fig. 2, with Fig. 13 showing a cross-sectional view and Fig. 14 showing a top view. Note that Fig. 14A and Fig. 14B show an example in which the high-density OFD 34 is shared by two pixels, and Fig. 14C shows an example in which the high-density OFD 34 is shared by four pixels.

[0053] By sharing the high-density OFD 34 among a plurality of adjacent pixels, the area occupied by the high-density OFD 34 in each pixel can be reduced compared to the case where a high-density OFD 34 is provided for each pixel.

[0054] FIG. 15 shows a cross-sectional view of a configuration example in which a PD 91 is additionally laminated within a Si substrate 11, as another modification (second modification) of the first configuration example of the solid-state imaging device.

[0055] As shown in the figure, when multiple PDs (pixel holding unit 31 and PD 91) are formed in the Si substrate 11, the PD 31 closer to the back surface mainly photoelectrically converts light on the short wavelength side, and the PD 91 farther away mainly photoelectrically converts light on the long wavelength side. Spectroscopic analysis is possible by photoelectrically converting light of different wavelengths using multiple PDs. Furthermore, by combining the outputs of multiple PDs, it is possible to increase Qs. Three or more layers of PDs may be formed in the Si substrate 11.

[0056] Figure 16 shows a cross-sectional view of a configuration example in which a photoelectric conversion film 92 such as an organic photoelectric conversion film is further added to the outside, away from the back surface of the Si substrate 11, in the second modification of Figure 15, as yet another modification (third modification) of the first configuration example of the solid-state imaging element.

[0057] As shown in the figure, when a photoelectric conversion film 92 is provided, the components photoelectrically converted by the photoelectric conversion film 92 can be extracted as output, and the light transmitted through the photoelectric conversion film 92 can be photoelectrically converted by each of the PDs 31 and 91. If multiple PDs 31 and 91 and the photoelectric conversion film 92 perform photoelectric conversion according to light of different wavelengths, it becomes possible to separate the light.

[0058] <Modification of the second configuration example of the solid-state imaging device according to the embodiment of the present technology> Next, FIG. 17 shows a modification (fourth modification) of the second configuration example of the solid-state imaging device shown in FIG.

[0059] In this fourth modified example, a photoelectric conversion film 101 such as an organic photoelectric conversion film is added to the outside away from the surface of the Si substrate 11, as compared to the second configuration example of Figure 5, and an FD 103 is added to the inside of the surface of the Si substrate 11 for storing charges generated by the photoelectric conversion film 101.

[0060] Furthermore, as a measure against dark current in the photoelectric conversion film 101, a GND terminal 105 is connected to the FD 103 via a RST transistor 104. The voltage of the GND terminal 105 is not limited to 0V, but may be any voltage lower than VDD. The same applies to other configuration examples and modified examples.

[0061] Furthermore, a drain layer 106 made of an N-type diffusion layer extending in the lateral direction is formed between the FD 103 and the GND terminal 105 and the charge holding unit 31 , and is connected to the vertical transistor 51 .

[0062] In the fourth modification, the drain layer 106 of the N-type diffusion layer is constantly turned on by the power from the vertical transistor 51 connected to the power source, so that the drain layer 106 functions as a drain for collecting charges leaking from the FD 103, the pixel transistor of the GND terminal 105, the P-type well contact 107, etc. This makes it possible to prevent the dark current of the charge holding unit 31 from deteriorating. In addition, the vertical transistor 51 to which power is supplied can be expected to act as a drain for collecting leaking charges, similar to the drain layer 106. If the vertical transistor 51 is also effective as a drain, the drain layer 106 may be omitted.

[0063] The above-mentioned fourth modified example can also be applied to the third configuration example shown in FIG.

[0064] <Another Modification of the Second Configuration Example of the Solid-State Imaging Device According to the Embodiment of the Present Technology> FIG. 18 shows another modification (fifth modification) of the second configuration example of the solid-state imaging device shown in FIG.

[0065] In this fifth modified example, a photoelectric conversion film 101 such as an organic photoelectric conversion film is added to the outside away from the surface of the Si substrate 11, as compared to the second configuration example in Figure 5, and an FD 103 is added to the inside of the surface of the Si substrate 11 for storing charges generated by the photoelectric conversion film 101.

[0066] Furthermore, as a measure against dark current in the photoelectric conversion film 101, a GND terminal 105 is connected to the FD 103 via a RST transistor 104.

[0067] In the fifth modified example, an AMP transistor 112 and a SEL transistor 113, which are omitted in the configuration examples and modified examples described up to this point, are illustrated.

[0068] In the fifth modification, insulating portions 111 and 114 are formed in a Si substrate 11 with an AMP transistor 112 and a SEL transistor 113 sandwiched therebetween.

[0069] In addition, a well isolation layer 115 made of an N-type diffusion layer extending in the horizontal direction is formed below the AMP transistor 112 and the SEL transistor 113. The well isolation layer 115 extends in the horizontal direction from the vertical transistor 51 and is also in contact with the insulating portions 111 and 114.

[0070] With this structure, the well region below the AMP transistor 112 and the SEL transistor 113 is electrically isolated from other regions (regions in which the RST transistor 104 that resets the FD 103 and the like are formed), and the potentials of both regions are different. In the case of the fifth modification, the potential of the regions below the AMP transistor 112 and the SEL transistor 113 is lower than that of the other well regions.

[0071] This allows the reset potential of the FD 103 to be set arbitrarily regardless of the input voltage of the AMP transistor 112, thereby making it possible to prevent degradation of imaging characteristics such as random noise and driving capability (gm) caused by the operating point of the AMP transistor 112.

[0072] When only the effect obtained by making the potentials of the region below the AMP transistor 112 and the SEL transistor 113 and the region where the RST transistor 104 and the like are formed different from each other is considered, the well isolation layer 115 does not have to be connected to the vertical transistor 51. In that case, the configuration examples shown in Figures 19 to 22 described below are possible.

[0073] 19, the well isolation layer 115 is extended from the N-type region 121 connected to the drain to below the AMP transistor 112 and the SEL transistor 113. In this case as well, the regions below the AMP transistor 112 and the SEL transistor 113 have a lower potential than the other well regions, and the above-mentioned effect can be obtained.

[0074] 20, by extending the well isolation layer 115 from the N-type region 121 connected to the drain to below the RST transistor 104, the region below the RST transistor 104 in the well region is electrically isolated from the other regions (regions in which the AMP transistor 112 and the SEL transistor 113, etc. are formed), and the potentials of both regions are different. In this case, the potential of the region below the RST transistor 104 is higher than that of the other well regions, and the above-mentioned effect can be obtained.

[0075] In addition, the fifth modified example shown in Figure 18 may be modified in the same manner as the configuration example in Figure 20, and a well isolation layer 115 extending from the vertical transistor 51 may be used to electrically isolate the region below the RST transistor 104 from other regions (regions in which the AMP transistor 112 and the SEL transistor 113, etc. are formed).

[0076] The configuration example shown in Fig. 21 is obtained by inverting the conductivity of each semiconductor in the configuration example shown in Fig. 20. In this case, the potential of the region below the RST transistor 104 becomes lower than the other well regions, and the above-mentioned effect can be obtained.

[0077] 22, the AMP transistor 112 and the SEL transistor 113 are formed of PMOS, and the lower part thereof is formed of an N-type well region. This electrically separates the lower region of the AMP transistor 112 and the SEL transistor 113 from the other region in which the RST transistor 104 and the like are formed, and makes the potentials of the two regions different, without forming a well isolation layer 115. In this case, the lower region of the AMP transistor 112 and the SEL transistor 113 has a higher potential than the other well regions, and the above-mentioned effect can be obtained.

[0078] <Still another modification of the second configuration example of the solid-state imaging device according to the embodiment of the present technology> Next, Fig. 23 shows yet another modified example (sixth modified example) of the second configuration example of the solid-state imaging element shown in Fig. 5. Specifically, this is a combination of the fourth modified example shown in Fig. 17 and the fifth modified example shown in Fig. 18. Fig. 24 is a top view of the sixth modified example shown in Fig. 23.

[0079] In the sixth modification, the drain layer 106 is constantly turned on by the power from the vertical transistor 51 connected to the power supply, so that the drain layer 106 functions as a drain for collecting charges leaking from the FD 103 and the GND terminal 105. This makes it possible to prevent the dark current of the charge holding unit 31 from deteriorating.

[0080] In addition, the well isolation layer 115 electrically separates the region below the AMP transistor 112 and the SEL transistor 113 from the other region in the well region, and the potentials of the two regions are different. This allows the reset potential of the FD 103 to be set arbitrarily regardless of the input voltage of the AMP transistor 112, so that deterioration of imaging characteristics such as random noise and driving capability (gm) caused by the operating point of the AMP transistor 112 can be suppressed.

[0081] The sixth modified example described above can also be applied to the third configuration example shown in FIG.

[0082] Next, Fig. 25 shows a top view of a configuration example in which the vertical transistor 51 in the sixth modification shown in Fig. 23 is shared by multiple pixels. In this case, the area occupied by each pixel can be reduced compared to the case in which the vertical transistor 51 is provided for each pixel.

[0083] <Example of use of solid-state imaging element 30> FIG. 26 shows an example of use of a solid-state imaging device 30 according to an embodiment of the present technology.

[0084] The solid-state imaging element 30 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.

[0085] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as on-board sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving (such as automatic stopping) and for recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles, etc. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication - Cosmetic devices such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports use Agricultural equipment such as cameras for monitoring fields and crop conditions

[0086] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0087] The present technology can also be configured as follows. (1) a charge holding section that generates and holds charges in response to incident light; an OFD section for discharging the charge saturated in the charge retention section; a potential barrier portion that serves as a barrier for the charge flowing from the charge retention portion to the OFD portion; on the light receiving surface side of a semiconductor substrate, The OFD section includes a low-concentration OFD section and a high-concentration OFD section having different concentrations of the same type of impurity, The high-concentration OFD portion and the potential barrier portion are formed with a gap therebetween. Solid-state imaging element. (2) The charge retention portion and the low-concentration OFD portion have the same concentration of impurities. The solid-state imaging device according to (1) above. (3) a first vertical transistor formed on a surface of the semiconductor substrate opposite to the light receiving surface and in contact with the high concentration OFD portion; The solid-state imaging device according to (1) or (2). (4) The first vertical transistor and the potential barrier portion are formed with a gap therebetween. The solid-state imaging device according to (3) above. (5) The pixel transistor is formed on the semiconductor substrate. The pixel transistor is disposed between the charge storage portion and the charge storage portion. The pixel transistor is disposed on the semiconductor substrate. The charge storage portion is disposed on the charge storage portion. The solid-state imaging device according to (3) above. (6) The drain layer is formed of a diffusion layer of the same type of impurity as the charge storage portion. The solid-state imaging device according to (5) above. (7) The semiconductor device further includes a well isolation layer extending laterally from the first vertical transistor, electrically isolating a lower region of a predetermined pixel transistor from other regions in the well region of the semiconductor substrate. The solid-state imaging device according to any one of (3) to (6). (8) The potential of the lower region of the specific pixel transistor, which is electrically isolated by the well isolation layer, is lower than the potential of the other regions. The solid-state imaging device according to (7) above. (9) The predetermined pixel transistor is an AMP transistor and a SEL transistor. The solid-state imaging device according to (7) or (8). (10) The RST potential, which is the input voltage of the AMP transistor as the predetermined pixel transistor, is lower than the drain voltage of the AMP transistor. The solid-state imaging device according to (9) above. (11) The predetermined pixel transistor is a RST transistor. The solid-state imaging device according to (7) above. (12) a second vertical transistor formed on a surface of the semiconductor substrate opposite to the light receiving surface and configured to read out the charge from the charge storage portion; The solid-state imaging device according to any one of (1) to (11) above. (13) A voltage higher than a voltage generated in the charge storage portion when charges are accumulated in the charge storage portion is applied to the high-concentration OFD portion. The solid-state imaging device according to any one of (1) to (12). (14) A voltage higher than a voltage generated in the charge retention portion when charge is accumulated in the charge retention portion is applied to the high-concentration OFD portion, the voltage being supplied from a surface of the semiconductor substrate opposite to the light-receiving surface via a through electrode penetrating the semiconductor substrate. The solid-state imaging device according to any one of (1) to (13). (15) The through electrode is provided for each of a plurality of pixels and is shared by the plurality of pixels. The solid-state imaging device according to (14) above. (16) A control unit for controlling the potential of the potential barrier unit is further provided. The solid-state imaging device according to any one of (1) to (15). (17) The high-density OFD portion is shared by the plurality of pixels. The solid-state imaging device according to any one of (1) to (16). (18) The charge retention portion is formed in a plurality of layers in the semiconductor substrate. The solid-state imaging device according to any one of (1) to (17). (19) A photoelectric conversion film formed on the outer side of the light receiving surface of the semiconductor substrate. The solid-state imaging device according to any one of (1) to (18) further comprises: (20) In an electronic device equipped with a solid-state imaging device, The solid-state imaging device includes: a charge holding section that generates and holds charges in response to incident light; an OFD section for discharging the charge saturated in the charge retention section; a potential barrier portion that serves as a barrier for the charge flowing from the charge retention portion to the OFD portion; on the light receiving surface side of a semiconductor substrate, The OFD section includes a low-concentration OFD section and a high-concentration OFD section having different concentrations of the same type of impurity, The high-concentration OFD portion and the potential barrier portion are formed with a gap therebetween. electronic equipment. [Explanation of symbols]

[0088] 30 solid-state imaging element, 31 charge retention section, 32 potential barrier section, 33 low-concentration OFD, 34 high-concentration OFD, 51 vertical transistor, 52 OFD, 71 power supply, 73 through electrode, 81 gate electrode, 82 vertical transistor, 91 PD, 92 photoelectric conversion film, 101 photoelectric conversion film, 106 drain layer, 115 well isolation layer

Claims

1. a charge holding section that generates and holds charges in response to incident light; an OFD section for discharging the charge saturated in the charge retention section; a potential barrier portion that serves as a barrier for the charge flowing from the charge retention portion to the OFD portion; in a semiconductor substrate, a first vertical transistor formed on a surface of the semiconductor substrate opposite to the light receiving surface and overlapping the OFD section in a plan view, the first vertical transistor being for discharging the charge from the OFD section; Light detection element.

2. The OFD section includes a low-concentration OFD section and a high-concentration OFD section having different concentrations of the same type of impurity, The high-concentration OFD portion and the potential barrier portion are formed with a gap therebetween. The photodetector element according to claim 1 .

3. The charge retention portion and the low-concentration OFD portion have the same concentration of impurities. The photodetector element according to claim 2 .

4. The first vertical transistor and the potential barrier portion are formed with a gap therebetween. The photodetector element according to claim 1 .

5. a drain layer extending laterally from the first vertical transistor between the pixel transistor formed on the semiconductor substrate and the charge storage portion; The photodetector element according to claim 1 .

6. The drain layer is formed of a diffusion layer of the same type of impurity as the charge storage portion. The photodetector element according to claim 5 .

7. The semiconductor device further includes a well isolation layer extending in a lateral direction from the first vertical transistor, electrically isolating a lower region of a predetermined pixel transistor from other regions in the well region of the semiconductor substrate. The photodetector element according to claim 1 .

8. The potential of the lower region of the specific pixel transistor, which is electrically isolated by the well isolation layer, is lower than the potential of the other regions. The photodetector element according to claim 7 .

9. The predetermined pixel transistor is an AMP transistor and a SEL transistor. The photodetector element according to claim 7 .

10. The RST potential, which is the input voltage of the AMP transistor as the predetermined pixel transistor, is lower than the drain voltage of the AMP transistor. The light detection element according to claim 9.

11. The predetermined pixel transistor is a RST transistor. The photodetector element according to claim 7 .

12. a second vertical transistor formed on a surface of the semiconductor substrate opposite to the light receiving surface and configured to read out the charge from the charge storage portion; The photodetector element according to claim 3 .

13. A voltage higher than a voltage generated in the charge storage portion when charges are accumulated in the charge storage portion is applied to the high-concentration OFD portion. The photodetector element according to claim 3 .

14. A control unit for controlling the potential of the potential barrier unit is further provided. The photodetector element according to claim 3 .

15. The high-density OFD portion is shared by multiple pixels. The photodetector element according to claim 3 .

16. The charge retention portion is formed in a plurality of layers in the semiconductor substrate. The photodetector element according to claim 3 .

17. A photoelectric conversion film formed on the outer side of the light receiving surface of the semiconductor substrate. The light detection element according to claim 3 further comprising:

18. In an electronic device equipped with a photodetector element, The photodetector element is a charge holding section that generates and holds charges in response to incident light; an OFD section for discharging the charge saturated in the charge retention section; a potential barrier portion that serves as a barrier for the charge flowing from the charge retention portion to the OFD portion; in a semiconductor substrate, a first vertical transistor formed on a surface of the semiconductor substrate opposite to the light receiving surface and overlapping the OFD section in a plan view, the first vertical transistor being for discharging the charge from the OFD section; electronic equipment.

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