Enterprise Host Memory Buffer

Abstract

The storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex / port, and a DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data in DRAM of the DRAM pool of the controller unit.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Non-provisional Application No. 17 / 543,473, entitled "Enterprise Host Memory Buffer," filed on December 6, 2021, the entire contents of which are incorporated by reference into this application for all purposes. [Background technology]

[0002] Technical Field TECHNICAL FIELD Embodiments of the present disclosure relate generally to data storage devices such as solid state drives (SSDs), and more specifically to using an external storage device via an interface between a data storage device and a host device.

[0003] 2. Description of Related Art Enterprise SSDs have certain requirements for integration into data center environments. For example, the requirements may include predictability and low latency of read operations, as well as maintaining the same level of quality of service (QoS) for reads from any part of the SSD's logical address range. Due to the requirements, the logical block address (LBA) to physical block address (PBA) (L2P) table may be stored in DRAM, where the DRAM capacity may be in a ratio of 1:1000 (e.g., 2TB SSD=2GB DRAM for L2P table caching). In some implementations, the ratio may be larger (e.g., 1:2000) at the expense of performance due to increased indirection. Thus, as the capacity of SSDs increases, the amount of DRAM included in the SSD may also increase, increasing the cost of the SSD.

[0004] Data storage devices for enterprise storage systems may be rated based on the drive writes per day (DWPD) over the life of the drive. Customers may choose to exceed the DWPD of a data storage device at the expense of wearing out the device faster. Thus, the cost of a data storage device is translated into the number of write cycles (e.g., program erase cycles (PEC)). Because DRAM does not wear out at the same rate as non-volatile memory such as NAND memory, large capacity data storage devices may have uneven memory usage such that non-volatile memory can be retired from use before DRAM needs to be retired from use.

[0005] Therefore, there is a need in the art for improved storage systems for better integration into data center environments. Summary of the Invention

[0006] The present disclosure relates generally to data storage devices such as solid state drives (SSDs), and more specifically to using an external storage device via an interface between the data storage device and a host device. The storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex / port, and a DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data in the DRAM of the DRAM pool of the controller unit.

[0007] In one embodiment, a storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch, the controller unit including a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool, the DRAM pool including one or more DRAM devices.

[0008] In another embodiment, a storage system includes a first data storage device, a second data storage device, a PCIe switch coupled to the first data storage device and the second data storage device, and a controller unit coupled to the first data storage device and the second data storage device, the controller unit including a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool, the DRAM pool including one or more DRAM devices.

[0009] In another embodiment, a storage system includes a first data storage device comprising a first memory means, a second data storage device comprising a second memory means, a PCIe switch coupled to the first data storage device and the second data storage device, and a controller unit coupled to the first data storage device and the second data storage device, the controller unit including a controller memory buffer (CMB) controller and a root complex / port. [Brief description of the drawings]

[0010] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, as the present disclosure may admit of other equally effective embodiments.

[0011] [Figure 1] 1 is a schematic block diagram illustrating a storage system in which a data storage device can function as a storage device for a host device, according to certain embodiments. [Diagram 2] 1 is a schematic block diagram illustrating a storage system in which an external controller unit can function as a storage device for a data storage device, according to certain embodiments. [Diagram 3] FIG. 2 is a schematic block diagram illustrating a storage system in which an external controller unit can function as a storage device for a first data storage device and a second data storage device, according to certain embodiments. [Figure 4] FIG. 2 is a schematic block diagram illustrating a storage system in which an external controller unit can function as a storage device for a first data storage device and a second data storage device, according to certain embodiments. [Diagram 5] FIG. 11 is a flow diagram illustrating a method for storing data in an external controller unit, according to certain embodiments. [Figure 6] FIG. 11 is a flow diagram illustrating a method for reading data from an external controller unit, according to certain embodiments.

[0012] To facilitate understanding, the same reference numbers have been used, whenever possible, to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific mention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the following, reference will be made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Instead, any combination of the following features and elements, whether associated with different embodiments or not, is contemplated to implement and practice the present disclosure. Furthermore, although embodiments of the present disclosure may achieve advantages over other possible solutions and / or over the prior art, whether or not a particular advantage is achieved by a given embodiment does not limit the present disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not considered elements or limitations of the appended claims unless expressly recited in the claim(s). Similarly, references to "the present disclosure" are not to be construed as a generalization of any inventive subject matter disclosed herein, and should not be considered elements or limitations of the appended claims unless expressly recited in the claims.

[0014] The present disclosure relates generally to data storage devices such as solid state drives (SSDs), and more specifically to using an external storage device via an interface between the data storage device and a host device. The storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex / port, and a DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data in the DRAM of the DRAM pool of the controller unit.

[0015] 1 is a schematic block diagram illustrating a storage system 100 in which a host device 104 communicates with a data storage device 106, according to certain embodiments. For example, the host device 104 may utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some implementations, the storage system 100 may include multiple storage devices, such as the data storage device 106, that may operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a Redundant Array of Inexpensive / Independent Disks (RAID) that collectively function as a mass storage device for the host device 104.

[0016] The host device 104 may store and / or retrieve data to and / or from one or more storage devices, such as the data storage device 106. As illustrated in Figure 1, the host device 104 may communicate with the data storage device 106 via an interface 114. The host device 104 may comprise any of a wide range of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone such as a so-called "smart" phone, a so-called "smart" pad, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other device capable of transmitting or receiving data from a data storage device, etc.

[0017] Data storage device 106 includes controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, and write buffer 116. In some embodiments, data storage device 106 may include additional components not shown in FIG. 1 for clarity. For example, data storage device 106 may include a printed circuit board (PCB) to which components such as data storage device 106 are mechanically attached and which includes conductive traces that electrically interconnect the components of data storage device 106. In some embodiments, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, Peripheral Component Interconnect (PCI), PCI Expansion (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, Mini PCI, etc.). In some embodiments, the data storage device 106 may be directly coupled to the motherboard of the host device 104 (e.g., soldered or plugged directly into a connector).

[0018] The interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: PCI, PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. It should be understood that other protocols not listed may be applicable to the embodiments described herein. The interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108 and provides an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, as illustrated in FIG. 1, power supply 111 may receive power from host device 104 via interface 114.

[0019] NVM 110 may include multiple memory devices or memory units. NVM 110 may be configured to store and / or retrieve data. For example, a memory unit of NVM 110 may receive data and a message from controller 108 instructing the memory unit to store the data. Similarly, a memory unit may receive a message from controller 108 instructing the memory unit to retrieve data. In some embodiments, each of the memory units may be referred to as a die. In some embodiments, NVM 110 may include multiple dies (i.e., multiple memory units). In some embodiments, each memory unit may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0020] In some embodiments, each memory unit may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0021] NVM 110 may include multiple flash memory devices or memory units. NVM flash memory devices may include NAND or NOR based flash memory devices and may store data based on the charge contained in the floating gate of the transistor of each flash memory cell. In an NVM flash memory device, the flash memory device may be divided into multiple dies, each of the multiple dies may include multiple physical or logical blocks, and the multiple physical or logical blocks may be further divided into multiple pages. Each of the multiple blocks in a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define each of the multiple pages. Each cell in each of the multiple pages may be electrically connected to a respective bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). Controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.

[0022] The power source 111 may provide power to one or more components of the data storage device 106. When operating in a standard mode, the power source 111 may provide power to one or more components using power provided by an external device, such as the host device 104. For example, the power source 111 may provide power to one or more components using power received from the host device 104 via the interface 114. In some embodiments, the power source 111 may include one or more power storage components configured to provide power to one or more components when operating in a shutdown mode, such as when the power source 111 stops receiving power from an external device. In this manner, the power source 111 may function as an on-board power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some embodiments, the amount of power that may be stored by the one or more power storage components may be a function of the cost and / or size (e.g., area / volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0023] The volatile memory 112 may be used by the controller 108 to store information. The volatile memory 112 may include one or more volatile memory devices. In some embodiments, the controller 108 may use the volatile memory 112 as a cache. For example, the controller 108 may store cached information in the volatile memory 112 until the cached information is written to the NVM 110. As illustrated in FIG. 1, the volatile memory 112 may consume power received from the power source 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0024] The controller 108 may manage one or more operations of the data storage device 106. For example, the controller 108 may manage reading data from and / or writing data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate the data storage command, store the data in the NVM 110, and monitor the progress of the data storage command. The controller 108 may determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0025] 2 is a schematic block diagram illustrating a storage system 200 in which a controller unit 206 may function as a storage device for a data storage device 212, according to certain embodiments. The data storage device 212 may be the data storage device 106 of FIG. 1. The storage system 200 includes a host device 202 coupled to a PCIe switch 204. The PCIe switch 204 is coupled to the controller unit 206 and the data storage device 212. The PCIe switch 204 may have two or more ports such that two or more data storage devices may be connected to the PCIe switch 204.

[0026] The controller unit 206 includes a DRAM host memory buffer (HMB) controller 208 and a DRAM pool 210. In some embodiments, the DRAM pool 210 may be similar to an HMB. The controller unit 206 may be a simplified version of the data storage device 212, where the controller unit 206 is separate from the data storage device 212. The DRAM pool 210 includes one or more DRAM devices. In some embodiments, the DRAM pool 210 may be any pool of volatile memory devices.

[0027] In some embodiments, the controller unit 206 may further include an NVM device. When power failure protection is required, the controller unit 206 may flush data stored in the DRAM pool 210 to the NVM device. In other embodiments, the controller unit 206 may flush data stored in the DRAM pool 210 to the memory device 222 of the data storage device 212. The DRAM HMB controller 208 may be responsible for allocating one or more DRAM devices from the DRAM pool 210 to the data storage device 212, as well as writing data to and reading data from one or more DRAM devices of the DRAM pool 210.

[0028] The data storage device 212 includes an HMB controller 214, a PCIe / NVMe front end (FE) 216, a memory device management unit 218, a memory device interface unit 220, and a memory device 222, which may be a pool of memory devices. The memory device 222 may be an NVM device. When the host device 202 sends a write command to the data storage device 212, the PCIe / NVMe FE 216 receives the write command. The PCIe / NVMe FE 216 may process the write command, which may include generating and encoding an error correction code for the data of the write command. The memory device management unit 218 may schedule a write command to program data to the memory device 222 and a read command to read data from the memory device 222. The memory device interface unit 220 may access the memory device 222 to program data to or read data from the memory device 222.

[0029] Once data is programmed into memory device 222, the LBA to PBA mapping of the data may be stored in an L2P table. Controller unit 206 may appear as a peer PCIe device to data storage device 212 and may be addressed using standard PCIe methods. Thus, HMB controller 214 may access controller unit 206 as an external storage device to store and retrieve L2P descriptors. For example, the L2P table for data storage device 212 may be stored in a DRAM device of DRAM pool 210 rather than in a DRAM device of data storage device 212.

[0030] 3 is a schematic block diagram illustrating a storage system 300 in which a controller unit 322 may function as a storage device for a first data storage device 306a and a second data storage device 306b, according to certain embodiments. Aspects of the storage system 300 may be similar to the storage system 200 of FIG. 2. It should be understood that one or more data storage devices may be coupled to the PCIe switch 304 and the controller unit 322.

[0031] The host device 302 is coupled to a PCIe switch 304. The first data storage device 306a and the second data storage device 306b each include a first port 308, a second port 310, an HMB controller 312, a PCIe / NVMe FE 314, a memory device management unit 316, a memory device interface unit 318, and a memory device 320, which may be a pool of memory devices. The memory device 222 may be an NVM device.

[0032] The controller unit 322 includes a DRAM HMB controller 326 and a DRAM pool 324. In some embodiments, the DRAM pool 324 may be similar to an HMB. The controller unit 322 may be a simplified version of the first data storage device 306a and the second data storage device 306b. The DRAM pool 324 includes one or more DRAM devices. In some embodiments, the DRAM pool 324 may be any pool of volatile memory devices (e.g., SRAM, DRAM, or both). In some embodiments, the controller unit 322 may further include an NVM device.

[0033] The first port 308 may be coupled to the PCIe switch 304 for interaction with the host device 302. The second ports 310 of the first data storage device 306a and the second data storage device 306b may be used for redundancy (in case the first port 308 fails) or, in some embodiments, may be connected to a DRAM HMB controller 326 of the controller unit 322. The DRAM HMB controller 326 may act as a root complex for one or more data storage devices. It should be understood that a data storage device may have more than two ports.

[0034] When the second port 310 is coupled to the controller unit 322 by using the DRAM pool 324 of the controller unit 322 as an external memory device, latency may be kept consistent since the second port may be used for read and write commands directed to the controller unit 322. Similarly, PCIe-based prioritization in the PCIe switch 304 may be used to ensure that access to the DRAM pool 324 is prioritized higher than normal data throughput to ensure consistent read access to the L2P entries stored in the DRAM pool 324.

[0035] If power failure protection is required, the controller unit 322 may flush data stored in the DRAM pool 324 to an NVM device. In other embodiments, the controller unit 206 may flush data stored in the DRAM pool 324 to the memory devices 320 of either the first data storage device 306a, the second data storage device 306b, or both the first data storage device 306a and the second data storage device 306b. The DRAM HMB controller 326 may be responsible for allocating DRAM devices of the DRAM pool 324 from the DRAM pool to the first data storage device 306a and the second data storage device 306b, as well as writing data to and reading data from one or more DRAM devices of the DRAM pool 324.

[0036] 4 is a schematic block diagram illustrating a storage system 400 in which a controller unit 402 may function as a storage device for a first data storage device 306a and a second data storage device 306b, according to certain embodiments. Aspects of the storage system 400 may be similar to the storage system 300 of FIG. 3. For simplicity, common elements between the storage system 400 and the storage system 300 may have the same or similar reference numbers.

[0037] Rather than using an HMB controller in the controller unit 402, the controller unit 402 uses a controller memory buffer (CMB) controller 406. The controller unit 402 includes a root complex / port 1 404 that may be connectable to multiple data storage devices, a CMB controller 406 coupled to a DRAM pool 408, a PCIe / NVMe FE 410, a memory device management unit 412, and a memory device interface unit 414. In some embodiments, the controller unit 402 may be a data storage device that does not include an NVM device. In other embodiments, the controller unit 402 may be a data storage device that is reused as a shared DRAM interface. In some embodiments, the interconnect to the DRAM pool 408 uses a Compute Express link that allows cache coherent access between multiple processing devices that use PCIe as an interconnect. Thus, the controller unit 402 may be a CXL memory device.

[0038] 5 is a flow diagram illustrating a method 500 for storing data in a controller unit, according to certain embodiments. The method 500 may be used by any of the storage systems 200, 300, 400 described above. For illustrative purposes, reference may be made to aspects of the storage system 200. In block 502, a controller of the data storage device 212, such as the HMB controller 214, determines that an external controller unit, such as the controller unit 206, is connected to the data storage device 212. The connection may be a direct connection or an indirect connection.

[0039] At block 504, HMB controller 214 receives a DRAM allocation from DRAM pool 210. For example, DRAM HMB controller 208 may allocate one or more DRAM devices from DRAM pool 210 for use by data storage device 212. At block 506, HMB controller 214 determines that a write to a DRAM device is required. This determination may be due to a write to memory device 222, a data management operation to memory device 222 such as garbage collection, etc. Thus, the mapping (LBA to PBA) may change, so the corresponding L2P entry in the corresponding L2P table needs to be updated. At block 508, HMB controller 214 sends a write command to DRAM HMB controller 208 to write the data to the allocated DRAM from DRAM pool 210 instead of using the DRAM of data storage device 212. Thus, the L2P table may be maintained externally, such as in the DRAM of DRAM pool 210.

[0040] 6 is a flow diagram illustrating a method 600 for reading data from a controller unit, according to certain embodiments. The method 600 may be used by any of the storage systems 200, 300, 400 described above. For purposes of illustration, reference may be made to aspects of the storage system 200. At block 602, a controller of the data storage device 212, such as the HMB controller 214, receives a read command from the host device 202 for data stored in the memory device 222.

[0041] At block 604, the HMB controller 214 finds an L2P table in the controller unit 206 that corresponds to the data storage device 212. At block 606, the HMB controller 214 sends a read command to the DRAM HMB controller 208 to retrieve data corresponding to the read command from the L2P table. At block 608, the data is read from the memory device 222 using the retrieved L2P table information and the data is delivered to the host device 202.

[0042] By having a storage system that includes an external controller unit or storage device for use as a volatile memory pool for one or more data storage devices, the cost of the one or more data storage devices may be reduced due to the reduced volatile memory requirements of the one or more data storage devices.

[0043] In one embodiment, a storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch, the controller unit including a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool, the DRAM pool including one or more DRAM devices.

[0044] The PCIe switch is directly coupled to the DRAM HMB controller. Each data storage device of the one or more data storage devices includes an HMB controller, a PCIe / NVMe front-end unit, a memory device management unit, a memory device interface unit, and a memory device. The controller unit serves as a root complex for the one or more data storage devices. The one or more data storage devices are separate from the controller unit. The controller unit appears to the one or more data storage devices as a peer PCIe device. The DRAM pool is shared by the one or more data storage devices. The one or more data storage devices are two or more data storage devices. Each data storage device of the one or more data storage devices includes a first port and a second port. The first port is coupled to the PCIe switch.

[0045] In another embodiment, a storage system includes a first data storage device, a second data storage device, a PCIe switch coupled to the first data storage device and the second data storage device, and a controller unit coupled to the first data storage device and the second data storage device, the controller unit including a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool, the DRAM pool including one or more DRAM devices.

[0046] The first data storage device and the second data storage device each have a first port and a second port. The first port is coupled to a PCIe switch. The second port is coupled to a controller unit. The second port is coupled to an HMB controller. The HMB controller is disposed in the first data storage device and the second data storage device. The second port is coupled to a DRAM HMB controller. The controller unit is configured to push data in the DRAM pool to either the first data storage device, the second data storage device, or both the first data storage device and the data storage device upon detecting a power failure event of the controller unit.

[0047] In another embodiment, a storage system includes a first data storage device comprising a first memory means, a second data storage device comprising a second memory means, a PCIe switch coupled to the first data storage device and the second data storage device, and a controller unit coupled to the first data storage device and the second data storage device, the controller unit including a controller memory buffer (CMB) controller and a root complex / port.

[0048] The first data storage device, the second data storage device and the controller unit each include a memory means interface, a memory means management unit and a PCIe / NVMe front-end unit. The first data storage device and the second data storage device each include a first port and a second port. The first port is coupled to the PCIe switch. The second port is coupled to the root complex / port. The CMB controller is coupled to the DRAM pool.

[0049] While the above is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the following claims.

Claims

1. 1. A storage system comprising: a first data storage device; A second data storage device; and a PCIe switch coupled to the first data storage device and the second data storage device; a controller unit coupled to the first data storage device and the second data storage device; the controller unit is a data storage device separate from the first data storage device and the second data storage device; The controller unit: a dynamic random access memory (DRAM) HMB controller for controlling one or more DRAM devices of said controller unit separate from a host memory buffer (HMB) of a host device; a DRAM pool; the DRAM pool comprises the one or more DRAM devices provided in the controller unit; each of the one or more DRAM devices being assigned by the DRAM HMB controller to the first data storage device and the second data storage device for use by the first data storage device and the second data storage device; the first data storage device and the second data storage device each have a first port and a second port, the first port being coupled to the PCIe switch; The second port is coupled to the controller unit.

2. 2. The storage system of claim 1, wherein the second port is coupled to an HMB controller.

3. The storage system of claim 2 , wherein the HMB controller is disposed within the first data storage device and the second data storage device.

4. 2. The storage system of claim 1, wherein the second port is coupled to the DRAM HMB controller.

5. 2. The storage system of claim 1, wherein the controller unit is configured to push data in the DRAM pool to either the first data storage device, the second data storage device, or both the first data storage device and the data storage device upon detecting a power failure event of the controller unit.

6. 1. A storage system comprising: a first data storage device comprising a first memory means; a second data storage device comprising a second memory means; a PCIe switch coupled to the first data storage device and the second data storage device; a controller unit coupled to the first data storage device and the second data storage device; the controller unit is a data storage device separate from the first data storage device and the second data storage device; The controller unit: a controller memory buffer (CMB) controller for controlling one or more dynamic random access memory (DRAM) devices of said controller unit separate from a host memory buffer (HMB) of a host device; A root complex / port; a DRAM pool; the DRAM pool comprises the one or more DRAM devices provided in the controller unit; each of the one or more DRAM devices is assigned by the CMB controller to the first data storage device and the second data storage device for use by the first data storage device and the second data storage device; a first data storage device and a second data storage device each comprising a first port and a second port, the first port being coupled to the PCIe switch and the second port being coupled to the root complex / port;

7. the first data storage device, the second data storage device, and the controller unit each include: a memory means interface; a memory means management unit; The storage system of claim 6, further comprising a PCIe / NVMe front-end unit.

8. 7. The storage system of claim 6, wherein said CMB controller is coupled to said DRAM pool.

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