Method for manufacturing back-illuminated CMOS sensor, method for manufacturing electron-bombarded CMOS sensor, pixel for back-illuminated CMOS sensor, and electron-bombarded CMOS sensor

Abstract

To provide manufacturing methods of a back-illuminated CMOS sensor and an electronic impact CMOS sensor, which can suppress an increase in deviation and variation in characteristics of an analog circuit formed on the surface.SOLUTION: A manufacturing methods of a back-illuminated CMOS sensor includes a forming step of forming an N-shaped light receiving portion 50 inside a silicon substrate 305, an injection step of injecting ions that form a P+ diffusion layer 270 on the back surface of the silicon substrate 305, and an irradiation step of irradiating with the laser from the back side to activate the injected ions. The irradiation with the laser is performed excluding a region on the front surface of the back-illuminated CMOS sensor where an analog circuit such as an AD converter connected to a pixel is formed.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a back-illuminated CMOS sensor, a method for manufacturing an electron bombarded CMOS sensor, a pixel for a back-illuminated CMOS sensor, and an electron bombarded CMOS sensor. [Background technology]

[0002] The following patent documents disclose back-illuminated CMOS sensors and methods for manufacturing back-illuminated CMOS sensors. For example, Patent Document 1 (JP 2003-031785 A) discloses the following XY-address type solid-state imaging element and its manufacturing method as a solution to the problem that in a pixel structure in which incident light is captured by a photodiode through a wiring layer, part of the light focused by a microlens is reflected by the wiring. The solid-state imaging element described in Patent Document 1 is an XY-address type solid-state imaging element in which unit pixels including active elements that convert signal charges photoelectrically converted by a photoelectric conversion element into an electrical signal and output it are arranged in a matrix, and has a wiring layer that provides wiring to the active elements on one side of the element layer in which the photoelectric conversion elements are formed, and incident light is taken into the photoelectric conversion elements from the other side of the element layer.

[0003] Moreover, Patent Document 2 (JP 2019-176089 A) discloses a solid-state imaging device that increases the degree of freedom regarding the arrangement of transistors. The solid-state imaging device described in Patent Document 2 includes a photoelectric conversion unit that performs photoelectric conversion, a trench that penetrates a semiconductor substrate in the depth direction and is formed between the photoelectric conversion units that are formed in adjacent pixels, and a PN junction region composed of a P-type region and an N-type region on the side wall of the trench, and includes a region in which the P-type region is not formed or a region in which the P-type region is thinly formed on some of the sides surrounding the photoelectric conversion unit. The PN junction region is formed on at least one of the four sides surrounding the photoelectric conversion unit, and no P-type region is formed on the remaining sides.

[0004] Moreover, Patent Document 3 (JP 2015-88568 A) discloses a solid-state imaging device capable of suppressing the generation of dark current and a method for manufacturing the solid-state imaging device. The solid-state imaging device described in Patent Document 3 includes a photoelectric conversion element, a trench, and a semiconductor region of a first conductivity type. The photoelectric conversion elements are formed by a semiconductor layer of a first conductivity type and semiconductor regions of a second conductivity type arranged two-dimensionally in a matrix in the semiconductor layer, and photoelectrically convert incident light into electric charges and store the electric charges. The trench is formed between adjacent photoelectric conversion elements and is formed from the surface of the semiconductor layer of the first conductivity type toward the depth direction. The semiconductor region of the first conductivity type is provided so as to surround the outer circumferential surface of the trench, and contains activated impurities of the first conductivity type.

[0005] Moreover, Patent Document 4 (JP 2015-164194 A) discloses a laser annealing system and method for annealing a semiconductor wafer with a very short dwell time. In the laser annealing system described in Patent Document 4, the annealing laser beam is scanned at a speed that allows the dwell time to be within a range of about 1 μs to about 100 μs. These very short dwell times make it difficult for the device side of the device wafer to be damaged by heating during the annealing process when annealing a product wafer formed from a thin device wafer.

[0006] The following inventions have been disclosed regarding electron bombarded CMOS sensors. Patent Document 5 (JP Patent Publication No. 2012-511711) discloses a processing method for a single-photon sensitive sensor and an apparatus using the same. The photon detection device described in Patent Document 5 comprises a sensor including a vacuum chamber, a photocathode arranged in the vacuum chamber and designed to convert photons into primary electrons, a converter for converting at least a part of the energy of the accelerated primary electrons into secondary charges which are collected by a number of detection cells, an acquisition circuit configured to read out the charges collected by the detection cells together with an integration time making it possible to obtain a collision density per unit time and per unit area of ​​the cells of the order of a single electron, means for identifying a cluster of adjacent detection cells, at least one of which is a so-called main cell having a collected charge amount greater than a threshold value, means for determining at least one characteristic of the cluster, means for storing at least one characteristic of a reference cluster resulting from the conversion of primary electrons, and means for comparing the determined characteristics of the cluster with the stored characteristics of the reference cluster in order to prove whether the cluster is due to the conversion of primary electrons.

[0007] Patent Document 6 (JP Patent Publication No. 2009-503857) discloses a method for manufacturing a high vacuum container that can be used as a package for an electron bombardment type CMOS sensor. Patent document 6 describes a method for manufacturing a high vacuum enclosure in which a semiconductor die is bonded to an inner surface of a package, comprising the steps of creating a plurality of bonding pads on a first surface of the die, creating a plurality of matching bonding pads on the inner surface of the package made of a material different from the first surface of the die, disposing a die bond material having a melting point below about 150°C between the combination of bonding pads, mating the surfaces and bonding pads with each other, disposing a photocathode in opposing relationship to the second surface of the die, disposing a spacer between the photocathode and the second surface of the die, and supporting the photocathode, spacer and die during a brazing cycle followed by an ultra-high vacuum processing cycle by arranging them together in contact to form a sealed vacuum enclosure.

[0008] Non-Patent Document 1 ("Energy- and spatial-resolved detection using a backside-illuminated CMOS sensor in the soft X-ray region" Tetsuo Harada et.al Applied Physics Express 12(8), 082012-082012, 2019-07-30 IOP Publishing) describes energy- and spatial-resolved detection in the soft X-ray region using an electron bombardment CMOS sensor. In the electron bombardment type CMOS sensor described in Non-Patent Document 1, a normal back-illuminated CMOS sensor is used to realize a soft X-ray sensor with high quantum efficiency, low readout noise, and a high frame rate. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2003-031785 A [Patent Document 2] JP 2019-176089 A [Patent Document 3] JP 2015-88568 A [Patent Document 4] JP 2015-164194 A [Patent Document 5] Special Publication No. 2012-511711 [Patent Document 6] Special Publication No. 2009-503857 [Non-patent literature]

[0010] [Non-Patent Document 1] “Energy- and spatial-resolved detection using a backside-illuminated CMOS sensor in the soft X-ray region” Tetsuo Harada et.al Applied Physics Express 12(8), 082012-082012, 2019-07-30 IOP Publishing. Summary of the Invention [Problem to be solved by the invention]

[0011] In a back-illuminated CMOS sensor, in which light is irradiated from the back side, electrons in electron-hole pairs generated by defects or other factors near the back side of the silicon substrate become dark current. Therefore, to make the area near the interface on the back side of the silicon substrate hole-rich, a negatively charged film such as hafnium oxide is formed on the back side, or boron or other materials are diffused near the interface on the back side to make the area near the interface P-type. Of these, the method of forming a negatively charged film such as hafnium oxide on the back surface does not require subsequent heat treatment, and therefore causes less damage to the surface of the silicon substrate on which the elements and wiring layer are formed. However, when a back-illuminated CMOS sensor with a film such as hafnium oxide formed on the back surface is used in an electron bombardment CMOS sensor, there are issues such as the accumulation of charge as electrons pass through the hafnium oxide film, which reduces the efficiency with which electrons reach the photodiode PD, and increases the dark current over time.

[0012] On the other hand, if a P+ diffusion layer is formed near the interface on the back surface, there is no increase in dark current due to charge accumulation. In this case, the pixels, analog circuits such as AD converters connected to the pixels, and wiring layers are formed on the front surface of the silicon substrate, and then the P+ diffusion layer is formed on the back surface. For this reason, this P+ diffusion layer is usually formed by ion implanting boron and activating the implanted boron ions by laser annealing. Laser annealing locally heats the back surface of the silicon substrate to a temperature at which silicon melts, activating the boron, and keeping the pixels, analog circuits, and wiring layers formed on the front surface within a temperature range where they are not significantly damaged. However, in order to keep the elements on the front side within a temperature range where they are not significantly damaged, the thermal diffusion distance, which is determined by the thermal annealing time, must be shorter than the thickness of the silicon substrate. In addition, since the analog circuits, which are part of the elements on the front side, are affected by even slight fluctuations in the threshold voltage of the MOS transistors, there was an issue that, particularly when the silicon substrate was made thinner - for example, when the silicon substrate was around 3 μm thick, which is the thickness of the silicon substrate used in recent years' typical back-illuminated CMOS sensors - the deviation and variation in the characteristics of the analog circuits formed on the front side would become greater, depending on the laser annealing irradiation conditions.

[0013] In addition, in back-illuminated CMOS sensors, the silicon substrate on which the sensor is formed is bonded to a support substrate to maintain mechanical strength. However, this bonding process often generates voids around the periphery of the wafer. There is also a certain probability of voids occurring in the center of the wafer. If a laser is applied to a part of the bonded wafer that has a void to heat it, the void may explode, causing fragments to be scattered on the surrounding chips, which may also cause the surrounding chips to become defective.

[0014] In addition, in recent years, electron bombardment type CMOS sensors using back-illuminated CMOS sensors have been developed as image sensors for detecting photons in low-light scenes (Patent Document 5) or for detecting soft X-rays (Non-Patent Document 1). In the electron bombardment type CMOS sensor, a CMOS sensor and a photocathode plate, the first surface of which faces the light-receiving surface of the CMOS sensor and the second surface of which is exposed to the outside, are enclosed in a vacuum chamber, and a negative high voltage is applied to the photocathode plate to collide photoelectrically converted electrons with the CMOS sensor at high speed, thereby multiplying the electrons and increasing the sensitivity of the sensor. On the other hand, CMOS sensors normally use a silicon substrate with a (100) surface. This is because when a MOS transistor is formed using the (100) surface, there are fewer interface states at the interface between the silicon substrate and the silicon oxide film, making it possible to form a MOS transistor with good characteristics. However, when a CMOS sensor with a (100) silicon substrate is used in an electron-bombarded CMOS sensor, when electrons are incident on a specific position of the silicon crystal from a direction perpendicular to the (100) plane, no interaction occurs between the incident electrons and the silicon atoms, and the electrons pass through the silicon crystal, weakening the electron multiplication effect inside the silicon substrate.

[0015] In the solid-state imaging device described in Patent Document 1, a P-type diffusion layer is formed on the back surface by doping boron. However, the thickness of the silicon substrate of the solid-state imaging device described in Patent Document 1 is about 10 μm, and it is thought that the deviation and increase in the variation of the characteristics of the analog circuit will not be a significant problem. Similarly, a P-type diffusion layer is provided on the back surface in Patent Documents 2 and 3. Although Patent Documents 2 and 3 do not disclose the thickness of the silicon substrate, they do not disclose any deviation in the characteristics of the analog circuit, an increase in variation, etc., and therefore the thickness of the silicon substrate is considered to be about the same as that of Patent Document 1. Furthermore, in the laser annealing system described in Patent Document 4, the device wafer 10a is described as having a thickness TH in the range of approximately 10 μm to 100 μm, and no consideration is given to silicon wafers with thicknesses of less than 10 μm. Furthermore, although Patent Documents 1 to 4 all describe laser annealing of bonded wafers, there is no mention of explosion of voids in the bonded wafers due to laser annealing.

[0016] Furthermore, the electron bombardment type CMOS sensors described in Patent Documents 5 and 6 and Non-Patent Document 1 also appear to use CMOS sensors using a (100) silicon substrate, but do not mention anything about the issues that arise when electrons are incident from a direction perpendicular to the (100) surface.

[0017] A primary object of the present invention is to provide a manufacturing method for a back-illuminated CMOS sensor in which boron ions are implanted into the back surface of a silicon substrate and the implanted boron is activated by laser annealing, which can suppress an increase in deviation and variation in the characteristics of analog circuits formed on the front surface. Another object of the present invention is to provide a manufacturing method for a back-illuminated CMOS sensor, which includes a step of bonding a silicon substrate on which a sensor is formed to a supporting substrate, that can avoid explosion of voids caused by laser heating for activating boron. It is still another object of the present invention to provide an electron-bombarded CMOS sensor incorporating a back-illuminated CMOS sensor using a (100) silicon substrate, which is capable of suppressing deterioration of the electron multiplication effect inside the silicon substrate caused by electrons being incident from a direction perpendicular to the (100) surface, and a method for manufacturing the same.

[0018] (1) A manufacturing method of a back-illuminated CMOS sensor according to one aspect includes a forming step of forming an N-type light receiving portion inside a silicon substrate, an implanting step of implanting ions to form a P+ diffusion layer on a back surface of the silicon substrate, and an irradiating step of irradiating a laser from the back surface to activate the implanted ions, wherein the laser is irradiated to an area of ​​the back-illuminated CMOS sensor excluding an area where an analog circuit is formed on a front surface. It is preferable that the ions for forming the P+ diffusion layer are boron ions.

[0019] Electron-hole pairs are generated by defects near the interface on the back surface of the silicon substrate, and when the electrons of these electron-hole pairs reach the light-receiving section, they become dark current. The reason for forming a P+ diffusion layer by injecting boron or the like into the back surface of the silicon substrate is to suppress the generation of dark current by recombining the electrons of the generated electron-hole pairs with the holes in the P+ diffusion layer.

[0020] As a method for forming this P+ diffusion layer, for example, Patent Document 3 describes a method in which boron ions are implanted into the back surface of a silicon substrate, and then the substrate is annealed by irradiating it with a short pulsed laser, thereby activating the implanted boron ions without causing any thermal effect on the readout gate connected to the light receiving section or the multilayer wiring formed on the front surface side. However, laser annealing has the following problems. For example, the maximum allowable temperature for multilayer wiring is typically said to be about 900° C. for copper interconnects and about 600° C. for aluminum interconnects. However, for MOS transistors, the threshold voltage is said to fluctuate at around 500° C. Even in this case, the fluctuation in the threshold voltage of the read gate can be compensated to some extent by a CDS (correlated double sampling) circuit, but high-precision analog circuits such as AD converters included in image sensor chips are vulnerable to threshold voltage fluctuations. Also, the thickness of the silicon substrate of the back-illuminated CMOS sensor was initially about 10 μm, as described in Patent Document 1 as about 10 μm and in Patent Document 4 as about 10 μm to 100 μm. However, as described in Non-Patent Document 1 as having a silicon substrate thickness of 3.5 μm in the back-illuminated CMOS sensor used in the electron bombardment CMOS sensor, the thickness of the silicon substrate has recently become thinner, to about 3 μm, with the reduction in pixel size. As the thickness of the silicon substrate becomes thinner, the effect of laser annealing on the analog circuit becomes even greater. The reason why the thickness of the silicon substrate is becoming thinner as the pixel size is reduced is that if the silicon substrate is thicker, there is a risk that crosstalk between pixels will occur due to obliquely incident light jumping into adjacent pixels, resulting in a decrease in resolution. According to Patent Document 4, when a laser with a long wavelength, for example 1 μm, is used for laser annealing, the optical absorption depth D AD The impact on analog circuits is of greater concern because they may also be an issue.

[0021] In a method for manufacturing a back-illuminated CMOS sensor according to one aspect, in an irradiation step of irradiating a laser from the back surface to activate the implanted ions, the laser is irradiated to the back-illuminated CMOS sensor excluding an area where an analog circuit is formed on the front surface, thereby reducing a temperature rise in the analog circuit due to laser irradiation and suppressing an increase in deviation and variation in the characteristics of the analog circuit. This makes it possible to manufacture a back-illuminated CMOS sensor with a higher signal-to-noise ratio and free of vertical stripes due to variations in analog characteristics between pixel columns.

[0022] (2) In a method for manufacturing a back-illuminated CMOS sensor according to a second aspect of the present invention, the laser may be irradiated only onto a pixel region of the back-illuminated CMOS sensor.

[0023] In this case, the laser is not irradiated onto the area behind the digital circuits such as the vertical selection circuit, so that the deviation and increase in the variations in the characteristics of the digital circuits can also be suppressed.

[0024] (3) In a method for manufacturing a back-illuminated CMOS sensor according to a third aspect of the present invention, the laser may be irradiated only onto a light receiving portion of the back-illuminated CMOS sensor.

[0025] In this case, the laser is not irradiated to the areas behind the circuits such as source follower transistors arranged around the light receiving area of ​​each pixel, so that the deviation and increase in the characteristics of the readout circuit can also be suppressed.

[0026] (4) A manufacturing method of a back-illuminated CMOS sensor according to a fourth aspect of the present invention may be such that, in the back-illuminated CMOS sensor, a light receiving section and a readout circuit of each pixel are alternately arranged in a direction perpendicular to a laser scanning direction, an analog circuit is arranged on a chip periphery where the light receiving section is extended along a direction perpendicular to the laser scanning direction, and a digital circuit is arranged on a chip periphery where the light receiving section is extended along the laser scanning direction, and the laser is irradiated onto the light receiving section of the back-illuminated CMOS sensor and an area where the digital circuit is formed on the surface.

[0027] Ideally, the laser should be directed only at the light receiving area in each pixel of a back-illuminated CMOS sensor, or only at the light receiving area in each pixel and the digital circuitry such as the vertical selection circuit around the chip. In order to direct the laser only at the light receiving area in each pixel and not at the readout circuitry in each pixel, it is necessary to precisely control the on / off state of the laser during the laser scan.

[0028] In contrast, in the manufacturing method of a back-illuminated CMOS sensor according to the fourth invention, the arrangement of the back-illuminated CMOS sensor is devised to enable irradiation only to the light receiving part in each pixel and the digital circuit part such as the V selection circuit around the chip. Specifically, the light receiving part and the readout circuit of each pixel are arranged alternately in the direction perpendicular to the laser scanning direction, so that the laser can be irradiated only to the light receiving part of each pixel during laser scanning. In addition, the analog circuit is arranged on the chip periphery where the light receiving part is extended along the direction perpendicular to the laser scanning direction, and the digital circuit is arranged on the chip periphery where the light receiving part is extended along the laser scanning direction, so that the analog circuit is not irradiated with the laser. This makes it possible to manufacture a back-illuminated CMOS sensor without precise on / off control during laser scanning.

[0029] (5) A manufacturing method of a back-illuminated CMOS sensor according to another aspect includes a forming step of forming, on a surface of a silicon substrate, a substantially rectangular pixel region having an N-type light receiving portion therein and an analog circuit region adjacent to one side or two opposing sides of the pixel region, an implantation step of implanting ions that form a P+ diffusion layer on the back surface of the silicon substrate, and an irradiation step of irradiating with a laser from the back surface to activate the implanted ions, wherein the laser is irradiated in a direction parallel to the one side or the two opposing sides of the pixel region adjacent to the analog circuit region.

[0030] In a CMOS sensor, the pixels in each pixel column are usually connected to a common vertical signal line, and analog circuits such as a sample hold, CDS, and AD converter are connected to this vertical signal line. In a method for manufacturing a back-illuminated CMOS sensor according to still another aspect, the entire wafer is irradiated with laser for laser annealing. In this case, although the analog circuit characteristics fluctuate to some extent, the laser scanning direction is parallel to the longitudinal direction of the analog circuit region. That is, the laser is irradiated across the portion of the analog circuit connected to the vertical signal line in each pixel column direction in common. Therefore, even if there is a characteristic fluctuation between the portions connected to the vertical signal lines of the analog circuit, the tendency of the characteristic fluctuation is similar, and therefore the characteristic variation between pixel columns is reduced.

[0031] (6) A manufacturing method of a back-illuminated CMOS sensor according to another aspect includes a forming step of forming an N-type light receiving portion inside a silicon substrate, a bonding step of bonding the silicon substrate with the N-type light receiving portion formed therein to a supporting substrate, an implantation step of implanting ions to form a P+ diffusion layer on the back surface of the silicon substrate, and an irradiation step of irradiating a laser from the back surface to activate the implanted ions, wherein the laser is irradiated excluding a peripheral region of the silicon wafer.

[0032] Normally, in a back-illuminated CMOS sensor, the silicon substrate on which the sensor is formed is bonded to a support substrate in order to increase the physical strength of the sensor. However, when the bonded wafers are bonded together, voids (air gaps) occur at the bonding interface. Voids occur more frequently especially around the periphery of the wafer due to the adhesion of particles and the inclusion of small air bubbles along the periphery of the wafer. When a laser is irradiated onto a void in a bonded wafer, the gas trapped in the void expands suddenly, causing an explosion around the void and scattering silicon fragments onto the surrounding chips. In a manufacturing method of a back-illuminated CMOS sensor according to another aspect, the laser is irradiated in the irradiation step, excluding a peripheral region of the silicon wafer, thereby preventing explosion of voids due to laser irradiation.

[0033] (7) A manufacturing method of a back-illuminated CMOS sensor according to a seventh aspect of the present invention may further include a recording step of recording the position of a chip in which a void occurs during the bonding step, and the laser may be irradiated excluding a peripheral region of the silicon wafer and the chip in which the void occurs.

[0034] In this case, it is possible to prevent not only the explosion of voids in the peripheral region of the silicon wafer, but also the explosion of voids present in the chip inside the silicon wafer.

[0035] (8) A manufacturing method of a back-illuminated CMOS sensor according to an eighth aspect of the present invention is the manufacturing method of a back-illuminated CMOS sensor according to any one of the aspects to the seventh aspect of the present invention, further including an oxide film formation step of forming an oxide film on the back surface of the silicon substrate, and a thickness measurement step of measuring a thickness of the formed oxide film, in which ions are implanted through the oxide film in the implantation step, and ion implantation energy in the implantation step may be determined according to the thickness of the oxide film.

[0036] The P+ diffusion layer formed on the back surface of a back-illuminated CMOS sensor is provided to prevent electrons in electron-hole pairs, which are generated due to defects existing at the interface between the back surface of the silicon substrate and an oxide film or the like formed on the back surface, from recombining with the numerous holes existing in the P+ diffusion layer and reaching the light receiving section to generate dark current. However, if a P+ diffusion layer is present on the back surface of the silicon substrate, the electrons photoelectrically converted by incident light in the P+ diffusion layer, or, in the case of an electron bombardment type CMOS sensor, the electrons multiplied by colliding with silicon crystals in the P+ diffusion layer, recombine with the holes in the P+ diffusion layer and do not reach the light receiving section. Therefore, it is desirable for the P+ diffusion layer formed on the back surface to have a shallow diffusion depth.

[0037] However, it is not easy to form a P+ diffusion layer with a shallow and steep profile even by ion implantation and laser annealing. One method for forming a P+ diffusion layer with a shallow and steep profile is to form an oxide film on the surface of silicon and implant ions through the oxide film. However, in this case, although it is possible to form a P+ diffusion layer with a steep profile, there is a problem that the diffusion depth of the P+ diffusion layer varies when the thickness of the oxide film varies. In the method for manufacturing a back-illuminated CMOS sensor according to the eighth aspect of the present invention, the thickness of the oxide film formed is measured, and the ion implantation energy is adjusted according to the thickness of the oxide film to form a P+ diffusion layer with little variation in diffusion depth and a steep profile. By forming a P+ diffusion layer with little variation in diffusion depth and a steep profile, it is possible to manufacture a back-illuminated CMOS sensor with small dark current and high sensitivity and little variation to photons in a wide energy range. Furthermore, an electron bombarded CMOS sensor using a back-illuminated CMOS sensor manufactured by this method as a sensor can obtain particularly high sensitivity characteristics. Furthermore, when an electron bombardment CMOS sensor is used as a sensor for soft X-rays, a thick P+ diffusion layer on the back surface may reduce sensitivity depending on the wavelength of the X-ray. The manufacturing method for a back-illuminated CMOS sensor according to the eighth invention makes it possible to form a shallow P+ diffusion layer with high precision, thereby manufacturing an electron bombardment CMOS sensor with good sensitivity regardless of the wavelength of the X-ray.

[0038] (9) A manufacturing method of a back-illuminated CMOS sensor according to a ninth aspect of the present invention is a manufacturing method of a back-illuminated CMOS sensor according to any one of the aspects to the eighth aspect of the present invention, further comprising a deep trench isolation forming step of forming a deep trench isolation around the light receiving portion on the back surface of the silicon substrate by trench dry etching, and in the implanting step, ions may be implanted to form a P+ diffusion layer not only on the back surface of the silicon substrate but also in the deep trench isolation.

[0039] In a back-illuminated CMOS sensor, deep trench isolation is formed around the light receiving area, and a light-shielding material is embedded or an air gap or other structure that has an optical reflection function is formed inside to block stray light from the light receiving area to the floating diffusion (FD) or the light receiving area of ​​an adjacent pixel. In addition, in an electron bombardment CMOS sensor using a back-illuminated CMOS sensor, it is possible to block the leakage of electrons multiplied in the silicon substrate to the light receiving area of ​​an adjacent pixel. However, dark current occurs due to defects at the interface of the deep trench isolation, just like the back surface of the silicon substrate. In the manufacturing method of a back-illuminated CMOS sensor according to the ninth aspect of the present invention, ions are injected to form a P+ diffusion layer not only in the back surface of the silicon substrate but also in the deep trench isolation, and the injected ions are activated by laser irradiation, thereby preventing an increase in dark current.

[0040] (10) A manufacturing method for a back-illuminated CMOS sensor according to a tenth aspect of the present invention may, in the manufacturing method for a back-illuminated CMOS sensor according to the eighth aspect of the present invention, further include a deep trench isolation formation step of forming a deep trench isolation around a light receiving portion on the back surface of the silicon substrate by trench dry etching, a hole-inducing film formation step of forming a film that induces holes on the back surface of the silicon substrate and on a surface of the deep trench isolation, and a polishing step of polishing and removing the hole-inducing film formed on the back surface of the silicon substrate by CMP.

[0041] When a film that induces holes is formed on the back surface of the silicon substrate facing the light receiving section, particularly in an electron bombardment type CMOS sensor that uses a back-illuminated CMOS sensor, a strong charge is generated in the film, and the dark current increases with longer use times. On the other hand, it is difficult to form a shallow diffusion layer by ion implantation at the interface of a deep trench isolation having an abrupt shape. In the manufacturing method of the back-illuminated CMOS sensor according to the tenth aspect of the present invention, a P+ diffusion layer is formed on the back surface by ion implantation, a film that induces holes is formed on the interface between the back surface and the deep trench isolation, and then the film that induces holes formed on the back surface is polished and removed by CMP. This makes it possible to avoid deterioration of durability due to charging of the film and suppress the generation of dark current at the interface of the deep trench isolation. As the film that induces holes, for example, a hafnium oxide (HfO2) film, an aluminum oxide (Al2O3) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a titanium oxide (TiO2) film can be used.

[0042] (11) A pixel for a back-illuminated CMOS sensor according to one aspect includes an N-type light receiving portion that generates an electric charge according to the amount of light or electrons incident from the back surface of a silicon substrate, a transfer gate formed on the front surface of the silicon substrate and one end connected to the light receiving portion, a floating diffusion formed on the front surface and one end connected to the other end of the transfer gate, and a deep trench isolation formed at a predetermined depth from the back surface to the front surface and surrounding the light receiving portion, and further includes a P+ diffusion layer formed on the back surface and on the front surface of the deep trench isolation.

[0043] In a back-illuminated CMOS sensor, deep trench isolation is formed around the light receiving area, and a light-shielding material is embedded or an air gap or other structure that has an optical reflection function is formed inside to block stray light from the light receiving area to the floating diffusion (FD) or the light receiving area of ​​an adjacent pixel. In addition, in an electron bombardment CMOS sensor using a back-illuminated CMOS sensor, it is possible to block the leakage of electrons multiplied in the silicon substrate to the light receiving area of ​​an adjacent pixel. However, dark current occurs due to defects at the interface of the deep trench isolation, just like the back surface of the silicon substrate. In a pixel for a back-illuminated CMOS sensor according to one aspect, an increase in dark current is prevented by providing a P+ diffusion layer formed by ion implantation and laser annealing on the back surface and on the surface of the deep trench isolation. In particular, when a back-illuminated CMOS sensor is used as an electron bombardment type, if electrons are multiplied near the deep trench, the P+ diffusion layer formed on the surface of the deep trench isolation can cancel out the multiplied electrons that leak to adjacent pixels before being accelerated, thereby preventing crosstalk between pixels and resulting in a sensor with higher sensitivity and better resolution.

[0044] (12) A pixel for a back-illuminated CMOS sensor according to another aspect includes an N-type light receiving portion that generates an electric charge according to the amount of light or electrons incident from the back surface of a silicon substrate, a transfer gate formed on the front surface of the silicon substrate and one end connected to the light receiving portion, a floating diffusion formed on the front surface and one end connected to the other end of the transfer gate, and a deep trench isolation formed at a predetermined depth from the back surface to the front surface and surrounding the light receiving portion, and further includes a P+ diffusion layer formed on the back surface, and a film that induces holes is formed only on the surface of the deep trench isolation.

[0045] When a film that induces holes is formed on the back surface of the silicon substrate facing the light receiving section, particularly in an electron bombardment type CMOS sensor that uses a back-illuminated CMOS sensor, a strong charge is generated in the film, and the dark current increases with longer use times. On the other hand, it is difficult to form a shallow diffusion layer by ion implantation at the interface of a deep trench isolation having an abrupt shape. In a pixel for a back-illuminated CMOS sensor according to another aspect, a P+ diffusion layer is formed on the back surface by ion implantation instead of a film that induces positive holes, thereby avoiding deterioration in durability due to charging of the film that induces positive holes, and on the other hand, a film that induces positive holes is formed on the surface of the deep trench isolation instead of a P+ diffusion layer by ion implantation, thereby ensuring that the surface of the deep trench isolation is in a hole-rich state. As the film that induces holes, for example, a hafnium oxide (HfO2) film, an aluminum oxide (Al2O3) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a titanium oxide (TiO2) film can be used. In particular, when using a back-illuminated CMOS sensor as an electron bombardment type, photoelectrically converted electrons enter the silicon substrate directly, so if a film that induces holes is formed on the surface of the silicon substrate, the electrons colliding within the film are far from the depletion layer in the Si, and there is a risk that the efficiency of collecting those electrons will deteriorate. Therefore, by forming a film that induces holes on the surface only within the deep trench to suppress the generation of dark current, and by forming only a P+ diffusion layer on the PD surface, it is possible to form an electron bombardment type sensor that can improve sensitivity and suppress crosstalk to adjacent pixels.

[0046] (13) A manufacturing method of an electron bombardment type CMOS sensor according to one aspect includes a fixing step of die-bonding a back-illuminated CMOS sensor manufactured by the manufacturing method of a back-illuminated CMOS sensor according to the first to tenth aspects of the present invention to the inside of a bottom surface of a hermetic package, a placement step of placing a photocathode plate on the upper surface of the hermetic package opposite a light receiving surface of the back-illuminated CMOS sensor, and an encapsulation step of sealing a space between the back-illuminated CMOS sensor and the photocathode plate in a vacuum state.

[0047] In this case, the analog circuit of the back-illuminated CMOS sensor has less variation in characteristics due to laser annealing or less variation in characteristics between pixel columns, and the manufacturing method of an electron-bombarded CMOS sensor according to one aspect makes it possible to manufacture an electron-bombarded CMOS sensor with high sensitivity and uniform characteristics.

[0048] (14) A manufacturing method of an electron bombarded CMOS sensor according to a fourteenth aspect of the present invention is such that, in the manufacturing method of an electron bombarded CMOS sensor according to one aspect, the silicon substrate used in the back-illuminated CMOS sensor is a (100) silicon substrate, and in the fixing step, the silicon substrate may be die-bonded in a state inclined at an angle of 7° or 22° with respect to the photocathode plate.

[0049] When a CMOS sensor with a (100) silicon substrate is used in an electron bombardment CMOS sensor, if electrons are incident on a specific position of the silicon crystal from a direction perpendicular to the (100) plane, there is no interaction between the incident electrons and the silicon atoms, and the electrons pass through the silicon crystal, weakening the electron multiplication effect inside the silicon substrate. This can cause the sensitivity of the electron bombardment CMOS sensor to deteriorate, or can cause localized deterioration resulting in black spots. In the method for manufacturing an electron bombardment type CMOS sensor according to the fourteenth aspect of the present invention, in the fixing step, the silicon substrate is die-bonded in a state inclined at an angle of 7° or 22° with respect to the photocathode plate. In this case, the electrons enter the (100) silicon substrate at an angle of 7° or 22° from the vertical, and so do not slip through the silicon crystals. As a result, the sensitivity of the electron-bombarded CMOS sensor is prevented from deteriorating, and localized degradation resulting in black spots is prevented.

[0050] (15) In one aspect of the electron bombardment CMOS sensor, a back-illuminated CMOS sensor using a (100) silicon substrate is sealed in a vacuum state, a photocathode plate is disposed opposite the light receiving surface of the back-illuminated CMOS sensor, and a negative voltage is applied to the photocathode plate, in which the silicon substrate is die-bonded at an angle of 7° or 22° to the photocathode plate.

[0051] An electron bombardment type CMOS sensor according to one aspect is an apparatus invention corresponding to the manufacturing method of the fourteenth aspect, in which the (100) face silicon substrate is die-bonded at an inclination of 7° or 22° with respect to the photocathode plate, thereby preventing electrons from passing through the silicon crystals and preventing deterioration of the sensitivity of the electron bombardment type CMOS sensor or localized deterioration resulting in black spots. [Brief description of the drawings]

[0052] [Figure 1] 1 is a schematic plan view of a back-illuminated CMOS sensor according to a first embodiment, as viewed from the front surface side. [Diagram 2] 2 is a schematic plan view showing an example of the arrangement of light receiving sections and readout circuits in a pixel region of the back-illuminated CMOS sensor according to the first embodiment. FIG. [Diagram 3] 1 is a schematic circuit diagram showing a configuration of a pixel of a back-illuminated CMOS sensor according to a first embodiment. [Figure 4] 1 is a schematic cross-sectional view of the periphery of a light receiving section of a back-illuminated CMOS sensor according to a first embodiment. [Diagram 5] 10 is a schematic diagram showing the relationship between the position of a void in a silicon wafer and a laser irradiation region in the second embodiment. FIG. [Figure 6] 13 is a graph showing a difference in the profile of boron ions implanted with and without an oxide film in the third embodiment. [Figure 7] FIG. 13 is a schematic cross-sectional view of the periphery of a light receiving section of a back-illuminated CMOS sensor according to a fourth embodiment. [Figure 8] FIG. 13 is a schematic cross-sectional view of the periphery of a light receiving section of a back-illuminated CMOS sensor according to a fifth embodiment. [Figure 9] 13A to 13C are schematic cross-sectional views illustrating a manufacturing method of a back-illuminated CMOS sensor according to a fifth embodiment. [Figure 10] 13A to 13C are schematic cross-sectional views for explaining the structure and operation of an electron bombardment type CMOS sensor according to a sixth embodiment. [Figure 11] 13A to 13C are schematic cross-sectional views for explaining the structure and operation of an electron bombardment type CMOS sensor according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals. Furthermore, when the reference numerals are the same, their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated.

[0054] [First embodiment] FIG. 1 is a schematic plan view of a back-illuminated CMOS sensor 100 of the first embodiment as viewed from the front side, FIG. 2 is a schematic plan view showing an example of an arrangement of a light receiving section 50 and a readout circuit 60 in a pixel region 20 of the back-illuminated CMOS sensor 100, FIG. 3 is a schematic circuit diagram showing the configuration of a pixel 10 of the back-illuminated CMOS sensor 100, and FIG. 4 is a schematic cross-sectional view of the periphery of the light receiving section 50 of the back-illuminated CMOS sensor 100.

[0055] (Arrangement of back-illuminated CMOS sensor 100) Fig. 1 shows an example of the overall layout of a back-illuminated CMOS sensor 100. The back-illuminated CMOS sensor 100 is composed of a pixel region 20, a digital circuit 30 (such as a vertical selection circuit), and an analog circuit 40 (such as a sample-and-hold circuit, an AD converter, etc.), and pixels 10 are arranged in a matrix in the horizontal direction (the lateral direction in Fig. 1) and vertical direction in the pixel region 20. In Fig. 1, the scanning direction 70 of laser irradiation in laser annealing, which will be described later, is also indicated by an arrow. Fig. 2 shows an example of the arrangement of the light receiving section 50 and readout circuit 60 of each pixel 10 inside the pixel region 20. The scanning direction 70 of the laser irradiation is also shown in Fig. 2. As can be seen from Fig. 2, the light receiving section 50 and readout circuit 60 of each pixel 10 are arranged in the horizontal direction parallel to the scanning direction 70 of the laser irradiation. Note that, although the readout circuit 60 exists independently for each pixel 10 in Fig. 2, the readout circuit 60 may be provided in common for two to four light receiving sections 50.

[0056] (Circuit configuration of pixel 10) Fig. 3 shows a schematic circuit diagram illustrating the configuration of a pixel 10 of a back-illuminated CMOS sensor 100. In Fig. 3, the pixel 10 is composed of a light receiving section 50 (PD in Fig. 3) and a readout circuit 60, and the readout circuit 60 is composed of a transfer gate TG having one end connected to the light receiving section 50, a floating diffusion FD connected to the other end of the transfer gate TG, a source follower transistor SF having a gate connected to the FD, a selection transistor SEL for selecting the pixel 10 to be read out, and a reset transistor RST. In FIG. 3, one readout circuit 60 is connected to one light receiving unit 50, but by providing only a transfer gate TG for each of the four light receiving units 50 and performing multiple sampling, the circuits after the FD can be shared by the four light receiving units 50.

[0057] (Schematic cross-sectional view of the light receiving section 50 and its periphery) 4 shows a schematic cross-sectional view of the light receiving section 50 and its periphery of the back-illuminated CMOS sensor 100. In FIG. 4, the lower side is the front side, and the upper side is the back side. The light receiving section 50 is formed as an N-type diffusion layer in P-type silicon 200, an N+ diffusion layer 260 is formed below it, and a P+ diffusion layer 250 is formed between the N+ diffusion layer 260 and the silicon oxide film 240. A transfer gate 220 is formed adjacent to the light receiving section 50 and the N+ diffusion layer 260, and when the transfer gate 220 is on, the charge accumulated in the light receiving section 50 is transferred to the floating diffusion 210. The charge transferred to the floating diffusion 210 is read out via the metal wiring 230, the source follower transistor SF, and the selection transistor SEL (see FIG. 3).

[0058] In the back-illuminated CMOS sensor 100, light is incident from the back surface of the silicon substrate 305 (upper side in FIG. 4). The back surface of the silicon substrate 305 is usually covered with a passivation film such as a silicon oxide film. However, electron-hole pairs are generated due to defects at the interface between the silicon substrate 305 and the passivation film, and when the electrons of the generated electron-hole pairs reach the light receiving section 50, they become dark current. In order to prevent the electrons of the generated electron-hole pairs from reaching the light receiving section 50, it is effective to increase the amount of holes at the interface and ensure that the electrons of the generated electron-hole pairs are recombined with the holes. Methods for increasing the amount of holes at the interface include a method of forming a P+ diffusion layer 270 at the interface and a method of forming a film that induces holes (hereinafter also referred to as a hole-inducing film) such as hafnium oxide at the interface. However, if a hole-inducing film is formed at the interface, reliability will deteriorate due to charge accumulation when the back-illuminated CMOS sensor 100 is used as a sensor for an electron bombardment CMOS sensor 360, so in the present invention, a P+ diffusion layer 270 is formed at the interface. Note that 280 is a silicon oxide film.

[0059] (Method of forming P+ diffusion layer 270) Although the P+ diffusion layer 270 is effective as a countermeasure against dark current, there is a problem that when photoelectric conversion is performed inside the P+ diffusion layer 270 to generate electrons, or when electrons are generated by collision in an electron impact sensor, the generated electrons recombine with holes and cannot contribute to the sensor output. Therefore, it is desirable for the diffusion depth of the P+ diffusion layer 270 to be shallow. In addition, the formation of the P+ diffusion layer 270 on the back surface is performed after the light receiving section 50 and the readout circuit 60 are formed on the front surface side of the silicon substrate 305, the front surface side of the silicon substrate 305 is bonded to the support substrate 310, and the back surface side is polished by a method such as CMP. Therefore, if the temperature on the front surface becomes too high during the formation of the P+ diffusion layer, it will have an adverse effect on the circuitry and metal wiring layer on the front surface side. For this reason, the P+ diffusion layer 270 on the back surface is formed by a method that can reduce the temperature rise on the surface, that is, a method in which boron ions are implanted and then irradiated with a laser to activate the boron ions.

[0060] Patent Document 4 discloses a method for preventing the device side of a device wafer from being scratched due to heating during annealing. However, the purpose of Patent Document 4 is for silicon substrates of 10μ or more and maximum temperatures of approximately 900°C for copper wiring and approximately 600°C for aluminum wiring, and does not consider the effect of heat on analog circuits such as AD converters (paragraphs

[0027] -

[0029] of the specification). Furthermore, although Patent Document 3 describes that annealing can be performed without adversely affecting the read gate 44 or the multilayer wiring 45 due to heat (paragraph

[0059] of the specification), the thickness of the silicon substrate is not described, and the effect of heat on analog circuits such as AD converters is not considered.

[0061] (Effect of laser irradiation on analog circuit 40) In the case of the analog circuit 40, slight variations in the threshold voltage of the MOS transistors may cause variations in the circuit characteristics. Also, the analog circuit 40 may use MOS capacitance as an important circuit element, and if the threshold voltage of the MOS transistors used in the MOS capacitance varies among the MOS capacitances, the ratio of the MOS capacitances will vary, often causing the characteristics of the analog circuit 40, such as an AD converter, to vary. Furthermore, the rise in temperature of the surface when the back surface of the silicon substrate 305 is irradiated with a laser depends on the thickness of the silicon substrate 305. In the original back-illuminated CMOS sensor 100, the thickness of the silicon substrate was about 10 μm as described in Patent Document 1, but recently, with the reduction in pixel size, the standard thickness has become around 3 μm, in which case the rise in temperature of the surface caused by irradiating the back surface with a laser becomes particularly large. The reason why the thickness of the silicon substrate 305 of the back-illuminated CMOS sensor 100 is becoming thinner is that if the silicon substrate 305 is thicker, crosstalk between pixels may occur due to diagonal incident light entering adjacent pixels, resulting in a decrease in resolution. This trend is expected to continue in the future.

[0062] (Laser irradiation method with minimal effect on analog circuit 40) In the method for manufacturing the back-illuminated CMOS sensor 100 of the first embodiment, one of the following methods 1) to 5) is adopted as a laser irradiation method that has little effect on the analog circuit 40.

[0063] 1) The surface of each chip is irradiated with a laser, excluding the area in which the analog circuit 40 (see FIG. 1) including an AD converter, a capacitor, etc. is formed. In this case, the laser is scanned in the horizontal direction in Fig. 1 (corresponding to the scanning direction 70 in Fig. 1) and the vertical position corresponding to the area around the chip where the analog circuit 40 is formed is not scanned, thereby reducing the effect of heat on the analog circuit 40. In addition, since the laser is irradiated onto the back surface of the light receiving portion 50 in the pixel 10, the boron ions implanted into the back surface of the light receiving portion 50 are activated.

[0064] 2) A laser is irradiated only onto the surface of the region where the pixel region 20 (see FIG. 1) is formed. This method can reduce the heat effects caused by laser irradiation not only on the analog circuit 40 but also on the digital circuit 30. However, in this method, while the silicon wafer 110 is being scanned in the horizontal direction with the laser, it is necessary to turn off the laser in the area of ​​the digital circuit 30 on the periphery of each chip, so it is necessary to select a laser scanning system that can handle such scanning.

[0065] 3) Irradiate only the rear surface of the light receiving section 50 with a laser. In this method, the laser is irradiated only to the light receiving section 50 that requires a P+ diffusion region on the back surface, so the thermal effects of laser irradiation on not only the analog circuit 40 but also the readout circuit 60 and the surrounding digital circuit 30 are reduced. However, in a typical image sensor, the readout circuits 60 are arranged above, below, left and right of the light receiving section 50. Therefore, in order to execute this method, it is necessary to select a laser scanning system that can scan a narrow area and can repeatedly turn on and off in a short time (at the beginning and end of the light receiving section 50).

[0066] 4) As shown in Fig. 2, the back-illuminated CMOS sensor 100 is arranged such that the light receiving sections 50 and the readout circuits 60 of the pixels 10 are alternately arranged in a direction perpendicular to the laser scanning direction 70, and as shown in Fig. 1, the analog circuit 40 is arranged on the chip periphery where the light receiving sections 50 are extended along the direction perpendicular to the laser scanning direction 70. Then, the digital circuit 30 is arranged on the chip periphery where the light receiving sections 50 are extended along the laser scanning direction 70, and a laser is irradiated onto the light receiving sections 50 of the back-illuminated CMOS sensor 100 and the area where the digital circuit 30 is formed on the surface. In this case, the laser is irradiated only to the light receiving section 50 and the surrounding digital circuit 30, which require a P+ diffusion region on the back surface, so that the thermal effects of laser irradiation on not only the analog circuit 40 but also the readout circuit 60 such as the source follower transistor SF are reduced. Furthermore, in the method of combining the arrangement of the light receiving unit 50 and the readout circuit 60 with the laser scanning method, although the laser needs to scan a narrow area, it is not necessary to turn the laser on and off while scanning the silicon wafer 110 in the horizontal direction, so that it is relatively easy to construct a laser scanning system. In the above methods 1)-4), the laser is selectively irradiated to a portion of the back surface of the silicon substrate 305, and the remaining portion is not irradiated with the laser. However, it is possible that a dark current will be generated in the portion not irradiated with the laser, adversely affecting the output of the sensor. In that case, in order to suppress the effect of deterioration of the characteristics of the pixel region, instead of not irradiating the remaining portion with the laser, a low-energy laser may be irradiated to the remaining portion. Alternatively, a low-energy laser may be irradiated to the entire surface.

[0067] 5) The back-illuminated CMOS sensor 100 is arranged such that, as shown in Fig. 1, digital circuits 30 such as vertical selection circuits connected to each pixel row are arranged adjacent to the substantially rectangular pixel region 20 in the laser scanning direction 70, so that the columns of the circuit parts connected to each pixel row are perpendicular to the laser scanning direction 70. Also, analog circuits 40 such as sample-hold circuits and AD converters to which vertical signal lines linking the outputs of each pixel column (OUT1 in Fig. 3) are connected are arranged adjacent to the pixel region 20 in the direction perpendicular to the laser scanning direction 70, so that the columns of the circuit parts connected to each vertical signal line are parallel to the laser scanning direction 70. Then, the entire back-illuminated CMOS sensor 100 arranged as described above is sequentially scanned with a laser along the scanning direction 70 in Fig. 1. In this case, since the area of ​​the analog circuit 40 is also scanned with the laser, there is a possibility that the characteristics of the analog circuit 40 may fluctuate due to heating; however, since the portions of the analog circuit 40 connected to the vertical signal lines of each pixel column are heated in almost the same manner, the fluctuations in the characteristics of the portions of the analog circuit 40 connected to the vertical signal lines of each pixel column are similar, and therefore the characteristic variation between pixel columns is reduced. Furthermore, with this method, only the scanning direction 70 is limited for the laser scanning system, and no difficult requirements such as laser on / off control arise.

[0068] [Second embodiment] FIG. 5 is a schematic diagram showing the relationship between the position of a void 130 in a silicon wafer 110 and a laser irradiated region 120 in the second embodiment. Typically, the physical strength of the back-illuminated CMOS sensor 100 is improved by bonding the front side of the silicon wafer 110, on which the light receiving section 50, the readout circuit 60, etc. are formed, to a silicon wafer that serves as the support substrate 310. However, when silicon wafers are bonded together, voids 130 (air gaps) occur at the bonding interface. In particular, more voids 130 occur around the wafer due to the adhesion of particles and the encapsulation of small air bubbles along the outer periphery of the wafer. When a laser is applied to the void 130 of the bonded wafer, the gas trapped in the void 130 suddenly expands, causing an explosion around the void 130, and silicon fragments are scattered onto the surrounding chips.

[0069] In the manufacturing method of the back-illuminated CMOS sensor 100 of the second embodiment, the following two methods are adopted to avoid an explosion that would occur if the void 130 were irradiated with a laser. First, the laser is not irradiated to the periphery of the silicon wafer 110 where voids 130 are more likely to occur. As shown in Fig. 5, the laser irradiation area 120 is limited to the periphery of the chip on which the back-illuminated CMOS sensor 100 is formed, and the laser is not irradiated to the periphery of the wafer where voids 130 are more likely to occur, thereby reducing the risk of explosion around the voids 130. Secondly, the silicon wafer 110 after bonding is inspected, and the positions of the chips in which the voids 130 exist are recorded, and during laser irradiation, in addition to the peripheral region of the silicon wafer 110, the chips in which the voids 130 exist are also excluded from the laser irradiation. If there are almost no voids 130 in areas other than the peripheral area of ​​the silicon wafer 110, it is sufficient to exclude only the peripheral area from the laser irradiation.

[0070] [Third embodiment] FIG. 6 is a graph showing the difference in the profile of boron ions implanted with and without an oxide film. The method for manufacturing the back-illuminated CMOS sensor 100 of the third embodiment relates to a method for implanting boron ions into the back surface of the back-illuminated CMOS sensor 100. 4, a P+ diffusion layer 270 is formed on the back surface (the surface on which light is incident) of the light receiving section 50. This is to prevent the electrons of the electron-hole pairs generated at the interface on the back surface from disappearing due to recombination with the holes in the P+ diffusion layer 270, thereby preventing dark current from occurring. On the other hand, if an incident photon undergoes photoelectric conversion inside this P+ diffusion layer 270, the back-illuminated CMOS sensor 100 cannot detect this photon. In addition, when the back-illuminated CMOS sensor 100 is used as a sensor for the electron bombardment CMOS sensor 360, the electrons that collide with silicon crystals inside the P+ diffusion layer 270 and are multiplied cannot be counted by the electron bombardment CMOS sensor 360.

[0071] Therefore, in forming the backside P+ diffusion layer 270, a relatively high concentration (e.g., 10 19 / cm 3 It is necessary to form a shallow diffusion (e.g., diffusion depth of 0.1 μm or less) at a high energy (depth of 1000 nm or more). In order to form such a shallow profile by ion implantation, it is necessary to implant ions at a very low energy of, for example, less than a few KeV, even if diffusion due to laser annealing can be ignored. However, there are cases where it is difficult to implant ions at such low energy. Another issue is the occurrence of white spots due to metal contamination during ion implantation. A possible countermeasure to this problem is to form an oxide film on the silicon surface, implant ions through the oxide film, anneal the silicon, and then remove the oxide film. Figure 6(a) shows the boron profile when boron is implanted into silicon with almost no oxide film, and Figure 6(b) shows the boron profile when boron is implanted through an oxide film. By comparing Figure 6(a) and Figure 6(b), it can be seen that the depth of the profile of ion-implanted boron from the silicon interface is shallower when boron is implanted through an oxide film. The horizontal axis of Figure 6 is the distance from the wafer surface, and the vertical axis is the ion implantation profile (linear scale).

[0072] However, when ions are implanted through an oxide film, a new problem arises in that the diffusion depth varies due to variations in the thickness of the formed oxide film. In the manufacturing method of the back-illuminated CMOS sensor 100 of the third embodiment, an oxide film is formed on the back surface of the back-illuminated CMOS sensor 100, the thickness of the oxide film is measured, and the ion implantation energy is adjusted according to the measured thickness of the oxide film, thereby forming a P+ diffusion layer 270 with a steep profile and little variation in diffusion depth regardless of the thickness of the oxide film formed. This makes it possible to manufacture a back-illuminated CMOS sensor 100 with a small dark current and high sensitivity and little variation to photons in a wide energy range. Furthermore, an electron bombardment CMOS sensor 360 using the back-illuminated CMOS sensor 100 manufactured by this method as a sensor can obtain particularly high sensitivity characteristics. Furthermore, when an electron bombardment CMOS sensor is used as a sensor for soft X-rays, a thick P+ diffusion layer on the back surface may reduce sensitivity depending on the wavelength of the X-rays. The manufacturing method for a back-illuminated CMOS sensor of the third embodiment can accurately form a shallow P+ diffusion layer, making it possible to manufacture an electron bombardment CMOS sensor with good sensitivity regardless of the wavelength of the X-rays.

[0073] [Fourth embodiment] 7 is an example of a schematic cross-sectional view of the periphery of the light receiving section 50 of the back-illuminated CMOS sensor 100 of the fourth embodiment. The back-illuminated CMOS sensor 100 of the fourth embodiment differs from the back-illuminated CMOS sensor 100 of the first embodiment in that a deep trench isolation 290 is formed at a predetermined depth from the back surface toward the front surface and surrounding the periphery of the light receiving section 50, and a P+ diffusion layer 270 is further formed in the deep trench isolation 290. In the back-illuminated CMOS sensor 100 of the fourth embodiment, a deep trench isolation 290 is formed around the light receiving section 50, and a light-shielding material is embedded therein, or a structure having an optical reflection function such as an air gap is formed inside, thereby blocking stray light from the light receiving section 50 to the floating diffusion 210 or the light receiving section 50 of the adjacent pixel 10. In addition, in the electron bombardment CMOS sensor 360 using the back-illuminated CMOS sensor 100, leakage of electrons multiplied in the silicon substrate 305 to the light receiving section 50 of the adjacent pixel 10 can be blocked. However, dark current is generated due to defects at the interface of the deep trench isolation 290, as in the back surface of the silicon substrate 305. For this reason, in the back-illuminated CMOS sensor 100 of the fourth embodiment, boron ions are implanted into the deep trench isolation 290 in addition to the back surface of the silicon substrate 305 to form a P+ diffusion layer 270, and the implanted ions are activated by laser irradiation to prevent an increase in dark current. In the example of FIG. 7, the silicon oxide film 280 is embedded inside the deep trench isolation 290, but it may be an air gap or may be embedded with aluminum or the like.

[0074] The method of forming the P+ diffusion layer 270 on the back surface of the silicon substrate 305 as well as on the deep trench isolation 290 is as follows. First, a deep trench isolation 290 is formed around the light receiving section 50 on the back surface of the back-illuminated CMOS sensor 100 by trench dry etching. Next, boron ions are implanted into the entire back surface, including the deep trench isolation 290 . Next, the entire back surface including the deep trench isolation 290 is irradiated with a laser to activate the boron. In addition, in the manufacturing method of the back-illuminated CMOS sensor 100 of the fourth embodiment, similar to the first embodiment, a laser irradiation method (any of 1) to 5) of the first embodiment) that has little effect on the analog circuit 40 is used.

[0075] [Fifth embodiment] Fig. 8 is an example of a schematic cross-sectional view of the periphery of the light receiving section 50 of the back-illuminated CMOS sensor 100 of the fifth embodiment, and Fig. 9 is a schematic cross-sectional view explaining a manufacturing method of the back-illuminated CMOS sensor 100 of the fifth embodiment. The back-illuminated CMOS sensor 100 of the fifth embodiment differs from the back-illuminated CMOS sensor 100 of the first embodiment in that a deep trench isolation 290 is formed at a predetermined depth from the back surface to the front surface and surrounding the periphery of the light receiving section 50, and a hole induction film 300 is further formed in the deep trench isolation 290. When a hole-inducing film 300 is formed on the back surface of the silicon substrate 305 facing the light receiving section 50, particularly in an electron bombardment type CMOS sensor 360 using a back-illuminated type CMOS sensor 100, a strong charge is generated in the film, and the dark current increases with the duration of use. On the other hand, it is difficult to form a shallow P+ diffusion layer 270 by ion implantation at the interface of the deep trench isolation 290 having an abrupt shape. In the back-illuminated CMOS sensor 100 of the fifth embodiment, a P+ diffusion layer 270 is formed by ion implantation on the back surface instead of a hole-inducing film 300, thereby avoiding deterioration in durability due to charging of the hole-inducing film 300, and on the other hand, a hole-inducing film 300 is formed by ion implantation on the surface of the deep trench isolation 290, instead of a P+ diffusion layer 270 by ion implantation, thereby ensuring that the surface of the deep trench isolation 290 is hole-rich.

[0076] A method for forming the P+ diffusion layer 270 on the back surface and the hole inducing film 300 on the surface of the deep trench isolation 290 will be described with reference to FIG. First, boron ions are implanted into the back surface of the back-illuminated CMOS sensor 100, and the implanted boron is activated by laser annealing. In this case, the boron ions may be implanted deeper than in the fifth embodiment. Next, deep trench isolation 290 is formed around the light receiving portion 50 on the back surface of the back-illuminated CMOS sensor 100 by trench dry etching. Next, as shown in FIG. 9( a ), a hole inducing film 300 is formed on the back surface of the back-illuminated CMOS sensor 100 and the surface of the deep trench isolation 290 . 9(b), the hole inducing film 300 formed on the back surface is polished and removed by a method such as CMP. If boron ions are implanted deeper, the silicon on the back surface is also polished and removed so that the depth of the boron diffusion layer becomes appropriate. Also, in the manufacturing method of the back-illuminated CMOS sensor 100 of the fifth embodiment, similar to the first embodiment, a laser irradiation method (any of 1) to 5) of the first embodiment) that has little effect on the analog circuit 40 is used.

[0077] [Sixth embodiment] FIG. 10 is a schematic cross-sectional view for explaining the structure and operation of an electron bombardment type CMOS sensor 360 according to the sixth embodiment. 10, a back-illuminated CMOS sensor 100, which is formed by bonding a silicon substrate 305 having an N-type light receiving portion 50 in a P-type silicon 200 and a P+ diffusion layer 270 and a silicon oxide film 280 formed on the back surface (upper surface in FIG. 10) and a support substrate 310, is sealed inside the bottom surface of a sealed package 350. A photocathode plate 320 is disposed facing the back surface (light receiving surface) of the back-illuminated CMOS sensor 100, and the space between the back-illuminated CMOS sensor 100 and the photocathode plate 320 is sealed in a vacuum state. A high negative voltage is applied to the photocathode plate 320 by a high-voltage power supply 340 with respect to the back-illuminated CMOS sensor 100. When a photon (PHOTON) is incident on the photocathode plate 320, an electron (ELECTRON) is generated, and the generated electrons are accelerated by the electric field applied between the back-illuminated CMOS sensor 100 and the photocathode plate 320 and enter the back-illuminated CMOS sensor 100. The electrons that reach the silicon substrate 305 of the back-illuminated CMOS sensor 100 collide with silicon crystals to generate electron-hole pairs, and the electrons multiplied by the generation of the electron-hole pairs reach the light receiving section 50 to become a sensor output.

[0078] The manufacturing method of the electron bombardment type CMOS sensor 360 of the sixth embodiment includes a fixing process of die-bonding the back-illuminated CMOS sensor 100 to the inside bottom surface of the sealed package 350, a placement process of placing a photocathode plate 320 on the upper surface of the sealed package 350 facing the light receiving surface of the back-illuminated CMOS sensor 100, and an encapsulation process of sealing the space between the back-illuminated CMOS sensor 100 and the photocathode plate 320 in a vacuum state. In the electron bombardment CMOS sensor 360 of the sixth embodiment, a shallow boron P+ diffusion layer 270 is formed on the back surface of the back-illuminated CMOS sensor 100 in order to reduce dark current. In the manufacturing method of the electron bombardment CMOS sensor 360 of the sixth embodiment, this P+ diffusion layer 270 is formed by ion implantation and laser annealing. In this laser annealing, it is desirable to use a laser irradiation method (any of 1) to 5) in the first embodiment) that has little effect on the analog circuit 40, as in the first embodiment. In addition, in order to avoid explosion around the void 130 during laser annealing, it is desirable to limit the laser irradiation area 120 as in the second embodiment. In order to form the shallow boron P+ diffusion layer 270 with high accuracy, it is desirable to perform the ion implantation through a silicon oxide film as in the fourth embodiment. In addition, in order to avoid leakage of multiplied electrons to adjacent pixels 10 while avoiding an increase in dark current, it is desirable to add the deep trench isolation 290 of the fifth or sixth embodiment to the back-illuminated CMOS sensor 100.

[0079] [Seventh embodiment] 11 is a schematic cross-sectional view for explaining the structure and operation of an electron bombardment type CMOS sensor 360 of the seventh embodiment. The structure of the electron bombardment type CMOS sensor 360 of the seventh embodiment is the same as that of the electron bombardment type CMOS sensor 360 of the sixth embodiment, except that a chip fixing base 370 made of a conductive material such as metal is inserted between the back-illuminated type CMOS sensor 100 and the inside bottom surface of the sealed package 350 in order to die-bond the back-illuminated type CMOS sensor 100 at an inclination of 7° or 22° with respect to the photocathode plate 320. The back-illuminated CMOS sensor 100 used in the electron bombardment CMOS sensor 360 of the seventh embodiment uses a (100) silicon substrate 305. In this case, when electrons are incident on a specific position of a silicon crystal from a direction perpendicular to the (100) plane, no interaction occurs between the incident electrons and silicon atoms, and the electrons pass through the silicon crystal, weakening the electron multiplication effect inside the silicon substrate 305. This may cause the sensitivity of the electron bombardment CMOS sensor 360 to deteriorate, or may cause localized deterioration resulting in black spots. In the electron bombardment CMOS sensor 360 of the seventh embodiment, as a countermeasure to this problem, the back-illuminated CMOS sensor 100 is die-bonded at an angle of 7° or 22° to the photocathode plate 320 so that electrons are incident from a direction inclined by 7° or 22°, which is an angle that ensures that electrons interact with silicon atoms regardless of the position of incidence.

[0080] In the present invention, silicon substrate 305 corresponds to the "silicon substrate", light receiving section 50 corresponds to the "light receiving section", P+ diffusion layer 270 corresponds to the "P+ diffusion layer", back-illuminated CMOS sensor 100 corresponds to the "back-illuminated CMOS sensor", analog circuit 40 corresponds to the "analog circuit", pixel area 20 corresponds to the "pixel area", scanning direction 70 corresponds to the "scanning direction", pixel 10 corresponds to the "pixel", readout circuit 60 corresponds to the "readout circuit", digital circuit 30 corresponds to the "digital circuit", support substrate 310 corresponds to the "support substrate", and silicon The silicon wafer 110 corresponds to a "silicon wafer", the void 130 corresponds to a "void", the deep trench isolation 290 corresponds to a "deep trench isolation", the hole inducing film 300 corresponds to a "film that induces holes", the transfer gate 220 corresponds to a "transfer gate", the floating diffusion 210 corresponds to a "floating diffusion", the hermetic package 350 corresponds to a "sealed package", the photocathode plate 320 corresponds to a "photocathode plate", and the electron-bombarded CMOS sensor 360 corresponds to an "electron-bombarded CMOS sensor".

[0081] Although the preferred embodiment of the present invention is as described above, the present invention is not limited thereto. It is understood that various other embodiments can be made without departing from the spirit and scope of the present invention. Furthermore, although the actions and effects of the configuration of the present invention are described in the present embodiment, these actions and effects are merely examples and do not limit the present invention. [Explanation of symbols]

[0082] 10 pixels 20 Pixel Area 30 Digital Circuits 40 Analog Circuits 50 Light receiving part 60 Readout circuit 70 Scanning Direction 100 Back-illuminated CMOS sensor 110 Silicon Wafer 130 Void 210 Floating Diffusion 220 Transfer Gate 230 Metal wiring 270 P+ diffusion layer 290 Deep Trench Isolation 300 Hole-Inducing Film 305 Silicon Substrate 310 Support substrate 320 Photocathode plate 350 sealed packages 360 Electron bombardment type CMOS sensor

Claims

1. forming an N-type light receiving portion inside a silicon substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; The laser is irradiated onto the back-illuminated CMOS sensor, excluding an area on the front surface of which an analog circuit is formed; In the back-illuminated CMOS sensor, the light receiving section and the readout circuit of each pixel are alternately arranged in a direction perpendicular to the scanning direction of the laser, the analog circuit is arranged on a chip periphery where the light receiving section is extended along the direction perpendicular to the scanning direction of the laser, and a digital circuit is arranged on a chip periphery where the light receiving section is extended along the scanning direction of the laser, The method for manufacturing a back-illuminated CMOS sensor, wherein the laser is irradiated onto the light receiving portion of the back-illuminated CMOS sensor and an area on the front surface where the digital circuit is formed.

2. A forming step of forming, on a surface of a silicon substrate, a substantially rectangular pixel region having an N-type light receiving portion therein and an analog circuit region adjacent to one side or two opposing sides of the pixel region; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; The method for manufacturing a back-illuminated CMOS sensor, wherein the laser is irradiated in a direction parallel to one side or two opposing sides of the pixel region to which the analog circuit region is adjacent.

3. forming an N-type light receiving portion inside a silicon substrate; a bonding step of bonding the silicon substrate on which the N-type light receiving portion is formed to a support substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; a recording step of recording the position of the chip in which the voids generated in the lamination step exist, The method for manufacturing a back-illuminated CMOS sensor, wherein the laser is irradiated excluding a peripheral region of a silicon wafer and a chip in which the void exists, and the peripheral region is not heated by the irradiation of the laser.

4. forming an N-type light receiving portion inside a silicon substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; The laser is irradiated onto the back-illuminated CMOS sensor, excluding an area on the front surface of which an analog circuit is formed; an oxide film forming step of forming an oxide film on the back surface of the silicon substrate; and a film thickness measuring step of measuring the film thickness of the oxide film formed. In the implantation step, ions are implanted through the oxide film, and ion implantation energy in the implantation step is determined according to a thickness of the oxide film.

5. forming an N-type light receiving portion inside a silicon substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; The laser is irradiated onto the back-illuminated CMOS sensor, excluding an area on the front surface of which an analog circuit is formed; The method further includes a deep trench isolation forming step of forming a deep trench isolation around the light receiving portion on the back surface of the silicon substrate by trench dry etching, In the implantation step, ions are implanted to form a P+ diffusion layer in the deep trench isolation as well as in the back surface of the silicon substrate.

6. forming an N-type light receiving portion inside a silicon substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; The laser is irradiated onto the back-illuminated CMOS sensor, excluding an area on the front surface of which an analog circuit is formed; a deep trench isolation forming step of forming a deep trench isolation around the light receiving portion on the back surface of the silicon substrate by trench dry etching; a hole inducing film forming step of forming a film that induces holes on the back surface of the silicon substrate and on a front surface of the deep trench isolation; a polishing step of removing the hole-inducing film formed on the back surface of the silicon substrate by CMP.

7. A forming process of forming an N-type light receiving portion inside a silicon substrate; a bonding step of bonding the silicon substrate on which the N-type light receiving portion is formed to a support substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; an oxide film forming step of forming an oxide film on the back surface of the silicon substrate; a film thickness measuring step of measuring the film thickness of the formed oxide film, The laser is irradiated except for a peripheral region of the silicon wafer, and the peripheral region is not heated by the irradiation of the laser, and In the implantation step, ions are implanted through the oxide film, and ion implantation energy in the implantation step is determined according to a thickness of the oxide film.

8. A forming process of forming an N-type light receiving portion inside a silicon substrate; a bonding step of bonding the silicon substrate on which the N-type light receiving portion is formed to a support substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; a deep trench isolation forming step of forming a deep trench isolation around the light receiving portion on the back surface of the silicon substrate by trench dry etching; The laser is irradiated except for a peripheral region of the silicon wafer, and the peripheral region is not heated by the irradiation of the laser, and In the implantation step, ions are implanted to form a P+ diffusion layer in the deep trench isolation as well as in the back surface of the silicon substrate.

9. A forming process of forming an N-type light receiving portion inside a silicon substrate; a bonding step of bonding the silicon substrate on which the N-type light receiving portion is formed to a support substrate; an implantation step of implanting ions to form a P+ diffusion layer on a rear surface of the silicon substrate; an irradiation step of irradiating the back surface with a laser to activate the implanted ions; a deep trench isolation forming step of forming a deep trench isolation around the light receiving portion on the back surface of the silicon substrate by trench dry etching; a hole inducing film forming step of forming a film that induces holes on the back surface of the silicon substrate and on a front surface of the deep trench isolation; a polishing step of removing the hole inducing film formed on the rear surface of the silicon substrate by CMP; A method for manufacturing a back-illuminated CMOS sensor, wherein the laser is irradiated excluding a peripheral region of a silicon wafer, and the peripheral region is not heated by the irradiation of the laser.

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