MEMORY ACCESS SYSTEM AND INFORMATION PROCESSING APPARATUS

Abstract

To realize efficient bandwidth control as compared with a case where bandwidth control is performed based on the settings and operating conditions of individual devices regardless of a connection structure between a memory and an access-based device.SOLUTION: A memory access system includes processing devices 11 that perform real-time processing including access to a memory, a processing device 12 that performs non-real-time processing including access to the memory, and a bandwidth control device 120 that performs bandwidth control to limit the bandwidth used by the processing device 12 included in the same functional block 10 as any of the processing devices 11 when the bandwidth used by the processing device 11 is insufficient, and further performs to limit the bandwidth used by the processing device 12 included in the functional block 10 different from the processing device 11 when the bandwidth used by the processing device 11 is insufficient.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a memory access system and an information processing device. [Background technology]

[0002] In information processing systems, multiple devices (masters) that access memory may be configured to directly access memory (DMA: Direct Memory Access). Such devices that access memory include devices that perform processes that require real-time performance (hereafter referred to as "real-time processing") and devices that do not require real-time performance (hereafter referred to as "non-real-time processing"). Real-time processing is processing that, once started, cannot change its speed or stop until a certain amount of processing is completed. In such systems, access to memory by each device is monitored, and bandwidth control is performed to ensure that the transfer bandwidth for memory access by devices that perform real-time processing (hereafter referred to as "real-time devices") is not insufficient.

[0003] Patent document 1 discloses a memory access system that monitors the amount of data used per specified time between a memory and multiple masters, and reduces access to the memory by low-priority masters among the multiple monitored masters (masters that perform data transfers by accessing the memory in non-real-time) in accordance with satisfaction of specified conditions regarding the monitored data amount.

[0004] Patent document 2 discloses a data processing device comprising: a first sub-arbiter that arbitrates access by a first master (a master ensuring real-time performance) and a second master that access data stored in a memory; a second sub-arbiter that arbitrates access to the memory by multiple masters other than the first and second masters; a main arbiter that prioritizes access to the memory from the first sub-arbiter over access to the memory from the second sub-arbiter; and a limiting unit that limits the amount of access to the memory by the second master to within a preset range. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-120490 A [Patent Document 2] JP 2014-160341 A Summary of the Invention [Problem to be solved by the invention]

[0006] In a connection structure between a memory and an accessing device, for example, a configuration may be adopted in which the transmission paths of multiple devices are combined for each device performing one function, and one port is shared to connect to the memory. In such a configuration, a bottleneck in data transfer may occur on a port-by-port basis. In this case, regardless of the connection relationship of each port, simply limiting the transfer bandwidth of a device performing non-real-time processing (hereinafter referred to as a "non-real-time device") does not necessarily result in effective bandwidth adjustment for the entire system.

[0007] The present invention aims to realize more efficient bandwidth control compared to bandwidth control based on the settings and operating conditions of individual devices, regardless of the connection structure between the memory and the device that is the subject of access. [Means for solving the problem]

[0008] The present invention according to claim 1 is a first processing device which is one of the devices that access the memory and performs real-time processing; a second processing device which is one of the devices that access the memory and performs non-real-time processing; A bandwidth control device that performs bandwidth control, The bandwidth control device includes: When a bandwidth allocated to any one of the first processing devices for accessing the memory is smaller than a first threshold, a bandwidth allocated to a specific second processing device using the same port as the first processing device for accessing the memory is limited. and increasing the bandwidth allocated to the first processing device. Bandwidth control is performed, When the bandwidth allocated to the first processing device using the same port as the specific second processing device is smaller than a second threshold value in a state where the bandwidth allocated to the specific second processing device is limited, the bandwidth allocated to the second processing device using a port different from the specific second processing device is limited. and increasing the bandwidth allocated to the first processing device. This memory access system is characterized by performing bandwidth control. The present invention according to claim 2 is The memory access system of claim 1 is characterized in that, when there are multiple second processing devices using ports different from the specific second processing device, the bandwidth control device selects one of the multiple second processing devices in a predetermined order, and sequentially limits the bandwidth allocated to the selected second processing device. The present invention according to claim 3 is The memory access system of claim 1, characterized in that the bandwidth control device controls the bandwidth allocated to the second processing device by changing the number of clocks required to transfer data between the second processing device and the memory. The present invention according to claim 4 is The memory access system of claim 3 is characterized in that the bandwidth control device changes the number of clocks required to transfer the data in the second processing device, which is the subject of bandwidth control, when processing of the second processing device is temporarily stopped. The present invention according to claim 5 is Memory, A plurality of blocks including one or more processing devices that are access subjects that access the memory from the same port, the one or more processing devices being either or both of a first processing device that performs real-time processing and a second processing device that performs non-real-time processing; A bandwidth control device that performs bandwidth control, The bandwidth control device includes: In the block including both the first processing device and the second processing device, when a bandwidth allocated to the first processing device for accessing the memory in the first processing device is smaller than a predetermined first threshold, the bandwidth allocated to the second processing device included in the block for accessing the memory in the second processing device is limited. and increasing the bandwidth allocated to the first processing device. Bandwidth control is performed, When a bandwidth allocated to a port used by a processing device included in the block including the first processing device is smaller than a second predetermined threshold, the bandwidth allocated to the second processing device included in a block different from the first processing device is limited. and increasing the bandwidth allocated to the first processing device. The information processing device is characterized by performing bandwidth control. The present invention according to claim 6 is The information processing device according to claim 5, characterized in that when there are multiple second processing devices included in a block different from the block including the first processing device, the bandwidth control device selects one of the multiple second processing devices in a predetermined order, and sequentially limits the bandwidth allocated to the selected second processing devices. The present invention according to claim 7 is Each of the blocks realizes a specific function by one or more of the processing devices included in the block; 6. The information processing device according to claim 5, wherein the bandwidth control device controls the bandwidth allocated to the second processing device when processing in the specific function is temporarily stopped. The present invention according to claim 8 is The information processing device of claim 7, characterized in that the bandwidth control device controls the bandwidth allocated to the second processing device by changing the number of clocks required to transfer data between the second processing device and the memory. Effect of the Invention

[0009] According to the invention of claim 1, compared to a case where the bandwidth control is performed based on the settings and operating conditions of each device regardless of the connection structure between the memory and the device that is the subject of the access, When the bandwidth shortage of the first processing device cannot be resolved only by the bandwidth adjustment between devices using the same port, further bandwidth adjustment is performed. can be done. Claim 2 According to the present invention, it is possible to reduce the influence on the entire system compared to the case where the bandwidth used by unspecified second processing devices is restricted. Claim 3 According to the invention, compared to a method of stopping the second processing device or shortening the burst length, it is possible to control the bandwidth without causing unnecessary access while operating the second processing device. Claim 4 According to the present invention, compared to a method of stopping the second processing device or shortening the burst length, it is possible to control the bandwidth adjustment at the timing required while operating the second processing device. Claim 5 According to the invention, compared to a case where bandwidth control is performed based on the settings and operating conditions of each device regardless of the connection structure between the memory and the device that is the subject of access, When the bandwidth shortage of the first processing device cannot be resolved only by the bandwidth adjustment between the same blocks, further bandwidth adjustment is performed. can be done. Claim 6 According to the present invention, it is possible to reduce the influence on the entire system compared to the case where the bandwidth used by unspecified second processing devices is restricted. Claim 7According to the present invention, compared to a method of stopping the second processing device or shortening the burst length, it is possible to control the bandwidth adjustment at the timing required while operating the second processing device. Claim 8 According to the invention, compared to a method of stopping the second processing device or shortening the burst length, it is possible to control the bandwidth without causing unnecessary access while operating the second processing device. [Brief description of the drawings]

[0010] [Figure 1] 1 is a diagram showing a configuration of an information processing device to which a memory access system according to the present embodiment is applied. [Diagram 2] FIG. 1 is a diagram showing a system configuration of a memory access system according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram illustrating a configuration of a monitoring device. [Figure 4] FIG. 2 is a diagram illustrating a configuration of a band control device. [Diagram 5] FIG. 5 is a diagram showing the configuration of the gate unit. [Figure 6] 4 is a flowchart showing a procedure of bandwidth control by the bandwidth control device. [Figure 7] FIG. 13 is a diagram illustrating an example of setting the selection order of restriction target devices. [Figure 8] FIG. 1 is a diagram showing a connection structure between a processor and a memory based only on the distinction between a real-time system device and a non-real-time system device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. <Target device configuration> 1 is a diagram showing the configuration of an information processing device to which the memory access system according to this embodiment is applied. The information processing device 1 includes a plurality of functional blocks 10 (10A, 10B, and 10C in the configuration example shown in FIG. 1). The information processing device 1 also includes a CPU (Central Processing Unit) 20, a cache coherency interconnect 30, a memory controller 40, and a memory 50.

[0012] The functional block 10 includes one or more processing devices 11, 12, each of which individually realizes a specific function. The processing devices 11, 12 are divided into the processing device 11 as a real-time device that executes real-time processing, and the processing device 12 as a non-real-time device that executes non-real-time processing. Each functional block 10 may include both real-time and non-real-time devices, may include only real-time devices, or may include only non-real-time devices. Although not shown in FIG. 1, each functional block 10 is provided with a DMAC (DMA Controller) for executing DMA for each of the processing devices 11, 12.

[0013] The processing devices 11 and 12 included in each functional block 10 are the access subjects that access the memory 50 by DMA. Each processing device 11 and 12 directly accesses the memory 50 without going through the CPU 20 to read and write data. When one functional block 10 includes multiple processing devices 11 and 12, the memory access transmission paths of each processing device 11 and 12 are combined by an interconnect 13 (13A, 13B, and 13C in the configuration example shown in FIG. 1). In other words, when one functional block 10 includes multiple processing devices 11 and 12, each processing device 11 and 12 shares a memory access transmission path for each functional block 10. However, the number of memory access transmission paths of each functional block 10 is not limited to one. For example, in the configuration example shown in FIG. 1, the functional block 10C combines the transmission paths of the three processing devices 11 and 12 by the interconnect 13C to form two transmission paths.

[0014] The CPU 20 is one of the entities that access the memory 50. The CPU 20 controls the operation of the entire information processing device 1. The memory access transmission path of the CPU 20 is integrated with the transmission paths of other access entities as necessary. For example, in the configuration example shown in FIG. 1, the transmission path of the CPU 20 and one of the transmission paths of the functional block 10C are integrated by the cache coherency interconnect 30. Note that the CPU 20 is a type of real-time system device, and may be understood to constitute one functional block 10 (functional block 10 including only one real-time system device) by itself.

[0015] The cache coherency interconnect 30 is an interconnect that aggregates multiple transmission paths while maintaining the consistency (cache coherency) of multiple caches. For example, in the configuration example shown in Fig. 1, memory access is executed while maintaining the consistency between the cache of the CPU 20 and the cache of any of the processing units 11 and 12 included in the functional block 10C.

[0016] The memory controller 40 is a control device that controls the interface of the memory 50. The memory controller 40 has a plurality of ports, and is connected to the CPU 20 and each of the processing devices 11 and 12, which are the main devices that access the memory 50, via these ports. As described above, the memory access transmission paths of each of the processing devices 11 and 12 are grouped together for each functional block 10, so that each of the processing devices 11 and 12 is connected to a port for each functional block 10. Therefore, when one functional block 10 includes a plurality of processing devices 11 and 12, each of the processing devices 11 and 12 accesses the memory 50 using the same port of the memory controller 40.

[0017] 1, the transmission path of the functional block 10A and the transmission path of the functional block 10B each use one port of the memory controller 40. In addition, the transmission path of the CPU 20 and one of the transmission paths of the functional block 10C are combined by the cache coherency interconnect 30 and use one port of the memory controller 40. The other transmission path of the functional block 10C uses another port of the memory controller 40.

[0018] The memory 50 is a main memory of the information processing device 1. As the memory 50, for example, a double-data-rate synchronous dynamic random access memory (DDR SDRAM) or the like is used.

[0019] The information processing device 1 is a device that realizes various functions by a functional block 10. The functions realized by the functional block 10 are specified according to the type of the information processing device 1. As an example, with reference to Fig. 1, a functional configuration example will be described in which the information processing device 1 of this embodiment is applied to an image processing device that is comprehensively equipped with an image reading function for reading an image recorded on paper or the like, a printing function for printing an image on paper or the like, and the like.

[0020] In this example, the functional blocks 10 of the image processing device (information processing device 1) include an image reading (SCAN) block 10A, an image processing block 10B, and a print (PRINT) block 10C. Of these, the image reading block 10A and the print block 10C include both a processing device 11, which is a real-time device, and a processing device 12, which is a non-real-time device. The image processing block 10B includes only the processing device 12, which is a non-real-time device.

[0021] The image reading block 10A includes an image reading device 11a (indicated as "SCAN" in FIG. 1) which is a real-time device and a processing device 11, and a processing device 12a (indicated as "IP" in FIG. 1) which is a non-real-time device. The image reading device 11a is a device (scanner controller) that reads image data from an electric signal obtained by receiving light reflected from a paper sheet with a light receiving element. The process of reading this image data is a real-time process. The processing device 12a is a so-called IP (Intellectual Property) core, and is a device that executes non-real-time processes such as operation settings associated with the process by the image reading device 11a. In addition, the processing device 11 is also a kind of IP core in a higher-level concept, and hereinafter, the processing devices 11 and 12 may be referred to as IP without distinguishing them from each other. The memory access transmission paths of the image reading device 11a and the processing device 12a are integrated by an interconnect 13A to form a single transmission path in the image reading block 10A. This transmission path is connected to one port of the memory controller 40.

[0022] The image processing block 10B includes a processing device 12b and a processing device 12c (both of which are indicated as "IP" in FIG. 1) that are non-real-time devices. The processing device 12b and the processing device 12c are so-called IP cores, and are devices that perform various image processing such as filter processing and image conversion on the image read by the image reading block 10A and the image to be printed by the printing block 10C. This image processing is non-real-time processing. The image processing block 10B does not include a processing device 11 that performs real-time processing. The transmission paths for memory access of the processing device 12b and the processing device 12c are combined by an interconnect 13B to form a single transmission path in the image processing block 10B. This transmission path is connected to one port of the memory controller 40.

[0023] The print block 10C includes a display device 11b (indicated as "LCD" in FIG. 1) which is a real-time device and a processing device 11, a printer 11c (indicated as "PRINT" in FIG. 1) which is a real-time device and a processing device 11, and a processing device 12d (indicated as "IP" in FIG. 1) which is a non-real-time device. The display device 11b is a device (LCD controller) that displays images to be printed on paper. The process of displaying these images is a real-time process. The printer 11c is a device that prints images on a recording medium such as paper based on image data to be processed. The process of printing these images is a real-time process. The processing device 12d is a so-called IP core, and is a device that executes non-real-time processes such as operation settings associated with the processes by the display device 11b and the printer 11c. The transmission paths for memory access of the display device 11b, the printer 11c, and the processing device 12d are combined by an interconnect 13C to form two transmission paths in the print block 10C. One of these transmission paths is combined with the transmission path of the CPU 20 by the cache coherency interconnect 30 and is connected to one port of the memory controller 40. The other path is directly connected to another port of the memory controller 40.

[0024] <How to deal with insufficient transmission bandwidth in functional blocks> 8 is a diagram showing a connection structure between the processing devices 11, 12 and a memory 50 based only on the distinction between real-time and non-real-time devices, unlike this embodiment. In the configuration example shown in FIG. 8, the information processing device 2 includes three processing devices (SCAN, LCD, PRINT) 11 which are real-time devices, and four processing devices (IP) 12 which are non-real-time devices, similar to the information processing device 1 shown in FIG. 1. The information processing device 2 also includes a CPU 20, a memory controller 40, and a memory 50.

[0025] In the configuration example shown in Fig. 8, unlike the information processing device 1 shown in Fig. 1, the processing devices 11 and 12 are not divided into blocks for each function. However, each processing device 11 corresponds to the processing devices 11a to 11c shown in Fig. 1, and each processing device 12 corresponds to the processing devices 12a to 12d shown in Fig. 1. Therefore, in the operation of each function, each processing device 11 and 12 operates for each function, similar to the function blocks 10A to 10C shown in Fig. 1.

[0026] In the configuration example shown in FIG. 8, the transmission paths for memory access of the processing device 11 and the CPU 20, which are real-time devices, are each individually connected to a port of the memory controller 40. The transmission paths for memory access of the four processing devices 12, which are non-real-time devices, are combined into one by the interconnect 13 and connected to the port of the memory controller 40. In this configuration, when the bandwidth used for memory access is insufficient in any of the processing devices 11, the bandwidth used by the processing device 12 is restricted, and the allocation of the bandwidth used by the corresponding processing device 11 is increased. At this time, how much the bandwidth used for each processing device 12 is restricted is determined according to a rule that is predetermined based on, for example, the operating state of each processing device 12. In this case, even if the bandwidth used by any of the processing devices 11 is insufficient, the bandwidth used by the processing device 12 is restricted according to this rule and allocated to the processing device 11.

[0027] Here, consider a case where the same bandwidth control as described above is performed in the configuration of this embodiment shown in FIG. 1. As an example, when the bandwidth used by any of the processing devices 11 is insufficient, the bandwidths used are restricted in the order of the processing devices 12a, 12b, 12c, and 12d, and are assigned to the processing device 11. In this case, even if the bandwidth used by the processing device (printing device) 11c included in the functional block (printing block) 10C of the processing devices 11 is insufficient, the bandwidth used by the processing device 12 is restricted in this order. However, when the bandwidth used by the processing device 11c is insufficient, in the entire information processing device 1, a shortage of transmission bandwidth (so-called bottleneck) in memory access occurs inside the functional block 10C. Therefore, in order to resolve the shortage of bandwidth used by the processing device 11c, it is necessary to accommodate the bandwidth used between the processing devices 11 and 12 included in the functional block 10C. Specifically, the bandwidth used by the processing device 12d included in the functional block 10C must be restricted to increase the bandwidth used by the processing device 11c. In other words, based on the above rules, even if the bandwidth usage of the processing device 12a in the functional block 10A and the processing devices 12b and 12c in the functional block 10B is restricted prior to the processing device 12d, the bandwidth usage of the processing device 11c cannot be increased.

[0028] Next, consider a case where the shortage of the bandwidth used by the processing device 11c is not resolved even if the bandwidth used by the processing device 12d is limited and allocated to the processing device 11c. In this case, the transmission bandwidth allocated to the functional block 10C in the information processing device 1 is insufficient. Therefore, even if the bandwidth used is shared between the processing devices 11 and 12 included in the functional block 10C as described above, the shortage of the transmission bandwidth of the functional block 10C itself is not resolved. Therefore, in this case, the bandwidth used by the processing device 12a of the functional block 10A and the processing devices 12b and 12c of the functional block 10B is limited, thereby reducing the transmission bandwidth allocated to the functional block 10A and the functional block 10B, and increasing the allocation of the transmission bandwidth of the functional block 10C. Then, based on the transmission bandwidth of the functional block 10C whose allocation has been increased, the bandwidth used by the processing device 11c is further increased.

[0029] In this manner, in this embodiment, for each functional block 10, a device configuration is taken into consideration in which the processors 11, 12 used to realize the function of that functional block 10 access memory collectively, and the bandwidth used is accommodated within the functional block 10 as a first stage of bandwidth control. Then, if the first stage of bandwidth control is unable to resolve the shortage of transmission bandwidth of the target functional block 10, the allocation of transmission bandwidth between the target functional block 10 and other functional blocks 10 is changed as a second stage of bandwidth control.

[0030] <Configuration of memory access system 100> Fig. 2 is a diagram showing the system configuration of the memory access system of this embodiment. The memory access system 100 includes a monitoring device 110, a band control device 120, and a gate unit 130 provided for each of the processing devices 11 and 12. In Fig. 2, one function block 10 and the processing devices 11 and 12 included in the function block 10 are shown as objects to be controlled, but in reality, as shown in Fig. 1, control is performed for each of the processing devices 11 and 12 of each function block 10 in the information processing device 1.

[0031] The monitoring device 110 is a device that branches and captures inputs and outputs (access signals) of each port of the memory controller 40, and monitors accesses to the memory 50 by each accessing entity. As described with reference to FIG. 1, the entities that access the memory 50 are the processing devices 11, 12, and the CPU 20, but in the following, the CPU 20 will be described as a type of the processing device 11, which is a real-time device. The monitoring device 110 particularly grasps the access status to the memory 50 by the processing device 11, which is a real-time device. For this reason, a bus that can individually identify the accessing entities is used as a bus that connects the accessing entities to the memory 50 and the memory 50. An example of such a bus is a bus compatible with AXI (Advanced eXtensible Interface).

[0032] The bandwidth control device 120 sets control information for the processing device 12 that is the target of the bandwidth usage restriction in the bandwidth control based on the monitoring result by the monitoring device 110. In this embodiment, the bandwidth usage restriction of the processing device 12 is realized by controlling the throughput of the processing device 12. Therefore, the bandwidth control device 120 generates a throughput setting value for the processing device 12 to be controlled as the control information.

[0033] In this embodiment, as described above, the first stage of bandwidth control involves sharing the bandwidth between the processing devices 11 and 12 in the same functional block 10, and the second stage of bandwidth control involves sharing the bandwidth between different functional blocks 10. Therefore, when the bandwidth control device 120 performs control to deal with a shortage of bandwidth used by a certain processing device 11, it first generates a throughput setting value that reduces the throughput for the processing device 12 included in the same functional block 10 as the processing device 11. If the shortage of bandwidth used by the processing device 11 is not resolved even by this throughput control, the bandwidth control device 120 then controls the throughput setting value that reduces the throughput for the processing device 12 included in a functional block 10 different from the functional block 10 including the processing device 11.

[0034] The gate unit 130 is a device that sets the throughput of the processing device 12 to be controlled by the throughput setting value generated by the bandwidth control device 120. The gate unit 130 is provided between each of the processing devices 11, 12 and the DMAC 14 corresponding to each of the processing devices 11, 12. The DMAC 14 is a DMA controller that executes DMA from each of the processing devices 11, 12 to the memory 50.

[0035] <Configuration of monitoring device 110> 3 is a diagram showing the configuration of the monitoring device 110. The monitoring device 110 includes a filter 111, a port counter 112, a real-time device counter 113, a total bandwidth counter 114, and a counter information transmission unit 115. An access signal for each port of the memory controller 40 input to the monitoring device 110 is sent to a counter group provided corresponding to each port, and the number of accesses is counted.

[0036] The filter 111 identifies and extracts the access signal of each processing device 11, which is a real-time device, from the access signal for each port of the memory controller 40. As described with reference to FIG. 1, in this embodiment, the processing devices 11 and 12 are grouped together for each functional block 10 and connected to one port of the memory controller 40. Therefore, the access signal for each port of the memory controller 40 is an access signal by the processing devices 11 and 12 for each functional block 10. Therefore, the filter 111 identifies and extracts the access signal of each processing device 11 included in each functional block 10 from the access signal for each functional block 10. When a bus corresponding to AXI is used as a bus for accessing the memory 50 in the information processing device 1, the access signal passing through the bus is assigned with identification information of the access subject that outputs the access signal. The filter 111 identifies the access signal of the processing device 11 as the access subject by this identification information.

[0037] The port counter 112 counts the number of accesses for each functional block 10 connected to each port, based on the access signal for each port of the memory controller 40. The real-time system device counter 113 counts the number of accesses for each processing device 11 corresponding to each filter 111, based on the access signal extracted by each filter 111 from the access signal for each port of the memory controller 40. The total bandwidth counter 114 counts the number of accesses to the memory 50 by all access subjects of the information processing device 1, based on all access signals input / output to / from each port of the memory controller 40.

[0038] In the example shown in FIG. 3, inputs and outputs of ports 0, 1, . . . , n of the memory controller 40 are taken into the monitoring device 110. Although not shown in the figure, it is assumed that m+1 processing devices 11 divided into a plurality of functional blocks 10 as shown in FIG. 1 are connected to the memory controller 40. The access signals taken into the monitoring device 110 are sent to a counter group provided for each port corresponding to the functional block 10 using each port. Here, in the example shown in FIG. 3, the functional block 10 using port 0 includes two processing devices 11, and these processing devices 11 are designated as IP0 and IP1. It is also assumed that no processing device 11 exists in the functional block 10 using port 1 (only the processing device 12 exists). It is also assumed that the functional block 10 using port n includes one processing device 11, and this processing device 11 is designated as IPm.

[0039] In the example shown in FIG. 3, an access signal captured from port 0 is sent to a port-specific counter 112 corresponding to port 0 (referred to as "port 0 counter" in FIG. 3) and is also branched and sent to two filters 111 corresponding to IP0 and IP1 (referred to as "IP0 filter" and "IP1 filter" in FIG. 3). Then, the filter 111 corresponding to IP0 extracts an access signal of IP0 and sends it to a real-time system device-specific counter 113 corresponding to IP0 (referred to as "IP0 counter" in FIG. 3). Also, the filter 111 corresponding to IP1 extracts an access signal of IP1 and sends it to a real-time system device-specific counter 113 corresponding to IP1 (referred to as "IP1 counter" in FIG. 3). The port-specific counter 112 corresponding to port 0 counts the number of accesses from all the processing devices 11 and 12 of the functional block 10 using port 0. Also, the real-time system device-specific counter 113 corresponding to IP0 counts the number of accesses from IP0 among the processing devices 11 and 12 of the functional block 10 using port 0. The port counter 112 corresponding to port 1 counts the number of accesses from all the processors 12 of the functional block 10 that use port 1.

[0040] Similarly, the access signal received from port 1 is sent to the port counter 112 (indicated as "port 1 counter" in FIG. 3) corresponding to port 1. Since the functional block 10 using port 1 does not have a processing device 11, the filter 111 that receives the access signal received from port 1 and the real-time system device counter 113 are not provided. The port counter 112 corresponding to port 1 counts the number of accesses from all processing devices 12 of the functional block 10 using port 1.

[0041] In addition, the access signal captured from port n is sent to a port-specific counter 112 corresponding to port n (referred to as "port n counter" in FIG. 3) and also branches off and is sent to one filter 111 corresponding to IPm (referred to as "IPm filter" in FIG. 3). Then, the filter 111 corresponding to IPm extracts the access signal of IPm and sends it to a real-time system device-specific counter 113 corresponding to IPm (referred to as "IPm counter" in FIG. 3). The port-specific counter 112 corresponding to port n counts the number of accesses from all the processing devices 11, 12 of the functional block 10 that use port n. In addition, the real-time system device-specific counter 113 corresponding to IPm counts the number of accesses from IPm among the processing devices 11, 12 of the functional block 10 that use port n.

[0042] The counter information transmission unit 115 transmits various count values ​​(number of accesses) counted by the counters 112, 113, and 114 to the bandwidth control device 120 by inter-device communication. The counter information transmission unit 115 is realized by, for example, a bus interface corresponding to a bus connecting the monitoring device 110 and the bandwidth control device 120.

[0043] As described above, in this embodiment, the number of accesses of the processing device 12, which is a non-real-time device, is not directly counted. However, the total number of accesses by the processing device 12 included in the functional block 10 using each port can be calculated from the count value of the port counter 112 and the count value of the real-time device counter 113. In addition, the counter group corresponding to the port used by the functional block 10 including only real-time devices includes the port counter 112 and the real-time device counter 113. The sum of the count value of the port counter 112 and the count value of the real-time device counter 113 is the same value. Note that the configuration of the monitoring device 110 described with reference to FIG. 3 is merely an example, and may be configured to include, for example, a filter that extracts an access signal of the processing device 12, which is a non-real-time device, and a counter that counts the number of accesses of the processing device 12.

[0044] <Configuration of Bandwidth Control Device 120> 4 is a diagram showing the configuration of the band control device 120. The band control device 120 includes a plurality of operation flag storage units 121, a counter information receiving unit 122, a band calculation unit 123, a setting determination unit 124, a threshold information storage unit 125, a setting value transmission unit 126, and a setting value storage unit 127.

[0045] The operation flag storage unit 121 stores an operation flag indicating the operation state of the processing device 11 (IP) of the real-time system device which is the subject of access to the memory 50 and is the target of bandwidth control. The operation flag storage unit 121 is provided in association with each processing device 11. In the example shown in Fig. 4, the number of processing devices 11 is m+1, and operation flag storage units 121 corresponding to IP0, IP1, ..., IPm respectively (in the figure, they are written as "IP0 operation flag storage unit", "IP1 operation flag storage unit", "IPm operation flag storage unit") are shown.

[0046] The operation flag indicates whether the corresponding processing device 11 is in operation or not. The bandwidth used by the processing device 11 cannot be changed while the processing device 11, which is a real-time device, is executing a process. Therefore, the bandwidth control device 120 judges whether the processing device 11 is executing a process or not based on the operation flag stored in the operation flag storage unit 121, and executes bandwidth control at the timing when the processing by the processing device 11 temporarily stops. As a specific example, in an image reading (scanning) process or a printing process, if processing is executed (active) for each row (main scanning) of a scanning line and the processing stops (inactive) to move to the next row (sub-scanning), the bandwidth control is executed when it becomes inactive.

[0047] The counter information receiving unit 122 receives access information of the processing devices 11 and 12 from the monitoring device 110 through inter-device communication. The bandwidth calculating unit 123 calculates the bandwidth used by the processing devices 11 and 12 to be controlled, using the access information of the processing devices 11 and 12 acquired by the counter information receiving unit 122. Specifically, for example, the transmission bandwidth of each functional block 10 using each port is obtained based on the number of accesses to the memory 50 by all access subjects of the information processing device 1 and the number of accesses for each port of the memory controller 40. Then, the bandwidth used by each processing device 11 is obtained based on the number of accesses for each port of the memory controller 40, the transmission bandwidth of each functional block 10, and the number of accesses of each processing device 11. In addition, the total bandwidth used by the processing device 12 for each functional block 10 is obtained based on the transmission bandwidth for each functional block 10 and the bandwidth used by each processing device 11 included in each functional block 10.

[0048] The setting determination unit 124 determines the current bandwidth setting of each processing device 11 and each functional block 10 based on the bandwidth used by each processing device 11 and the transmission bandwidth of each functional block 10 calculated by the bandwidth calculation unit 123. The bandwidth setting is determined by comparing the calculated values ​​of the bandwidth used by each processing device 11 and the transmission bandwidth of each functional block 10 with a predetermined threshold. When the setting determination unit 124 determines that the bandwidth used for any of the processing devices 11 is insufficient, it generates a throughput setting value for the processing of the processing device 12 to limit the bandwidth used by the processing device 12 and eliminate the insufficient bandwidth used by the processing device 11. The generation of the throughput setting value will be described later in detail.

[0049] Furthermore, the setting determination unit 124 determines the operating state of the processing device 11 that is the target of bandwidth control by referring to the operation flag stored in the operation flag storage unit 121. Then, the setting determination unit 124 outputs a switching signal for switching the throughput setting value of the processing device 12 that is applied to perform the bandwidth control of the processing device 11 at the timing when the processing by the processing device 11 that is the target of control becomes inactive.

[0050] The threshold information storage unit 125 holds thresholds used by the setting determination unit 124 to determine the current bandwidth settings of each processing device 11 and each functional block 10. The thresholds provided are a first threshold used to determine the bandwidth used by the processing device 11 when bandwidth control is performed between the processing devices 11 and 12 in the same functional block 10, and a second threshold used to determine the transmission bandwidth of the functional block 10 when bandwidth control is performed between different functional blocks 10. The threshold information storage unit 125 is realized by, for example, a ROM (Read Only Memory).

[0051] The setting value transmission unit 126 transmits the throughput setting value generated by the setting determination unit 124 to the gate unit 130 added to the processing device 12 to be limited in the bandwidth used, by device-to-device communication. The setting value transmission unit 126 also transmits the switching signal output from the setting determination unit 124 to the processing device 12 to be controlled. The setting value storage unit 127 holds the throughput setting value generated by the setting determination unit 124.

[0052] In the bandwidth control device 120, the operation flag storage unit 121 and the setting value storage unit 127 are realized, for example, by a static random access memory (SRAM). The counter information receiving unit 122 is realized, for example, by a bus interface corresponding to a bus connecting the monitoring device 110 and the bandwidth control device 120. The bandwidth calculation unit 123 and the setting determination unit 124 are realized, for example, by a processor such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The threshold information storage unit 125 is realized, for example, by a read only memory (ROM). The setting value transmission unit 126 is realized, for example, by a bus interface corresponding to a bus connecting the bandwidth control device 120 and the gate unit 130.

[0053] <Configuration of Gate Unit 130> FIG. 5 is a diagram showing the configuration of the gate unit 130. FIG. 5 shows the positioning of the gate unit 130 with respect to the processing by the processing device 12, which is a non-real-time device, and the DMA control operation by the DMAC 14, rather than the physical connection relationship between the gate unit 130 and other devices. In the example shown in FIG. 5, the processing device 12 reads data to be processed, and sequentially executes processes 1 to n on the read data. Here, each of processes 1 to n is performed for each minimum unit of data to be processed (hereinafter referred to as a "processing unit"). Furthermore, processes 1 to n may be executed in parallel, for example, by pipeline processing. Then, the processing device 12 writes the data resulting from the processing to the memory 50.

[0054] As a specific example, when the processing device 12 executes image processing (filter processing on an image, etc.), the processing device 12 shown in Fig. 5 reads data for n pixels and performs image processing for n pixels one pixel at a time (processing 1 to processing n). In this case, data for one pixel is the processing unit.

[0055] Data reading in the processing device 12 is performed under the control of the DMAC 14 (indicated in FIG. 5 by an arrow from the DMAC 14 on the left side to process 1). Data writing from the processing device 12 to memory 50 is performed under the control of the DMAC 14 (indicated in FIG. 5 by an arrow from process n through gate unit 130 to the DMAC 14 on the right side). Therefore, the two DMACs 14 shown in FIG. 5 are actually one DMAC 14 (see FIG. 2) that reads and writes data from and to memory 50.

[0056] As shown in FIG. 5, the gate unit 130 is interposed between the processing device 12 and the DMAC 14, and controls the throughput of the processing result of the processing device 12 and sends it to the DMAC 14. The gate unit 130 includes an information storage unit 131 and a control timer 132. The gate unit 130 receives a throughput setting value generated by the bandwidth control device 120, and controls the output timing of data of the processing result by the processing device 12 according to the received throughput setting value. This controls the bandwidth used in memory access by the processing device 12. The gate unit 130 also receives a switching signal output from the bandwidth control device 120. The gate unit 130 switches the throughput at the timing when the switching signal is input.

[0057] The information storage unit 131 stores and holds the throughput setting value received from the bandwidth control device 120. The information storage unit 131 is realized by, for example, an SRAM. The throughput setting value stored in the information storage unit 131 is information indicating the output interval of the processing result of the processing device 12 in terms of the number of clocks. The control timer 132 measures the time (number of clocks) for controlling the output interval of the processing result of the processing device 12 based on the throughput setting value stored in the information storage unit 131 and the clock signal.

[0058] In the example shown in FIG. 5, the throughput setting value stored in the information storage unit 131 sets the number of clocks per processing unit to N clocks (clk). Then, each of the processes 1 to n is executed at one clock per processing unit. In this case, in each data transfer between the DMAC 14, the process 1, the process 2, ..., the process n, and the gate unit 130, data of one processing unit is transferred per clock. And, data transfer from the gate unit 130 to the DMAC 14 transfers data of one processing unit per N clocks. As a result, the bandwidth used in memory access by the processing device 12 becomes 1 / N of that in the case where control by the throughput setting value is not performed.

[0059] <Operation of Bandwidth Control Device 120> 6 is a flowchart showing the procedure of bandwidth control by the bandwidth control device 120. The bandwidth control device 120 first focuses on one of the multiple processing devices 11 constituting the information processing device 1, and checks whether the focused processing device 11 is in operation. In the following explanation of the operation, the focused processing device 11 is called "IP(x)". Note that "x" in IP(x) is a value satisfying 0≦x≦m. IP(x) indicates that it is any one of IP0 to IPm, which are the processing devices 11 described with reference to FIGS. 3 and 4.

[0060] If IP(x), which is the processing device 11 of interest, is not in operation (NO in S601), there is no need to perform bandwidth control, so the current bandwidth setting is maintained (S602). On the other hand, if IP(x) is in operation (YES in S601), the bandwidth control device 120 checks whether the current bandwidth used by IP(x) is greater than a first threshold. The first threshold is a threshold set to determine whether to limit the bandwidth used by the processing device 12 in the same functional block 10 as IP(x) for bandwidth control of IP(x). The first threshold set for the bandwidth used in memory access of the processing device 11 is an example of an individual control condition.

[0061] If the bandwidth used by IP(x) is greater than the first threshold (YES in S603), there is no need to increase the bandwidth used by IP(x). Therefore, the current bandwidth setting is maintained (S602). On the other hand, if the bandwidth used by IP(x) is equal to or less than the first threshold (NO in S603), it is necessary to further increase the bandwidth used by IP(x). Therefore, the bandwidth control device 120 next checks whether the current bandwidth used by IP(x) is greater than the second threshold. The second threshold is a threshold set to determine whether to limit the transmission bandwidth of the functional block 10 different from IP(x) for the bandwidth control for IP(x). The second threshold is a value smaller than the first threshold. The second threshold set for the bandwidth used in the memory access of the processing device 11 is an example of an overall control condition.

[0062] If the bandwidth used by IP(x) is greater than the second threshold (YES in S604), then in order to increase the bandwidth used by IP(x), it is sufficient to simply limit the bandwidth used by the processing device 12 in the same functional block 10 as IP(x). Thus, the bandwidth control device 120 selects a processing device 12 for which the bandwidth used is to be limited from among the processing devices 12 in the same functional block 10 as IP(x), and generates a throughput setting value for lowering the throughput for the selected processing device 12. This performs bandwidth control within the functional block 10 including IP(x) (S605).

[0063] When the bandwidth used by IP(x) is equal to or less than the second threshold (NO in S604), in order to increase the bandwidth used by IP(x), it is not enough to limit the bandwidth used by the processing device 12 in the same functional block 10 as IP(x), but it is necessary to limit the transmission bandwidth of different functional blocks 10. Therefore, in addition to the bandwidth control for the processing device 12 in the same functional block 10 as IP(x) as the limitation target device, the bandwidth control device 120 selects a processing device 12 to limit the bandwidth used among the processing devices 12 in the functional block 10 different from IP(x), and generates a throughput setting value for lowering the throughput for the selected processing device 12. As a result, the bandwidth control is performed in the entire system of the information processing device 1, which shares the bandwidth used between the functional blocks 10 (S606).

[0064] In the above operation example, in S604, the bandwidth used by IP(x) is compared with the first threshold and the second threshold, and depending on the comparison result, the bandwidth control is performed in the functional block 10 including IP(x) or the entire system. In contrast, for IP(x) with a bandwidth shortage, the bandwidth control may be performed in the same functional block 10 first, and if the bandwidth shortage of IP(x) is not resolved, the bandwidth control may be performed again for a functional block 10 different from IP(x). In addition, in the above operation example, both the first threshold and the second threshold are set for the bandwidth used by IP(x). In contrast, the second threshold may be set for the transmission bandwidth of the functional block 10 itself including IP(x), and the bandwidth control may be performed in the entire system when the transmission bandwidth of the port of the memory controller 40 to which the functional block 10 is connected is equal to or less than the second threshold.

[0065] <Specific example of a method for selecting the processing device 12 to be limited in bandwidth usage> In the operations of S605 and S606 in Fig. 6, the bandwidth control device 120 generates a throughput setting value by selecting a processing device 12 for which the bandwidth usage is to be limited (hereinafter referred to as a "restriction target device"). An example of a method for selecting a restriction target device will be described. Here, an example of selecting a restriction target device will be described for the case where the bandwidth usage of the image reading device 11a, which is the processing device 11 in the image reading block 10A, is insufficient, and the case where the bandwidth usage of the printing device 11c, which is the processing device 11 in the printing block 10C, is insufficient, in the device configuration shown in Fig. 1.

[0066] As an example, the order (selection order) of the processing devices 12 to be selected as the restriction target devices is determined in advance according to the type of the processing device 11 that is lacking in the bandwidth used. In this embodiment, the first stage of bandwidth control involves sharing the bandwidth used within the functional block 10, and the second stage of bandwidth control involves changing the allocation of the transmission bandwidth between the functional block 10 and the processing device 11 that is lacking in the bandwidth used. Therefore, in the first stage of bandwidth control, if there are multiple processing devices 12 in the same functional block 10 as the processing device 11 that is lacking in the bandwidth used, the selection order of the multiple processing devices 12 as the restriction target devices is determined in advance. Also, in the second stage of bandwidth control, if there are multiple processing devices 12 in a functional block 10 different from the processing device 11 that is lacking in the bandwidth used, the selection order of the multiple processing devices 12 as the restriction target devices is determined in advance. Note that the method of determining the selection order of the restriction target devices is not particularly limited. For example, the selection order may be determined so that the processing devices 12 that are least loaded during the operation of the functional block 10 are selected as the restriction target devices in descending order.

[0067] Furthermore, when there are multiple functional blocks 10 different from the processing device 11 with insufficient bandwidth, a selection order of the functional blocks 10 to be selected as the restriction target device may be determined in order to specify which functional block 10 to select as the restriction target device. In this case, the selection order may be determined so that the functional block 10 that does not have the processing device 11 that is a real-time device is selected first. Also, the selection order may be determined so that the functional block 10 that is not executed in parallel during the operation of the functional block 10 including the processing device 11 with insufficient bandwidth is selected first.

[0068] FIG. 7 is a diagram showing an example of the selection order of restriction target devices. The band control device 120 may hold a table as shown in FIG. 7 and refer to it when selecting restriction target devices. In the example shown in FIG. 7, the selection order of restriction target devices is shown for each of the cases of performing the first-stage band control for the image reading device 11a of the image reading block 10A shown in FIG. 1, performing the first-stage band control for the printing device 11c of the printing block 10C, and performing the second-stage band control. In the example shown in FIG. 7, the subscripts a to d are used to the reference characters of the processing devices 12a to 12d shown in FIG. 1, and each processing device 12 is described as "IP(a)", "IP(b)", "IP(c)", and "IP(d)". For example, IP(a) in FIG. 7 corresponds to the processing device 12a shown in FIG. 1.

[0069] Furthermore, in this example, when performing the second stage bandwidth control, the processing devices 12b and 12c (IP(b) and IP(c) in FIG. 7) of the image processing block 10B, which does not have the processing device 11, which is a real-time device, are selected first as devices to be restricted. Since the image processing block 10B has two processing devices 12b and 12c, the selection order as devices to be restricted is also determined for these processing devices 12b and 12c. Furthermore, in the example shown in FIG. 7, the processing device 12b (IP(b)) and processing device 12c (IP(c)) are selected as devices to be restricted in that order.

[0070] 1 and 7, when the available bandwidth of the image reading device 11a, which is the processing device 11 of the image reading block 10A, is insufficient, the bandwidth control device 120 first performs a first stage of bandwidth control on the image reading block 10A. In this case, the bandwidth control device 120 selects the processing device 12a (IP(a)) of the same image reading block 10A as the image reading device 11a as the device to be restricted.

[0071] If the bandwidth shortage of the image reading device 11a is not resolved even by the first-stage bandwidth control, the bandwidth control device 120 performs a second-stage bandwidth control on the image processing block 10B. In this case, the bandwidth control device 120 first selects the processing device 12b (IP(b)) as the device to be restricted from among the processing devices 12b and 12c of the image processing block 10B in the selection order shown in Fig. 7. If the bandwidth shortage of the image reading device 11a is not resolved even by the bandwidth control with the processing device 12b as the device to be restricted, the bandwidth control device 120 selects the processing device 12c (IP(c)) as the device to be restricted.

[0072] If the bandwidth shortage of the image reading device 11a is not resolved even by bandwidth control with the processing device 12c as the device to be restricted, the bandwidth control device 120 performs a second stage of bandwidth control with the printing block 10C as the remaining functional block 10. In this case, the bandwidth control device 120 selects the processing device 12d (IP(d)) of the printing block 10C as the device to be restricted.

[0073] 1 and 7, when the available bandwidth of the printing device 11c, which is the processing device 11 of the printing block 10C, is insufficient, the bandwidth control device 120 first performs the first stage of bandwidth control on the printing block 10C. In this case, the bandwidth control device 120 selects the processing device 12d (IP(d)) of the same printing block 10C as the printing device 11c as the device to be restricted.

[0074] If the bandwidth shortage of the printer 11c is not resolved by the first-stage bandwidth control, the bandwidth control device 120 performs a second-stage bandwidth control on the image processing block 10B. In this case, as in the case of the bandwidth control for the bandwidth shortage of the image reading device 11a, the bandwidth control device 120 first selects the processing device 12b (IP(b)) as the device to be restricted. Then, if the bandwidth shortage of the printer 11c is not resolved by the bandwidth control for the processing device 12b as the device to be restricted, the bandwidth control device 120 selects the processing device 12c (IP(c)) as the device to be restricted.

[0075] If the shortage of available bandwidth of the printer 11c is not resolved even by bandwidth control with the processing device 12c as the device to be restricted, the bandwidth control device 120 performs a second stage of bandwidth control with the image reading block 10A as the remaining functional block 10. In this case, the bandwidth control device 120 selects the processing device 12a (IP(a)) of the image reading block 10A as the device to be restricted.

[0076] In the examples shown in Figures 1 and 7, the image reading block 10A and the printing block 10C, which have the processing device 11 that is a real-time device, each have only one processing device 12 that is a non-real-time device. Therefore, in the first stage of bandwidth control, the processing device 12 to be selected as the device to be restricted is specified. In contrast, when multiple processing devices 12 exist in the same functional block 10 as the processing device 11 that has a shortage of available bandwidth, the selection order of the processing devices to be restricted is preset, similar to the processing devices 12b and 12c shown in Figure 7.

[0077] In the example shown in FIG. 1 and FIG. 7, there are only two functional blocks 10 having a processing device 11, which is a real-time device, and only one functional block 10 having no processing device 11. Therefore, when performing the second-stage bandwidth control, the functional blocks 10 having no processing device 11 are first selected as restriction target devices, and when performing further bandwidth control, the remaining functional blocks 10 having processing devices 11 are selected as restriction target devices. In contrast, when there are multiple functional blocks 10 having no processing device 11, the order of the functional blocks 10 from which the bandwidth control device 120 selects the control target devices is determined in advance. Similarly, when there are three or more functional blocks 10 having processing devices 11, the order of the functional blocks 10 from which the bandwidth control device 120 selects the control target devices is determined in advance. In addition, when performing the second-stage bandwidth control, instead of selecting a restriction target device for each functional block 10, the selection order of the restriction target devices may be determined for the processing devices 12 of all functional blocks 10 other than the processing device 11 whose bandwidth is insufficient.

[0078] Although the embodiment of the present invention has been described above, the technical scope of the present invention is not limited to the above embodiment. For example, in the above embodiment, the selection order of the restriction target device was described with reference to the table shown in FIG. 7, but the band control device 120 may select the restriction target device with reference to the table shown in FIG. 7, or may select the restriction target device according to a predetermined rule without preparing such a table. In addition, in the configuration example shown in FIG. 1, an example of applying this embodiment to an image processing device is shown, but this embodiment is not limited to the example shown in FIG. 1 and may be applied to various information processing devices having multiple function blocks 10 provided for each function. In addition, various modifications and alternative configurations that do not deviate from the scope of the technical idea of ​​the present invention are included in the present invention. [Explanation of symbols]

[0079] 1, 2...information processing device, 10...functional block, 11, 12...processing device, 13...interconnect, 14...DMAC, 20...CPU, 30...cache coherency interconnect, 40...memory controller, 50...memory, 100...memory access system, 110...monitoring device, 111...filter, 112...port counter, 113...real-time device counter, 114...total bandwidth counter, 115...counter information transmitter, 120...bandwidth control device, 121...operation flag storage unit, 122...counter information receiver, 123...bandwidth calculation unit, 124...setting judgment unit, 125...threshold information storage unit, 126...setting value transmitter, 127...setting value storage unit, 130...gate unit, 131...information storage unit, 132...control timer

Claims

1. a first processing device which is one of the devices that access the memory and performs real-time processing; a second processing device which is one of the entities that access the memory and performs non-real-time processing; A bandwidth control device that performs bandwidth control, The bandwidth control device includes: when a bandwidth allocated to any one of the first processing devices for accessing the memory is smaller than a first threshold value, performing bandwidth control to limit a bandwidth allocated to a specific second processing device using the same port as the first processing device for accessing the memory and to increase a bandwidth allocated to the first processing device; A memory access system characterized in that, when the bandwidth allocated to the specific second processing device is restricted and the bandwidth allocated to the first processing device using the same port as the specific second processing device is smaller than a second threshold value, bandwidth control is performed to restrict the bandwidth allocated to the second processing device using a port different from the specific second processing device and increase the bandwidth allocated to the first processing device.

2. 2. The memory access system according to claim 1, characterized in that, when there are multiple second processing devices using ports different from the specific second processing device, the bandwidth control device selects one of the multiple second processing devices in a predetermined order, and sequentially limits the bandwidth allocated to the selected second processing device.

3. 2. The memory access system according to claim 1, wherein the bandwidth control device controls the bandwidth allocated to the second processing device by changing the number of clocks required to transfer data between the second processing device and the memory.

4. 4. The memory access system according to claim 3, wherein the bandwidth control device changes the number of clocks required to transfer the data in the second processing device when processing of the second processing device that is the subject of bandwidth control is temporarily stopped.

5. Memory, a plurality of blocks including one or more processing devices that are access subjects that access the memory from a same port, the one or more processing devices being either or both of a first processing device that performs real-time processing and a second processing device that performs non-real-time processing; A bandwidth control device that performs bandwidth control, The bandwidth control device includes: performing bandwidth control in the block including both the first processing device and the second processing device, when a bandwidth allocated to the first processing device for accessing the memory in the first processing device is smaller than a predetermined first threshold, by limiting a bandwidth allocated to the second processing device included in the block for accessing the memory and increasing a bandwidth allocated to the first processing device; An information processing device characterized in that, in the block including the first processing device, when the bandwidth allocated for transmission to a port used by the processing device included in the block is smaller than a predetermined second threshold, the information processing device performs bandwidth control to limit the bandwidth allocated to the second processing device included in a block different from the first processing device and to increase the bandwidth allocated to the first processing device.

6. The information processing device according to claim 5, characterized in that, when there are multiple second processing devices included in a block different from the block including the first processing device, the bandwidth control device selects one of the multiple second processing devices in a predetermined order, and sequentially limits the bandwidth assigned to the selected second processing device.

7. Each of the blocks realizes a specific function by one or more of the processing devices included in the block; 6. The information processing apparatus according to claim 5, wherein said bandwidth control device controls the bandwidth allocated to said second processing apparatus when the processing in said specific function is temporarily stopped.

8. 8. The information processing device according to claim 7, wherein the bandwidth control device controls the bandwidth allocated to the second processing device by changing the number of clocks required to transfer data between the second processing device and the memory.

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