Method and system for buck converter current reuse - Patents.com

Abstract

The step-down voltage converter includes a high-side switch (412), a low-side switch (414), a capacitor (418), an inductor (416), a gate driver circuit (342) having outputs coupled to the gate terminals of the high-side switch and the low-side switch, and a separate voltage regulator circuit that powers the circuit elements in the step-down voltage converter (430). The voltage regulator circuit includes a multiplexer (440) having a first multiplexer input coupled to the input voltage source (390), a second multiplexer input coupled to the step-down output of the step-down voltage converter (392), and one or more multiplexer control inputs that select which of the two multiplexer inputs is coupled to the multiplexer output, and a pass transistor (446) having a first terminal coupled to the multiplexer output and a second terminal coupled to a regulator output (480) of the voltage regulator.

Description

[Technical field]

[0001] A buck converter is a DC-DC power converter that steps down or reduces the voltage between its input from a mains power source and its output while boosting the current. It is used in circuits that require a DC output voltage lower than the DC input voltage. It is a switched mode power supply typically composed of at least two semiconductors, which can be two transistors that form a high-side switch that is coupled to the supply voltage and a low-side switch that is coupled to ground. It also consists of at least one energy storage element, which can be a capacitor or an inductor, or a combination of the two, that stores energy during high-side conduction and discharges during low-side conduction. [Background technology]

[0002] During the on-period of the high-side transistor, current flows through the inductor to the load. The inductor reacts to oppose the change in current flow and also stores energy. A switching transistor between the input and output nodes of the buck converter switches on and off continuously at high frequency, alternating between the supply voltage and ground. To maintain a continuous output, the circuit uses the energy stored in the inductor during the on-period of the high-side switch and filters it to smooth out the ripple.

[0003] In switching operation, buck converters have two modes: discontinuous conduction mode (DCM) and continuous conduction mode (CCM). In DCM, there is a period when the inductor is fully discharged and the current is cut off, while CCM is characterized by the absence of a period when the inductor current is zero. CCM is more commonly used in DC-DC converters because it reduces the output ripple voltage and harmonics resulting from discontinuities in the current flow.

[0004] In CCM, when the high-side switch is off and the low-side switch is on, a reverse current flows from the energy stored in the inductor for the reverse recovery time. In CCM, one of the two switches is always on, so there is no period during which the inductor current becomes zero.

[0005] Design considerations for a buck converter include maintaining an accurate output voltage within acceptable tolerances, minimizing ripple voltage on the output, maximizing the power efficiency of the converter by comparing the delivered output power to the supplied input power, maintaining a minimum switching frequency to avoid interference with adjacent circuit elements, and avoiding runaway of the output voltage. The last two requirements can sometimes conflict with each other at very light loads, because the minimum switching frequency means that power must be continuously returned to the circuit due to the minimum on-time of the switch. This can lead to a situation where energy continues to accumulate without dissipation from the load, causing the output voltage to continue to rise until it reaches a runaway condition. Summary of the Invention

[0006] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description, including the drawings provided. This Summary is not intended to limit the scope of the claimed subject matter.

[0007] The described embodiments include a DC-DC buck converter with a guaranteed minimum switching frequency during pulse skip mode and a method for preventing output voltage runaway at zero load current by means of reusing energy that would be wasted to supply an internal low buck regulator (LDO) as an equivalent dummy load for the buck converter.

[0008] One example of the present invention is a step-down voltage converter operating in pulse skip mode including a high-side switch having a first terminal coupled to an input voltage source, an inductor having a first terminal coupled to the second terminal of the high-side switch and a second terminal coupled to an output of the step-down voltage converter, the step-down voltage converter further including a low-side switch having a first terminal coupled to ground and a second terminal coupled to the first terminal of the inductor and to the second terminal of the high-side switch, a capacitor having a first terminal coupled to the output of the step-down voltage converter and a second terminal coupled to ground, a gate driver circuit that receives an input from the state machine and has an output coupled to a gate terminal of the high-side switch and a gate terminal of the low-side switch, and a voltage regulator circuit that powers circuit elements internal to the step-down voltage converter.

[0009] The internal voltage regulator includes a multiplexer having a multiplexer output, a first input from a supply voltage source, a second input from the step-down voltage converter output, one or more control outputs derived from comparing a difference between the output of the step-down voltage converter and an input voltage source that controls the selection of which input should be coupled to the output, and a pass transistor having a first terminal coupled to the output of the multiplexer and a second terminal coupled to the output of the internal voltage regulator, wherein the output of the internal voltage regulator circuit is the sole power supply for the state machine circuitry and the internal logic circuitry of the step-down voltage converter. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 shows a block diagram for an example of a current-mode controlled DC-DC buck converter operating in CCM only.

[0011] [Figure 2A] 1 shows voltage and current waveforms plotted as a function of time for a PSM scheme in burst mode at no load.

[0012] [Figure 2B]1 shows voltage and current waveforms plotted as a function of time for a no-load PSM scheme.

[0013] [Figure 2C] 1 shows voltage and current waveforms plotted as a function of time for a PSM scheme with a dummy load.

[0014] [Diagram 3] 1 shows a block diagram for an example of the claimed buck converter with an internally powered logic LDO.

[0015] [Figure 4] 1 shows a simplified representation for an example of the claimed buck converter with an internally powered logic LDO.

[0016] [Diagram 5] 1 shows a schematic diagram for a logic LDO block of the claimed buck converter with an internally powered LDO.

[0017] [Figure 6] 1 illustrates a simplified state diagram for an example of an asynchronous converter state machine for a logic LDO block of a buck converter with an internally powered LDO.

[0018] In the various drawings, like reference numerals refer to like elements. Details of one or more implementations of the present disclosure are set forth in the accompanying drawings and the following description. The figures are not drawn to scale and are provided merely to illustrate the present disclosure. Specific details, relationships, and methods are described to provide an understanding of the present disclosure. Other features and advantages may be apparent from the description and drawings, and from the claims. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] FIG. 1 illustrates an example DC-DC step-down converter. The step-down converter includes an input voltage source 110, which may be a battery or some other type of DC power source. A typical voltage range for the input voltage source in one embodiment may be 2.2V to 4.9V. The input voltage source 110 is coupled to a source of a high-side switch PMOS transistor 112. The drain of transistor 112 is coupled to one terminal of an inductor 116 and to a drain of a low-side switch NMOS transistor 114, the source of which is electrically connected to ground. The gates of 112 and 114 are controlled by output signals 132 and 134, respectively, of a gate driver circuit 142. The other terminal of inductor 116 is coupled to one terminal of a capacitor 118, the other terminal of which is electrically connected to ground.

[0020] The load of the buck converter is represented by a load resistor 120. A buck converter operates by converting an input voltage source V IN 110 to the output voltage V at node 140 OUT In order to regulate the current, the voltage may be controlled, or the current may be controlled, or a combination of both.

[0021] The buck converter further includes a control logic block 144 for controlling a gate driver circuit 142 which drives the gate of the high side switch 112 with signal 132 and drives the low side switch 114 with signal 134. The input to the control logic block 144 is the output voltage V OUT The feedback voltage 130, which represents 140, is the internal reference voltage V REF 136, converting it to a current using a V / I converter 154, and comparing it to an input current sample 158 using a current comparator 156. The control logic block 144 is clocked by an oscillator 148 that operates at a fixed frequency. In some embodiments, a current reference can be used instead of a voltage reference.

[0022] The basic operation of a buck converter can be best understood in terms of the relationship between inductor current and voltage. Initially, both high-side switch 112 and low-side switch 114 are off, and the current through the circuit and the voltage across inductor 116 are zero. When high-side gate control signal 132 turns on high-side switch 112, the voltage across the inductor is derived by subtracting buck regulator output voltage 140 from input voltage source 110, causing the current to increase. During this time, energy is stored in inductor 116 in the form of a magnetic field, and the inductor current is split into one current flowing through load resistor 120 and another current charging the output capacitor. Thus, energy from the input is transferred to three elements: it is stored in inductor 116 and output capacitor 118, and is dissipated in load resistor 120.

[0023] The inductor current increases only if the voltage at the input voltage source 110 is greater than the buck regulator output voltage 140. Therefore, power can be continuously transferred from the input to the output only if the buck regulator output voltage 140 is less than the input voltage source 110.

[0024] When the high-side gate control signal 132 turns off the high-side switch 112, the input voltage source 110 no longer supplies energy to the circuit. The low-side switch 114 is turned on, providing a low impedance path between the inductor 116 and ground. As the voltage across the inductor 116 immediately reverses to the negative buck regulator output voltage, its current decreases and the energy previously stored in the magnetic field is transferred back into the magnetic field from the capacitor 318. Then, at the beginning of the next switching cycle, energy is transferred from the inductor 116 and capacitor 118 to the input voltage source 110. This is normal operation when the current through the load resistance is less than half the ripple current of the inductor 116.

[0025] There are several modes in which a buck converter can operate. A buck converter operates in continuous conduction mode (CCM) when there is never a period of time when the current through the inductor 116 is zero, meaning that either the high-side switch 112 or the low-side switch 114 is always on. There is no time in CCM when both the high-side switch 112 and the low-side switch 114 are off at the same time. The boundary between CCM and DCM is called boundary or critical conduction mode.

[0026] In DCM operation, the switching frequency is typically the same as in CCM operation so that losses associated with the switching operation, e.g., capacitive losses, remain constant. Although the output power of DCM can be very low, the efficiency is typically lower than CCM because the switching losses do not decrease. This is because at low power, the switching losses typically dominate the conduction losses associated with the switch and inductor resistances. Pulse Frequency Modulation (PFM) can be used to minimize the switching losses. PFM can reduce the switching frequency at light loads, thus preventing the inductor current from dropping below zero.

[0027] Most switched mode power supplies operate at a fixed frequency, using pulse width modulation to regulate the output. There is a minimum on-time for the FET, i.e. the time the FET must be turned on before it is turned off again. At high switching frequencies and low duty cycles, this can lead to a pulse skip mode (PSM) of operation. PSM can achieve smaller harmonics, faster response speed, and higher light load efficiency than pulse width modulation or DCM operation.

[0028] In fixed frequency control, the PSM needs to adjust the number of skipped pulses to prevent runaway of the output voltage at zero load. To achieve the required minimum switching frequency (e.g., audible noise above 60KHz), the maximum number of skipped pulses must be limited and can be calculated for a given oscillator switching frequency by the following formula: Skip frequency = oscillator frequency / number of pulses

[0029] As an example, with an oscillator clock frequency of 1.5 MHz and a 60 KHz audible noise threshold frequency, the maximum number of pulses that can be skipped is 25. 60KHz=1.5MHz / number of pulses ⇒Maximum number of skipped pulses = 1.5MHz / 60KHz = 25

[0030] The buck converter closed loop frequency from the oscillator is much higher than the audible noise threshold frequency of 60KHz, which allows for a large number of skipped pulses in this case. However, there are applications where the minimum frequency of the converter must be higher than the audible noise and even higher than the converter closed loop frequency to avoid disturbing adjacent electrical circuits. For example, in handheld devices, capacitive touch screens require sampling frequencies above 400KHz to avoid unwanted noise in the sensing frequency band. In these applications and with the zero load current of the buck converter, the minimum number of pulses is strictly limited and an additional dummy load must be added to the buck converter to avoid runaway of the output voltage.

[0031] In addition to the requirements of adjacent circuits, the high minimum switching frequency in PSM avoids burst mode behavior due to repeated forced switching of the power stage. An additional benefit of PSM is lower ripple on the output voltage, which is a requirement for voltage converters supplying displays.

[0032] FIG. 2A plots the voltage and current waveforms as a function of time for a PSM scheme in burst mode with no load. In the voltage plot, the dotted line shows the desired regulated DC voltage. This illustrates the drawback of burst mode, which results in higher output voltage ripple that may be unacceptable in some applications. FIG. 2B plots the voltage and current waveforms as a function of time for a PSM scheme with no load. The voltage ripple is much improved over the burst mode example, but with no load and a strict requirement to maintain a minimum switching frequency, the output voltage will run away and cannot be kept within the desired DC voltage range because there is no mechanism to reduce the output voltage level without dropping below the minimum switching frequency.

[0033] The prior art solution to this problem is to add an additional dummy load to avoid output voltage runaway. Figure 2C plots the voltage and current waveforms as a function of time for a PSM scheme using a dummy load. The dummy load technique achieves correct output voltage accuracy and provides low output voltage ripple, but results in low system power efficiency because the current passing through the dummy load is wasted. In battery-powered systems, low standby power consumption is important to conserve battery life. When the load current is zero, the circuitry being fed from the buck converter is assumed to be operating in standby mode. In order for the buck converter to meet the minimum switching frequency requirement in a PSM scheme, the prior art converter uses a dummy load to control the output voltage under minimum inductor on-time control. However, this has a major drawback because the wasted current through the dummy load reduces battery life, which is undesirable in handheld electronic applications.

[0034] FIG. 3 shows a block diagram of an example of a claimed buck converter with an internally powered logic LDO. This provides a means of preventing voltage runaway at the output at zero load current by recycling charge that would otherwise be wasted through a dummy load to supply an internally biased low dropout regulator (LDO). Using an internal logic LDO as an alternative dummy load for the buck converter prevents output voltage runaway of the buck converter, resulting in a higher overall power supply efficiency and less battery current drawn to operate in standby or low power operation. This is done by powering the logic LDO from the buck converter output instead of the battery when no other current is being drawn from the buck converter output. However, the battery can still be used to power the logic LDO when there is a higher load on the buck converter output.

[0035] FIG. 3 is a schematic diagram of an example of a buck converter with guaranteed minimum switching frequency for use in pulse skip mode. Buck converter 300 includes an input voltage source 310, which may be a battery or some other type of DC power source. In one embodiment, a typical voltage range for the input voltage source may be 2.2V to 4.9V. Input voltage source 310 is coupled to the source of a high side switch PMOS transistor 312 and to one input of a sampling voltage-to-current converter 368, which samples the current through transistor 312. The drain of transistor 312 is coupled to one side of an inductor 316 and to the drain of a low side switch NMOS transistor 314, whose source is electrically connected to ground. The drain of transistor 312 is also coupled to a second input of sampling voltage-to-current converter 368. The gates of transistors 312 and 314 are controlled by output signals 332 and 334, respectively, of gate driver circuit 342. The other side of inductor 316 is coupled to V OUT A node 340 is coupled to one side of a capacitor 318, the other side of which is electrically connected to ground.

[0036] The load of the buck converter is represented by a load resistor 320. In other embodiments, the buck converter may use voltage control, current control, or a combination of both to regulate V from the input voltage source 310 under a given buck converter load 320. OUT The output voltage at 340 can be adjusted.

[0037] The buck converter further includes a state machine 344 having outputs HSON 382 and LSON 384 coupled to a gate driver circuit 342 that drives the gate of the high side switch 312 with a gate control signal 332 and drives the low side switch 314 with a gate control signal 334. The state machine 344 has five inputs. The first input is a SKIP input 386, which is derived from comparing the feedback voltage 330, which is a scaled version of the output voltage 340, to an internal reference voltage 336 using a comparator 360 in a comparator 364, placing the output through a voltage-to-current converter 362, and then comparing that output to a signal 302 from a logic block 394 that represents a function of the voltage at the input voltage source 310 and the output voltage at node 340.

[0038] A second input to state machine 344 is a clock signal generated by oscillator 348, which operates at a fixed frequency. A third input to state machine 344 is ZERO_COMP 378, which is the output of comparator 388, whose inputs are the source and drain of transistor 314.

[0039] A fourth input to state machine 344 is PEAK_COMP 372, which is the output of comparator 376, whose input is sampling voltage-to-current converter 368, which is the sum of slope compensator 374 and voltage-to-current converter 362. A fifth input to state machine 344 is FPWM 380, which is the output of programmable register 370, a user-specific setting (FPWM) 380 to select between CCM only and CCM or DCM operation.

[0040] 4 shows a simplified representation of one example of the claimed buck converter with internal powered logic LDO of FIG. 3. An input supply voltage source 410 feeds the source terminal of a high side switch 412 and is coupled to one input of a supply multiplexer 440. The supply multiplexer 440 is shown in FIG. 4 as an ideal switch, but may be two transistors or any type of multiplexer integrated circuit. The supply multiplexer 440 supplies an internal supply voltage AV 1 , which is used as a supply voltage for the buck converter's digital circuitry 430, input / output circuitry 452, and other circuitry 454 between the input supply voltage source 410 and the output of the buck converter. DD As a source for generating V OUT Choose 450.

[0041] The drain of the high-side switch 412 is coupled to one side of an inductor 416 and to the drain of a low-side switch 414, the source of which is electrically connected to ground. The other side of the inductor 416 is coupled to one side of a capacitor 418, the other side of which is electrically connected to ground. The node where the inductor 416 and the capacitor 418 are coupled together is the buck converter output voltage V OUT It also provides 450V buck converter output voltage V OUT 450 is also coupled to a second input of the supply multiplexer 440 .

[0042] The schematic of Figure 4 consists of the buck converter from Figure 1 with an additional LDO circuit to generate an internal supply voltage for powering the buck converter's digital circuitry 430, input / output circuitry 452, and other circuitry 454. The LDO circuit is connected to the input supply voltage source 410 or the buck converter's output voltage V OUT 3. The control signals 390 and 392 for supply multiplexer 440, which select between the two inputs, are from logic block 394 in FIG.

[0043] The control signals 390 and 392 for the supply multiplexer 440 correspond to the output voltage V OUT 450 is the internal logic supply voltage AV DD The internal logic supply voltage, AV, must be at least 1 V, unless it is too low to support the generation of DD The output voltage V of the buck converter is always used as the source for generating OUT 450. This logic signal that controls the supply multiplexer 440 can be the output of the comparator 360 or another signal derived therefrom. OUT The internal logic supply voltage AV 450 is too low DD If the input supply voltage source 410 cannot support the generation of the internal logic supply voltage AV DD Provides generation of

[0044] Internal logic supply voltage AV DD 480 provides a supply voltage that is coupled to the buck converter's digital circuitry 430, the input / output circuitry 452, and any other circuitry 454 inside the buck converter device that the designer may choose to power from this source. It powers the state machine 344 that feeds the gate driver 342. Normally, loading a buck converter with such circuitry is undesirable, as it would reduce the efficiency of the converter by increasing the switching frequency. However, in this case, the extra load is only added when the converter needs to switch, so the energy for supply is effectively unlimited, thus increasing the overall efficiency of the converter.

[0045] A more detailed schematic of the logic LDO block is shown in Figure 5. The LDO consists of a pass transistor 446, an output capacitor 438, a feedback path voltage divider with resistors 460 and 462, and an amplifier 470 with input from voltage reference 436 and voltage divider feedback from resistors 460 and 462. The LDO output voltage node is AV DD480, and the load to the LDO is represented by resistor 482. PMOS transistors 456 and 458 couple the input supply voltage source 410 and the output V OUT 3. The gate of transistor 456 is coupled to the EN_IN signal 390 from logic block 394 of FIG. 3. EN_IN 390 and EN_OUT 392 are connected to the output VOUT of the buck converter. OUT 450 and the input voltage V IN 410. The gate of transistor 458 is coupled to an EN_OUT signal 392 from logic block 394. EN_IN 390 and EN_OUT 392 combine to either connect the input supply voltage source 410 to the drain of pass transistor 446 by enabling PMOS transistor 456, or connect the buck converter output voltage 450 to the drain of pass transistor 446 by enabling PMOS transistor 458. The select signal EN_OUT 392, which enables PMOS transistor 458, determines whether the buck converter output voltage 450 is equal to the LDO output voltage AV DD It triggers as soon as it exceeds the sum of 480 and the voltage drop across pass transistor 446 .

[0046] In this way, when the load requirement drops below a minimum threshold, the buck converter will dump energy through the dummy load to ground, thus increasing its output V, rather than wasting that energy. OUT It reuses the energy from 450 to power itself. In this way, the buck converter output is used as a logic power supply in combination with an internal logic LDO to meet the specification that the buck converter always switches above a certain minimum switching frequency while achieving low output voltage ripple.

[0047] Repeat the calculations from above to determine the maximum number of pulses that can be skipped while still meeting the minimum sampling frequency specification of 400 KHz to satisfy the requirements imposed by systems with capacitive touch screens and keeping the oscillator clock frequency at 1.5 MHz. The maximum number of pulses that can be skipped is 3. 400KHz=1.5MHz / number of pulses ⇒Maximum number of skipped pulses = 1.5MHz / 400KHz = 3.75 → 3

[0048] A state diagram for an asynchronous converter state machine 600 for implementing a PSM mode that allows skipping no more than two consecutive pulses is shown in FIG. 6. Although the state machine in this example is designed for a maximum of two consecutive pulses to be skipped, the state machine can be modified for any desired number of required maximum skipped pulses based on the oscillator frequency used and the required minimum switching frequency. In an example buck converter with a 1.5 MHz oscillator clock, the minimum switching frequency is 500 KHz. This is higher than the required minimum switching frequency of 400 KHz to avoid disrupting capacitive touch screens, and also provides low output voltage ripple. Thus, the state machine is well suited for use in a buck converter supplying a display.

[0049] The asynchronous converter state machine 600 is implemented with the circuit elements shown as state machine block 344 in Figure 3. Beginning at step 610 in Figure 6, the converter is enabled with a global enable (EN) signal 396 from register 370 and a rising clock 398 from oscillator 348. Each switching cycle in the peak current control system begins with a high-side switch 312 on-time, step 640, indicated by state 3 (HS ON).

[0050] As soon as the peak current reference is triggered by the sensed current through inductor 316, the current comparator signal (PEAK_COMP) 372 is triggered to switch from high-side conduction STATE 3 to low-side conduction STATE 1 (step 620) to discharge inductor 316. This is done by switching off high-side switch 312 and switching on low-side switch 314. To ensure a fixed frequency in any transient conditions, the maximum on-time is also achieved by triggering on the falling edge of CLK 398.

[0051] CCM operation occurs only in State 1 (step 620) and State 3 (step 640). From State 1 (step 620), the state machine can enter State 2 (step 630) or return to State 3 (step 640). With the following zero current detection (ZERO_COMP) 378 and user specific settings (FPWM) 380 to select between CCM only and CCM or DCM operation, State 2 (step 630) is entered as soon as the inductor current crosses zero before the CLK triggers.

[0052] The state machine leaves State 2 (step 630) on the next CLK cycle. Then, either another inductor charging period begins in State 3 (step 640) or the next pulse is skipped by entering State 4 (step 650). This decision is determined by the value of the pulse skip mode signal (SKIP) 386, which is derived from the output voltage discharge during DCM mode and is equal to V IN V in comparator 364 OUT The next CLK cycle during state 4, step 650, again determines whether to skip another pulse and move to state 5 (step 660) during the second idle pulse, or otherwise return to the inductor charging period in state 3 (step 640). After the second pulse is skipped in state 5 (step 660), the next CLK cycle forces the converter to switch again to maintain the minimum switching frequency.

[0053] The transition from state 2 (620) to state 4 (650) to state 5 (660) generates the first and second skipped pulses. The transition from state 5 (660) to state 3 (640) forces the buck converter to switch. In this way, the state machine ensures that no more than two consecutive clock cycles are skipped. The state machine enters state 4 (650) or state 5 (660) only if the current drawn from the output load 320 is very low. Otherwise, the state machine remains in the normal operating states of state 1 (620), state 2 (630), and state 3 (640) when the required load current is higher and no pulses are skipped.

[0054] The terms "substantially the same," "substantially equal," and "about the same" are intended to describe a quantitative relationship between two objects that may be desired to be equal by design, but that anticipates that a certain amount of variation may be introduced by the manufacturing process.

[0055] Although operations are shown in the figures in a particular order, this should not be understood as requiring that all illustrated operations be performed to achieve a desired result, unless such order is recited in one or more claims. In some situations, multitasking and parallel processing may be advantageous. Also, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments.

Claims

1. 1. A step-down voltage converter, comprising: a high side switch having a first terminal coupled to the input voltage source and a second terminal; a low-side switch having a first terminal coupled to ground and a second terminal coupled to the second terminal of the high-side switch; an inductor having a first terminal coupled to the second terminal of the high-side switch and the second terminal of the low-side switch, and a second terminal coupled to a step-down output of the step-down voltage converter; a capacitor having a first terminal coupled to the step-down output of the step-down voltage converter and to the second terminal of the inductor, and a second terminal coupled to ground; a gate driver circuit having a first output coupled to a gate terminal of the high side switch and a second output coupled to a gate terminal of the low side switch; a voltage regulator circuit for powering circuit elements in the step-down voltage converter, the voltage regulator circuit comprising: a multiplexer having a first multiplexer input coupled to the input voltage source, a second multiplexer input coupled to a step-down output of the step-down voltage converter, and one or more multiplexer control inputs for selecting which of the two multiplexer inputs is coupled to a multiplexer output, the one or more multiplexer control inputs being derived from comparing the step-down output to the input voltage source; a pass transistor having a first terminal coupled to the multiplexer output and a second terminal coupled to a regulator output of the voltage regulator circuit; the voltage regulator circuit comprising: a step-down voltage converter.

2. 2. The step-down voltage converter of claim 1, A step-down voltage converter, wherein only a regulator output of the voltage regulator circuit powers the circuit elements for a state machine and internal logic circuitry of the step-down voltage converter.

3. 3. The step-down voltage converter of claim 2, A step-down voltage converter, wherein the regulator output is capacitively coupled to ground.

4. 3. The step-down voltage converter of claim 2, The multiplexer includes two transistors.

5. 5. The step-down voltage converter of claim 4, The transistors include a p-channel field effect transistor and an n-channel field effect transistor.

6. 3. The step-down voltage converter of claim 2, 2. The step-down voltage converter, wherein the voltage regulator circuit further comprises an amplifier having a first input coupled to a voltage reference, a second input coupled to a regulator output of the voltage regulator circuit through a first resistor and to ground through a second resistor, and an output coupled to a gate terminal of the pass transistor.

7. 1. A state machine comprising: a skip input signal derived by subtracting a scaled version of a buck output of a step-down voltage converter from a reference voltage and comparing the output of the subtraction with a signal representative of the difference between the input supply voltage and the buck output; a Zero_Comp input signal that is the output of a comparator whose inputs are the first and second terminals of the low-side switch; an FPWM input signal, the setting of which selects between continuous conduction mode (CCM) only and CCM or discontinuous conduction mode (DCM) operation; a Peak_Comp input signal which is the output of a comparator having a first input representing the amount of current drawn from an input voltage source and a second input representing the difference between the buck output and the reference voltage; an EN input signal for enabling the step-down voltage converter; an HS output coupled to a gate driver circuit that controls a high side switch; an LS output coupled to the gate driver circuit that controls the low side switch; Including, determining a maximum number of consecutive pulses that may be skipped; enabling the step-down voltage converter with the EN input signal and a clock edge; using the HS output to switch on the high-side switch to supply power from the input voltage source through an inductor to a load and continuously monitor an inductor current; discharging the inductor by switching off the high-side switch using the HS output and switching on the low-side switch using the LS output after a peak current reference level is reached in the inductor current; determining whether the inductor current has reached zero; switching off the low-side switch using the LS output and switching on the high-side switch using the HS output when the inductor current reaches zero, or skipping a first pulse using a Skip input signal when the inductor current has not reached zero; determining whether the inductor current has reached zero and whether a maximum number of consecutive pulses that may be skipped has been reached during a next clock cycle; switching off the low side switch using the LS output and switching off the high side switch using the HS output switch when the inductor current reaches zero or when a maximum number of consecutive pulses that may be skipped is reached, or skipping a second pulse using a Skip input signal when the inductor current has not reached zero and has not reached a maximum number of consecutive pulses that may be skipped. A state machine configured as follows.

8. 8. A state machine as claimed in claim 7, comprising: A state machine wherein the maximum number of consecutive pulses that may be skipped is determined by dividing an oscillator frequency by a minimum switching frequency.

9. 8. A state machine as claimed in claim 7, comprising: The maximum number of consecutive pulses that may be skipped is two.

10. 1. A step-down voltage converter, comprising: a high side switch having a first terminal coupled to the input voltage source and a second terminal; a low-side switch having a first terminal coupled to ground and a second terminal coupled to the second terminal of the high-side switch; an inductor having a first terminal coupled to the second terminal of the high-side switch and the second terminal of the low-side switch, and a second terminal coupled to a step-down output of the step-down voltage converter; a capacitor having a first terminal coupled to the step-down output and to the second terminal of the inductor, and a second terminal coupled to ground; a gate driver circuit that receives an input from a state machine, the gate driver circuit having outputs coupled to a gate terminal of the high side switch and a gate terminal of the low side switch; a voltage regulator circuit for supplying power to circuit elements within the step-down voltage converter, the voltage regulator circuit comprising: a multiplexer having a first multiplexer input coupled to the input voltage source, a second multiplexer input coupled to the step-down output, and one or more multiplexer control inputs for selecting which of the two multiplexer inputs is coupled to a multiplexer output, the one or more multiplexer control inputs being derived from comparing the step-down output to the input voltage source; a pass transistor having a first terminal coupled to the multiplexer output and a second terminal coupled to a regulator output of the voltage regulator; the voltage regulator circuit comprising: a step-down voltage converter.

11. 11. The step-down voltage converter of claim 10, A step-down voltage converter, wherein only a regulator output of the voltage regulator circuit powers the circuit elements for a state machine and internal logic circuitry of the step-down voltage converter.

12. 11. The step-down voltage converter of claim 10, The state machine, a Skip input signal derived by subtracting a scaled version of the buck output from a reference voltage and comparing the output of the subtraction to a signal representative of the difference between an input supply voltage and the buck output; a Zero_Comp input signal that is the output of a comparator whose inputs are the first and second terminals of the low-side switch; an FPWM input signal providing a setting to select between continuous conduction mode (CCM) only and CCM or discontinuous conduction mode (DCM) operation; a Peak_Comp input signal which is the output of a comparator having a first input representing the amount of current drawn from the input voltage source and a second input representing the difference between the step-down output and the reference voltage; an EN input signal for enabling the step-down voltage converter; an HS output coupled to the gate driver circuit that controls the high side switch; an LS output coupled to the gate driver circuit that controls the low side switch; a step-down voltage converter.

13. 13. A step-down voltage converter as claimed in claim 12, comprising: The state machine, determining a maximum number of consecutive pulses that may be skipped; enabling the step-down voltage converter with the EN input signal and a clock edge; using the HS output to switch on the high-side switch to supply power from the input voltage source through the inductor to a load and continuously monitor an inductor current; discharging the inductor by switching off the high-side switch using the HS output and switching on the low-side switch using the LS output after a peak current reference level is reached in the inductor current; determining whether the inductor current has reached zero; switching off the low-side switch using the LS output and switching on the high-side switch using the HS output when the inductor current reaches zero, or skipping a first pulse using the Skip input when the inductor current has not reached zero; determining whether the inductor current has reached zero and whether a maximum number of consecutive pulses that may be skipped has been reached during a next clock cycle; a step-down voltage converter configured to switch off the low-side switch using the LS output and switch off the high-side switch using the HS output switch when the inductor current reaches zero or the maximum number of consecutive pulses that may be skipped is reached, or to skip a second pulse using the Skip input when the inductor current has not reached zero or the maximum number of consecutive pulses that may be skipped is not reached.

14. 13. A step-down voltage converter as claimed in claim 12, comprising: A step-down voltage converter in which the maximum number of consecutive pulses that may be skipped is determined by dividing the oscillator frequency by the minimum switching frequency.

15. 13. A step-down voltage converter as claimed in claim 12, comprising: A step-down voltage converter, wherein the maximum number of consecutive pulses that may be skipped is two.

16. 11. The step-down voltage converter of claim 10, The multiplexer includes a p-channel field effect transistor and an n-channel field effect transistor.

17. 11. The step-down voltage converter of claim 10, 2. The voltage regulator circuit of claim 1, further comprising an amplifier having a first input coupled to a voltage reference, a second input coupled to the regulator output through a first resistor and to ground through a second resistor, and an output coupled to the gate terminal of the pass transistor.

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