Gate driving circuit and display panel

Abstract

To improve the yield of a gate drive circuit by providing a patch line and hence normally outputting a pulse signal.SOLUTION: A gate drive circuit 100 includes a multistage gate drive unit and at least one patch line 12, where a gate drive unit 10 of the n-th stage is connected to at least a first signal control line 11, the first control signal line 11 accesses a scanning signal G1(n) of the n-th stage, the gate drive unit 10 of the n-th stage is used for outputting a pulse signal G3(n) of the n-th stage under the control of a scanning signal G1(n) of the n-th stage, the patch line 12 is provided in a different layer while crossing the first control signal line 11, the patch line 12 is used for transmitting a scanning signal G1(m) of the m-th stage, and both of n and m are positive integers larger than 0, and n is larger or smaller than m.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to the field of display technology, and in particular to gate driving circuits and display panels. [Background technology]

[0002] Gate Driver On Array (GOA) is a driving method that integrates gate driver circuits on the array substrate of a display panel to achieve progressive scanning. (See, for example, Chinese Patent Application Publication No. 115620658) This driving technology has the advantage of eliminating the need for a gate IC chip, reducing production costs and enabling narrow-frame panel designs, and is therefore used in many displays.

[0003] In general, in an internal compensation circuit of a pixel, in order to achieve the purpose of compensation and adjustment of the brightness of the display panel, etc., the gate drive circuit needs to output a pulse signal with an adjustable width. Meanwhile, an internal compensation circuit usually requires multiple sets of scanning signals output by multiple sets of gate drive circuits, which is disadvantageous for narrowing the frame of the display panel. In order to simplify the gate drive circuit design of a pixel circuit that requires multiple sets of scanning signals, the control signal of the wide pulse gate drive circuit is provided by the scanning signal output by another gate drive circuit. However, if another gate drive circuit breaks down, the wide pulse gate drive circuit also breaks down, and it becomes impossible to output a pulse signal of a predetermined width, resulting in a decrease in yield. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a gate driving circuit and a display panel for solving a technical problem in the prior art that a gate driving circuit that outputs a pulse signal cannot output a pulse signal of a predetermined width when another gate driving circuit that provides a scanning signal fails. [Means for solving the problem]

[0005] The present application provides a gate drive circuit, A multi-stage gate driving unit, the n-stage gate driving unit is at least connected to a first control signal line, the first control signal line is for accessing a n-stage scanning signal, and the n-stage gate driving unit is used for outputting a n-stage pulse signal under the control of the n-stage scanning signal; At least one patch line, the patch line being arranged in a different layer and crossing the first control signal line, the patch line being used to transmit a scanning signal of an mth stage, n and m are both positive integers greater than 0, and n is greater than or less than m.

[0006] Preferably, in some embodiments of the present application, the gate driving circuit further includes a signal transmission line, the signal transmission line is used to transmit the scanning signal of the nth stage, the signal transmission line is arranged in a different layer and crosses the first control signal line, and the signal transmission line is connected to the first control signal line through a via.

[0007] Preferably, in some embodiments of the present application, the gate drive circuit includes k patch lines, each of which accesses a corresponding mth stage scanning signal, where k is a positive integer greater than 1, and m is less than n.

[0008] Preferably, in some embodiments of the present application, the gate drive circuit includes k patch lines, each of which accesses a corresponding mth stage scanning signal, where k is a positive integer greater than 1, and m is greater than n.

[0009] Preferably, in some embodiments of the present application, the patch lines include at least one first patch line and at least one second patch line; The first patch line accesses a scan signal of the mth stage, where m is less than n, and the second patch line accesses a scan signal of the mth stage, where m is greater than n.

[0010] Preferably, in some embodiments of the present application, the first patch line and the second patch line are located on either side of the first control signal line, respectively.

[0011] Preferably, in some embodiments of the present application, a repair mark is provided on the patch line, and an intersection of the patch line and the first control signal line corresponds to the repair mark.

[0012] Preferably, in some embodiments of the present application, the nth stage gate driving unit comprises: a pull-up control module connected to a high potential wiring, a first low potential wiring, the first control signal line, a second control signal line and a pull-up node, and used to control the potential of the pull-up node; a pull-up output module connected to the high potential wiring, the pull-up node and a signal output terminal, and used for outputting the pulse signal of the nth stage at the signal output terminal under the control of the potential of the pull-up node; a pull-down control module connected to the high potential wiring, the second control signal line, the stage transmission wiring, the pull-up node, the first low potential wiring and a pull-down node, and used to control the potential of the pull-down node; a pull-down module connected to a second low potential wiring, the signal output terminal and the pull-down node, and used for pulling down the potential of the signal output terminal under the control of the potential of the pull-down node.

[0013] Preferably, in some embodiments of the present application, the pull-up control module includes a first transistor, a second transistor, a third transistor and a fourth transistor; The gate of the first transistor and the gate of the second transistor are both connected to the first control signal line, the source of the first transistor is connected to the high potential wiring, the drain of the first transistor is connected to the source of the second transistor, the drain of the second transistor is connected to the pull-up node, the gate of the third transistor and the gate of the fourth transistor are both connected to the second control signal line, the source of the third transistor is connected to the first low potential wiring, the drain of the third transistor and the source of the fourth transistor are connected to a first node, and the drain of the fourth transistor is connected to the pull-up node.

[0014] Preferably, in some embodiments of the present application, the pull-up control module further includes a fifth transistor, a sixth transistor, a seventh transistor and a first capacitor; The gate of the fifth transistor, the drain of the sixth transistor and one end of the first capacitor are all connected to the pull-up node, the source of the fifth transistor is connected to the high potential wiring, the drain of the fifth transistor, the source of the sixth transistor and the drain of the seventh transistor are all connected to the first node, the gate of the sixth transistor and the gate of the seventh transistor are all connected to the pull-down node, the source of the seventh transistor is connected to the first low potential wiring, and the other end of the first capacitor is connected to the signal output terminal.

[0015] Preferably, in some embodiments of the present application, the pull-down control module includes an eighth transistor, a ninth transistor and a second capacitor; A gate of the eighth transistor is connected to the stage transmission wiring, a source of the eighth transistor is connected to the second control signal line, a drain of the eighth transistor, one end of the second capacitor and a gate of the ninth transistor are connected together, the other end of the second capacitor and a source of the ninth transistor are all connected to the high potential wiring, and a drain of the ninth transistor is connected to the pull-down node.

[0016] Preferably, in some embodiments of the present application, the pull-down control module further includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor; A gate of the tenth transistor and a gate of the eleventh transistor are all connected to the pull-up node, a drain of the tenth transistor, a drain of the twelfth transistor and a gate of the fourteenth transistor are all connected to the pull-down node, a source of the tenth transistor, a drain of the eleventh transistor, a source of the twelfth transistor, a drain of the thirteenth transistor and a drain of the fourteenth transistor are all connected to a second node, a source of the eleventh transistor and a source of the thirteenth transistor are all connected to the first low potential wiring, a gate of the twelfth transistor and a gate of the thirteenth transistor are all connected to the first control signal line, and a source of the fourteenth transistor is connected to the high potential wiring.

[0017] Accordingly, the present application further provides a display panel, the display panel including a display area and a non-display area connected to the display area, the display panel including a gate drive circuit as described above, the gate drive circuit being located in the non-display area. Effect of the Invention

[0018] The present application provides a gate driving circuit and a display panel. The gate driving circuit includes a multi-stage gate driving unit and at least one patch line, where the gate driving unit of the nth stage is connected to at least a first control signal line, the first control signal line accesses the scanning signal of the nth stage, the gate driving unit of the nth stage is used to output the pulse signal of the nth stage under the control of the scanning signal of the nth stage, the patch line is arranged in a different layer crossing the first control signal line, the patch line is used to transmit the scanning signal of the mth stage, n and m are both positive integers greater than 0, and n is greater than or less than m. The embodiment of the present application adds a patch line, so that when the scanning signal of the nth stage is faulty, the scanning signal of the mth stage can be provided through the patch line to replace the scanning signal of the nth stage, so that the pulse signal of the nth stage can be normally output, thereby improving the yield of the gate driving circuit. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a first schematic structural diagram of a gate driving circuit provided in the present application. [Diagram 2] FIG. 2 is a second schematic structural diagram of a gate driving circuit provided in the present application. [Diagram 3] FIG. 3 is a third schematic structural diagram of a gate driving circuit provided in the present application. [Figure 4] FIG. 2 is a circuit schematic diagram of the n-th stage gate driving unit provided in the present application; [Diagram 5] FIG. 2 is a signal timing diagram of the nth stage gate driver unit provided in the present application; [Figure 6] FIG. 2 is a schematic structural diagram of a display panel provided in the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The technical solutions in the embodiments of the present application will be described below clearly and completely with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0021] In addition, the terms "first", "second", etc. in the specification and claims of this application are used to distinguish different objects, not to describe a particular order. The terms "comprise" and "have" and any variations thereof are intended to cover a non-exclusive inclusion.

[0022] The present application provides a gate driving circuit and a display panel, which will be described in detail below. Note that the order of description of the following embodiments does not limit the preferred order of the embodiments of the present application.

[0023] Referring to FIG. 1, FIG. 1 is a first schematic structural diagram of a gate driving circuit provided in the present application. The gate driving circuit 100 includes a multi-stage gate driving unit and at least one patch line 12. Wherein, the gate driving unit 10 of the nth stage is at least connected to a first control signal line 11. The first control signal line 11 accesses the scanning signal G1(n) of the nth stage. The gate driving unit 10 of the nth stage is used to output the pulse signal G3(n) of the nth stage under the control of the scanning signal G1(n) of the nth stage. The patch line 12 is disposed in a different layer across the first control signal line 11. The patch line 12 is used to transmit the scanning signal G1(m) of the mth stage, where n and m are both positive integers greater than 0, and n is greater than or equal to m.

[0024] In the embodiment of the present application, the multi-stage gate driving unit included in the gate driving circuit 100 does not perform stage transmission itself, but controls the gate driving circuit 100 by the multi-stage scanning signal output from another set of GOA circuits, thereby realizing the progressive on of the gate driving circuit 100, thereby realizing the output of multiple sets of pulse signals. Here, the other set of GOA circuits refers to other GOA circuits different from the gate driving circuit 100 included in the display panel, which are used to provide multiple sets of scanning signals required by the internal compensation circuit.

[0025] For convenience of explanation, in the following embodiments of the present application, when m is greater than n, the scanning signal G1(m) of the mth stage is represented by the scanning signal G1(n+k) of the n+kth stage, and when m is less than n, the scanning signal G1(nk) of the nkth stage is represented by the scanning signal G1(m), where k is an integer greater than or equal to 1.

[0026] Here, the nth stage scanning signal G1(n), the n+kth stage scanning signal G1(n+k) and the nk stage scanning signal G1(nk) may be scanning signals output from the same GOA circuit. The patch line 12 may be connected to the output of the GOA circuit to access the n+kth stage scanning signal G1(n+k) and the nk stage scanning signal G1(nk).

[0027] The k in the n+k stage scanning signal G1(n+k) and the nk stage scanning signal G1(nk) can be adjusted according to the driving requirements of the pixel circuit. For example, when n is 3, k can be 1, 2, etc., when n is 5, k can be 1, 2, 3, etc., which are not listed here.

[0028] As can be understood, when the gate driving circuit 100 is applied to a pixel circuit, the pixel circuit can tolerate the phase of the pulse signal G3(n) of the nth stage fluctuating within a certain range, so that the k value can be set according to the simulation result of the pixel circuit. For example, when the scanning signal G1(n) of the nth stage is broken, if the scanning signal G1(nk) of the nkth stage is used to repair it, the phase of the pulse signal G3(n) of the nth stage will advance by k stages, and the driving signal of the pixel circuit will fluctuate, and the allowable fluctuation range needs to be determined according to the compensation and display effect of the pixel circuit.

[0029] In the embodiment of the present application, by adding a patch line 12, when the nth stage scanning signal G1(n) is broken, the patch line 12 can be connected to the first control signal line 11 by laser or other repair methods, and the patch line 12 can provide the n-th stage scanning signal G1(nk) or the n+kth stage scanning signal G1(n+k), such as the n-1th stage scanning signal G1(n-1), the n+1th stage scanning signal G1(n+1), etc., so that the nth stage pulse signal G3(n) can be output normally, thereby improving the independence of the gate driving circuit 100 and improving the yield of the gate driving circuit 100.

[0030] In the embodiment of the present application, the gate driving circuit 100 further includes a signal transmission line 13. The signal transmission line 13 is used to transmit the nth stage scanning signal G1(n). The signal transmission line 13 is disposed in a different layer to cross the first control signal line 11. The signal transmission line 13 is connected to the first control signal line 11 through a via 130.

[0031] In some embodiments, the signal transmission line 13 may be provided in the same layer as the patch line 12, thereby simplifying the film layer structure.

[0032] Of course, in other embodiments, the signal transmission line 13 may be provided in the same layer as the first control signal line 11, so as to avoid signal transmission failure due to the connection method of the via 130.

[0033] In some embodiments, when the nth stage scanning signal G1(n) is faulty and the patch line 12 is connected to the first control signal line 11, the signal transmission line 13 can be disconnected from the first control signal line 11, thereby preventing the faulty nth stage scanning signal G1(n) from affecting the normal operation of the nth stage gate driving unit 10.

[0034] In the embodiment of the present application, only one patch line 12 may be provided corresponding to the nth stage gate driving unit 10. In this way, when the nth stage scanning signal G1(n) is broken, the patch line 12 can be connected to the first control signal line 11 by laser or other repair methods, and the n-th stage scanning signal G1(nk) or the n+kth stage scanning signal G1(n+k) can be provided through the patch line 12, so that the nth stage pulse signal G3(n) can be output normally. At the same time, the number of wirings is reduced, making it easier to realize a narrow frame.

[0035] In the embodiment of the present application, multiple patch lines 12 may be provided corresponding to the n-th stage gate driving unit 10. When the n-th stage scanning signal G1(n) is broken, only one of the patch lines 12 is selected by laser or other repair methods and connected to the first control signal line 11. The purpose of providing multiple patch lines 12 is to improve the repair yield.

[0036] 1, the patch line 12 includes at least one first patch line 121 and at least one second patch line 122. The first patch line 121 accesses the scanning signal G1(nk) of the nk stage. The second patch line 122 accesses the scanning signal G1(n+k) of the n+k stage.

[0037] For example, the patch line 12 includes k first patch lines 121 and k second patch lines 122. The first first patch line 121 accesses the scanning signal G1(n-1) of the n-1th stage. The second first patch line 121 accesses the scanning signal G1(n-2) of the n-2th stage. The kth first patch line 121 accesses the scanning signal G1(nk) of the nk stage. The first second patch line 122 accesses the scanning signal G1(n+1) of the n+1th stage. The second second patch line 122 accesses the scanning signal G1(n+2) of the n+2th stage. The kth first patch line 121 accesses the scanning signal G1(n+k) of the n+kth stage. By this analogy, the description will not be repeated here. That is, the number of the first patch lines 121 or the second patch lines 122 is k.

[0038] Of course, in some embodiments, the number of the first patch lines 121 or the second patch lines 122 does not have to be k. In other words, it is sufficient to select an appropriate n-th stage scanning signal G1(nk) to access the corresponding first patch line 121, and to select an appropriate n+k-th stage scanning signal G1(n+k) to access the corresponding second patch line 122, and this application is not particularly limited thereto.

[0039] In the embodiment of the present application, by providing at least one first patch line 121 and at least one second patch line 122, the scanning signal G1(nk) of the nk stage and the scanning signal G1(n+k) of the n+k stage are both repair signals, so that in practice, an appropriate signal can be selected according to the requirements of the pixel circuit to repair the scanning signal G1(n) of the nth stage, and the yield of the gate driving unit 10 of the nth stage can be further improved.

[0040] In some embodiments of the present application, the first patch line 121 and the second patch line 122 are respectively located on both sides of the first control signal line 11. On the one hand, the wiring space around the nth stage gate driving unit 10 can be fully utilized. On the other hand, the positions of the first patch line 121 and the second patch line 122 can be clearly distinguished, which makes it easy to select the scanning signal G1(nk) of the nkth stage or the scanning signal G1(n+k) of the n+kth stage as the repair signal according to actual requirements.

[0041] In some embodiments of the present application, the patch line 12 is provided with a repair mark 120. An intersection point A between the patch line 12 and the first control signal line 11 corresponds to the repair mark 120. Specifically, the intersection point A is provided so as to at least partially overlap the repair mark 120.

[0042] As can be seen, the patch line 12 can be connected to the first control signal line 11 using a laser. The energy of the laser is very high, so in order to avoid damaging other film layers, the present application provides a repair mark 120 on the patch line 12, and the intersection point A between the first control signal line 11 and the patch line 12 corresponds to the repair mark 120, thereby improving the accuracy of the laser. This improves the connection yield between the patch line 12 and the first control signal line 11, and also prevents damage to other film layers caused by the laser.

[0043] The repair mark 120 may also be a protrusion or a groove provided on the patch line 12. The repair mark 120 may also be a graphic mark such as "-", "+", or "x" provided on the patch line 12. This is not particularly limited in the present application.

[0044] Referring to Fig. 2, Fig. 2 is a second schematic structural diagram of the gate driving circuit provided in the present application. The difference from the gate driving circuit 100 shown in Fig. 1 is that in the embodiment of the present application, the gate driving circuit 100 includes k patch lines 12, the first patch line 12 accesses the scanning signal G(n+1) of the n+1th stage, and the kth patch line 12 accesses the scanning signal G1(n+k) of the n+kth stage.

[0045] As can be understood, k determines the phase relationship between the nth stage scanning signal G(n) and the nth stage pulse signal. The rising edge of the phase of the nth stage scanning signal G(n) and the nth stage pulse signal is aligned, and when the nth stage scanning signal G(n) is faulty, the nth stage scanning signal G1(n+k) is used to repair, and the phase of the nth stage pulse signal G3(n) is shifted backward by k stages. The embodiment of the present application reduces the number of patch lines 12, and the phase of the nth stage pulse signal G3(n) after repair is shifted backward by k stages, thereby improving the uniformity of the repair.

[0046] In addition, the k patch lines 12 may be provided on the same side of the first control signal line 11, or on both sides of the first control signal line 11, and specifically, can be designed according to the wiring space of the gate drive circuit 100.

[0047] Referring to Fig. 3, Fig. 3 is a third schematic structural diagram of a gate driving circuit provided in the present application. Different from the gate driving circuit 100 shown in Fig. 1, in the embodiment of the present application, the gate driving circuit 100 includes k patch lines 12. The first patch line 12 accesses the scanning signal G(n-1) of the n-1th stage. The kth patch line 12 accesses the scanning signal G1(nk) of the nkth stage.

[0048] Similarly, k determines the phase relationship between the nth stage scanning signal G(n) and the nth stage pulse signal. The rising edge of the phase of the nth stage scanning signal G(n) and the nth stage pulse signal is aligned, and when the nth stage scanning signal G(n) is broken, if the nth stage scanning signal G1(nk) is used to repair, the phase of the nth stage pulse signal G3(n) advances by k steps. The embodiment of the present application reduces the number of patch lines 12 and advances the phase of the nth stage pulse signal G3(n) by k steps after repair, thereby improving the uniformity of the repair.

[0049] In addition, the gate driving unit 10 of the nth stage may need multiple sets of scanning signals output by other GOA circuits. Therefore, the technical solutions described in the above embodiments can be applied to each set of scanning signals. That is, the gate driving unit 10 of the nth stage is not limited to being connected to one first control signal line 11, or the first control signal line 11 is not limited to accessing the scanning signal G(n) of the nth stage.

[0050] Specifically, the following embodiments of the present application will be described taking a specific gate driving circuit 100 as an example, but should not be construed as limiting the present application.

[0051] 1 and 4, FIG. 4 is a circuit schematic diagram of the nth stage gate driver unit provided in the present application. In the embodiment of the present application, the nth stage gate driver unit 10 includes a pull-up control module 101, a pull-up output module 102, a pull-down control module 103 and a pull-down module 104.

[0052] The pull-up control module 101 is connected to the high potential wiring 14, the first low potential wiring 15, the first control signal line 11, the second control signal line 16 and the pull-up node Q. The pull-up control module 101 is used to control the potential of the pull-up node Q.

[0053] Here, the high potential wiring 14 is used to transmit the high potential signal VGH. The first low potential wiring 15 is used to transmit the first low potential signal VGL1. The second control signal line 16 is used to transmit the second scanning signal G2(n). The pull-up control module 101 is used to pull up the potential of the pull-up node Q or pull down the potential of the pull-up node Q under the control of the nth stage scanning signal G1(n), the high potential signal VGH, the first low potential signal VGL1 and the second scanning signal G2(n).

[0054] The pull-up output module 102 is connected to the high potential wiring 14, the pull-up node Q and the signal output end P. The pull-up output module 102 is used for outputting the pulse signal G3(n) of the nth stage at the signal output end P under the control of the potential of the pull-up node Q.

[0055] The pull-down control module 103 is connected to the high potential wiring 14, the second control signal line 16, the stage transmission wiring 17, the pull-up node Q, the first low potential wiring 15 and the pull-down node QB. The pull-down control module 103 is used to control the potential of the pull-down node QB.

[0056] Here, the stage transmission wiring 17 is used to transmit the stage transmission signal Cout. The pull-down control module 103 is used to pull up the potential of the pull-down node QB or pull down the potential of the pull-down node QB under the control of the high potential signal VGH, the stage transmission signal Cout and the second scanning signal G2(n).

[0057] The pull-down module 104 is connected to the second low potential wiring 18, the signal output terminal P and the pull-down node QB. The pull-down module 104 is used to pull down the potential of the signal output terminal P under the control of the potential of the pull-down node QB.

[0058] Here, the second low potential wiring 18 is used to transmit the second low potential signal VGL2. In the embodiment of the present application, the potential of the first low potential signal VGL1 and the potential of the second low potential signal VGL2 may be the same or different.

[0059] In the embodiment of the present application, the transmission stage transmission signal Cout and the second scanning signal G2(n) may be from other GOA circuits. Other signals, such as the high potential signal VGH and the first low potential signal VGL1, can be shared with other GOA circuits to reduce wiring and achieve a narrower frame.

[0060] The gate driving circuit 100 provided in the embodiment of the present application can control the phase difference between the nth stage scanning signal G1(n) and the second scanning signal G2(n) to realize the control of the output pulse width of the nth stage pulse signal G3(n), thereby meeting practical requirements.

[0061] Specifically, in some embodiments of the present application, the pull-up control module 101 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.

[0062] The gate of the first transistor T1 and the gate of the second transistor T2 are both connected to a first control signal line 11. The source of the first transistor T1 is connected to a high potential wiring 14. The drain of the first transistor T1 is connected to a source of the second transistor T2. The drain of the second transistor T2 is connected to a pull-up node Q. The gate of the third transistor T3 and the gate of the fourth transistor T4 are both connected to a second control signal line 16. The source of the third transistor T3 is connected to a first low potential wiring 15. The drain of the third transistor T3 and the source of the fourth transistor T4 are connected to a first node N1. The drain of the fourth transistor T4 is connected to the pull-up node Q.

[0063] The transistors used in all the embodiments of the present application may be thin film transistors, field effect transistors, or other devices with the same characteristics, and the source and drain of the transistors used here are symmetrical, so the source and drain can be interchanged. In the embodiments of the present application, in order to distinguish between the two electrodes other than the gate of the transistor, one electrode is called the source and the other electrode is called the drain. In the switching transistor, the intermediate end is defined as the gate, the signal input end is the source, and the output end is the drain in the form shown in the figure.

[0064] In addition, the transistors used in the embodiments of the present application may include P-type transistors and / or N-type transistors, where the P-type transistors are turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistors are turned on when the gate is at a high level and turned off when the gate is at a low level. The transistors in the following embodiments of the present application will all be described using N-type transistors as examples, but this should not be understood as limiting the present application.

[0065] In addition, in some embodiments of the present application, the pull-up control module 101 further includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor.

[0066] The gate of the fifth transistor T5, the drain of the sixth transistor T6, and one end of the first capacitor C1 are all connected to the pull-up node Q. The source of the fifth transistor T5 is connected to the high potential wiring 14. The drain of the fifth transistor T5, the source of the sixth transistor T6, and the drain of the seventh transistor T7 are all connected to the first node N1. The gate of the sixth transistor T6 and the gate of the seventh transistor T7 are all connected to the pull-down node QB. The source of the seventh transistor T7 is connected to the first low potential wiring 15. The other end of the first capacitor C1 is connected to the signal output terminal P.

[0067] As can be seen, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the first capacitor C1 form a leakage prevention unit to prevent leakage of the pull-up node Q. Specifically, when the potential of the pull-up node Q is pulled up, the fifth transistor T5 is turned on and a high potential signal VGH is transmitted to the first node N1. The potential of the first node N1 is pulled up. At this time, the potential of the first node N1 is not lower than the potential of the pull-up node Q, so that the charge of the pull-up node Q reduces or cuts off the leakage path via the fourth transistor T4, and the high potential state of the pull-up node Q can be maintained for a longer period.

[0068] Of course, in some embodiments, the pull-up control module 101 may not include the sixth transistor T6 and the seventh transistor T7.

[0069] In some embodiments of the present application, the pull-down control module 103 includes an eighth transistor T8, a ninth transistor T9 and a second capacitor C2.

[0070] The gate of the eighth transistor T8 is connected to the stage transmission wiring 17. The source of the eighth transistor T8 is connected to the second control signal line 16. The drain of the eighth transistor T8, one end of the second capacitor C2 and the gate of the ninth transistor T9 are connected together. The other end of the second capacitor C2 and the source of the ninth transistor T9 are all connected to the high potential wiring 14. The drain of the ninth transistor T9 is connected to the pull-down node QB.

[0071] In addition, in some embodiments of the present application, the pull-down control module 103 further includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13 and a fourteenth transistor T14.

[0072] The gate of the tenth transistor T10 and the gate of the eleventh transistor T11 are all connected to the pull-up node Q. The drain of the tenth transistor T10, the drain of the twelfth transistor T12, and the gate of the fourteenth transistor T14 are all connected to the pull-down node QB. The source of the tenth transistor T10, the drain of the eleventh transistor T11, the source of the twelfth transistor T12, the drain of the thirteenth transistor T13, and the drain of the fourteenth transistor T14 are all connected to the second node N2. The source of the eleventh transistor T11 and the source of the thirteenth transistor T13 are all connected to the first low potential wiring 15. The gate of the twelfth transistor T12 and the gate of the thirteenth transistor T13 are all connected to the first control signal line 11. The source of the fourteenth transistor T14 is connected to the high potential wiring 14.

[0073] Here, the tenth transistor T10 and the eleventh transistor T11 can maintain the low potential of the pull-down node QB. When the potential of the pull-up node Q is pulled up to a high potential, the tenth transistor T10 and the eleventh transistor T11 are turned on, and the first low potential signal VGL1 is transmitted to the pull-down node QB, so that the pull-down node QB can be maintained at a low potential. Similarly, the twelfth transistor T12 and the thirteenth transistor T13 can also maintain the low potential of the pull-down node QB. When the nth stage scanning signal G1(n) is at a high potential, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the first low potential signal VGL1 is transmitted to the pull-down node QB, so that the pull-down node QB can be maintained at a low potential.

[0074] Furthermore, when the potential of the pull-down node QB is pulled up, the fourteenth transistor T14 is turned on and the high potential signal VGH is transmitted to the second node N2. The potential of the second node N2 is pulled up. At this time, the potential of the second node N2 does not become lower than the potential of the pull-down node QB, so that the leakage path through which the charge of the pull-down node QB is discharged via the eleventh transistor T11 or the thirteenth transistor T13 is alleviated or cut off, and the high potential state of the pull-down node QB can be maintained for a longer period of time.

[0075] Of course, in some embodiments, the pull-down control module 103 may not include the tenth transistor T10 and the eleventh transistor T11, or may not include the twelfth transistor T12 and the thirteenth transistor T13.

[0076] In some embodiments of the present application, the pull-up output module 102 includes a fifteenth transistor T15. The gate of the fifteenth transistor T15 is connected to the pull-up node Q. The source of the fifteenth transistor T15 is connected to the high potential wiring 14. The drain of the fifteenth transistor T15 is connected to the signal output terminal P.

[0077] In some embodiments of the present application, the pull-down module 104 includes a sixteenth transistor T16. The gate of the sixteenth transistor T16 is connected to the pull-down node QB. The source of the sixteenth transistor T16 is connected to the second low potential wiring 18. The drain of the sixteenth transistor T16 is connected to the signal output terminal P.

[0078] 4 and 5, Fig. 5 is a signal timing diagram of the nth stage gate driver unit provided in the present application. In the embodiment of the present application, the operation timing of the nth stage gate driver unit 10 includes a pulse output stage t1 and a reset stage t2.

[0079] Pulse output stage t1: When the nth stage scanning signal G1(n) is at high level, the first transistor T1 and the second transistor T2 are turned on, and the pull-up node Q is charged to high level. The fifteenth transistor T15, the fifth transistor T5, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are all turned on. At the same time, the stage transmission signal Cout is at high level, and the second scanning signal G2(n) is at low level. The third transistor T3 and the fourth transistor T4 are all turned off. The eighth transistor T8 that is turned on discharges the gate of the ninth transistor T9 to low level, and the pull-down node QB is fully discharged to low level by the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13. The sixteenth transistor T16 is turned off, and the Nth stage pulse signal G3(n) starts to output high level.

[0080] Reset stage t2: when the second scanning signal G2(n) is at high level, the third transistor T3 and the fourth transistor T4 are turned on, the pull-up node Q is discharged to low level, and the fifteenth transistor T15, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are turned off. At the same time, the stage transmission signal Cout is switched to high level, the eighth transistor T8 is turned on, and the eighth transistor T8 in the on state charges the gate of the ninth transistor T9 to high level, and the pull-down node QB is charged to high level by the ninth transistor T9. The sixteenth transistor T16 is turned on, and the pulse signal G3(n) of the Nth stage outputs low level.

[0081] As is clear from the above timing, when the nth stage scanning signal G1(n) is at high level and the second scanning signal G2(n) is at low level, the potential of the pull-up node Q is pulled up, and the Nth stage pulse signal G3(n) is output at high level through the fifteenth transistor T15. When the nth stage scanning signal G1(n) is at low level and the second scanning signal G2(n) is at high level, the potential of the pull-down node QB is pulled up, and the Nth stage pulse signal G3(n) is pulled down through the sixteenth transistor T16. Therefore, by controlling the phase difference between the nth stage scanning signal G1(n) and the second scanning signal G2(n), the pulse width of the Nth stage pulse signal G3(n) can be adjusted. For example, as shown in FIG. 5, when the n+1th stage scanning signal G1(n+1) is provided through a patch line to replace the nth stage scanning signal G1(n), the waveform of the Nth stage pulse signal after repair is shown in G3(n)_repair1. When the n+2th stage scanning signal G1(n+2) is provided through a patch line to replace the nth stage scanning signal G1(n), the waveform of the Nth stage pulse signal after repair is shown in G3(n)_repair2.

[0082] Accordingly, referring to Fig. 6, an embodiment of the present application further provides a display panel 1000. The display panel 1000 includes a display area AA and a non-display area NA connected to the display area AA. The display panel 1000 includes a gate driving circuit 100 as described above, and the gate driving circuit 100 is located in the non-display area NA.

[0083] The display panel 1000 further includes other GOA circuits (not shown) to provide multiple sets of scanning signals required by the gate driving circuit 100, such as the nth stage scanning signal, the second scanning signal, and so on.

[0084] In the display panel 1000 provided in the embodiment of the present application, the gate driving circuit 100 includes a multi-stage gate driving unit and at least one patch line. The embodiment of the present application adds a patch line, so that when the nth stage scanning signal accessed by the nth stage gate driving unit is broken, the mth stage scanning signal can be provided through the patch line, so that the nth stage pulse signal can be output normally, thereby improving the yield of the gate driving circuit 100 and improving the quality of the display panel 1000.

[0085] The above is a detailed introduction of the embodiments of the present application. In this specification, the principles and embodiments of the present application are described by applying specific examples, but the description of the above examples is intended to aid in the understanding of the method and core idea of ​​the present application, and is not intended to limit the scope of the patent of the present application. It is clear that the use of equivalent structures or equivalent flow conversions to the contents of the specification and drawings of the present application, or the direct or indirect application in other related technical fields, are also included in the scope of the claims of the present application.

Claims

1. A gate drive circuit, A multi-stage gate driving unit, wherein a gate driving unit of an nth stage in the multi-stage gate driving unit is at least connected to a first control signal line, the first control signal line accesses a scanning signal output from the nth stage of another gate driving circuit different from the gate driving circuit, and the gate driving unit of the nth stage is used to output a pulse signal of an nth stage under the control of the scanning signal output from the nth stage of the other gate driving circuit; a first control signal line and a second control signal line, the second control signal line and the third control signal line are connected to each other through the first control signal line, and the second control signal line and the third control signal line are connected to each other through the first control signal line, the third control signal line and the fourth control signal line are connected to each other through the first control signal line, and the fourth control signal line and the fourth control signal line are connected to each other through the first control signal line, the fourth control signal line and the fourth control signal line are connected to each other through the first control signal line, and the fifth control signal line and the fourth control signal line are connected to each other through the first control signal line, the fourth control signal line and the fourth control signal line are connected to each other through the first control signal line, and the fifth control signal line and the fourth control signal line are connected to each other through the first control signal line, and the fifth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fourth control signal line and the fifth ...

2. 2. The gate driving circuit according to claim 1, further comprising a signal transmission line for transmitting a scanning signal output from the nth stage of the other gate driving circuit, the signal transmission line being provided in a different layer intersecting the first control signal line, and the signal transmission line being connected to the first control signal line through a via.

3. The gate drive circuit as described in claim 1, characterized in that each of the patch lines accesses a scanning signal output from the mth stage of the corresponding other gate drive circuit.

4. The gate drive circuit as described in claim 1, characterized in that each of the patch lines accesses a scanning signal output from the mth stage of the corresponding other gate drive circuit.

5. the patch lines include at least one first patch line and at least one second patch line; 2. The gate drive circuit of claim 1, wherein the first patch line accesses a scanning signal output from the mth stage of the other gate drive circuit, where m is less than n, and the second patch line accesses a scanning signal output from the mth stage of the other gate drive circuit, where m is greater than n.

6. 6. The gate driving circuit according to claim 5, wherein the first patch line and the second patch line are located on both sides of the first control signal line, respectively.

7. 2. The gate drive circuit according to claim 1, wherein a repair mark is provided on the patch line, and an intersection of the patch line and the first control signal line corresponds to the repair mark.

8. The nth stage gate driving unit includes: a pull-up control module connected to a high potential wiring, a first low potential wiring, the first control signal line, a second control signal line and a pull-up node, and used to control the potential of the pull-up node; a pull-up output module connected to the high potential wiring, the pull-up node and a signal output terminal, and used for outputting the pulse signal of the nth stage at the signal output terminal under the control of the potential of the pull-up node; a pull-down control module connected to the high potential wiring, the second control signal line, the stage transmission wiring, the pull-up node, the first low potential wiring and the pull-down node, and used to control the potential of the pull-down node; 2. The gate driving circuit as claimed in claim 1, further comprising: a pull-down module connected to a second low potential wiring, the signal output terminal and the pull-down node, and used to pull down the potential of the signal output terminal under the control of the potential of the pull-down node.

9. the pull-up control module includes a first transistor, a second transistor, a third transistor and a fourth transistor; 9. The gate drive circuit according to claim 8, wherein a gate of the first transistor and a gate of the second transistor are both connected to the first control signal line, a source of the first transistor is connected to the high potential wiring, a drain of the first transistor is connected to the source of the second transistor, a drain of the second transistor is connected to the pull-up node, a gate of the third transistor and a gate of the fourth transistor are both connected to the second control signal line, a source of the third transistor is connected to the first low potential wiring, a drain of the third transistor and a source of the fourth transistor are connected to a first node, and a drain of the fourth transistor is connected to the pull-up node.

10. the pull-up control module further includes a fifth transistor, a sixth transistor, a seventh transistor, and a first capacitor; 10. The gate drive circuit of claim 9, wherein a gate of the fifth transistor, a drain of the sixth transistor, and one end of the first capacitor are all connected to the pull-up node, a source of the fifth transistor is connected to the high potential wiring, a drain of the fifth transistor, a source of the sixth transistor, and a drain of the seventh transistor are all connected to the first node, a gate of the sixth transistor and a gate of the seventh transistor are all connected to the pull-down node, a source of the seventh transistor is connected to the first low potential wiring, and the other end of the first capacitor is connected to the signal output terminal.

11. the pull-down control module includes an eighth transistor, a ninth transistor and a second capacitor; 9. The gate drive circuit of claim 8, wherein a gate of the eighth transistor is connected to the stage transmission wiring, a source of the eighth transistor is connected to the second control signal line, a drain of the eighth transistor, one end of the second capacitor and a gate of the ninth transistor are connected to each other, the other end of the second capacitor and a source of the ninth transistor are all connected to the high potential wiring, and a drain of the ninth transistor is connected to the pull-down node.

12. the pull-down control module further includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; 12. The gate drive circuit according to claim 11, wherein a gate of the tenth transistor and a gate of the eleventh transistor are all connected to the pull-up node, a drain of the tenth transistor, a drain of the twelfth transistor and a gate of the fourteenth transistor are all connected to the pull-down node, a source of the tenth transistor, a drain of the eleventh transistor, a source of the twelfth transistor, a drain of the thirteenth transistor and a drain of the fourteenth transistor are all connected to a second node, a source of the eleventh transistor and a source of the thirteenth transistor are all connected to the first low potential wiring, a gate of the twelfth transistor and a gate of the thirteenth transistor are all connected to the first control signal line, and a source of the fourteenth transistor is connected to the high potential wiring.

13. A display panel, comprising a display area and a non-display area connected to the display area, the display panel comprising a gate drive circuit according to any one of claims 1 to 12, and another gate drive circuit different from the gate drive circuit, the gate drive circuit being located in the non-display area.

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