MEMORY DEVICE, METHOD FOR OPERATING A MEMORY DEVICE, MEMORY SYSTEM - Patent application

Abstract

Embodiments provide a memory, a method for operating a memory, and a memory system, the method for operating a memory including: concurrently performing programming operations on at least two memory planes of the memory by employing a multi-plane programming scheme; and, in response to determining that a memory plane with a programming exception exists in the at least two memory planes, sequentially performing programming operations on the at least two memory planes by employing a single-plane programming scheme.

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to the field of semiconductors, and more particularly to memories, methods for operating the same, and memory systems. [Background technology]

[0002] According to the structural configuration of the memory cell array of a memory, the memory can be classified as a single-plane type and a multi-plane type. A single-plane type memory has one memory plane. A multi-plane type memory includes multiple memory planes. For a multi-plane type memory, a multi-plane programming method can be used to simultaneously perform programming operations on two or more memory planes of the memory to improve programming efficiency.

[0003] Although the adoption of a multi-plane programming method can improve programming efficiency, it inevitably has the problem of adjacent plane interference. For example, in the case of a multi-plane programming method, if a programming fault occurs in one memory plane, it often causes programming faults in other memory planes that are programmed at the same time. Therefore, it is urgent to provide a programming method that reduces the adverse effects of adjacent interference while ensuring a certain programming efficiency. Summary of the Invention [Problem to be solved by the invention]

[0004] To solve one or more of the existing technical problems, embodiments of the present disclosure provide a memory, a method for operating a memory, and a memory system. [Means for solving the problem]

[0005] An embodiment of the present disclosure provides a method for operating a memory, the method including: concurrently performing programming operations on at least two memory planes of the memory by employing a multi-plane programming scheme; and, in response to determining that a memory plane having a programming exception exists in the at least two memory planes, sequentially performing programming operations on the at least two memory planes by employing a single-plane programming scheme.

[0006] In the above-mentioned embodiment, continuing to sequentially perform programming operations on each of the at least two memory planes by adopting a single-plane programming mode includes: responsive to employing the single plane programming mode, for each of the at least two memory planes, applying a first programming voltage on a first selected word line on the respective memory plane; The first programming voltage may be less than the second programming voltage, the second programming voltage may be a programming voltage applied to a first selected word line on each memory plane determined to have a programming exception, and the first selected word line may be a selected word line on each memory plane determined to have a programming exception.

[0007] In the foregoing embodiment, the method further comprises: The method further includes applying a first turn-on voltage to unselected word lines on the respective memory plane in response to applying the first programming voltage to the first selected word lines of the respective memory plane, where the first turn-on voltage may be less than the second turn-on voltage, and the second turn-on voltage may be a turn-on voltage applied to the unselected word lines on the respective memory plane determined to have a programming exception.

[0008] In the above embodiment, determining that a memory plane having a programming exception exists in at least two memory planes includes: Detecting a number of times a programming verify is performed on currently programmed memory cells in the at least two memory planes; and determining that a memory plane having a programming exception exists in the at least two memory planes in response to a number of programming verifications occurring that exceeds a preset number corresponding to the current data to be written.

[0009] In the foregoing embodiment, the method further comprises: It further includes programming verify voltages to currently programmed memory cells in the different memory planes by using different voltage sources.

[0010] In the foregoing embodiment, the method further comprises: The method further includes applying programming verify voltages to memory cells respectively corresponding to different word lines on a same memory plane by using different voltage sources.

[0011] In the above embodiment, in response to determining that a memory plane having a programming exception exists in the at least two memory planes, continuing to sequentially perform programming operations in each of the at least two memory planes by employing a single-plane programming mode includes: in response to determining that a memory plane having a programming exception exists in the at least two memory planes, continuing to sequentially perform programming operations in each of the at least two memory planes by directly employing a single-plane programming mode; or In response to determining that a memory plane having a programming exception exists in the at least two memory planes, pausing the programming operations, and, after receiving a second instruction, continuing to sequentially perform the programming operations in each of the at least two memory planes by employing a single-plane programming mode.

[0012] In the foregoing embodiment, the method further comprises: storing a first flag in response to determining that a memory plane having a programming exception exists in the at least two memory planes; and storing data allocated to the memory plane in which the programming exception exists in another memory plane in the memory after receiving a first instruction, the first instruction may be configured to instruct dumping the data stored in the memory plane corresponding to the first flag.

[0013] In the above-mentioned embodiment, continuing to sequentially perform programming operations on each of the at least two memory planes by adopting a single-plane programming mode includes: continuing to perform programming operations on a first memory plane of the at least two memory planes; and in response to determining that the programming operation for the first memory plane has failed or is completed, continuing to perform the programming operation on a second memory plane of the at least two memory planes.

[0014] In the foregoing embodiment, the method further comprises: Further included is continuing to perform programming operations on the at least two memory planes by employing a multi-plane programming mode in response to determining that no memory plane has a programming exception in the at least two memory planes.

[0015] An embodiment of the present disclosure provides a memory including a memory plane and a peripheral circuit coupled to the memory plane, wherein the peripheral circuit is configured to concurrently perform programming operations on at least two memory planes of the memory by employing a multi-plane programming scheme, and in response to determining that a memory plane having a programming exception exists in the at least two memory planes, sequentially perform programming operations on the at least two memory planes by employing a single-plane programming scheme.

[0016] In the above-described embodiment, the peripheral circuitry may include a control circuit and a row driver, the row driver being coupled to at least two memory planes and controlled by the control circuit; The row drivers may be configured to apply word line drive voltages to at least two memory planes in which programming operations are performed simultaneously in a multi-plane programming mode; The row driver may be further configured to apply a word line drive voltage to the selected memory plane in a single plane programming mode.

[0017] In the aforementioned embodiment, the row driver is configured for each of the at least two memory planes to apply a first programming voltage to a first selected word line on the respective memory plane after switching from the multi-plane programming mode to the single-plane programming mode.

[0018] The first programming voltage may be less than the second programming voltage, the second programming voltage may be a programming voltage applied to a first selected word line on each memory plane determined to have a programming exception, and the first selected word line may be a selected word line on each memory plane determined to have a programming exception.

[0019] In the aforementioned embodiment, the row driver may be further configured to apply a first turn-on voltage to unselected word lines on the respective memory plane in response to applying the first programming voltage on the first selected word line of the respective memory plane, where the first turn-on voltage may be less than the second turn-on voltage, where the second turn-on voltage may be a turn-on voltage applied to unselected word lines on the respective memory plane determined to have a programming exception.

[0020] In the above embodiment, the peripheral circuitry includes: Detecting a number of programming verify operations performed on currently programmed memory cells in the at least two memory planes; The memory plane may be further configured to determine that a memory plane having a programming exception exists in the at least two memory planes in response to a number of programming verify exceeding a preset number corresponding to the current data to be written.

[0021] In the above-mentioned embodiment, the peripheral circuit may further include a plurality of programming verify voltage generators, each of the plurality of programming verify voltage generators may be respectively coupled to one of the at least two memory planes and controlled by the control circuit; The multiple programming verify voltage generators may be configured to respectively apply programming verify voltages to currently programmed memory cells in different memory planes.

[0022] In the above embodiment, each of the plurality of programming verify voltage generators may be respectively coupled to a word line of one of the at least two memory planes; The multiple programming verify voltage generators may be configured to respectively apply programming verify voltages to memory cells corresponding to different word lines on the same memory plane.

[0023] In any of the foregoing embodiments, the peripheral circuitry may be configured, in response to determining that a memory plane having a programming exception exists in the at least two memory planes, to continue sequentially performing programming operations in each of the at least two memory planes by directly adopting a single-plane programming mode; or The peripheral circuitry may be further configured to, in response to determining that a memory plane having a programming exception exists in the at least two memory planes, pause the programming operations, and, after receiving a second instruction, continue sequentially performing programming operations in each of the at least two memory planes by employing a single-plane programming mode.

[0024] In the aforementioned embodiment, the peripheral circuit may further include a register configured to store a first flag in response to determining that a memory plane having a programming exception exists in the at least two memory planes; The peripheral circuit may be configured to store data assigned to the memory plane in which the programming exception exists in another memory plane in the memory after receiving a first instruction, and the first instruction may be configured to instruct the data stored in the memory plane corresponding to the first flag to be dumped.

[0025] In the above-described embodiments, the memory may include a 3D NAND type memory.

[0026] An embodiment of the present disclosure further provides a memory system, the memory system including one or more memories described in the previous embodiments; a memory controller coupled to the memory.

[0027] In the above embodiment, the method or system includes: the peripheral circuitry is configured to receive a second instruction, and in response to the second instruction, concurrently perform programming operations in at least two of the plurality of memory planes by employing a multi-plane programming mode, and in response to determining that a memory plane having a programming exception exists in the at least two memory planes, suspend the programming operations and store a first flag; The memory controller may be configured to issue a third instruction according to the first flag; The peripheral circuitry may be further configured to receive a third instruction and, in response to the third instruction, continue to sequentially perform programming operations on each of the at least two memory planes by employing a single-plane programming mode.

[0028] In the embodiment of the present disclosure, when a problem occurs in the programming operation simultaneously performed on multiple memory planes by adopting the multi-plane programming mode, instead of always remaining in the multi-plane programming mode, the programming operation continues to be performed sequentially on each of the multiple memory planes by adopting the single-plane programming mode. That is, in the embodiment of the present disclosure, upon receiving an instruction for a programming operation, the programming operation may be performed in the multi-plane programming mode by default, thereby ensuring a certain programming efficiency. Upon determining that there is a programming exception, the programming operation continues by switching to the single-plane programming mode, which limits the programming exception in the memory plane having the exception and further mitigates the impact of the programming exception on other normal memory planes. That is, the adverse effect of adjacent plane interference can be reduced. [Brief description of the drawings]

[0029] One or more embodiments are illustrated by the accompanying drawing figures, which do not constitute any limitations of the embodiments. Unless otherwise stated, the drawing figures are not to be considered as limiting in scale. [Figure 1] 1 is a schematic flow chart of a method for operating a memory according to one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic structural diagram of a memory according to one embodiment of the present disclosure. [Diagram 3] 1 is another schematic flow chart of a method for operating a memory, according to an embodiment of the present disclosure. [Figure 4] FIG. 1 is a schematic structural diagram of a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. However, it can be understood by those skilled in the art that in various embodiments of the present disclosure, many technical details are proposed to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this specification can be realized.

[0031] The memory in the embodiment of the present disclosure includes, but is not limited to, a 3D NAND type memory. For ease of understanding, a 3D NAND type memory is used as an example for explanation. However, it should be understood that the embodiment of the concept of the present disclosure is not limited to the configuration and can also be applied to a 2D NAND memory. Furthermore, without departing from the scope of the present disclosure, the present disclosure can also be applied to other non-volatile memory devices such as an electrically erasable programmable read only memory (EEPROM), a NOR type flash memory, a chase random access memory (PRAM), a magnetoresistive random access memory (MRAM), a resistive random access memory (RRAM), and a ferroelectric random access memory (FRAM®).

[0032] In practical applications, the 3D NAND memory may include a memory cell array and peripheral circuits. The memory cell array may have multiple memory planes, each memory plane may include multiple memory blocks, and each memory block may include multiple memory pages. The memory page may be the smallest unit for read and write (i.e., programming) operations, and the memory block may be the smallest unit for erase operations.

[0033] The peripheral circuitry may include any suitable digital, analog, and / or mixed signal circuitry configured to facilitate various operations of the memory, such as read, write, and erase operations. For example, the peripheral circuitry may include control logic (e.g., control circuitry or controller), data buffers, decoders (also called decoders), drivers, read / write circuits, and the like. When the control logic receives a read / write operation command and address data, under the operation of the control logic, the decoder can apply corresponding voltages from the drivers to corresponding bit lines and word lines based on the decoded address to read / write data and exchange data with the outside via the data buffer.

[0034] 3D NAND memory in memory systems has various defects, some of which can be detected at the time of shipment, and some of which appear as the usage environment changes after shipment. In practical applications, some memory cell arrays of 3D NAND memory may have structural weaknesses. These structural weaknesses may develop and become defects after a long time or multiple programming and erasing operations. For example, the memory cell arrays of 3D NAND memory must withstand high pressure stress during programming and erasing cycles, and the weak structure of some memory cell arrays of 3D NAND memory may develop into defects after cycling.

[0035] When a defect occurs in a 3D NAND memory, data loss may occur. If the defect is a short circuit in a word line (WL), the data of the memory cells corresponding to the entire WL may be destroyed. Since each WL may correspond to multiple strings of memory cells, a large amount of data may be lost, thereby causing the failure of the memory system. This type of failure is generally defined as a reliability failure of the 3D NAND memory, and may further cause the failure of the memory system in the field.

[0036] In the case of Programming Status Failed (PSF), the memory system may recover the lost data using Redundant Arrays of Independent Disks (RAID). Generally, memory systems employ plane-level RAID, which can only recover one memory plane from a failure. If programming fails on multiple memory planes, the memory system cannot recover the data. In the case of such failure, the memory system may perform RAID at the die level, but this increases the configuration cost of the memory system.

[0037] In 3D NAND memories, the internal voltage bias power supply is usually shared between different planes during programming operations to save circuit area and power consumption. If one of the memory planes is defective, the other memory planes sharing the internal voltage bias power supply may not reach the target level. Therefore, even if only one memory plane is physically defective, programming failures often occur in multiple memory planes, i.e., the Neighbor Plane Disturb (NPD) mentioned above. It is clear that the Neighbor Plane Disturb has adverse effects such as data loss, as mentioned above. From this, if a physical defect exists in only one memory plane, it is desirable that only the defective memory plane is disturbed.

[0038] One embodiment of the present invention proposes a method for operating a memory (memory device). Figure 1 is a schematic flow chart of a method for operating a memory according to one embodiment of the present disclosure. The method includes the following steps:

[0039] In step 101, a programming operation is performed simultaneously on at least two of a plurality of memory planes of a memory by employing a multi-plane programming scheme.

[0040] In step 102, in response to determining that a memory plane having a programming exception exists in the at least two memory planes, programming operations are sequentially performed in the at least two memory planes by employing a single-plane programming scheme.

[0041] Here, a memory may include multiple memory planes, which may be programmed simultaneously depending on the configuration of the memory. The multiple memory planes may be grouped into groups, and multiple memory planes within each group may be programmed simultaneously.

[0042] In step 101, it is understood that in a multi-plane programming scheme, multiple memory planes included in a memory may be simultaneously programmed under the control of one controller, and multiple memory planes that are simultaneously programmed may share the same row driver. In practical applications, for multiple memory planes that are simultaneously programmed, the same row (word line) may be simultaneously programmed, or different rows (word lines) may be simultaneously programmed according to the configuration of the row driver.

[0043] In practical applications, the operation commands in the single-plane programming scheme and the multi-plane programming scheme may be different. In order to increase the programming speed of the memory, the multi-plane programming scheme may be a more common choice of the programming scheme.

[0044] In step 102, a programming exception may be understood as a programming failure of a particular memory plane that is being programmed simultaneously due to a memory plane defect or other factor.

[0045] In practical applications, when performing programming operations on multiple memory planes simultaneously, a word line driving voltage may be simultaneously applied to the word lines in the corresponding memory planes for each memory plane during the programming operation. Here, the word line driving voltage may include a programming voltage applied to the selected word line and a turn-on voltage applied to the unselected word lines. During a programming verify process, a programming verify voltage may be simultaneously applied on the word lines in the corresponding memory planes. If the programming verify for one memory plane fails, multiple memory planes programmed simultaneously may fail the programming verify.

[0046] In practical applications, the embodiments of the present disclosure do not limit a particular method for determining that a memory plane with a programming exception exists among multiple memory planes that are programmed simultaneously.

[0047] In some embodiments, determining that a memory plane with a programming exception exists in at least two memory planes may include the following operations.

[0048] The number of programming verify operations performed on currently programmed memory cells in the at least two memory planes can be detected.

[0049] In response to the number of programming verify operations performed on the currently programmed memory cells exceeding a preset number corresponding to the current data to be written, it can be determined that a memory plane having a programming exception exists in at least two memory planes.

[0050] Here, the preset number can be understood as the maximum number of programming verifications corresponding to a certain data state (programmed state).

[0051] In practical application, a relationship table between data state and maximum number of programming verifications can be established first according to empirical values. In the table, the maximum number of programming verifications (i.e., the preset number of programming verifications) corresponding to the data state can be found according to the data state. In practical application, the maximum number of programming verifications can be related to the data written and the type of memory cell (single-level cell type or multi-level cell type) for writing data.

[0052] Take a Trinary-Level Cell (TLC) type memory cell as an example. The Trinary-Level Cell has eight data states, one of which (the 0th state) is an erased state, and the remaining seven of which are programming states (the 1st state to the 7th state) in which an Incremental Step-Pulse Programming (ISPP) method is adopted. According to empirical values, it can be determined how many programming pulses should be applied (i.e., how many programming verifications should be performed) to reach the first state of programming. For example, six programming verifications should be completed to reach the first state of programming, and nine programming verifications should be completed to reach the second programming state. In general, the higher the data state is reached, the more programming verifications are required. That is, the preset number of programming verifications may be related to the number of bits of the data state, and typically, the more bits of the data state, the higher the preset number of programming verifications corresponding to the data state.

[0053] In practical applications, for any one of multiple memory planes that are simultaneously programmed during a programming operation, in some embodiments, once programming to a data state is completed, programming verification of the corresponding data state can be performed on all memory cells in a memory page, while in other embodiments, after programming of a memory page is completed, programming verification can be performed sequentially from low state to high state on the programming states of each memory cell in the memory page.

[0054] A trinary level cell (TLC) type memory cell is further taken as an example for illustration. For the programming verification performed on each memory cell in a memory page, when the programming of one data state is completed for all memory cells in one memory page, the programming verification of the corresponding data state is performed. Specifically, a first state is programmed on all memory cells, and then all memory cells are verified whether they can reach the first state within a preset number (e.g., 6) of programming verifications. If so, a second state is programmed on the memory cells whose written data exceeds the first state, and then the verification of the second state is performed. If a verification failure occurs at a certain data state during the period, i.e., the preset number of the corresponding programming verifications is exceeded but the corresponding data state is not reached, it can be indicated that the currently programmed memory plane is a memory plane with a programming exception.

[0055] In one embodiment, it should be noted that when performing programming verification, it does not mean that the currently programmed memory plane is determined as a memory plane with a programming exception when the number of programming verifications of any memory cell in one memory page exceeds a preset number but does not reach a specified data state. It can be understood that a memory has a certain error correction capability. For example, an error correction circuit (ECC) can be used to correct a certain number of memory cells with errors. Therefore, instead of determining the currently programmed memory plane as a memory plane with a programming exception for a limited number of programming verification errors (within the error correction capability range), the currently programmed memory plane may be determined as a memory plane with a programming exception only when the number of verification errors exceeds the error correction capability range.

[0056] In practical applications, a flag may be set to indicate a multi-plane programming fault, and the flag to indicate the multi-plane programming fault may be stored in a status register of the memory. In one embodiment, if the memory sees a flag in the status register to indicate a multi-plane programming fault, the control logic may directly switch to a single-plane programming mode for programming. In another embodiment, if the memory sees a flag in the status register to indicate a multi-plane programming fault, the multi-plane programming state may be suspended. At that point, the memory system or host may check the status register to discover that the memory has an exception to multi-plane programming if it has suspended the multi-plane programming state. An instruction may also be issued by the memory system or host to instruct the memory to switch to a single-plane programming mode for programming.

[0057] Based thereon, in response to determining that a memory plane having a programming exception exists in the at least two memory planes, sequentially performing programming operations on the at least two memory planes by employing a single-plane programming scheme, in response to determining that a memory plane having a programming exception exists in the at least two memory planes, sequentially performing programming operations on the at least two memory planes by directly employing a single-plane programming scheme; or In response to determining that a memory plane having a programming exception exists in the at least two memory planes, pausing the programming operations, and after receiving a second instruction, sequentially performing the programming operations on the at least two memory planes by employing a single-plane programming scheme.

[0058] That is, in practical applications, when there is an exception in the multi-plane programming scheme, the memory can automatically switch from the multi-plane programming scheme to the single-plane programming scheme. The memory can also switch from the multi-plane programming scheme to the single-plane programming scheme after receiving an instruction to instruct the memory to adopt the single-plane programming scheme issued by a host or a memory controller in a memory system.

[0059] In practical applications, after the single-plane programming method is completed, the memory system or host can detect a programming fault through the status register, in which case the memory system or host can take further measures, such as issuing an instruction to dump the data stored in the memory plane using a programming exception.

[0060] Based on this, in some embodiments, the method may further include:

[0061] storing a first flag in response to determining that a memory plane having a programming exception exists in the at least two memory planes; and storing data allocated to the memory plane in which the programming exception exists in another memory plane in the memory upon receiving a first instruction, the first instruction configured to instruct dumping the stored data in the memory plane corresponding to the first flag.

[0062] Here, the first flag may represent that the memory plane with the programming exception exists in at least two memory planes. The first instruction may be configured to instruct to dump the stored data in the memory plane corresponding to the first flag. In practical applications, among multiple memory planes to be simultaneously programmed, memory plane A has a structural defect (such as leakage current), and memory plane B has no structural defect. When memory plane A and memory plane B are simultaneously powered using the same voltage source, the word lines of memory plane A and memory plane B are originally prepared to be applied with the same verify voltage. However, due to the cross-plane shared voltage source, the verify voltage actually applied to the word lines of memory plane A may differ from the verify voltage applied to the word lines of memory plane B (the actual applied voltage to the word lines of memory plane A with leakage current is low), which may cause an offset from the target applied voltage. It will be understood that the target value of the write threshold voltage Vt is related to the programming voltage, and when the programming voltages applied to the two memory planes are different, the target voltages of the write thresholds of the two memory planes may differ. In this case, there may be a mismatch in the data written to memory plane A and in the data written to memory plane B. That is, even if the memory planes without structural defects pass the multi-plane programming method, the distribution of the write threshold voltages Vt of the memory cells may be turned off due to incorrect verification conditions for the mismatch of the cross-plane shared verify voltage. In this case, the independent power supply can mitigate the potential problem.

[0063] In some embodiments, the method comprises: It further includes applying programming verify voltages to the currently programmed memory cells in the different memory planes respectively by using different voltage sources.

[0064] wherein in some embodiments, the method comprises: The method further includes applying programming verify voltages to memory cells respectively corresponding to different word lines in a same memory plane by using different voltage sources.

[0065] In practical application, during programming voltage verification, different voltage sources can be used to power selected WLs in different memory planes. Based on the independent supply of programming verification voltage sources to different memory planes, WLs of different rows in the same memory plane can also be powered by different voltage sources. Note that the independent power sources in this specification may refer to physical isolation for each of the voltage sources.

[0066] In this manner, it can be appreciated that it is possible to apply independent programming verify voltages to different memory planes, thereby ensuring that the programming verify results of memory planes without structural defects are accurate.

[0067] It should be noted that in step 102, in one embodiment, it may be possible to determine only whether a problem exists in at least one memory plane of the multiple memory planes being simultaneously programmed, without determining which memory plane of the multiple memory planes being simultaneously programmed has a problem.

[0068] In an embodiment of the present disclosure, if it is determined that there is a memory plane with a programming exception, a single plane programming scheme may be configured to simultaneously perform programming operations on the programmed memory planes. Here, a single plane programming scheme may be understood to program only one memory plane included in the memory at a time. In a single plane programming scheme, a row driver may apply a word line drive voltage to only one selected memory plane.

[0069] In some embodiments, sequentially performing programming operations on at least two memory planes by employing a single-plane programming scheme includes: performing a programming operation on a first memory plane of the at least two memory planes; and in response to determining that the programming operation on the first memory plane has failed or is completed, performing a programming operation on a second memory plane of the at least two memory planes.

[0070] Here, both the first memory plane and the second memory plane may be any one of a plurality of memory planes that are programmed simultaneously.

[0071] In practical applications, after switching to the single-plane programming scheme, at least two memory planes may be programmed sequentially in a random sequence, or the programming operations of the memory planes may be performed sequentially in a prescribed order. For each memory plane, if it is programmed, it may continue to be in the previous programming state.

[0072] For example, a multi-plane programming scheme may be adopted to simultaneously program memory plane A, memory plane B, and memory plane C of the memory. In the multi-plane programming scheme, if it is detected that there is a memory plane with a programming exception, it may be assumed that the programming exception is due to a structural defect in memory plane A, and memory planes B and C do not have structural defects. When switching to a single-plane programming scheme, programming operations may be performed on memory plane A, memory plane B, and memory plane C. It may be assumed that memory plane A is programmed first, and data for continuing to perform the programming operation may be obtained from a page buffer (PB) of memory plane A. For example, the memory cells may be of a trinary level cell (TLC) type, and the second state of some of the memory cells in the first word line may be programmed in response to a multi-plane verify failure. Then, the programming operation may continue for the second state of some of the memory cells in the first word line. Since memory plane A has a defect, memory plane A may eventually end up with a programming failure at the plane level. Then, if memory plane A indicates a programming failure (at this time, it can be determined that the defective memory plane is memory plane A), a programming operation can start to be performed on memory plane B. Data for continuing the programming operation may be obtained from the PB of memory plane B. Once the programming operation on memory plane B is completed, the programming operation on memory plane C may be started again, and data for continuing the programming operation may be obtained from the PB of memory plane C until the programming operation on memory plane C is completed.

[0073] It should be noted that, for the defective memory plane A, if all data to be written in a programming operation is always stored in the PB of memory plane A, the data that has failed to be written in memory plane A may be transferred to another defective memory plane. If the PB of memory plane A dynamically stores only the data to be written in a programming operation, the above-mentioned RAID can be used to perform data recovery, and the recovered unwritten data in memory plane A can be transferred to another good memory plane.

[0074] In practical applications, multiple memory planes that are programmed simultaneously by adopting a multi-plane programming scheme may be provided with word line driving voltages by using the same row driver. However, if there is a defective memory plane among the multiple memory planes that are programmed simultaneously, such as a memory plane with leakage current, the voltage generated by the power supply may be higher than the voltage actually applied to the word lines on the memory plane. After switching to single-plane programming, the leakage current distribution may change, and the voltage generated by the high power supply may cause over-programming problems.

[0075] Based on this, in some embodiments, sequentially performing programming operations on at least two memory planes by employing a single-plane programming scheme includes: applying, for each of the at least two memory planes, a first programming voltage to a first selected word line on the respective memory plane; The first programming voltage is less than the second programming voltage, the second programming voltage being a programming voltage applied to a first selected word line on each memory plane determined to have a programming exception, the first selected word line being a selected word line on each memory plane determined to have a programming exception.

[0076] In practical applications, for each of the memory planes, the initial programming voltage Vpgm applied to the selected word line can be set to a low level when continuing to perform the programming operation. That is, if the multi-plane programming fails, the programming voltage applied to the selected word line (i.e., the first word line) can be appropriately reduced. In practical applications, the reduction amount can be determined based on empirical values. It is noted that reducing the programming voltage can alleviate the over-programming problem to some extent.

[0077] In some embodiments, the method comprises: Further including applying a first turn-on voltage to unselected word lines on the respective memory plane in response to applying the first programming voltage to the first selected word lines of the respective memory plane, the first turn-on voltage being less than a second turn-on voltage, the second turn-on voltage being a turn-on voltage applied to the unselected word lines on the respective memory plane that have been determined to be programming exceptions.

[0078] In practical applications, for each memory plane, the initial turn-on voltage Vpass applied to the unselected word lines may be set to a low level when continuing to perform programming operations.

[0079] In some embodiments, the Vpgm / Vpass of the wordlines on a memory plane can be determined according to the programming verify voltages of each memory plane in multi-plane programming.

[0080] In some embodiments, the method comprises: Further including, in response to determining that no memory plane has a programming exception in the at least two memory planes, continuing to perform programming operations on the at least two memory planes by employing a multi-plane programming scheme.

[0081] That is, if there are no exceptions to multi-plane programming, the multi-plane programming method may always be used for programming.

[0082] In the solution proposed in the embodiment of the present disclosure, the multi-plane programming failure can be handled by pausing the multi-plane programming scheme. Then, the programming operation can be performed in the single-plane programming scheme. The solution proposed in the embodiment of the present disclosure can address the adjacent plane interference failure of the 3D NAND memory, and also improve the reliability of the 3D NAND memory. In the embodiment of the present disclosure, even if one memory plane is bad and the voltage bias of the bad memory plane becomes inaccurate due to leakage current, the programming verification of all memory planes can be performed more accurately. The solution proposed in the embodiment of the present disclosure may be used to detect possible defects in the memory cell array. In the solution proposed in the embodiment of the present disclosure, the internal misalignment can be returned to normal when switching to the single-plane programming scheme to avoid the over-programming problem.

[0083] An embodiment of the present disclosure further provides a memory including a plurality of memory planes and peripheral circuits coupled to the memory planes.

[0084] The peripheral circuitry may be implemented by, for example, a controller, logic circuitry, etc., which may be correspondingly configured with respective firmware, for example, by executing the firmware to perform programming operations simultaneously on at least two of the plurality of memory planes by employing a multi-plane programming scheme. In response to determining that a memory plane having a programming exception exists in the at least two memory planes, programming operations are performed sequentially on the at least two memory planes by employing a single-plane programming scheme.

[0085] 2 is a block diagram of a memory 1 according to an embodiment of the present disclosure. The memory 1 may have a dual memory plane structure and include peripheral circuits. The peripheral circuits may include a control circuit 10, a voltage generation circuit 11, a row driver 12, and column drivers 131 and 132. The memory planes may include memory planes 141 and 142. Although a dual memory plane structure is used in the embodiment, it should be understood that other numbers of memory planes may be used within the scope of the present disclosure. When a multi-plane programming scheme is employed, the memory planes 141 and 142 can be programmed simultaneously.

[0086] In practical applications, the control circuit 10 may be coupled to a voltage generating circuit 11, a row driver 12, and column drivers 131 and 132. The voltage generating circuit 11 may be coupled to the row driver 12. The row driver 12 may be coupled to a memory plane 141 via a string selection line SSL1, word lines WL1(1) to WL1(N), and a ground selection line GSL1, where N is a positive integer, for example, N=128. The row driver 12 may be coupled to a memory plane 142 via a string selection line SSL2, word lines WL2(1) to WL2(N), and a ground selection line GSL2. The column driver 131 may be coupled to the memory plane 141 via bit lines BL1(1) to BL1(M), where M is a positive integer, for example, M=131072. The column driver 132 may be coupled to the memory plane 142 via bit lines BL2(1) to BL2(M). Each of memory planes 141 and 142 may include multiple memory blocks, each of memory blocks may include multiple memory pages, and each memory page may include multiple memory cells. Memory cells in memory plane 141 may be addressed by word lines WL1(1)-WL1(N) and bit lines BL1(1)-BL1(M), and memory cells in memory plane 142 may be addressed by word lines WL2(1)-WL2(N) and bit lines BL2(1)-BL2(M).

[0087] The control circuit may communicate with a host or memory controller to receive data for storing data in the memory planes 141 and 142 and to transmit data obtained from the memory planes 141 and 142. The control circuit may receive commands, addresses, or data from the host or memory controller, and may generate column address signals Scadr1, Scadr2, row address signals Sradr, and voltage control signals Svc. The voltage generation circuit may generate voltages for read, programming, erase, and verify operations in response to the voltage control signals Svc from the control circuit. The voltages generated by the voltage generation circuit 11 may exceed the power supply voltages supplied to the memory 1. The row driver 12 may operate in response to the row address signals Sradr from the control circuit 10 to select word lines for read, programming, erase, and verify operations. The column drivers 131 and 132 may operate in response to the column address signals Scadr1 and Scadr2 from the control circuit 10 to generate bit line signals for selecting bit lines for read, programming, erase, and verify operations.

[0088] During a programming operation, the voltage generation circuit 11 can use a power supply voltage (e.g., 3.3V), a programming voltage (e.g., 20V), and a programming pass voltage (e.g., 10V). The row driver 12 can apply programming pulses having an amplitude of the programming voltage on the selected word line, a programming pass voltage to the unselected word lines, a power supply voltage to the string select lines SSL1, SSL2, and a ground voltage to the ground select lines GSL1, GSL2. Also, the column drivers 131 and 132 may apply a ground voltage (e.g., 0V) to the selected bit lines and a power supply voltage to the unselected bit lines. During a verify operation, the voltage generation circuit can generate the appropriate verify voltages, and the row driver may apply the appropriate verify voltage to the selected word line, a power supply voltage to the string select lines SSL1, SSL2, and a power supply voltage to the ground select lines GSL1, GSL2. Then, column drivers 131 and 132 can apply ground voltage to unselected bit lines and power supply voltage to selected bit lines of memory planes 141 and 142, respectively, to read data from selected memory cells on the selected bit lines. If the data read is incorrect, control circuit 10 can verify that the selected memory cell is faulty, and if the data read is correct, control circuit 10 can verify that the selected memory cell is pass.

[0089] The memory cells may be of single-level cell (SLC) type, multi-level cell (MLC) type, tertiary-level cell (TLC) type, quad-level cell (QLC) type, penta-level cell (PLC) type, or higher level type. Each memory cell can maintain one of Q possible data states, where Q is a positive integer equal to or greater than 2. For example, for SLC, Q=2, for MLC, Q=4, for TLC, Q=16, for QLC, and Q=32 for PLC. The Q possible data states can include an erased state S(0) and programming states S(1)-S(Q-1), where programming state S(1) is the lowest programming state and programming state S(Q-1) is the highest programming state. In one example, the TLC may be programmed to one of eight possible data states, with programming state S(1) being the lowest programming state and programming state S(7) being the highest programming state.

[0090] The memory cells may be initially set to an erased state S(0), and then a series of programming verify operations may be performed on the memory cells to program the memory cells to corresponding target programming states. The series of programming verify operations may start with the lowest programming state S(1) and then proceed to higher programming states until the threshold voltage of the selected memory cell reaches the corresponding verify voltage level of the corresponding target programming state. In some embodiments, the verify voltages may be selected as the minimum threshold voltages of the threshold voltage distribution curves of the programming states S(1)-S(Q-1), respectively. Each programming verify operation may include a programming operation and a subsequent verify operation. During the programming operation, some of the memory cells may be selected row by row, from the first row to the Nth row, or from the Nth row to the first row, to be programmed to the programming state.

[0091] In some embodiments, the peripheral circuitry includes a control circuit and a row driver, the row driver coupled to the at least two memory planes and controlled by the control circuit.

[0092] The row drivers may be configured to apply word line drive voltages to at least two memory planes in which programming operations are performed simultaneously in a multi-plane programming scheme.

[0093] The row driver may be further configured to apply a word line drive voltage to a selected memory plane in a single plane programming scheme.

[0094] The row drivers herein may be understood with reference to the row drivers of Figure 2, except that in this embodiment the row drivers are coupled to multiple memory planes, whereas in a single-plane approach the row drivers apply word line drive voltages to only one of the selected memory planes, where the word line drive voltages may include a programming voltage applied to the selected word line and a turn-on voltage applied to the unselected word lines, or may include a programming pass voltage.

[0095] In some embodiments, the row driver may be configured to apply a first programming voltage to a first selected word line on the respective memory plane after switching from the multi-plane programming scheme to the single-plane programming scheme for each of the at least two memory planes.

[0096] The first programming voltage is less than the second programming voltage, the second programming voltage being a programming voltage applied to a first selected word line on each memory plane determined to have a programming exception, and the first selected word line being the selected word line on each memory plane determined to have a programming exception.

[0097] In some embodiments, the row driver may be further configured to apply a first turn-on voltage to unselected word lines on the respective memory plane in response to applying the first programming voltage to the first selected word line of the respective memory plane, the first turn-on voltage being less than a second turn-on voltage, the second turn-on voltage being a turn-on voltage applied to unselected word lines on the respective memory plane that have been determined to be a programming exception.

[0098] In practical applications, the control circuit may control the voltage generation circuit to output a lower level initial programming voltage / initial turn-on voltage (Vpgm / Vpass), and then control the row driver to apply Vpgm to only the selected word lines of one selected memory plane and Vpass to the unselected word lines.

[0099] In some embodiments, the peripheral circuitry comprises: Detecting a number of programming verify operations performed on currently programmed memory cells in the at least two memory planes; The memory controller may be further configured to determine that a memory plane having a programming exception exists in the at least two memory planes in response to a number of programming verifications exceeding a preset number corresponding to the current data to be written.

[0100] In some embodiments, the peripheral circuitry may further include a plurality of programming verify voltage generators, each of which may be respectively coupled to one of the at least two memory planes and controlled by the control circuitry.

[0101] The multiple programming verify voltage generators may be configured to respectively apply programming verify voltages to currently programmed memory cells in different memory planes.

[0102] In some embodiments, each of the multiple programming verify voltage generators may be respectively coupled to a word line in one of the at least two memory planes.

[0103] The multiple programming verify voltage generators may be configured to apply programming verify voltages to memory cells corresponding to different word lines within the same memory plane.

[0104] Here, multiple programming verify voltage generators may belong to sub-circuits of the voltage generation circuit of Figure 2. Note that multiple programming verify voltage generators can still be physically isolated from each other when applying to word lines of different memory planes via row drivers.

[0105] In some embodiments, the peripheral circuitry may further include a register configured to store a first flag in response to determining that a memory plane having a programming exception exists in the at least two memory planes.

[0106] The peripheral circuitry may be configured to store data allocated to the memory plane in which the programming exception exists in another memory plane in the memory upon receiving a first instruction, the first instruction being configured to instruct dumping data stored in the memory plane corresponding to the first flag.

[0107] Here, the register may be a status register.

[0108] In practical applications, the control circuit can determine whether to switch programming methods, and after the single-plane programming method is completed, the memory system or host can detect a programming failure through the status register, in which case the memory system or host can take further measures, such as issuing an instruction to dump data stored in the memory plane using a programming exception.

[0109] Note that the memory may suspend the multi-plane programming state if it sees a flag in the status register to indicate a multi-plane programming fault. At that point, the memory system or host may check the status register to discover that the memory has an exception to multi-plane programming if it has suspended the multi-plane programming state. Also, an instruction may be issued by the memory system or host to instruct the memory to switch to a single-plane programming scheme for programming.

[0110] In some embodiments, the memory comprises a 3D NAND type memory.

[0111] Hereinafter, the present disclosure will be described in more detail with reference to embodiments of the present application.

[0112] An application embodiment of the present disclosure provides a method for operating a memory. Figure 3 is a schematic flow chart for implementing the method for operating a memory according to an embodiment of the present disclosure. As shown in Figure 3, the method includes the following steps 301 to 308:

[0113] In step 301 the process begins.

[0114] In the initial stage, the memory performs preparatory tasks such as initialization.

[0115] Processing continues to step 302 when the control circuitry receives an instruction from a host or memory controller to perform a multi-plane programming operation.

[0116] In step 302, a programming operation is performed by employing a multi-plane programming scheme.

[0117] Here, the peripheral circuitry may simultaneously program multiple memory planes in the memory by employing a multi-plane programming scheme.

[0118] In this step, the programming voltage can be shared among the memory planes. If the memory cell array in any memory plane is faulty, the programming voltage may not reach its target. The programming operation may proceed very slowly and even lead to PSF on other memory planes.

[0119] After step 302, the process proceeds to step 303.

[0120] In step 303, it is determined whether a programming exception exists in the memory plane.

[0121] Here, the control circuit can determine whether a programming exception exists in the memory plane according to whether the number of programming voltage verify exceeds a preset number.

[0122] In this step, the number of programming verifications for different PV levels can be tracked, and it can be checked whether the number of programming verifications exceeds a preset number. If the number of verifications for a certain PV level exceeds a preset number, it may indicate that a programming exception exists in the memory plane. In this case, a structural defect in the growth of a certain memory plane may be one of the causes of the programming exception.

[0123] If the determination result indicates that there is a memory plane with a programming exception, processing may proceed to step 304, and if the determination result indicates that there is no memory plane with a programming exception, processing may proceed to step 305.

[0124] In step 304, a flag is set to signal a pause using the multiplane programming method.

[0125] In this step, a flag may be set to indicate a multi-plane programming fault, and the flag indicating the multi-plane programming fault may be stored in a status register of the memory. After the memory suspends the multi-plane programming operation, the memory may further switch to a single-plane programming operation. Once the entire programming operation is completed, the host or memory system may detect the flag in the status register and perform subsequent processing accordingly. After step 304, processing proceeds to step 306.

[0126] In step 305, the programming operation continues to be performed by employing a multi-plane programming scheme.

[0127] Here, the peripheral circuitry can continue to simultaneously perform programming operations on multiple memory planes in the memory by employing a multi-plane programming scheme.

[0128] In step 306, Vpgm / Vpass is modified to a lower voltage.

[0129] Here, the control circuit may apply Vpgm / Vpass to the word lines of the memory plane using the row drivers, while controlling the voltage generation circuit to set Vpgm / Vpass to a lower level.

[0130] In step 307, the programming operation is performed by employing a single plane programming method.

[0131] Here, the peripheral circuitry may employ a single-plane programming scheme to sequentially perform programming operations on multiple memory planes.

[0132] In this step, if the programming operation is performed in a single plane manner, programming pass / fail can occur at the single plane level.

[0133] It should be noted that in practical applications, there may be no strict order between step 306 and step 307, and step 306 may actually be performed when each memory plane in step 307 begins a programming operation.

[0134] In step 308, the process ends.

[0135] An embodiment of the present disclosure further provides a memory system 1000, the memory system comprising: One or more memories 1 described in the above embodiment; The memory controller 2 is coupled to the memory 1.

[0136] Here, in some embodiments, the peripheral circuitry may be configured to receive a second instruction, and in response to the second instruction, concurrently perform programming operations in at least two of the plurality of memory planes by employing a multi-plane programming scheme, and in response to determining that a memory plane having a programming exception exists in the at least two memory planes, suspend the programming operations and store the first flag.

[0137] The memory controller may be configured to issue a third instruction according to the first flag.

[0138] The peripheral circuitry may be further configured to receive a third instruction and, in response to the third instruction, sequentially perform programming operations on the at least two memory planes by employing a single-plane programming scheme.

[0139] Here, the second instruction may be configured to instruct memory 1 to perform a programming operation in a multi-plane programming manner, and the third instruction may be configured to instruct memory 1 to perform a programming operation in a single-plane programming manner.

[0140] In practical application, the memory controller 2 may be configured to control the memory 1 to perform erase, read or write operations, and further decode, analyze or operate on commands issued or received in the memory. The memory controller 2 may be connected to the memory 1 through a memory interface (I / F).

[0141] In practical application, the first flag may be stored in a status register corresponding to each memory 1. When there is a pause programming operation on the memory 1, the memory controller 2 may access the status register corresponding to the memory 1, and the memory controller 2 may issue a third instruction to the memory 1 whose programming is paused according to the first flag. After receiving the third instruction, the memory 1 whose programming is paused may be programmed by adopting a single-plane programming manner.

[0142] It should be noted that "first," "second," etc. are used to distinguish between similar objects and are not necessarily used to describe a particular sequence or order.

[0143] In addition, the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without contradiction.

[0144] The above descriptions are only preferred embodiments of the present disclosure, and are not intended to limit the scope of protection of the present disclosure.

Claims

1. 1. A method for operating a memory device, comprising: applying a multi-plane programming scheme to simultaneously perform programming operations on each of at least two memory planes of the memory device; in response to determining that the at least two memory planes include an exception memory plane having a programming fault, switching to a single-plane programming scheme to sequentially perform programming operations on each of the at least two memory planes; 23. A method for operating a memory device, comprising:

2. Sequentially performing programming operations on each of the at least two memory planes includes:

2. The method of claim 1, comprising applying a first programming voltage to selected word lines on the exception memory plane, the first programming voltage being less than a second programming voltage applied to the selected word lines of the exception memory plane if the exception memory plane is determined to have the programming failure.

3. Sequentially performing programming operations on each of the at least two memory planes includes: applying a first turn-on voltage to unselected word lines of the exception memory plane when applying the first programming voltage to the selected word lines of the exception memory plane; 3. The method of claim 2, wherein the first turn-on voltage is less than a second turn-on voltage applied to the unselected word lines of the exception memory plane if the exception memory plane is determined to have the programming fault.

4. Determining that the exception memory plane has the programming fault includes: Counting a number of programming verify operations performed on programming memory cells in the at least two memory planes; determining, in response to the programming verify number exceeding a preset number corresponding to written data, that the at least two memory planes include the exception memory plane having the programming failure; The method of claim 1 , comprising:

5. 5. The method of claim 4, further comprising applying programming verify voltages to the programming memory cells in different memory planes respectively by using different voltage sources.

6. 5. The method of claim 4, further comprising: applying programming verify voltages to the programming memory cells corresponding to different word lines in a same memory plane, respectively, by using different voltage sources.

7. storing a flag in a status register to indicate the exception memory plane after determining that the exception memory plane has the programming fault; storing data allocated to the exception memory plane in another memory plane within the memory device in response to receiving a first instruction to dump data stored in the exception memory plane corresponding to the flag; The method of claim 1 further comprising:

8. pausing the programming operation of the multi-plane programming scheme after determining that the exception memory plane has the programming fault; sequentially performing programming operations on each of the at least two memory planes after receiving a second command to switch from the multi-plane programming scheme to the single-plane programming scheme; The method of claim 7 further comprising:

9. Sequentially performing programming operations on each of the at least two memory planes includes: performing a programming operation on a first memory plane of the at least two memory planes; 2. The method of claim 1 , further comprising: in response to determining that the programming operation on the first memory plane has failed or is completed, performing a programming operation on a second memory plane of the at least two memory planes.

10. 1. A memory device comprising: At least two memory planes; a peripheral circuit coupled to the at least two memory planes; The peripheral circuit includes: applying a multi-plane programming scheme to simultaneously perform programming operations on each of the at least two memory planes; responsive to determining that the at least two memory planes include an exception memory plane having a programming failure, switch to a single-plane programming scheme to sequentially perform programming operations on each of the at least two memory planes.

11. The peripheral circuit includes: a row driver coupled to the at least two memory planes; A control circuit comprising: applying a second programming voltage to selected word lines of the at least two memory planes in the multi-plane programming scheme; applying a first programming voltage, lower than the second programming voltage, to selected word lines of the exception memory plane in the single plane programming scheme; a control circuit configured to control the row drivers; The memory device of claim 10 , comprising:

12. The row driver applying a second turn-on voltage to unselected word lines of the at least two memory planes in the multi-plane programming scheme; applying a first turn-on voltage lower than the second turn-on voltage to unselected word lines of the exception memory plane in the single-plane programming scheme; The memory device of claim 11 configured as follows:

13. The peripheral circuit includes: Counting the number of programming verify operations performed on programming memory cells in the at least two memory planes; determining, in response to the number of programming verifications exceeding a preset number corresponding to the written data, that the at least two memory planes include the exception memory plane having the programming failure; The memory device of claim 12 configured as follows:

14. The peripheral circuit includes: a plurality of programming verify voltage generators, each coupled to one of the at least two memory planes; 14. The memory device of claim 13, wherein the control circuitry is further configured to control the multiple programming verify voltage generators to respectively apply programming verify voltages to programming memory cells in different memory planes.

15. Each programming verify voltage generator is coupled to a word line of one of the at least two memory planes; 15. The memory device of claim 14, wherein the control circuitry is further configured to control the plurality of programming verify voltage generators to respectively apply programming verify voltages to the programming memory cells corresponding to different word lines in a same memory plane.

16. The peripheral circuit includes: a status register configured to store a flag indicating the exception memory plane in response to determining that the at least two memory planes include the exception memory plane having the programming fault; 11. The memory device of claim 10, wherein the peripheral circuitry is configured to, in response to receiving a first instruction to dump data stored in the exception memory plane corresponding to the flag, control another memory plane in the memory device to store data assigned to the exception memory plane.

17. The peripheral circuit includes: suspending the programming operation of the multi-plane programming scheme after determining that the exception memory plane has the programming fault; sequentially performing programming operations on each of the at least two memory planes after receiving a second instruction to switch from the multi-plane programming scheme to the single-plane programming scheme. The memory device of claim 16 configured as follows:

18. The peripheral circuit includes: performing a programming operation on a first memory plane of the at least two memory planes; In response to determining that the programming operation on the first memory plane has failed or completed, performing a programming operation on a second memory plane of the at least two memory planes. The memory device of claim 10 further configured to:

19. The memory device of claim 10 , wherein the memory device comprises a 3D NAND memory device.

20. 1. A memory system comprising: One or more memory devices configured to store data, each comprising: At least two memory planes; a peripheral circuit coupled to the at least two memory planes, the peripheral circuit comprising: The peripheral circuit includes: applying a multi-plane programming scheme to simultaneously perform programming operations on each of the at least two memory planes; and peripheral circuitry configured to, in response to determining that the at least two memory planes include an exception memory plane having a programming failure, switch to a single-plane programming scheme to sequentially perform programming operations on each of the at least two memory planes. one or more memory devices; a memory controller coupled to the one or more memory devices and configured to control the one or more memory devices via the peripheral circuits; A memory system including:

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