Information processing device, information processing method, and program

Abstract

To calculate a solution of a combinatorial optimization problem at a high speed.SOLUTION: An information processing system solves a combinatorial optimization problem. The information processing system includes an Ising machine and a host unit. The Ising machine is hardware configured to perform a search process for searching for the ground state of an Ising model that represents the combinatorial optimization problem. The host unit is hardware connected to the Ising machine via an interface and configured to control the Ising machine. In the search process, for each of a plurality of Ising spins, the Ising machine alternately repeats an auxiliary variable update process for updating an auxiliary variable by a main variable and a main variable update process for updating the main variable by the auxiliary variable multiple times. Prior to the search process, the host unit transmits, to the Ising machine, an initial value of the auxiliary variable corresponding to each of the plurality of Ising spins.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] An embodiment of the present invention relates to an information processing device, an information processing method, and a program. [Background technology]

[0002] The optimization of complex systems in a variety of application fields, including finance, logistics, control, and chemistry, often reduces to a mathematical combinatorial optimization problem: finding a combination of discrete values ​​that minimizes a function of discrete variables, called a cost function.

[0003] In recent years, a special-purpose device called an Ising machine that searches for the ground state of the Ising model has been attracting attention. The problem of searching for the ground state of the Ising model is called the Ising problem. The Ising problem is a combinatorial optimization problem that minimizes a cost function given by a quadratic function of a variable (Ising spin) that represents two values. The cost function is called the Ising energy. Many practical combinatorial optimization problems can be converted into an Ising problem. Therefore, a system that solves combinatorial optimization problems can solve the desired combinatorial optimization problem by using an Ising machine.

[0004] The system for solving combinatorial optimization problems includes an Ising machine that performs a search process for the ground state of the Ising model, and a host unit that performs processes other than the search process. The Ising problem is defined by a set of coupling coefficients (J matrix) and a set of external magnetic field coefficients (h vector).

[0005] In such a system for solving combinatorial optimization problems, the host unit transmits a J matrix and an h vector to the Ising machine and receives the respective values ​​of a plurality of optimized Ising spins from the Ising machine. The Ising machine also receives the J matrix and the h vector from the host unit and returns the respective values ​​of a plurality of Ising spins optimized to minimize the Ising energy. Such a system for solving combinatorial optimization problems is required to efficiently transmit and receive information between the host unit and the Ising machine and to shorten the time from starting the calculation process for the combinatorial optimization problem to outputting the solution. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6207584 [Patent Document 2] JP 2019-145010 A [Patent Document 3] JP 2019-159566 A [Patent Document 4] JP 2020-046715 A [Patent Document 5] JP 2020-046766 A [Patent Document 6] JP 2020-046784 A [Patent Document 7] JP 2020-046887 A [Non-patent literature]

[0007] [Non-Patent Document 1] Hayato Goto, Kosuke Tatsumura, Alexander R. Dixon, “Combinatorial optimization by simulating adiabatic bifurcations in nonlinear Hamiltonian systems”, Science Advances, Vol. 5, no. 4, eaav2372, 19 Apr. 2019 Summary of the Invention [Problem to be solved by the invention]

[0008] The problem to be solved by the present invention is to quickly calculate a solution to a combinatorial optimization problem. [Means for solving the problem]

[0009] An information processing device according to an embodiment includes a host unit. The host unit is connected to an Ising machine via an interface and controls the Ising machine. The Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem. Prior to the search process, the host unit: Acquire coefficient information including a plurality of coupling coefficients that define the Ising model, Among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, one piece of circuit information representing a circuit capable of searching for the ground state of the Ising model is Based on the number or accuracy of the plurality of coupling coefficients included in the coefficient information and reconfiguring the Ising machine based on the selected circuit information. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing the functional configuration of an information processing system according to a first embodiment. [Diagram 2] FIG. 1 is a diagram showing a graph representing an Ising model. [Diagram 3] FIG. 1 is a diagram showing variables stored in an Ising machine. [Figure 4] 1 is a flowchart showing the flow of a search process by an Ising machine. [Diagram 5] FIG. 1 is a diagram showing a hardware configuration of an information processing system. [Figure 6] FIG. 2 is a sequence diagram showing a processing flow of the information processing system. [Figure 7] FIG. 11 is a diagram showing the hardware configuration of an information processing system according to a second embodiment. [Figure 8] 11 is a flowchart of a first example of the second embodiment. [Figure 9] 10 is a timing chart of a first example of the second embodiment. [Figure 10] 13 is a flowchart of a second example of the second embodiment. [Figure 11] 11 is a flowchart showing a flow of preprocessing. [Figure 12] 10 is a timing chart of a second example of the second embodiment. [Figure 13] FIG. 13 is a diagram showing the functional configuration of an information processing system according to a third embodiment. [Figure 14] 13 is a flowchart of a third embodiment. [Figure 15] 13 is a flowchart of a timer interrupt according to the third embodiment. [Figure 16] 13 is a timing chart according to a third embodiment. [Figure 17] 13 is a flowchart of a timer interrupt according to the fourth embodiment. [Figure 18] 13 is a timing chart according to the fourth embodiment. [Figure 19] FIG. 13 is a diagram showing processing times when reconstruction is not performed and when reconstruction is performed. [Figure 20] FIG. 13 is a diagram showing coupling information including a coupling coefficient. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (First embodiment) FIG. 1 is a diagram showing the functional configuration of an information processing system 10 according to the first embodiment.

[0012] The information processing system 10 is a device that solves a combinatorial optimization problem. The information processing system 10 according to the first embodiment includes an Ising machine 12 and a host unit 14.

[0013] The Ising machine 12 is hardware that executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem. The Ising machine 12 is, for example, a reconfigurable semiconductor device such as an FPGA (Field Programmable Gate Array). Note that, in the first embodiment, the Ising machine 12 does not have to be a reconfigurable semiconductor device. In the first embodiment, the Ising machine 12 may be, for example, a non-reconfigurable semiconductor device or a processing circuit that executes information processing according to a program.

[0014] The host unit 14 is connected to the Ising machine 12 via a physical interface and is hardware that controls the Ising machine 12. The host unit 14 is a processing circuit that executes information processing according to a program. The host unit 14 executes processes other than the search process executed by the Ising machine 12 among a series of processes for solving a combinatorial optimization problem.

[0015] When searching for a ground state of an Ising model that represents a combinatorial optimization problem to be solved, the host unit 14 transmits a J matrix and an h vector, which are definition information that define the Ising model, control parameters for controlling a search process executed by the Ising machine 12, and initial values ​​of each of a plurality of auxiliary variables (p1, p2, p3, ...) (described in detail below) to the Ising machine 12 via the interface. Note that the host unit 14 may further transmit initial values ​​of a plurality of main variables (x1, x2, x3, ...) (described in detail below) to the Ising machine 12 via the interface.

[0016] The Ising machine 12 executes a search process to search for a ground state of an Ising model defined by a J matrix and an h vector. At the start of the search process, the Ising machine 12 assigns an initial value received from the host unit 14 to each of a plurality of auxiliary variables (p1, p2, p3, ...). Furthermore, at the start of the search process, the Ising machine 12 assigns a predetermined value such as 0 to each of a plurality of main variables (x1, x2, x3, ...) as an initial value. The Ising machine 12 may generate a value based on a random number or the like for each of the plurality of main variables (x1, x2, x3, ...) and assign the generated value as the initial value. Note that when the Ising machine 12 receives the initial values ​​of each of the plurality of main variables (x1, x2, x3, ...) from the host unit 14, it assigns the received value to each of the plurality of main variables (x1, x2, x3, ...). Then, the Ising machine 12 assigns initial values ​​to each of the multiple main variables (x1, x2, x3, . . . ) and each of the multiple auxiliary variables (p1, p2, p3, . . . ) and then starts a search.

[0017] The Ising machine 12 executes a search process to calculate values ​​of multiple main variables (x1, x2, x3, ...) that minimize the Ising energy in the Ising model. Then, the Ising machine 12 transmits the values ​​of N Ising spins (s1, s2, s3, ...) obtained by binarizing each of the values ​​of the multiple main variables (x1, x2, x3, ...) after the search process to the host unit 14 via an interface as search results. The Ising machine 12 may transmit the values ​​of the multiple main variables (x1, x2, x3, ...) after the search process to the host unit 14 as search results. Then, the host unit 14 outputs the values ​​of the multiple Ising spins (s1, s2, s3, ...) as a solution to the combinatorial optimization problem.

[0018] 2 is a diagram showing a graph representing an Ising model. The energy (E(s)) of the Ising model including N Ising spins is expressed by the following formula (1).

number

[0019] N is the number of Ising spins included in the Ising model and is an integer equal to or greater than 3. i and j represent the indices of the Ising spins and are integers equal to or greater than 1 and equal to or less than N. i represents the i-th Ising spin. s j represents the j-th Ising spin. i and s j represents either -1 or +1. The N Ising spins are grouped together into an s vector (s1,s2,…,s N The s vector represents the -1 or +1 configuration of the N Ising spins.

[0020] J ij is the element in row i and column j of the J matrix. The J matrix has identical elements for the symmetric components (J ij =J ji ), a square matrix with N rows and N columns. In the Ising model, a coupling coefficient is defined for every pair of two Ising spins contained in the N Ising spins. J ij represents the coupling coefficient that represents the interaction between the ith Ising spin and the jth Ising spin.

[0021] h i is the i-th element in the h vector. In the Ising model, an external magnetic field coefficient is defined that represents the external magnetic field that affects each of the N Ising spins individually. h i represents the external magnetic field coefficient that affects the ith Ising spin.

[0022] The N-size Ising problem is the problem of calculating the spin configuration that minimizes the Ising energy for an Ising model that contains N Ising spins. The spin configuration (S vector) that minimizes the energy is called the ground state.

[0023] Figure 2 shows a graph representing the Ising model for N = 6. The graph vertices correspond to Ising spins. The graph edges correspond to the coupling coefficients J ijCorresponding to the external magnetic field coefficient h i is assigned to a graph vertex.

[0024] A general combinatorial optimization problem is expressed as an Ising problem defined by a J matrix and an h vector. The Ising machine 12 receives the J matrix and the h vector as the problem to be solved, internally searches for a spin configuration with a lower Ising energy, and outputs the optimized spin configuration as a solution.

[0025] A spin configuration with the minimum Ising energy corresponds to an exact solution. A spin configuration with an Ising energy close to the minimum corresponds to an approximate solution. In general, the performance of the Ising machine 12 is represented by the time it takes to output a solution and the accuracy of the solution (the smaller the energy, the higher the accuracy of the solution). The Ising machine 12 may output not only an exact solution but also an approximate solution as the solution. Furthermore, the search process for searching for a ground state by the Ising machine 12 includes not only a process for searching for an exact solution but also a process for searching for an approximate solution.

[0026] Furthermore, the Ising machine 12 capable of solving an N-sized Ising problem can also solve an Ising problem smaller than a size N. For example, the Ising machine 12 can search for an Ising problem smaller than a size N as an N-sized Ising problem by setting the coupling coefficient and the external magnetic field coefficient of an element in which no Ising spin exists in the J matrix and the h matrix to 0.

[0027] The simulated annealing (SA) method has been known as a method for solving the Ising problem. A device that searches for the ground state of the Ising model according to the SA method is called an SA-based Ising machine.

[0028] Also, a simulated bifurcation (SB) method is known as a solution method for solving the Ising problem. The Ising machine 12 also performs a search process for the ground state of the Ising model by the simulated bifurcation method. For example, the simulated bifurcation method is proposed in Non-Patent Document 1 and Patent Documents 2 to 7. The simulated bifurcation method is an algorithm in which the equation of motion in an optimization algorithm based on adiabatic change in classical mechanics is modified into a form suitable for high-speed simulation. The Ising machine 12 performs a search process for the ground state of the Ising model by using such a simulated bifurcation method.

[0029] In the simulated bifurcation method, two main variables (x i ) and auxiliary variables (p i ) is used. N particles correspond to N Ising spins. In the simulated bifurcation method, the primal variable (x i ) represents the position of the i-th particle among N particles (i = 1, 2, . . . , N). In the simulated bifurcation method, the auxiliary variable (p i ) represents the momentum of the i-th particle. N main variables (x i ) and N auxiliary variables (p i ) are continuous variables represented by real numbers.

[0030] In the simulated bifurcation method, for example, simultaneous ordinary differential equations of the following formulas (2) and (3) are numerically solved for each of the N virtual particles.

number

[0031] Here, H is the Hamiltonian of the following equation (4).

number

[0032] c is a predetermined coefficient. D is a predetermined coefficient, and corresponds to detuning. K is a coefficient corresponding to a positive Kerr coefficient. t is a variable representing time. p(t) corresponds to pumping amplitude, and is a function whose value increases monotonically according to the number of updates during calculation of the simulated bifurcation method. The initial value of p(t) may be set to 0. α(t) is a function whose value increases monotonically with p(t).

[0033] Now, using the Symplectic Euler method, we can solve the differential equations given by equations (2) and (3). When using the Symplectic Euler method, the differential equations are rewritten into discrete recurrence equations, as shown in equations (5) and (6) below.

number

[0034] Therefore, the Ising machine 12 alternately executes the calculations of formula (5) and formula (6) while increasing t by Δt until t reaches a predetermined end time (T). Then, the Ising machine 12 calculates the finally obtained N main variables (x i ) are binarized into N Ising spins (s i ) or the values ​​of the N main variables (x i ) is output as the search result.

[0035] The Ising machine 12 may execute an algorithm that calculates expressions other than those of formula (3) and formula (4) as long as the algorithm uses a simulated bifurcation method. For example, the Ising machine 12 may execute an algorithm that calculates an expression obtained by modifying formula (3) and formula (4). Also, for example, the Ising machine 12 may execute an algorithm that performs a predetermined control process in addition to the calculation of formula (3) and formula (4) or the calculation of an expression obtained by modifying formula (3) and formula (4).

[0036] In the Ising machine 12, performance indexes such as convergence speed and accuracy of the solution reached may change by changing the algorithm to be executed. Therefore, the algorithm applied to the Ising machine 12 may differ depending on the Ising problem to be solved and the purpose (e.g., emphasis on convergence speed or accuracy). The Ising machine 12 may execute the search process by an algorithm selected by a user from among a plurality of preset algorithms. For example, when the Ising machine 12 is a reconfigurable semiconductor device, the host unit 14 reconfigures the semiconductor device based on circuit information representing a circuit that executes the algorithm selected by the user. This allows the Ising machine 12 to execute the search process of the ground state of the Ising model by an appropriate circuit according to the Ising problem to be solved and the purpose.

[0037] FIG. 3 is a diagram showing variables stored in the Ising machine 12. The Ising machine 12 executes an algorithm using a simulated bifurcation method by a hardware circuit. When performing a search process for the ground state of an Ising model including N Ising spins, the Ising machine 12 stores N main variables (x i ) and N auxiliary variables (p i ) to remember.

[0038] In this way, the Ising machine 12 stores 2×N variables inside. Therefore, the Ising machine 12 has a different configuration from the SA-based Ising machine that stores N variables. i ) is converted to the Ising spin (s i ) is converted to the auxiliary variable (p i ) is the Ising spin (s i ) is not used for conversion.

[0039] In addition, the N main variables (x i ) and N auxiliary variables (p i) are initialized at the start of the search process. The Ising machine 12 can solve problems where the J matrix and the h vector are the same by using the auxiliary variables (p i ) is different, a different solution (approximation) may be output. For this reason, the Ising machine 12 uses the auxiliary variable (p i ) and perform a search process for problems with the same J matrix and h vector, it is possible to obtain a more accurate solution.

[0040] 4 is a flowchart showing the flow of the search process by the Ising machine 12. The Ising machine 12 executes the search process according to the flow shown in FIG.

[0041] First, in S111, the Ising machine 12 performs a setting process. Specifically, the Ising machine 12 sets, for example, the coefficients of K and D, functions such as p(t) and α(t), and the number of iterations, etc. Furthermore, the Ising machine 12 sets a J matrix and an h vector based on the definition information received from the host unit 14.

[0042] Next, in S112, the Ising machine 12 calculates N main variables (x1 to x N ) and N auxiliary variables (p1~p N For example, the Ising machine 12 initializes the values ​​of N main variables (x1 to x N The Ising machine 12 sets each of the N main variables (x1 to x N ) are received from the host unit 14, the N main variables (x1 to x N ) to the initial value received from the host unit 14. Furthermore, the Ising machine 12 sets the N auxiliary variables (p1 to p N ) are set to the initial values ​​received from the host unit 14.

[0043] Next, the Ising machine 12 repeats the loop process from S113 to S120 a set number of times.

[0044] In steps S114 to S116 in the loop, the Ising machine 12 executes an auxiliary variable update process while incrementing i by 1 from i=1 to i=N (S114, S115, S116). In the auxiliary variable update process (S115) for updating the i-th auxiliary variable, the Ising machine 12 updates N main variables (x1 to x N ), the i-th main variable (x i ) and the other (N-1) main variables (x 1~i-1, x i+1~N ) N coupling coefficients (J i,j ), and the i-th external magnetic field coefficient (h j ) and the i-th auxiliary variable (p i ) to update the

[0045] Specifically, the Ising machine 12 calculates the i-th auxiliary variable (p i ) is calculated.

[0046] The Ising machine 12 may execute the process of S115 in parallel. As a result, the Ising machine 12 calculates N auxiliary variables (p1 to p N ) can be calculated quickly.

[0047] Next, in S117 to S119, the Ising machine 12 executes a main variable update process while incrementing i by 1 from i=1 to i=N (S117, S118, S119). In the main variable update process (S118) for updating the i-th main variable, the Ising machine 12 updates the i-th auxiliary variable (p i ) to determine the i-th main variable (x i ) to update the

[0048] Specifically, the Ising machine 12 calculates the i-th main variable (x i ) is calculated.

[0049] The Ising machine 12 may execute the process of S118 in parallel. As a result, the Ising machine 12 calculates the N main variables (x1 to x N ) can be calculated quickly.

[0050] Then, when the Ising machine 12 has executed the loop process between S113 and S120 a set number of times, the Ising machine 12 advances the process to S121. Note that, in the loop process from S113 to S120, the Ising machine 12 may execute the processes of S117 to S119 first, and execute the processes of S114 to S116 later.

[0051] In S121, the Ising machine 12 outputs the search result to the host unit 14. For example, the Ising machine 12 outputs the search result to the host unit 14. N ) are binarized into N Ising spins (s1 to s N ), or N main variables (x1~x N ) to the host unit 14. Then, when the Ising machine 12 finishes the process of S121, it ends the search process.

[0052] As described above, the Ising machine 12 generates N Ising spins (s1 to s N ), an auxiliary variable update process (S115) for updating the auxiliary variables using the main variables and a main variable update process (S118) for updating the main variables using the auxiliary variables are alternately repeated multiple times. Furthermore, the Ising machine 12 outputs a value based on the main variables after alternately executing the auxiliary variable update process (S115) and the main variable update process (S118) multiple times as a search result. This allows the Ising machine 12 to execute an algorithm using the simulated bifurcation method and execute a search process for the ground state of the Ising model.

[0053] 5 is a diagram showing an example of a hardware configuration of the information processing system 10. For example, the information processing system 10 includes an FPGA 32, a CPU (Central Processing Unit) 34, a main memory device 36, a circuit information memory device 38, an input device 40, a display device 42, and a bus 44.

[0054] The FPGA 32 receives circuit information from the CPU 34 via the bus 44, and is configured as a predetermined circuit in accordance with the received circuit information. In this way, the FPGA 32 functions as the Ising machine 12.

[0055] The FPGA 32 receives definition information and control parameters from the CPU 34 via the bus 44, and executes a search process according to the received definition information and control parameters. The definition information is information that defines an Ising model. Specifically, it is a J matrix and an h vector. The control parameters are information for controlling the search process. For example, the control parameters are coefficients (c, D, K), functions (α(t), p(t)), unit time (Δt), and the number of iterations of the loop process.

[0056] In addition, prior to the search process, the FPGA 32 calculates N auxiliary variables (p i ) stored in the main memory 36 from the CPU 34 via the bus 44. Furthermore, prior to the search process, the FPGA 32 calculates the initial values ​​of N main variables (x i ) may be received from the CPU 34 via the bus 44, with initial values ​​stored in the main memory 36.

[0057] After completing the search process, the FPGA 32 outputs the search results to the host unit 14 via the bus 44. Specifically, the FPGA 32 outputs the main variables (x i ) are binarized Ising spins (s i ) or the values ​​of several main variables (x i) to the host unit 14.

[0058] The CPU 34 operates according to a program stored in the main memory 36. As a result, the CPU 34 and the main memory 36 function as the host unit 14.

[0059] The CPU 34 executes pre-processing, parameter transmission processing, result reception processing, and main processing. In the pre-processing, the CPU 34 generates definition information and control parameters. In the pre-processing, the CPU 34 also generates a plurality of auxiliary variables (p i In preprocessing, the CPU 34 generates initial values ​​for each of the main variables (x i ) may further generate initial values ​​for each of

[0060] In the parameter transmission process, the CPU 34 transmits definition information, control parameters, and a plurality of auxiliary variables (p i ) to the FPGA 32 via the bus 44. In the parameter transmission process, the CPU 34 further transmits the initial values ​​of the main variables (x i ) may be sent to FPGA 32 via bus 44.

[0061] In the result reception process, the CPU 34 receives the search results from the FPGA 32 via the bus 44, and outputs a solution to the combinatorial optimization problem based on the received search results. The CPU 34 also executes processes other than the preprocessing, the parameter transmission process, and the result reception process as main processing.

[0062] The main memory device 36 is a random access memory (RAM) and is used as a working area for the CPU 34 to process data.

[0063] The circuit information storage device 38 is a non-volatile storage device that stores circuit information for configuring the FPGA 32 as a circuit for searching for the ground state of the Ising model.

[0064] The circuit information storage device 38 may store a plurality of pieces of circuit information. Each of the plurality of pieces of circuit information may be, for example, information representing a circuit having a different maximum size of a solvable Ising model. Also, each of the plurality of pieces of circuit information may be, for example, information representing a circuit performing a search process using a different algorithm. The CPU 34 selects circuit information designated by the user from the plurality of pieces of circuit information, and reconfigures the FPGA 32 using the selected circuit information.

[0065] The input device 40 is a device for inputting instructions and the like from a user. The input device 40 is, for example, a mouse and a keyboard. The input device 40 receives an instruction to start processing from a user. When the input device 40 receives the instruction to start processing from the user, the CPU 34 starts a process of calculating a solution to the combinatorial optimization problem.

[0066] The display device 42 is a device for displaying information to a user. The display device 42 displays a solution to a combinatorial optimization problem.

[0067] The bus 44 connects the FPGA 32, the CPU 34, the main memory device 36, the circuit information memory device 38, the input device 40, and the display device 42 to transmit and receive data. The bus 44 functions as an interface that connects the Ising machine 12 and the host unit 14.

[0068] 6 is a sequence diagram showing the flow of processing of the information processing system 10. When the FPGA 32 calculates a solution of an Ising model including N Ising spins, the information processing system 10 executes processing according to the flow shown in FIG.

[0069] First, in S11, the CPU 34 executes a main process. Then, in S12, the CPU 34 executes a pre-processing. Specifically, in the pre-processing, the CPU 34 prepares definition information (J, h), control parameters, and N auxiliary variables (p1 to p NFurther, the CPU 34 generates an initial value for each of the N main variables (x1 to x N ) may generate initial values ​​for each of

[0070] Next, in S13, the CPU 34 transmits the definition information (J, h), the control parameters, and the N auxiliary variables (p1 to p N ) to the FPGA 32 via the bus 44. Furthermore, the CPU 34 transmits the initial values ​​of the N main variables (x1 to x N ) may be transmitted to FPGA 32 via bus 44.

[0071] Next, in S14, the FPGA 32 executes a search process. Specifically, the FPGA 32 searches for the main variable (x i ) to determine the auxiliary variable (p i ) and the auxiliary variable update process to update the auxiliary variable (p i ) to the main variable (x i ) are alternately repeated multiple times. Specifically, the FPGA 32 executes the process shown in FIG.

[0072] At the start of the search process, the FPGA 32 calculates N auxiliary variables (p i ) to the initial value received from the CPU 34. Furthermore, at the start of the search process, the FPGA 32 sets the N main variables (x i ) are set to a predetermined value such as 0 as an initial value. i ) may be set to an initial value by generating a value based on a random number or the like internally. i ), the initial values ​​of each of the N main variables (x i ) are set to the initial values ​​received from the CPU 34.

[0073] Next, in S14, the FPGA 32 transmits the search result to the CPU 34. Specifically, the FPGA 32 transmits the search result to the CPU 34. N ) are binarized into N Ising spins (s1 to s N ), or N main variables (x1~x N ) to the CPU 34 via the bus 44. Then, in S15, the CPU 34 receives the search result from the FPGA 32 via the bus 44.

[0074] As described above, the information processing system 10 according to this embodiment transmits, from the host unit 14 (CPU 34 and main memory device 36) to the Ising machine 12 (FPGA 32) via the interface (bus 44), not only definition information (J, h) and control parameters that define an Ising model, but also a plurality of auxiliary variables (p i The Ising machine 12 (FPGA 32) transmits the initial values ​​of the main variables (x i Even if the value of the auxiliary variable (p i In other words, the host unit 14 (CPU 34) transmits the main variable (x i ) without sending the initial value of the auxiliary variable (p i ) can be changed to allow the Ising machine 12 (FPGA 32) to execute an appropriate search process. Therefore, the information processing system 10 according to this embodiment can i ) and transmission processing, the processing time and communication time can be reduced. In this way, the information processing system 10 according to the present embodiment can quickly calculate a solution to a combinatorial optimization problem.

[0075] Second embodiment Next, an information processing system 10 according to a second embodiment will be described. The information processing system 10 according to the second embodiment has almost the same configuration as the first embodiment. Therefore, in the description of the information processing system 10 according to the second embodiment, the components that are almost the same as those in the first embodiment are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0076] The information processing system 10 according to the second embodiment sequentially solves a plurality of combinatorial optimization problems one by one.

[0077] 7 is a diagram showing a hardware configuration of an information processing system 10 according to the second embodiment. The CPU 34 according to the second embodiment includes a first flag storage circuit 51. The first flag storage circuit 51 stores a first flag indicating whether or not the search process by the FPGA 32 has ended. The first flag storage circuit 51 is, for example, a flag register provided in the CPU 34. The first flag storage circuit 51 may be provided outside the CPU 34 (for example, in the main storage device 36).

[0078] The first flag can be written to and read from the first flag storage circuit 51 by the CPU 34. At the same time, the first flag is set in the first flag storage circuit 51 according to the operation status of the FPGA 32. For example, when the first flag is 0, it indicates that the search process by the FPGA 32 has not been completed, and when the first flag is 1, it indicates that the search process by the FPGA 32 has been completed.

[0079] In the second embodiment, the CPU 34 can also execute the search process in place of the FPGA 32. In this case, the CPU 34 executes a predetermined search program to execute the search process.

[0080] 8 is a flowchart showing a process flow of the CPU 34 according to a first example of the second embodiment. In the first example, in the information processing system 10, the CPU 34 executes the search process instead of the FPGA 32. In the first example, the CPU 34 executes the process according to the flow shown in FIG.

[0081] In the first example, the CPU 34 executes the loop process between S21 and S24 L times. L represents the number of combinatorial optimization problems to be solved and is a predetermined integer equal to or greater than 2. The CPU 34 executes a main process (S22) and a search process (S23) in each loop process. The main process (S22) is the same as the process of S11 shown in FIG. 6. The search process (S23) is the same as the process of S14 shown in FIG. 6. Then, when the CPU 34 executes the loop process L times, it ends this flow (S24).

[0082] 9 is a timing chart of processing executed by the information processing system 10 according to the first example of the second embodiment. m represents an index of the combinatorial optimization problem to be solved, and is an integer from 1 to L. The information processing system 10 increments m by 1, and sequentially solves the combinatorial optimization problem where m=1 to where m=L.

[0083] 9, in the first example, the CPU 34 alternately and repeatedly executes a main process and a search process, thereby enabling the information processing system 10 according to the first example of the second embodiment to solve a plurality of combinatorial optimization problems in sequence.

[0084] 10 is a flowchart showing a process flow of the CPU 34 according to a second example of the second embodiment. In the second example, in the information processing system 10, the FPGA 32 executes the search process, and the CPU 34 executes processes other than the search process. In the second example, the CPU 34 executes the process according to the flow shown in FIG.

[0085] In the second example, the CPU 34 executes the loop process between S31 and S41 L times. The CPU 34 executes the processes from S32 to S40 in each loop process.

[0086] In S32, the CPU 34 executes a main process. The main process (S32) is the same as the process of S11 shown in Fig. 6. Then, in S33, the CPU 34 executes a pre-process. The pre-process of S33 will be described later with reference to Fig. 11.

[0087] Next, in S34, the CPU 34 judges whether or not to reconfigure the FPGA 32. For example, the CPU 34 judges whether or not the circuit currently configured in the FPGA 32 corresponds to an Ising model that represents a combinatorial optimization problem to be solved. Then, the CPU 34 judges not to reconfigure if it corresponds, and to reconfigure if it does not correspond. If the reconfiguration is not to be performed (No in S34), the CPU 34 advances the process to S36. If the reconfiguration is to be performed (Yes in S34), the CPU 34 advances the process to S35. In S35, the CPU 34 provides the FPGA 32 with circuit information that corresponds to the Ising model that represents a combinatorial optimization problem to be solved, and causes the FPGA 32 to be reconfigured.

[0088] Next, in S36, the CPU 34 transmits the parameters generated in the pre-processing (S33) to the FPGA 32. Specifically, the CPU 34 transmits the definition information (J, h), the control parameters, and N auxiliary variables (p1 to p N ) to the FPGA 32 via the bus 44. Furthermore, the CPU 34 transmits the initial values ​​of the N main variables (x1 to x N ) may be transmitted to FPGA 32 via bus 44.

[0089] Next, in S37, the CPU 34 instructs the FPGA 32 to start the search process. Prior to starting the search process, the FPGA 32 sets the first flag (bs_flag) to 0, which is a value indicating that the search process has not ended. When the search process ends, the FPGA 32 sets the first flag (bs_flag) to 1, which is a value indicating that the search process has ended.

[0090] Next, in S38, the CPU 34 checks whether or not the search process by the FPGA 32 is completed. Specifically, the CPU 34 acquires a first flag (bs_flag).

[0091] Next, in S39, the CPU 34 judges whether the search process has ended. If the search process has ended, that is, if bs_flag==1 (Yes in S39), the process proceeds to S40. If the search process has not ended, that is, if bs_flag==1 is not true (No in S39), the process returns to S38, and the processes of S38 and S39 are repeated. That is, the CPU 34 performs polling, which is a process of repeatedly checking the first flag (bs_flag) to confirm that the search process has ended, from when it issues an instruction to start the search process until the search process ends.

[0092] In S40, the CPU 34 receives the search result from the FPGA 32. Then, when the CPU 34 has executed the loop process L times, it ends this flow (S41).

[0093] 11 is a flow chart showing the flow of the pre-processing (S33). In the pre-processing (S32), the CPU executes the processes from S51 to S54.

[0094] In S51, the CPU 34 calculates N auxiliary variables (p1 to p N The CPU 34 generates the initial values ​​of the N main variables (x i ) may further generate initial values ​​for each of

[0095] Next, in S52, the CPU 34 generates a J matrix. Next, in S53, the CPU 34 generates an h vector. Next, in S54, the CPU 34 generates control parameters including coefficients (c, D, K), functions (α(t), p(t)), unit time (Δt), and the number of iterations. After completing the process of S54, the CPU 34 returns the process to the flow of FIG. 10.

[0096] FIG. 12 is a timing chart of the process executed by the information processing system 10 according to the second example of the second embodiment. As shown in FIG. 12, in the second example of the second embodiment, the CPU 34 executes the main process, the pre-process, and the parameter transmission process, and then the FPGA 32 executes the search process. The CPU 34 checks whether the search process is completed by polling while the FPGA 32 is executing the search process, and executes the result reception process after the search process is completed. Then, the CPU 34 starts the main process of the next problem after the result reception process. In this way, in the information processing system 10 according to the second example of the second embodiment, the CPU 34 and the FPGA 32 execute the process at an exclusive timing. As a result, the information processing system 10 according to the second example of the second embodiment can solve a plurality of combinatorial optimization problems in sequence.

[0097] Here, the FPGA32 calculates the N main variables (x1 to x N ) and N auxiliary variables (p1~p N ) in parallel. Therefore, the FPGA 32 can perform large-scale parallel calculations. In contrast, the CPU 34 generally has a limited number of cores and threads, and therefore cannot perform large-scale parallel calculations. Therefore, the information processing system 10 according to the second example can significantly shorten the search process, compared to the information processing system 10 according to the first example, although pre-processing, parameter transmission processing, and result reception processing are added. Therefore, the information processing system 10 according to the second example can increase the throughput overall.

[0098] Third embodiment Next, an information processing system 10 according to a third embodiment will be described. The information processing system 10 according to the third embodiment has almost the same configuration as that of the second embodiment. Therefore, in the description of the information processing system 10 according to the third embodiment, the components that are almost the same as those of the second embodiment are given the same reference numerals, and detailed description thereof will be omitted.

[0099] The information processing system 10 according to the third embodiment sequentially solves a plurality of combinatorial optimization problems one by one, and executes a main process by the CPU 34 and a search process by the FPGA 32 in parallel.

[0100] Fig. 13 is a diagram showing a functional configuration of an information processing system 10 according to a third embodiment. The CPU 34 according to the third embodiment further includes a second flag storage circuit 52, as compared with the configuration of the second embodiment shown in Fig. 7. The second flag storage circuit 52 stores a second flag indicating whether the CPU 34 has received a search result from the FPGA 32. The second flag storage circuit 52 is, for example, a flag register provided in the CPU 34. The second flag storage circuit 52 may be provided outside the CPU 34 (for example, in the main storage device 36).

[0101] The second flag storage circuit 52 is writable and readable by the CPU 34. For example, when the second flag is 0, it indicates that the CPU 34 has not received the search result, and when the second flag is 1, it indicates that the CPU 34 has received the search result.

[0102] 14 is a flowchart showing the flow of processing by the CPU 34 according to the third embodiment. The CPU 34 according to the third embodiment executes processing in the flow shown in FIG.

[0103] First, in S61, the CPU 34 sets the first flag (bs_flag) to 0, which is a value indicating that the search process is not completed, and further sets the second flag (rcv_flag) to 1, which is a value indicating that the search result has been received.

[0104] Next, the CPU 34 executes the loop process between S62 and S75 L times. The CPU 34 executes the processes from S63 to S74 in each loop process.

[0105] In S63, the CPU 34 enables a timer interrupt. The timer generates a timer flag at every predetermined time. When the timer interrupt is enabled, the CPU 34 executes the process shown in FIG. 15 each time the timer flag is generated.

[0106] Next, in S64, the CPU 34 executes the main process. The main process (S64) is the same as the process of S32 shown in FIG.

[0107] Next, in S65, the CPU 34 executes pre-processing. The pre-processing (S65) is the same as the processing of S33 shown in FIG.

[0108] Next, in S66, the CPU 34 disables the timer interruption that was enabled in S63. After that, until the next timer interruption is enabled, the CPU 34 does not execute the process shown in FIG.

[0109] Next, in S67, the CPU 34 judges whether or not the second flag (rcv_flag) indicates that the search result has not been received. If the second flag (rcv_flag) indicates that the search result has been received, that is, if rcv_flag==0 is not satisfied (No in S67), the CPU 34 advances the process to S71. If the second flag (rcv_flag) indicates that the search result has not been received, that is, if rcv_flag==0 is satisfied (Yes in S67), the CPU 34 advances the process to S68.

[0110] Next, in S68, the CPU 34 checks whether or not the search process by the FPGA 32 is completed. Specifically, the CPU 34 acquires the first flag (bs_flag).

[0111] Next, in S69, the CPU 34 judges whether the search process has been completed. If the search process has been completed, that is, if bs_flag==1 (Yes in S69), the process proceeds to S70. If the search process has not been completed, that is, if bs_flag==1 is not true (No in S69), the process returns to S68, and the processes of S68 and S69 are repeated. That is, the CPU 34 performs polling to confirm that the search process has been completed from the time when the search process is started until the search process is completed.

[0112] In S70, the CPU 34 receives the search result from the FPGA 32. Furthermore, when reception of the search result is completed, the CPU 34 sets the second flag (rcv_flag) to 1, which is a value indicating that the search result has been received.

[0113] Next, in S71, the CPU 34 determines whether or not to reconfigure the FPGA 32. If the reconfiguration is not to be performed (No in S71), the CPU 34 advances the process to S73. If the reconfiguration is to be performed (Yes in S71), the CPU 34 advances the process to S72. In S72, the CPU 34 provides the FPGA 32 with circuit information corresponding to an Ising model that represents the combinatorial optimization problem to be solved, and causes the FPGA 32 to be reconfigured.

[0114] Next, in S73, the CPU 34 transmits the parameters generated in the pre-processing (S65) to the FPGA 32. The parameter transmission processing (S73) is the same as the processing of S36 shown in FIG.

[0115] Next, in S74, the CPU 34 instructs the FPGA 32 to start search processing. Furthermore, the CPU 34 sets the second flag (rcv_flag) to 0, which is a value indicating that no search results have been received. Then, when the CPU 34 has executed the loop processing L times, it ends this flow (S75).

[0116] 15 is a flowchart showing a process flow when a timer interrupt occurs in the CPU 34 according to the third embodiment. When a timer interrupt occurs in a state where the timer interrupt is permitted, the CPU 34 according to the third embodiment executes the process according to the flow shown in FIG.

[0117] First, in S81, the CPU 34 judges whether or not the second flag (rcv_flag) indicates that the search result has not been received. If the second flag (rcv_flag) indicates that the search result has been received, that is, if rcv_flag==0 is not satisfied (No in S81), the CPU 34 ends the timer interrupt flow. If the second flag (rcv_flag) indicates that the search result has not been received, that is, if rcv_flag==0 (Yes in S81), the CPU 34 advances the process to S82.

[0118] In S82, the CPU 34 checks whether or not the search process is completed by the FPGA 32. Specifically, the CPU 34 acquires a first flag (bs_flag).

[0119] Next, in S83, the CPU 34 judges whether the search process has been completed. If the search process has been completed, that is, if bs_flag==1 (Yes in S83), the process proceeds to S84. If the search process has not been completed, that is, if bs_flag==1 is not true (No in S83), the CPU 34 ends the timer interrupt flow.

[0120] In S84, the CPU 34 receives the search result from the FPGA 32. Furthermore, when reception of the search result is completed, the CPU 34 sets the second flag (rcv_flag) to 1, which is a value indicating that the search result has been received. Then, when the process of S84 ends, the CPU 34 ends the timer interrupt flow.

[0121] 16 is a timing chart of processing executed by the information processing system 10 according to the third embodiment. In the information processing system 10 according to the third embodiment, the CPU 34 executes main processing for the combinatorial optimization problem to be solved next during search processing by the FPGA 32. For example, when the information processing system 10 executes a first search processing (m=1) for searching the ground state of a first Ising model and then executes a second search processing (m=2) for searching the ground state of a second Ising model, the CPU 34 and FPGA 32 perform processing as follows.

[0122] First, the CPU 34 executes a first main process to generate information used in executing the first search process (m=1), and then executes a pre-processing and a parameter transmission process for the first search process (m=1). Next, after the first main process is executed by the CPU 34, the FPGA 32 executes the first search process (m=1).

[0123] Next, the CPU 34 executes a second main process to generate information used to execute the second search process (m=2) while the FPGA 32 is executing the first search process (m=1). When the first search process (m=1) by the FPGA 32 ends while the CPU 34 is executing the second main process, the CPU 34 temporarily suspends the second main process and executes a result receiving process to receive the search results of the first search process (m=1). Then, the FPGA 32 executes the second search process (m=2) after the CPU 34 executes the second main process.

[0124] In this way, the information processing system 10 according to the third embodiment operates the CPU 34 and the FPGA 32 in parallel. This allows the information processing system 10 according to the third embodiment to shorten the overall processing time and increase the overall throughput.

[0125] (Fourth embodiment) Next, an information processing system 10 according to a fourth embodiment will be described. The configuration of the information processing system 10 according to the fourth embodiment is the same as the configuration of the information processing system 10 according to the third embodiment shown in FIG. 13. Furthermore, the processing of the information processing system 10 according to the fourth embodiment is different from that of the information processing system 10 according to the third embodiment in the processing when a timer interrupt occurs, but the other processing is the same. Therefore, in the description of the information processing system 10 according to the fourth embodiment, components that are almost the same as those in the third embodiment are given the same reference numerals, and detailed description thereof will be omitted.

[0126] The information processing system 10 according to the fourth embodiment sequentially solves a plurality of combinatorial optimization problems one by one, and executes in parallel the main processing by the CPU 34 and the search processing by the FPGA 32. Furthermore, the information processing system 10 according to the fourth embodiment executes the search processing multiple times during the main processing by the CPU 34, if possible.

[0127] 17 is a flowchart showing a process flow when a timer interrupt occurs in the CPU 34 according to the fourth embodiment. When a timer interrupt occurs in a state where the timer interrupt is permitted, the CPU 34 according to the fourth embodiment executes the process according to the flow shown in FIG.

[0128] First, in S91, the CPU 34 judges whether or not the second flag (rcv_flag) indicates that the search result has not been received. If the second flag (rcv_flag) indicates that the search result has been received, that is, if rcv_flag==0 is not satisfied (No in S91), the CPU 34 ends the timer interrupt flow. If the second flag (rcv_flag) indicates that the search result has not been received, that is, if rcv_flag==0 (Yes in S91), the CPU 34 advances the process to S92.

[0129] In S92, the CPU 34 checks whether or not the search process is completed by the FPGA 32. Specifically, the CPU 34 acquires a first flag (bs_flag).

[0130] Next, in S93, the CPU 34 judges whether the search process has been completed. If the search process has been completed, that is, if bs_flag==1 (Yes in S93), the process proceeds to S94. If the search process has not been completed, that is, if bs_flag==1 is not true (No in S93), the CPU 34 ends the timer interrupt flow.

[0131] In S94, the CPU 34 receives the search result from the FPGA 32. Furthermore, when reception of the search result is completed, the CPU 34 sets the second flag (rcv_flag) to 1, which is a value indicating that the search result has been received.

[0132] Next, in S95, the CPU 34 calculates N auxiliary variables (p1 to p N The CPU 34 generates the initial values ​​of the N main variables (x1 to x N ) may further generate initial values ​​for each of

[0133] In this embodiment, the FPGA 32 can execute multiple search processes during one main process by the CPU 34. In S95, the CPU 34 generates initial values ​​for executing the second and subsequent search processes (ini=2 and subsequent) of the multiple search processes executed during one main process. In S95, the CPU 34 sets N auxiliary variables (p1 to p N ) and the initial values ​​of the N main variables (x1~x N ) to generate initial values ​​for each of

[0134] Next, in S96, the CPU 34 calculates the N auxiliary variables (p1 to p N ) to the FPGA 32. Furthermore, the CPU 34 transmits the initial values ​​of the main variables (x1 to x N ), the initial values ​​of the generated N main variables (x1~x N) to the FPGA32.

[0135] Next, in S97, the CPU 34 instructs the FPGA 32 to start a search process. Furthermore, the CPU 34 sets the second flag (rcv_flag) to 0, which is a value indicating that the search result has not been received.

[0136] When the FPGA 32 receives an instruction to start a search process from the CPU 34, the FPGA 32 searches for N auxiliary variables (p1 to p N ) and the initial values ​​of the N main variables (x1~x N ) and starts the search process. Then, when the CPU 34 finishes the process of S97, it ends the timer interrupt flow.

[0137] FIG. 18 is a timing chart of the processing executed by the information processing system 10 according to the fourth embodiment.

[0138] In the information processing system 10 according to the fourth embodiment, the CPU 34 executes a main process for the combinatorial optimization problem to be solved next during a search process by the FPGA 32. Furthermore, the FPGA 32 maintains N auxiliary variables (p1 to p N ) and execute the search process multiple times while changing the initial values ​​of each of the

[0139] For example, when the information processing system 10 executes a first search process (m=1) to search for the ground state of a first Ising model, and then executes a second search process (m=2) to search for the ground state of a second Ising model, the CPU 34 and FPGA 32 perform processing as follows.

[0140] First, the CPU 34 executes a first main process, and then executes a pre-processing and a parameter transmission process for the first search process (m=1). Then, the FPGA 32 executes the first search process (m=1). Then, the CPU 34 executes a second main process during the period in which the FPGA 32 executes the first search process (m=1).

[0141] Here, when the first search process (m=1) by the FPGA 32 is completed while the CPU 34 is executing the second main process, the CPU 34 temporarily suspends the second main process and executes a result receiving process for receiving the search result of the first search process (m=1). Furthermore, the CPU 34 sets N auxiliary variables (p1 to p N ) and causes the FPGA 32 to execute the first search process again using the new initial values. Then, the CPU 34 causes the FPGA 32 to repeat the first search process until the execution of the second main process is completed.

[0142] Then, when the CPU 34 receives a plurality of search results of the first search process having different initial values ​​of the auxiliary variables during execution of the second main process, the CPU 34 generates a search result of the first search process based on the received plurality of search results.

[0143] In this way, the information processing system 10 according to the fourth embodiment can shorten the overall processing time and increase the overall throughput by operating the CPU 34 and the FPGA 32 in parallel. Furthermore, the information processing system 10 according to the fourth embodiment can obtain multiple search results for one combinatorial optimization problem and output a solution based on the multiple search results. This allows the information processing system 10 according to the fourth embodiment to output a more accurate solution.

[0144] (First Modification) Next, a first modified example will be described. The first modified example is applicable to all of the second to fourth embodiments.

[0145] The information processing system 10 according to the first modification solves a plurality of combinatorial optimization problems one by one in sequence. Before solving each combinatorial optimization problem, the information processing system 10 determines whether the circuit currently configured in the FPGA 32 is appropriate, and if it is not appropriate, reconfigures the FPGA 32, and if it is appropriate, proceeds with the processing without reconfiguring the FPGA 32.

[0146] For example, the CPU 34 selects, from among a plurality of pieces of circuit information, circuit information representing a circuit that executes an appropriate algorithm according to the combinatorial optimization problem to be solved or the purpose (e.g., emphasis on convergence speed or accuracy), and reconfigures the FPGA 32 using the selected circuit information. Also, for example, the CPU 34 determines whether or not to reconfigure so as to shorten the overall processing time including the reconfiguration time.

[0147] 19 is a diagram illustrating the processing time when the FPGA 32 is not reconfigured and the processing time when the FPGA 32 is reconfigured. For example, consider a case where the information processing system 10 executes an application that solves a combinatorial optimization problem in which the size of the J matrix changes dynamically.

[0148] The application solves a large-scale problem (N=N large ) and then solve the small problem (N=N small ) is solved. Note that N large >N small In the second process (m=2), if no reconfiguration is performed, the FPGA32 will large Therefore, if the second process (m=2) does not involve reconfiguration, the processing time is N large main variables and N large It is determined by the variable update time for updating the auxiliary variables and the number of times the update process is repeated.

[0149] The second process (m=2) is N=N small The search process for the specified state can be performed by a circuit for solving N=N smallThe time it takes to update variables using a circuit to solve the problem is N=N large However, the FPGA32 has a variable update time of N=N small When implementing a circuit to solve the problem, a reconfiguration process must be performed. In other words, if the total time of the processing time and the reconfiguration time in the reconfigured circuit is shorter than the processing time of the previous circuit without reconfiguration, the FPGA32 can shorten the overall processing time of the second process (m=2).

[0150] Therefore, when a first circuit capable of searching for the ground state of a first Ising model is configured in FPGA 32, when a search process is executed to search for the ground state of a second Ising model that can be searched by the first circuit, CPU 34 executes the following process.

[0151] First, a first time representing an expected execution time of the search process executed by the first circuit is compared with a second time including a reconfiguration time for reconfiguring the FPGA 32 into a second circuit and an expected execution time of the search process executed by the second circuit. Here, the second circuit is a circuit capable of searching for the ground state of the second Ising model and has a shorter search time than the first circuit.

[0152] If the second time is equal to or longer than the first time, the CPU 34 does not reconfigure the FPGA 32 in which the first circuit is configured, and causes the FPGA 32 to execute a search process for searching for the ground state of the second Ising model. If the second time is shorter than the first time, the CPU 34 reconfigures the FPGA 32 to the second circuit, and causes the FPGA 32 to execute a search process for searching for the ground state of the second Ising model. By executing such processing, the information processing system 10 can shorten the overall processing time.

[0153] In addition, after searching for the ground state of the second Ising model, the information processing system 10 may further continuously search for the ground states of one or more Ising models whose ground states can be searched for by the second circuit. In such a case, the CPU 34 adds to the first time the predicted execution time when the first circuit searches for each of the ground states of one or more Ising models subsequent to the second Ising model. Furthermore, the CPU 34 adds to the second time the predicted execution time when the second circuit searches for each of the ground states of one or more Ising models subsequent to the second Ising model. This allows the information processing system 10 to shorten the overall processing time even when the second circuit continuously searches for the ground states of multiple Ising models.

[0154] (Second Modification) Next, a second modified example will be described. The second modified example is applicable to all of the first to fourth embodiments.

[0155] 20 is a diagram showing coupling information including coupling coefficients. In the second modified example, the information processing system 10 acquires definition information defining an Ising model that represents a combinatorial optimization problem to be solved from a user or the like. The definition information includes coupling information in which a plurality of coupling coefficients that define the Ising model are described. For example, the information processing system 10 acquires filed coupling information described in a predetermined format.

[0156] Each of the multiple coupling coefficients included in the coupling information is associated with an index for specifying the i-th coupling coefficient and an index for specifying the j-th coupling coefficient. In addition, for example, the coupling information describes multiple coupling coefficients arranged in the raster scan order of the i and j indexes. Therefore, the CPU 34 can detect the size of the J matrix from the index (i, j) of the coupling coefficient at the final position. For example, in the example of FIG. 20, the CPU 34 detects N≧max(i,j) to detect N=4 as the size of the Ising model. Note that max() is a function that detects the maximum value of i and j among the multiple coupling coefficients included in the coupling information.

[0157] Prior to the search process for the combinatorial optimization problem, the CPU 34 selects appropriate circuit information from among the multiple pieces of circuit information stored in the circuit information storage device 38, and provides the selected circuit information to the FPGA 32 to configure a circuit in the FPGA 32. In this case, the CPU 34 selects the circuit information based on the size of the Ising model detected from the coefficient information. For example, the CPU 34 selects circuit information representing a circuit for searching for an Ising model that is equal to or larger than the size detected from the coefficient information and has the smallest size.

[0158] Furthermore, the CPU 34 may select the circuit represented by the circuit information selected based on the connection information as the second circuit in the first modified example.

[0159] In addition, when the circuit information storage device 38 includes a plurality of circuit information representing circuits with different precision of the coupling coefficients, the circuit information storage device 38 may select one piece of circuit information representing a circuit capable of searching for the ground state of the Ising model, based on the precision of the coupling coefficients described in the coupling information.

[0160] For example, the CPU 34 selects circuit information representing a circuit that performs calculations with 16-bit integer precision if all of the multiple coupling coefficients described in the coupling information are expressed as integers and are in the range of −32768 to 32767. Furthermore, the CPU 34 selects circuit information representing a circuit that performs calculations with floating-point or fixed-point precision if any one of the multiple coupling coefficients described in the coupling information includes a coupling coefficient that represents a decimal number.

[0161] Furthermore, the CPU 34 may display the selected circuit information, the size of the detected Ising model, and the accuracy of the coupling coefficients on the display device 42. This allows the CPU 34 to notify the user of this information.

[0162] In this way, the information processing system 10 according to the second modification detects the size of the Ising model and the accuracy of the coupling coefficients included in the J matrix from the coupling information describing the coupling coefficients, and selects appropriate circuit information from among multiple pieces of circuit information based on the detected size and accuracy, and configures the circuit information in the FPGA 32. In this way, the information processing system 10 according to the second modification can eliminate the user's effort in specifying circuit information and the risk of specifying incorrect information. Note that the format of the filed coupling information, the method of detecting the size, and the method of detecting the accuracy of the coupling coefficients are not limited to the above-mentioned methods, and any method may be used.

[0163] (Third Modification) Next, a third modified example will be described. The third modified example is applicable to all of the first to fourth embodiments.

[0164] In the third modification, the circuit information storage device 38 stores a plurality of pieces of circuit information for implementing circuits that execute search processing using mutually different algorithms. In the third modification, the user inputs information other than information for specifying the algorithm. For example, the user inputs definition information (J matrix, h vector) and control parameters.

[0165] In the third example, the CPU 34 determines the main variable (x i ) and auxiliary variables (p i Then, the CPU 34 sequentially reconfigures the FPGA 32 for each of the two or more selected circuit information, executes a search process, and receives the search results. In this case, the FPGA 32 calculates the same definition information, the same control parameters, and the same main variables (x i ) and the initial values ​​of the same auxiliary variables (p i) to obtain the search result. Then, the CPU 34 outputs the search result to the user by displaying on the display device 42 a set of information for identifying the algorithm and the search result for each of the two or more pieces of circuit information.

[0166] In the Ising machine 12, performance indexes such as the convergence speed and the accuracy of the solution reached may change by changing the algorithm. The information processing system 10 according to the third modification executes a search process using a plurality of algorithms and outputs the search results for each of the plurality of algorithms, thereby being able to notify the user of an algorithm that is likely to produce an appropriate search result.

[0167] (Fourth Modification) Next, a fourth modified example will be described. The fourth modified example is applicable to all of the first to fourth embodiments.

[0168] As shown in FIG. 4, the FPGA 32 (Ising machine 12) calculates the auxiliary variable (y i ) and the main variable (x i ) for each iteration in FIG. 4. i ) update history and N auxiliary variables (y i For example, during the update process, the FPGA 32 (Ising machine 12) stores the number of iterations and the N main variables (x i ) and N auxiliary variables (y i ) stored in the memory in association with the values ​​of the N main variables (x i ) and N auxiliary variables (y i ) and displays the received update history, for example as a graph, on the display device 42.

[0169] As a result, the information processing system 10 according to the fourth modification can calculate the N main variables (x i ) and N auxiliary variables (y i ) update history can be referenced by users to study combinatorial optimization problems, etc.

[0170] Although the embodiments of the present invention have been described above, the above-mentioned embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These novel embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0171] 10. Information Processing Systems 12 Ising machine 14 Host Division 32 FPGA 34 CPU 36 Main memory 38 Circuit information storage device 40 Input Devices 42 Display device 44 Bus 51 First flag memory circuit 52 Second flag memory circuit

Claims

1. An information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. having the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit Acquire coefficient information including a plurality of coupling coefficients that define the Ising model, Among a plurality of pieces of circuit information representing circuits that realize the search process in the semiconductor device, one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model is selected based on the number or accuracy of the plurality of coupling coefficients included in the coefficient information, and the Ising machine is reconfigured by the selected circuit information. Information processing device.

2. When the search process for searching the ground state of a second Ising model is executed in a state in which a first circuit capable of searching the ground state of a first Ising model is configured in the semiconductor device, the host unit determines whether or not it is possible to search the ground state of the second Ising model by the first circuit, and if it is possible, causes the search process to be executed without reconfiguring the Ising machine, and if it is not possible, causes the Ising machine to be reconfigured and causes the search process to be executed. The information processing device according to claim 1 .

3. The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result.

3. The information processing device according to claim 1 or 2.

4. Prior to the search process, the Ising machine sets the initial values ​​of the N main variables to predetermined values. The information processing device according to claim 3 .

5. Prior to the search process, the host unit transmits the initial values ​​of the N main variables to the Ising machine. The information processing device according to claim 3 .

6. The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N main variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result.

3. The information processing device according to claim 1 or 2.

7. Prior to the search process, the Ising machine sets the initial values ​​of the N auxiliary variables to predetermined values. The information processing device according to claim 6.

8. Prior to the search process, the host unit transmits the initial values ​​of the N auxiliary variables to the Ising machine. The information processing device according to claim 6.

9. Prior to the search process, the host unit Transmitting definition information for defining the Ising model and control parameters for controlling the search process to the Ising machine. The information processing device according to claim 3 .

10. a first flag storage circuit that stores a first flag indicating whether the search process has been completed; The first flag storage circuit updates a value of the first flag in response to a notification transmitted when the search process is completed from the Ising machine, The host unit receives the search result from the Ising machine according to the value of the first flag. The information processing device according to claim 3 .

11. When performing a second search process to search for the ground state of a second Ising model after performing a first search process to search for the ground state of a first Ising model, The host unit executes a first main process to generate information used in executing the first search process; The Ising machine executes the first search process after the first main process is executed by the host unit, The host unit executes a second main process to generate information used in executing the second search process during a period in which the Ising machine executes the first search process, The Ising machine executes the second search process after the second main process is executed by the host unit. The information processing device according to claim 3 .

12. The present invention further comprises a circuit information storage device for storing the plurality of pieces of circuit information. The information processing device according to claim 3 .

13. An information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. having the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; When a second search process for searching the ground state of a second Ising model is executed after a first search process for searching the ground state of a first Ising model is executed, the host unit executes a first main process for generating information used in the execution of the first search process, The Ising machine executes the first search process after the first main process is executed by the host unit, The host unit executes a second main process to generate information used in executing the second search process during a period in which the Ising machine executes the first search process, The Ising machine executes the second search process after the second main process is executed by the host unit, When the first search process is completed during the execution of the second main process, the host unit transmits new initial values ​​of the N auxiliary variables and causes the Ising machine to execute the first search process again using the new initial values ​​of the N auxiliary variables; When the host unit receives a plurality of search results of the first search process in which the initial values ​​of the N auxiliary variables are different during the execution of the second main process, the host unit generates the search result of the first search process based on the received plurality of search results. Information processing device.

14. An information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. having the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; In a state in which a first circuit capable of searching for a ground state of a first Ising model is configured in the semiconductor device, when the search process is executed to search for a ground state of a second Ising model that can be searched for by the first circuit, the host unit: comparing a first time representing an expected execution time of the search process executed by the first circuit with a second time including a reconfiguration time for reconfiguring the semiconductor device into a second circuit and the expected execution time of the search process executed by the second circuit; When the second time is shorter than the first time, the semiconductor device is reconfigured to the second circuit, and the Ising machine is caused to execute the search process; The second circuit is capable of searching for a ground state of the second Ising model and has a shorter search time than the first circuit. Information processing device.

15. An information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. having the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; When receiving an instruction to search for the ground state of the Ising model, the host unit: selecting two or more pieces of circuit information having different algorithms for calculating the N main variables and the N auxiliary variables in the main variable update process and the auxiliary variable update process from the plurality of pieces of circuit information; reconfiguring the semiconductor device for each of the two or more pieces of circuit information in sequence, executing the search process, and receiving the search results; Outputting the search result received from the two or more pieces of circuit information Information processing device.

16. An information processing device, comprising: A host unit that is connected to an Ising machine via an interface and controls the Ising machine. having the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; The Ising machine stores values ​​of the N main variables in association with the number of times the main variable update process is repeated each time the main variable update process is executed, After the search process, the host unit receives values ​​of the N main variables associated with the number of iterations of the main variable update process. Information processing device.

17. An information processing method executed by an information processing device, The information processing device is connected to an Ising machine via an interface and controls the Ising machine; the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the information processing device: Acquire coefficient information including a plurality of coupling coefficients that define the Ising model, Among a plurality of pieces of circuit information representing circuits that realize the search process in the semiconductor device, one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model is selected based on the number or accuracy of the plurality of coupling coefficients included in the coefficient information, and the Ising machine is reconfigured by the selected circuit information. Information processing methods.

18. An information processing method executed by an information processing device, comprising: The information processing device is connected to an Ising machine via an interface and controls the Ising machine; the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the information processing device selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the information processing device transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the information processing device receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; When executing a second search process for searching the ground state of a second Ising model after executing a first search process for searching the ground state of a first Ising model, the information processing device executes a first main process for generating information used in executing the first search process, The Ising machine executes the first search process after the first main process is executed by the information processing device, The information processing device executes a second main process to generate information used in executing the second search process during a period during which the Ising machine executes the first search process, The Ising machine executes the second search process after the second main process is executed by the information processing device, When the first search process is completed during the execution of the second main process, the information processing device transmits new initial values ​​of the N auxiliary variables and causes the Ising machine to execute the first search process again using the new initial values ​​of the N auxiliary variables; When the information processing device receives a plurality of search results of the first search process having different initial values ​​of the N auxiliary variables during the execution of the second main process, the information processing device generates the search result of the first search process based on the received plurality of search results. Information processing methods.

19. An information processing method executed by an information processing device, comprising: The information processing device is connected to an Ising machine via an interface and controls the Ising machine; the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the information processing device selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; In a state in which a first circuit capable of searching for a ground state of a first Ising model is configured in the semiconductor device, when the search process is executed to search for a ground state of a second Ising model that can be searched by the first circuit, the information processing device: comparing a first time representing an expected execution time of the search process executed by the first circuit with a second time including a reconfiguration time for reconfiguring the semiconductor device into a second circuit and the expected execution time of the search process executed by the second circuit; When the second time is shorter than the first time, the semiconductor device is reconfigured to the second circuit, and the Ising machine is caused to execute the search process; The second circuit is capable of searching for a ground state of the second Ising model and has a shorter search time than the first circuit. Information processing methods.

20. An information processing method executed by an information processing device, comprising: The information processing device is connected to an Ising machine via an interface and controls the Ising machine; the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the information processing device selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the information processing device transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the information processing device receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; When receiving an instruction to search for a ground state of the Ising model, the information processing device: selecting two or more pieces of circuit information having different algorithms for calculating the N main variables and the N auxiliary variables in the main variable update process and the auxiliary variable update process from the plurality of pieces of circuit information; reconfiguring the semiconductor device for each of the two or more pieces of circuit information in sequence, executing the search process, and receiving the search results; Outputting the search result received from the two or more pieces of circuit information Information processing methods.

21. An information processing method executed by an information processing device, comprising: The information processing device is connected to an Ising machine via an interface and controls the Ising machine; the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the information processing device selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the information processing device transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the information processing device receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; The Ising machine stores values ​​of the N main variables in association with the number of times the main variable update process is repeated each time the main variable update process is executed, After the search process, the information processing device receives values ​​of the N main variables associated with the number of iterations of the main variable update process. Information processing methods.

22. A program for causing an information processing device to function as a host device, The information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. Function as a the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit Acquire coefficient information including a plurality of coupling coefficients that define the Ising model, Among a plurality of pieces of circuit information representing circuits that realize the search process in the semiconductor device, one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model is selected based on the number or accuracy of the plurality of coupling coefficients included in the coefficient information, and the Ising machine is reconfigured by the selected circuit information. program.

23. A program for causing an information processing device to function as a host device, comprising: The information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. Function as a the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; When a second search process for searching the ground state of a second Ising model is executed after a first search process for searching the ground state of a first Ising model is executed, the host unit executes a first main process for generating information used in the execution of the first search process, The Ising machine executes the first search process after the first main process is executed by the host unit, The host unit executes a second main process to generate information used in executing the second search process during a period in which the Ising machine executes the first search process, The Ising machine executes the second search process after the second main process is executed by the host unit, When the first search process is completed during the execution of the second main process, the host unit transmits new initial values ​​of the N auxiliary variables and causes the Ising machine to execute the first search process again using the new initial values ​​of the N auxiliary variables; When the host unit receives a plurality of search results of the first search process in which the initial values ​​of the N auxiliary variables are different during the execution of the second main process, the host unit generates the search result of the first search process based on the received plurality of search results. program.

24. A program for causing an information processing device to function as a host device, comprising: The information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. Function as a the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; In a state in which a first circuit capable of searching for a ground state of a first Ising model is configured in the semiconductor device, when the search process is executed to search for a ground state of a second Ising model that can be searched for by the first circuit, the host unit: comparing a first time representing an expected execution time of the search process executed by the first circuit with a second time including a reconfiguration time for reconfiguring the semiconductor device into a second circuit and the expected execution time of the search process executed by the second circuit; When the second time is shorter than the first time, the semiconductor device is reconfigured to the second circuit, and the Ising machine is caused to execute the search process; The second circuit is capable of searching for a ground state of the second Ising model and has a shorter search time than the first circuit. program.

25. A program for causing an information processing device to function as a host device, comprising: The information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. Function as a the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; When receiving an instruction to search for the ground state of the Ising model, the host unit: selecting two or more pieces of circuit information having different algorithms for calculating the N main variables and the N auxiliary variables in the main variable update process and the auxiliary variable update process from the plurality of pieces of circuit information; reconfiguring the semiconductor device for each of the two or more pieces of circuit information in sequence, executing the search process, and receiving the search results; Outputting the search result received from the two or more pieces of circuit information program.

26. A program for causing an information processing device to function as a host device, comprising: The information processing device, A host unit that is connected to an Ising machine via an interface and controls the Ising machine. Function as a the Ising machine is a reconfigurable semiconductor device, and executes a search process for searching for a ground state of an Ising model that represents a combinatorial optimization problem; Prior to the search process, the host unit selects one piece of circuit information representing a circuit capable of searching for a ground state of the Ising model from among a plurality of pieces of circuit information representing circuits that cause the semiconductor device to realize the search process, and reconfigures the Ising machine using the selected circuit information; The Ising machine stores N main variables and N auxiliary variables (N is an integer equal to or greater than 2), an i-th main variable (i is an integer equal to or greater than 1 and equal to or less than N) among the N main variables corresponds to an i-th Ising spin among N Ising spins included in the Ising model, and an i-th auxiliary variable among the N auxiliary variables corresponds to the i-th Ising spin, In the search process, the Ising machine For the i-th Ising spin, an auxiliary variable update process for updating the i-th auxiliary variable by the i-th main variable and a main variable update process for updating the i-th main variable by the i-th auxiliary variable are alternately repeated a plurality of times; outputting a value based on the N main variables after alternately executing the main variable update process and the auxiliary variable update process a plurality of times as a search result; Prior to the search process, the host unit transmits initial values ​​of the N auxiliary variables to the Ising machine; After the search process, the host unit receives the search result from the Ising machine and outputs a solution to the combinatorial optimization problem based on the received search result; The Ising machine stores values ​​of the N main variables in association with the number of times the main variable update process is repeated each time the main variable update process is executed, After the search process, the host unit receives values ​​of the N main variables associated with the number of iterations of the main variable update process. program.

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