Arsenic diffusion profile engineering for transistors

Abstract

To provide a method for forming source / drain extensions.SOLUTION: Forming a fin field effect transistor (FinFET) 100 includes forming a gate electrode structure 130 and a gate spacer 133 on a first portion of a semiconductor fin 121, removing a second portion 404 of the semiconductor fin 121 to expose the sidewalls and bottom, forming a silicon arsenide (Si:As) layer on the sidewalls and bottom, and forming source / drain regions in the Si:As layer. During the deposition of the Si:As layer and the formation of the source / drain regions, an arsenic dopant diffuses from the Si:As layer into a third portion 406 of the semiconductor fin located below the gate spacer, the third portion becomes a doped source / drain extension region. By utilizing the Si:As layer, the doping of the source / drain extension region is controlled, and the diffusion of dopants into the channel region is suppressed while contact resistance is reduced.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to methods of forming transistors, and more particularly, to methods of forming source / drain extensions. [Background technology]

[0002]

[0002] Transistors are the main building blocks of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to its gate width, so in general, a high-speed transistor requires a large gate width. Therefore, there is a trade-off between transistor size and speed, and to address the conflicting goals of a transistor with maximum drive current and minimum size, the FinFET was developed. FinFETs are characterized by a fin-shaped channel region that allows the transistor size to be increased without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, FinFETs still have some drawbacks.

[0003]

[0003] For example, in n-channel metal-oxide-semiconductor (nMOS) devices, strong diffusion of phosphorus atoms from heavily phosphorus-doped silicon (Si:P) regions into the channel is a concern in small FinFETs. Thus, although a higher concentration of phosphorus atoms can provide a much lower contact resistance and beneficially reduce the resistivity of the source and drain regions of FinFETs, the risk of phosphorus atoms diffusing from the source / drain extensions into the channel increases significantly, especially for FinFETs with smaller geometries.

[0004] Therefore, there is a need for improved methods of forming transistors. Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure relate generally to a method for forming a transistor, and more particularly, to a method for forming source / drain extensions. In one embodiment, a transistor includes a gate electrode structure disposed on a channel region, an arsenic doped source / drain extension region disposed adjacent to the channel region, an arsenic doped silicon layer disposed in the source / drain extension region, and a source / drain region disposed in the arsenic doped silicon layer.

[0006] In another embodiment, a method of forming a transistor includes removing a first portion of a semiconductor fin to expose a sidewall and a bottom, where a second portion of the semiconductor fin is disposed below a gate electrode structure, The method further includes forming an arsenic doped silicon layer on the sidewalls and the bottom by a selective epitaxial deposition process, and forming source / drain regions in the arsenic doped silicon layer while doping the second portion of the semiconductor fin with arsenic.

[0007] In another embodiment, a non-transitory computer readable storage medium having stored thereon instructions, the instructions including instructions for controlling components of a processing system to perform a process of removing a first portion of a semiconductor fin to expose a sidewall and a bottom, where a second portion of the semiconductor fin is disposed beneath a gate electrode structure, the process further including forming an arsenic doped silicon layer on the sidewalls and the bottom by a selective epitaxial deposition process, and forming source / drain regions in the arsenic doped silicon layer while doping the second portion of the semiconductor fin with arsenic.

[0008]

[0008] In order that the above-mentioned features of the present disclosure may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings merely depict exemplary embodiments, and therefore should not be considered as limiting the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic perspective view of a FinFET according to an embodiment of the present disclosure. [Diagram 2] 2 is a schematic cross-sectional view of the FinFET of FIG. 1 according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a flow diagram of a process for forming the FinFET of FIG. 1 in accordance with an embodiment of the present disclosure. [Figure 4A] 4A-4C are schematic cross-sectional views of a semiconductor device corresponding to various stages of the process of FIG. 3 according to an embodiment of the present disclosure. [Figure 4B] 4A-4C are schematic cross-sectional views of a semiconductor device corresponding to various stages of the process of FIG. 3 according to an embodiment of the present disclosure. [Figure 4C] 4A-4C are schematic cross-sectional views of a semiconductor device corresponding to various stages of the process of FIG. 3 according to an embodiment of the present disclosure. [Figure 4D] 4A-4C are schematic cross-sectional views of a semiconductor device corresponding to various stages of the process of FIG. 3 according to an embodiment of the present disclosure. [Diagram 5] FIG. 4 is a schematic top view of an example of a multi-chamber processing system suitable for carrying out the process of FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0014] To facilitate understanding, wherever possible, the same reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further detail.

[0011]

[0015] An embodiment of the present disclosure relates to a method for forming source / drain extensions. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose sidewalls and a bottom, forming an arsenic doped silicon (Si:As) layer on the sidewalls and bottom, and forming source / drain regions in the Si:As layer. During deposition of the Si:As layer and formation of the source / drain regions, arsenic dopants diffuse from the Si:As layer into a third portion of the semiconductor fin below the gate spacer, which becomes a doped source / drain extension region. Utilizing the Si:As layer provides controlled doping of the source / drain extension region, reducing the diffusion of dopants into the channel region while reducing contact resistance.

[0012]

[0016] 1 is a schematic perspective view of a FinFET 100 according to an embodiment of the present disclosure. The FinFET 100 includes a semiconductor substrate 101, an insulating region 102 disposed on the semiconductor substrate 101, a semiconductor fin 121 extending from the semiconductor substrate 101, and a gate electrode structure 130 disposed on the insulating region 102 and the semiconductor fin 121. An upper portion of the semiconductor fin 121 is exposed to and electrically coupled to a source contact (not shown) of the FinFET 100, another upper portion of the semiconductor fin 121 is exposed to and electrically coupled to a drain contact (not shown) of the FinFET 100, and a central portion of the semiconductor fin 121 includes a channel region of the FinFET 100. The gate electrode structure 130 functions as a gate of the FinFET 100.

[0013]

[0017] The semiconductor substrate 101 may be a bulk silicon (Si) substrate, a bulk germanium (Ge) substrate, a bulk silicon germanium (SiGe) substrate, etc. The insulating region 102, alternatively referred to as shallow trench isolation (STI), may include one or more dielectric materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or multiple layers thereof. The insulating region 102 may be formed by high density plasma (HDP), flowable chemical vapor deposition (FCVD), etc.

[0014]

[0018] Fin spacers (not shown for clarity) may be disposed on the sidewalls of the semiconductor fin 121. The semiconductor fin 121 may be formed from the semiconductor substrate 101 or may be formed from various semiconductor materials deposited on the semiconductor substrate 101. In the latter case, the various semiconductor materials may include silicon germanium, III-V compound semiconductor materials, etc.

[0015]

[0019] The gate electrode structure 130 includes a gate electrode layer 131, a gate dielectric layer 132, a gate spacer 133, and a mask layer 136. In some embodiments, the gate electrode layer 131 includes a polysilicon layer or a metal layer covered with a polysilicon layer. In other embodiments, the gate electrode layer 131 includes a material selected from metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), and molybdenum nitride (MoNx)), metal carbides (such as tantalum carbide (TaC) and hafnium carbide (HfC)), metal nitride carbides (such as TaCN), metal oxides (such as molybdenum oxide (MoOx)), metal oxynitrides (such as molybdenum oxynitride (MoOxNy)), metal silicides (such as nickel silicide), and combinations thereof. The gate electrode layer 131 may also be a metal layer covered with a polysilicon layer.

[0016]

[0020] The gate dielectric layer 132 may include silicon oxide (SiOx), which may be formed by thermal oxidation of the semiconductor fin 121. In other embodiments, the gate dielectric layer 132 is formed by a deposition process. Materials suitable for forming the gate dielectric layer 132 include silicon oxide, silicon nitride, oxynitrides, metal oxides such as HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx, and combinations and multilayers thereof. Gate spacers 133 are formed on the sidewalls of the gate electrode layer 131, with each gate spacer 133 including a nitride portion 134 and / or an oxide portion 135, as shown. In some embodiments, a mask layer 136 is formed on the gate electrode layer 131, as shown, and may include silicon nitride.

[0017]

[0021] Figure 2 is a schematic cross-sectional view of a FinFET 100 according to an embodiment of the present disclosure. The cross-sectional view shown in Figure 2 is taken along the line AA in Figure 1. As shown in Figure 2, the FinFET 100 includes a semiconductor fin 121 having source and drain regions 201, a Si:As layer 204, source and drain extension regions 202, and a channel region 205.

[0018]

[0022] The source and drain regions 201 include a relatively high concentration of an n-type dopant, such as phosphorus (P) or arsenic (As). For example, in some embodiments, the concentration of n-type dopant in the source and drain regions 201 is greater than or equal to 5E21 atoms / cm. 3 The source and drain regions 201 may be as high as 100 nm. The source and drain regions 201 may be fabricated by any suitable method. In one embodiment, the source and drain regions 201 are formed by in situ doping of a semiconductor layer using an epitaxial deposition process. In another embodiment, the source and drain regions are formed by first depositing a semiconductor layer and then doping the deposited semiconductor layer.

[0019]

[0023] Each source / drain region 201 is disposed in a Si:As layer 204. The Si:As layer 204 has a thickness in the range of about 1 nm to about 10 nm. The Si:As layer 204 may be deposited by any suitable method, such as an epitaxial deposition process. The source and drain extension regions 202 are doped with As. In some embodiments, the source and drain extension regions 202 are formed with a thickness 202A substantially the same as the width 133A of the gate spacer 133.

[0020]

[0024] In the small geometries associated with modern FinFET devices, the width 133A of the gate spacer 133, which is approximately the distance between the channel region 205 and the source / drain regions 201, may be only a few nanometers. Conventionally, the undoped source and drain extension regions are first removed, and the doped source and drain extension regions are formed on both sides of the channel region. During the formation of the doped source and drain extension regions, dopants may diffuse into the channel region. Alternatively, doping the undoped source and drain extension regions by any doping method may also lead to the diffusion of dopants into the channel region.

[0021]

[0025] The Si:As layer 204 is utilized to form the doped source and drain extension regions 202 without the risk of dopant diffusion into the channel region 205. During deposition of the Si:As layer 204 and deposition of the source and drain regions 201, As atoms diffuse from the Si:As layer 204 into the source and drain extension regions 202. The diffusion of As atoms from the Si:As layer 204 can be controlled by controlling the amount of excess point defects in the Si:As layer 204. By depositing the Si:As layer 204 at a low temperature, such as about 500° C. to about 700° C., and a high deposition rate, such as about 50 Å / min to about 500 Å / min, the deposited Si:As layer 204 is point defect rich. During deposition of the source and drain regions 201, a deposition temperature, such as about 500° C. to about 700° C., increases the diffusion of As atoms into the source and drain extension regions 202 due to the point defect flux in the Si:As layer 204. Near the end of the deposition of the source and drain regions 201, excess point defects in the Si:As layer 204 migrate to the interface between the Si:As layer 204 and the source / drain extension regions 202, and the diffusion of As atoms from the Si:As layer 204 to the source / drain extension regions 202 stops. Therefore, the amount of excess point defects in the Si:As layer 204 controls the diffusion depth of the As atoms. That is, during the deposition of the source and drain regions 201, the excess point defects are depleted in the Si:As layer 204, the source and drain regions 201, and the surfaces exposed to the chamber environment, which prevents the As atoms from further diffusing from the Si:As layer 204 to the source / drain extension layers 202. In some embodiments, the diffusion of As atoms from the Si:As layer 204 to the source and drain extension layers 202 can be controlled by performing a heat treatment process on the Si:As layer 204 before depositing the source and drain regions 201. The heat treatment process may be a spike anneal process.

[0022]

[0026] FIG. 3 is a flow diagram of a process 300 for forming an nMOS FinFET, according to an embodiment of the present disclosure. FIGS. 4A-4D are schematic cross-sectional views of a semiconductor device corresponding to various stages of the process 300, according to an embodiment of the present disclosure. Although the process 300 is illustrated to form n-type doped source / drain extension regions, the process 300 may also be employed to form other structures in a substrate. The process 300 begins at step 302, as shown in FIG. 4A, where a gate electrode structure 130 and a gate spacer 133 are formed in the semiconductor fin 121. The gate electrode structure 130 and the gate spacer 133 are disposed in a first portion 402 of the semiconductor fin 121, exposing a second portion 404 of the semiconductor fin. The first portion 402 of the semiconductor fin 121 includes a channel region 205 disposed below the gate electrode structure 130 and a third portion 406 disposed below the gate spacer 133.

[0023]

[0027] In step 304, an etching process is performed to remove the second portion 404 of the semiconductor fin 121, as shown in FIG. 4B. The etching process may be an anisotropic etching process, which may be, for example, a deep reactive ion etching (DRIE) process during which the gate electrode structure 130 and the gate spacer 133 are masked. The etching process exposes the sidewalls 401 and the bottom 403 of the third portion 406 of the semiconductor fin. The bottom 403 may be the surface of the semiconductor substrate 101.

[0024]

[0028] In step 306, as shown in FIG. 4C, a Si:As layer 204 is deposited on the sidewalls 401 and bottom 403. The Si:As layer 204 may have a thickness in the range of about 1 nm to about 10 nm. The Si:As layer 204 may be deposited by an epitaxial deposition process, such as a selective epitaxial deposition process. For example, the Si:As layer 204 is deposited on the sidewalls 401 and bottom 403 made of a semiconductor material such as Si, and the Si:As layer 204 is not deposited on the gate spacer 133 and mask layer 136 made of a dielectric material. The deposition process may be performed at a chamber pressure in the range of about 1 Torr to about 600 Torr, e.g., about 10 Torr to about 20 Torr, and a deposition temperature (temperature of the substrate) in the range of about 500° C. to about 700° C., e.g., about 600° C. to about 625° C. A silicon-containing precursor and an arsenic-containing precursor are flowed into the process chamber. The silicon-containing precursor may be silane, disilane, dichlorosilane (DCS), trichlorosilane (TCS), or any suitable silicon-containing precursor. The silicon-containing precursor may include two or more silicon-containing gases. The silicon-containing precursor may have a flow rate ranging from about 1 sccm to about 1000 sccm, for example, from 1 sccm to about 500 sccm, or from 10 sccm to about 1000 sccm. The arsenic-containing precursor may be arsine, tertiarybutylarsine (TBA), or any suitable arsenic-containing precursor. The arsenic-containing precursor may include two or more arsenic-containing gases. The arsenic-containing precursor may have a flow rate ranging from about 0.1 sccm to about 100 sccm. In some embodiments, a carrier gas, such as nitrogen gas or hydrogen gas, may be flowed with the silicon-containing precursor and the arsenic-containing precursor. In some embodiments, an etchant may be flowed with the silicon-containing precursor and the arsenic-containing precursor to perform a selective etch-back to improve the selectivity of the Si:As deposition. An example of the etching solution is hydrochloric acid.

[0025]

[0029] The amount of excess point defects in the Si:As layer 204 can be controlled by varying process conditions such as precursor partial pressure, precursor ratio, process temperature, and / or layer thickness. The amount of excess point defects in the Si:As layer 204 can control the diffusion of As atoms into the third portion 406 of the semiconductor fin 121. During deposition of the Si:As layer 204, As atoms are diffused into the third portion 406 of the semiconductor fin 121.

[0026]

[0030] In step 308, source and drain regions 201 are formed in the Si:As layer 204, as shown in FIG. 4D. The source and drain regions 201 may be a doped semiconductor material, such as silicon doped with phosphorus. The source and drain regions 201 may be formed by any suitable method, such as an epitaxial deposition process. During deposition of the source and drain regions 201, As atoms in the Si:As layer 204 continue to diffuse into the third portion 406 of the semiconductor fin 121, and the doped third portion 406 of the semiconductor fin 121 becomes the source and drain extension regions 202, as shown in FIG. 4D. The source and drain extension regions 202 have a lower dopant concentration compared to the source and drain regions 201. For example, each source / drain extension region 202 may have a dopant concentration of about 1E17 atoms / cm. 3 to about 2E20 atoms / cm 3 The dopant of the source and drain regions 201 may be the same as or different from the dopant of the source and drain extension regions 202. In one embodiment, the dopant in the source and drain regions 201 is phosphorus and the dopant in the source and drain extension regions 202 is arsenic.

[0027]

[0031] Examples of processing systems that may be suitably modified according to the teachings provided herein include the ENDURA®, PRODUCER®, or CENTURA® integrated processing systems available from Applied Materials, Inc., Santa Clara, Calif., or other suitable processing systems. It is contemplated that other processing systems, including from other manufacturers, may be adapted to benefit from aspects described herein. FIG. 5 is a schematic top view of an example of a multi-chamber processing system 500 that may be used to complete the method 300 shown in FIG. 3, according to an embodiment of the present disclosure. As shown in FIG. 5, a plurality of process chambers 502 are coupled to a first transfer chamber 504. The first transfer chamber 504 is also coupled to a first pair of pass-through chambers 506. The first transfer chamber 504 has a centrally located transfer robot (not shown) for transferring substrates between the pass-through chamber 506 and the process chamber 502. The pass-through chamber 506 is coupled to a second transfer chamber 510 that is coupled to a process chamber 514 and a process chamber 516. The second transfer chamber 510 has a centrally located transfer robot (not shown) for transferring substrates between a set of load lock chambers 512 and the process chambers 514 or 516. A factory interface 520 is connected to the second transfer chamber 510 by the load lock chambers 512. The factory interface 520 is coupled to one or more pods 530 on the opposite side of the load lock chambers 512. The pods 530 are typically front-opening unified pods (FOUPs) accessible from a clean room.

[0028]

[0032] During operation, the substrate is first transferred to process chamber 514, in which step 302 may be performed. The substrate is then transferred to process chamber 516, in which step 304 may be performed. The substrate is then transferred to one or more process chambers 502, in which steps 306 and 308 may be performed. Because steps 302, 304, 306, and 308 are all performed within the same processing system 500, vacuum is not broken as the substrate is transferred to the various chambers, reducing the chance of contamination and improving the quality of the deposited epitaxial film.

[0029]

[0033] In some embodiments, step 304 is performed in an etch chamber that is not part of the processing system 500 .

[0030]

[0034] A system controller 580 is coupled to the processing system 500 to control the processing system 500 or its components. For example, the system controller 580 may control the operation of the processing system 500 using direct control of the chambers 502, 504, 506, 510, 512, 514, 516 of the processing system 500 or by controlling controllers associated with the chambers 502, 504, 506, 510, 512, 514, 516. In operation, the system controller 580 enables data collection and feedback from each chamber to adjust the performance of the processing system 500.

[0031]

[0035] The system controller 580 generally includes a central processing unit (CPU) 582, a memory 584, and support circuits 586. The CPU 582 may be one of any form of general-purpose processor available in an industrial environment. The memory 584, a non-transitory computer-readable medium, or machine-readable storage device, is accessible by the CPU 582 and may be one or more of memory, such as a random access memory (RAM), a read-only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage, local or remote. The support circuits 586 are coupled to the CPU 582 and may include cache, clock circuits, an input / output subsystem, power supplies, and the like. The system controller 580 is configured to execute the method 300 stored in the memory 584. The various embodiments disclosed in the present disclosure may generally be implemented under the control of the CPU 582 by executing computer instruction codes stored in the memory 584 (or the memory of a particular process chamber), for example as a computer program product or software routine. That is, the computer program product is tangibly embodied in memory 584 (or a non-transitory computer readable medium or machine readable storage device). When the computer instruction codes are executed by CPU 582, CPU 582 controls the chamber to perform the processes according to various embodiments.

[0032]

[0036] By utilizing the Si:As layer between the source and drain regions and the source and drain extension regions, the doping of the source and drain extension regions is controlled, so that As atoms do not diffuse into the channel region. Furthermore, processes such as source and drain extension recess, source and drain extension regrowth, etc. can be omitted.

[0033]

[0037] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, as determined by the following claims.

Claims

1. A transistor, A substrate; a semiconductor fin disposed on the substrate, a source region, a drain region, and a channel region disposed between the source region and the drain region; a first arsenic doped silicon layer disposed between the source region and the substrate and between the drain region and the substrate; and a second arsenic doped silicon layer disposed between the first arsenic doped silicon layer and the source region and between the first arsenic doped silicon layer and the drain region; a semiconductor fin comprising: a gate electrode structure disposed over the channel region of the semiconductor fin; A transistor comprising:

2. The transistor of claim 1 , wherein the gate electrode structure comprises a gate electrode layer, a gate dielectric layer, and a gate spacer.

3. The transistor of claim 2 , wherein the gate spacer is disposed over the first arsenic doped silicon layer.

4. 10. The transistor of claim 1, wherein the source and drain regions comprise a dopant other than arsenic.

5. 2. The transistor of claim 1, wherein the source and drain regions are doped with phosphorus.

6. 2. The transistor of claim 1, wherein the first arsenic doped silicon layer is disposed between the source region and the channel region and between the drain region and the channel region.

7. The transistor of claim 1, wherein the dopant concentration of the first arsenic-doped silicon layer is less than or equal to 1 / 10 of the dopant concentration of each of the source and drain regions.

8. 1. A method of forming a transistor, comprising: forming an arsenic doped silicon layer on sidewalls and a bottom of a fin-type structure of semiconductor material; the fin structure includes a channel region and an outer portion between the channel region and the arsenic doped silicon layer; the arsenic doped silicon layer is formed by a deposition process; and a gate electrode structure disposed on the fin-type structure; forming an arsenic doped silicon layer; doping the outer portion of the fin structure with arsenic while forming source / drain regions on the arsenic doped silicon layer; A method comprising:

9. 9. The method of claim 8, wherein a chamber pressure during the deposition process ranges from 1 Torr to 600 Torr.

10. The method of claim 8, wherein the temperature during the deposition process is in the range of 500°C to 700°C.

11. 10. The method of claim 8, further comprising flowing a silicon-containing precursor and an arsenic-containing precursor into a process chamber during the deposition process.

12. 10. The method of claim 8, further comprising flowing an etchant through the process chamber during the deposition process to achieve a selective deposition process.

13. 9. The method of claim 8, further comprising doping the outer portion of the fin-type structure during formation of the arsenic doped silicon layer.

14. The outer portion of the fin structure has a density of 1E17 atoms / cm ３ to 2E20 atoms / cm ３ The method of claim 8 , having a dopant concentration in the range of

15. 9. The method of claim 8, wherein the dopant concentration in the outer portion of the fin-type structure is 1 / 10 or less than the dopant concentration in the source / drain regions.

16. 9. The method of claim 8, further comprising performing a heat treatment process on the arsenic doped silicon layer before forming the source / drain regions.

17. The method of claim 16 , wherein the heat treatment process is a spike anneal process.

18. A non-transitory computer readable storage medium storing a plurality of instructions, the plurality of instructions comprising: forming an arsenic doped silicon layer on sidewalls and a bottom of a fin-type structure of semiconductor material; the fin structure includes a channel region and an outer portion between the channel region and the arsenic doped silicon layer; the arsenic doped silicon layer is formed by a deposition process; and a gate electrode structure disposed on the fin-type structure; forming an arsenic doped silicon layer; doping the outer portion of the fin structure with arsenic while forming source / drain regions on the arsenic doped silicon layer; A non-transitory computer-readable storage medium comprising instructions for controlling components of a processing system to perform the method of the present invention.

19. 20. The non-transitory computer readable storage medium of claim 18, wherein the plurality of instructions further comprises instructions for controlling components of the processing system to maintain a chamber pressure during the deposition process between 1 Torr and 600 Torr.

20. 20. The non-transitory computer readable storage medium of claim 18, wherein the plurality of instructions further comprises instructions for controlling components of the processing system to maintain a temperature between 500°C and 700°C during the deposition process.

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