Semiconductor device and its manufacturing method

Abstract

This field-effect transistor includes a first arsenide layer (107a) and a second arsenide layer (107b) configured of a III-V group compound semiconductor including As as a V-group element. The first arsenide layer (107a) and the second arsenide layer (107b) are arranged on a cap layer (106) so as to sandwich a gate electrode forming region. The first arsenide layer (107a) and the second arsenide layer (107b) are formed by arseniding the cap layer (106). A first contact layer (108a) and a second contact layer (108b) are formed on the first arsenide layer (107a) and the second arsenide layer (107b), a source electrode (109) is formed on the first contact layer (108a), and a drain electrode (110) is formed on the second contact layer (108b).

Description

[Technical field]

[0001] The present invention relates to a semiconductor device using a nitride semiconductor and a method for manufacturing the same. [Background technology]

[0002] GaN channel HEMT is a high-speed, high-voltage electronic device that has already been put to practical use as a high-power wireless communication device. In order to further improve the performance (high-frequency characteristics) of GaN channel HEMT, it is essential to reduce the resistance of the device. The device structure of a GaN channel HEMT used for high-frequency applications is shown in Figure 11A.

[0003] In general, a device structure is fabricated by first stacking a buffer layer (nucleation layer) 302 on a substrate 301 such as SiC, sapphire, or Si by a crystal growth method. The device structure typically comprises the buffer layer 302, a back barrier layer 303, a GaN channel layer 304, an AlGaN or AlN barrier layer 305, and a GaN cap layer 306. The buffer layer 302 may be made highly resistive. Also, the back barrier layer 303 may not be provided.

[0004] The source electrode 309 and the drain electrode 310 are formed by depositing materials such as Ti / Al / Ni / Au by electron beam deposition or the like. The source electrode 309 and the drain electrode 310 are alloyed by annealing so as to be in contact (connected) with the channel layer 305. The gate electrode 311 is formed as a Schottky electrode by Ni / Au or the like. An oxide film or a nitride film with a high dielectric constant may be deposited between the gate electrode 311 and the device structure (the cap layer 306, the barrier layer 305, and the channel layer 304).

[0005] To increase the speed of GaN channel HEMTs, it is necessary to miniaturize the device by shortening the gate length (scaling), to make the barrier layer thinner and to increase the Al composition, and to reduce the contact resistance of the source and drain electrodes. In the general device structure described with reference to Fig. 10A, when the contacts of the source electrode 309 and the drain electrode 310 are formed by alloying, an AlGaN barrier layer 305 is interposed between them. However, because AlGaN has high resistance, there is a certain limit to the reduction in contact resistance by such a technique.

[0006] In order to reduce the contact resistance, a method has been proposed in which source contact 307a and drain contact 307b made of highly doped GaN are formed on channel layer 304' by regrowth, as shown in Fig. 11B (Non-Patent Document 1). This structure is formed by first etching the source / drain formation regions of channel layer 304' by dry etching or the like, and then regrowing highly n-type doped GaN by MBE or the like. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] K. Shinohara et al., "Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave MMIC Applications", IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 2982-2996, 2013. Summary of the Invention [Problem to be solved by the invention]

[0008] However, the above-mentioned conventional technology has the following problems. First, it is extremely difficult to reduce the resistance of the GaN regrown in the source / drain formation region. It is extremely difficult to dope wide-gap semiconductor materials at a high concentration, and even if doped, the activation rate of the dopant is not high.

[0009] Secondly, in order to reduce the resistance, it is necessary to alloy the electrode that forms the ohmic contact with the GaN layer. This alloying is performed by high-temperature heat treatment in an N2 atmosphere or the like. However, the metal alloying process deteriorates the morphology of the electrode, and the alloy is formed non-uniformly, which causes variations in the contact resistance. Thus, with conventional technology, there was a problem that it was not easy to reduce the contact resistance of the electrode in semiconductor devices using nitride semiconductors.

[0010] The present invention has been made to solve the above problems, and has an object to reduce the contact resistance of electrodes in a semiconductor device using a nitride semiconductor. [Means for solving the problem]

[0011] The semiconductor device of the present invention comprises a transistor structure made of a nitride semiconductor, an electrode connected to the transistor structure, a top layer of the transistor structure made of a nitride semiconductor not containing Al at a location where the electrode is to be disposed, an As-containing layer disposed between the top layer and the electrode and formed by converting a portion of the top layer in the thickness direction to As, and a contact layer disposed between the As-containing layer and the electrode and made of a III-V compound semiconductor containing at least one of P, As, and Sb as a group V element.

[0012] In addition, a method for manufacturing a semiconductor device includes a first step of forming a transistor structure composed of a nitride semiconductor on a substrate, a second step of forming an As-containing layer by converting a part of a thickness direction of a top layer of the transistor structure, the top layer being composed of a nitride semiconductor not containing Al, at a location where an electrode will be disposed, into As, a third step of forming a contact layer composed of a III-V compound semiconductor containing at least one of P, As and Sb as a group V element on the As-containing layer, and a fourth step of forming an electrode on the contact layer. Effect of the Invention

[0013] As described above, according to the present invention, the uppermost layer of a transistor structure at the location where an electrode is to be disposed is provided with an As-containing layer formed by converting a portion of the uppermost layer into As, thereby making it possible to reduce the contact resistance of an electrode in a semiconductor device using a nitride semiconductor. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a configuration diagram showing a configuration of another semiconductor device according to an embodiment of the present invention. [Figure 3A] FIG. 3A is a cross-sectional view showing a state of a semiconductor device in the middle of a process for illustrating a manufacturing method of an element for illustrating the concept of the semiconductor device according to the embodiment of the present invention. [Figure 3B] FIG. 3B is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a manufacturing method of an element for illustrating the concept of the semiconductor device according to the embodiment of the present invention. [Figure 3C] FIG. 3C is a cross-sectional view showing a state of a semiconductor device in the middle of a process for illustrating a manufacturing method of an element for illustrating the concept of the semiconductor device according to the embodiment of the present invention. [Figure 4A] FIG. 4A is a characteristic diagram showing the characteristics of an element for explaining the concept of a semiconductor device according to an embodiment of the present invention. [Figure 4B]FIG. 4B is a characteristic diagram showing the characteristics of an element for explaining the concept of the semiconductor device according to the embodiment of the present invention. [Figure 5A] FIG. 5A is a cross-sectional view showing a state of a semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5B] FIG. 5B is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5C] FIG. 5C is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5D] FIG. 5D is a cross-sectional view showing a state of the semiconductor device in the middle of a process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5E] FIG. 5E is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 5F] FIG. 5F is a cross-sectional view showing a state of the semiconductor device in the middle of a process for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6A] FIG. 6A is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 6B] FIG. 6B is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 6C] FIG. 6C is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 6D] FIG. 6D is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 6E] FIG. 6E is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 7A] FIG. 7A is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 7B] FIG. 7B is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 7C] FIG. 7C is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 7D] FIG. 7D is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 7E] FIG. 7E is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 7F] FIG. 7F is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 8A] FIG. 8A is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method of manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 8B] FIG. 8B is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 8C] FIG. 8C is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 8D] FIG. 8D is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 8E] FIG. 8E is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device in accordance with the embodiment of the present invention. [Figure 9A]FIG. 9A is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 9B] FIG. 9B is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 9C] FIG. 9C is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 10A] FIG. 10A is a cross-sectional view showing a state of another semiconductor device midway through a process, illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 10B] FIG. 10B is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 10C] FIG. 10C is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 10D] FIG. 10D is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 10E] FIG. 10E is a cross-sectional view showing a state of another semiconductor device in the middle of a process, for illustrating a method of manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 10F] FIG. 10F is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device in accordance with an embodiment of the present invention. [Figure 10G] FIG. 10G is a cross-sectional view showing a state of another semiconductor device midway through a process for illustrating a method for manufacturing the other semiconductor device according to the embodiment of the present invention. [Figure 11A] FIG. 11A is a cross-sectional view showing the configuration of a conventional semiconductor device. [Figure 11B] FIG. 11B is a cross-sectional view showing the configuration of a conventional semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] A semiconductor device according to an embodiment of the present invention will be described below. The semiconductor device includes a transistor structure (element structure) made of a nitride semiconductor, and an electrode connected to the transistor structure. The semiconductor device also includes an As-based layer arranged between the electrode and the top layer of the transistor structure at the location where the electrode is to be arranged, and a contact layer arranged between the As-based layer and the electrode. The electrode is formed in contact with (connected to) the contact layer. The electrode is electrically connected to the top layer made of a nitride semiconductor via a path of the contact layer-As-based layer-top layer.

[0016] The top layer is made of a nitride semiconductor that does not contain Al. The As-containing layer is formed by As-containing a part of the top layer in the thickness direction, and is made of a III-V compound semiconductor that does not contain N and contains As as a group V element. The contact layer is made of a III-V compound semiconductor that does not contain N and contains at least one of P, As, and Sb as a group V element.

[0017] As described above, the surface of the nitride semiconductor layer (top layer) is arsenicized to form an arsenic layer, a contact layer is formed on the arsenic layer, and an electrode is connected to the contact layer, thereby reducing the contact resistance of the electrode.

[0018] The transistor structure is, for example, a field effect transistor having a channel layer 104 made of a nitride semiconductor as shown in FIG. 1, and the electrodes are a source electrode 109 and a drain electrode 110 electrically connected to the channel layer 104.

[0019] This field effect transistor is a so-called high electron mobility transistor (HEMT), and includes a substrate 101, a buffer layer 102 formed on the substrate 101, a back barrier layer 103 formed on the buffer layer 102, a channel layer 104 formed on the back barrier layer 103, a barrier layer 105 formed on the channel layer 104, and a cap layer 106 formed on the barrier layer 105. In this example, a transistor structure is formed by the channel layer 104, the barrier layer 105, and the cap layer 106. In this example, the cap layer 106 is the uppermost layer.

[0020] The substrate 101 may be made of, for example, sapphire, silicon carbide, silicon, GaN, etc. The buffer layer 102 may be made of, for example, GaN. The back barrier layer 103 may be made of, for example, AlGaN. The channel layer 104 may be made of, for example, GaN. The barrier layer 105 may be made of, for example, AlGaN. The cap layer 106 may be made of, for example, GaN. The cap layer 106 may be made of not only GaN but also a nitride semiconductor that does not contain Al, such as InGaN or InN. The reason for this will be described later.

[0021] When the substrate 101 is made of a different material such as sapphire, silicon carbide, or silicon, a buffer layer 102 can be formed on the substrate 101 by heteroepitaxial growth, and the above-mentioned layers can be formed on the buffer layer 102 by epitaxial growth. When the substrate 101 is made of single crystal GaN, the above-mentioned layers can be formed by epitaxial growth. These layers can be grown by a vapor phase growth method such as metalorganic chemical vapor deposition or molecular beam epitaxy.

[0022] The field effect transistor also includes a first As-based layer 107a and a second As-based layer 107b made of a III-V group compound semiconductor containing As as a group V element. The first As-based layer 107a and the second As-based layer 107b are disposed on the cap layer 106 so as to sandwich a gate electrode formation region. The first As-based layer 107a and the second As-based layer 107b can be made of, for example, GaAs. The first As-based layer 107a and the second As-based layer 107b are formed by As-based the cap layer 106 as described later. Therefore, the cap layer 106 made of a nitride semiconductor and in contact with the first As-based layer 107a and the second As-based layer 107b and the first As-based layer 107a and the second As-based layer 107b contain the same group III element.

[0023] A first contact layer 108a and a second contact layer 108b are formed on the first As-based layer 107a and the second As-based layer 107b, a source electrode 109 is formed on the first contact layer 108a, and a drain electrode 110 is formed on the second contact layer 108b. The first contact layer 108a and the second contact layer 108b can be made of, for example, InGaAs. A gate electrode 111 is formed on the cap layer 106 in the gate formation region between the source electrode 109 and the drain electrode 110. The gate electrode 111 is, for example, connected by a Schottky electrode.

[0024] In this example, a first As-doped layer 107a and a second As-doped layer 107b are disposed between the cap layer 106, which is the uppermost layer of the transistor structure at the location where the source electrode 109 and the drain electrode 110 are disposed, and the source electrode 109 and the drain electrode 110. A first contact layer 108a and a second contact layer 108b are formed between the first As-doped layer 107a and the second As-doped layer 107b and the source electrode 109 and the drain electrode 110. The source electrode 109 and the drain electrode 110 are formed in contact with the first contact layer 108a and the second contact layer 108b.

[0025] The transistor structure is, for example, a heterojunction bipolar transistor including a collector layer 124, a base layer 125, and an emitter layer 126 made of a nitride semiconductor, as shown in FIG.

[0026] This heterojunction bipolar transistor includes a substrate 121, a buffer layer 122 formed on the substrate 121, a sub-collector layer 123 formed on the buffer layer 122, a collector layer 124 formed on the sub-collector layer 123, a base layer 125 formed on the collector layer 124, an emitter layer 126 formed on the base layer 125, and an emitter contact layer 127 formed on the emitter layer 126. In this example, the collector layer 124, the base layer 125, and the emitter layer 126 form a transistor structure. In this example, the base layer 125 to which the base electrode 131 is connected is the uppermost layer.

[0027] The substrate 121 may be made of, for example, n-type GaN. The buffer layer 122 may be made of, for example, n-type GaN. The sub-collector layer 123 may be made of, for example, n-type GaN. The collector layer 124 may be made of, for example, n-type GaN. The base layer 125 may be made of, for example, p-type GaN. The emitter layer 126 may be made of, for example, n-type AlGaN. The emitter contact layer 127 may be made of, for example, n-type GaN. An emitter electrode 128 is formed on the emitter contact layer 127.

[0028] Each layer made of the above-mentioned nitride semiconductor can be formed by epitaxial growth on the substrate 121 by a vapor phase growth method such as metal organic chemical vapor deposition or molecular beam epitaxy. Each layer can be formed as N polarity (group V polarity) with the main surface being the -c plane by crystal growth in the -c axis direction. By fabricating in this manner, a two-dimensional hole gas is formed at the interface between the emitter layer 126 and the base layer 125 due to a built-in potential in the heterostructure of the nitride semiconductor formed in the c axis direction, and the base resistance can be reduced.

[0029] This heterojunction bipolar transistor also includes an As-alloyed layer 129 made of a III-V group compound semiconductor containing As as a group element. The As-alloyed layer 129 is formed on the base layer 125 around the mesa structure formed by the emitter layer 126. The As-alloyed layer 129 can be made of GaAs, for example. The As-alloyed layer 129 is formed by As-alloying the base layer 125. Therefore, the As-alloyed layer 129 and the base layer 125 made of a nitride semiconductor in contact with the As-alloyed layer 129 have the same group III element.

[0030] Moreover, a contact layer 130 is formed on the As-based layer 129, and a base electrode 131 is formed on the contact layer 130. A collector electrode 132 is formed and connected to the rear surface of the substrate 121. In this example, the As-based layer 129 is disposed between the base electrode 131 and a base layer 125, which is the uppermost layer of the transistor structure at the location where the base electrode 131 is disposed. Moreover, the contact layer 130 is disposed between the As-based layer 129 and the base electrode 131. The base electrode 131 is formed in contact with the contact layer 130.

[0031] Next, the principle of the present invention will be described with reference to FIG. 3A to FIG. 3C. First, the formation of a layer of a III-V group compound semiconductor having low resistance to GaN will be described. First, as shown in FIG. 3A, a sample is prepared in which a buffer layer 142 of GaN is formed on a substrate 141, and a semiconductor layer 143 made of GaN is formed on the buffer layer 142. For example, the buffer layer 142 and the semiconductor layer 143 can be formed by heteroepitaxial growth on various substrates 141 such as sapphire, silicon carbide, and silicon. Also, a GaN single crystal substrate can be used as the substrate 141. Each layer can be formed by a vapor phase growth method such as metalorganic chemical vapor deposition and molecular beam epitaxy. In this description, the semiconductor layer 143, which is the top layer, is GaN, but it can also be InGaN. The semiconductor layer 143 may be any nitride semiconductor that does not contain Al, such as GaN, InGaN, or InN.

[0032] Next, as shown in FIG. 3B, the fabricated sample is exposed to an As atmosphere under reduced pressure (pressure range lower than 760 Torr) and heated to convert the semiconductor layer 143 to As from the surface side, forming an As-containing layer 144 of GaAs. The conversion to As proceeds from the surface side toward the inside of the layer. Although it depends on the atmosphere, the outermost surface of GaN is thermally decomposed even at a heating temperature of about 700° C. under reduced pressure, and dangling bonds are formed. In this state, if arsenic is present in the atmosphere, N, which is a group V element constituting the semiconductor layer 143, is replaced by As in the atmosphere, and Ga-As is formed. The rate of decomposition of crystals by heat increases with the pressure reduction. The process of substituting N of the nitride semiconductor with As as described above requires a certain amount of energy, and in order to accelerate the decomposition, it is important to make the atmosphere a reduced pressure environment lower than normal pressure (760 Torr).

[0033] The above-mentioned As conversion can be carried out, for example, in a general growth apparatus capable of carrying out well-known metalorganic chemical vapor deposition, using H2, N2, Ar, or the like as a carrier gas. The rate of As conversion, which progresses from the surface side to the inside of the layer, can be controlled by changing the type and pressure of the carrier gas. For example, if H2 is used as the carrier gas, the As conversion rate increases, and if N2 is used, it decreases. Furthermore, the As conversion rate increases with increasing heating temperature when As conversion is carried out.

[0034] The experimental change in arsenic conversion is shown in Figure 4A. Figure 4A shows the measurement of the time change in reflectance of the surface of the semiconductor layer undergoing arsenic conversion during the heat treatment process for arsenic conversion. A white LED (light emitting diode) was used as the light source, and wavelengths of 405 nm and 633 nm were used to measure the reflectance. The atmosphere in which the arsenic conversion process was carried out was an arsenic atmosphere with a set pressure of 12,500 Pa or more, H2 as the carrier gas, and AsH3 as the raw material gas.

[0035] In Figure 4A, (a) and (b) show the change in reflectance over time. The reflectance increases around the time when the set temperature of the surface of the semiconductor layer undergoing As conversion reaches a specified temperature (heat treatment temperature), and after the specified time has elapsed, it transitions to a saturated state where the reflectance barely changes. In this saturated state, the surface of the semiconductor layer made of GaN has been replaced by As, and has become almost entirely GaAs.

[0036] As described above, the surface of the semiconductor layer 143 is converted to As to form the As-containing layer 144, and then the process temperature is changed to an appropriate condition, and the group III and group V raw materials are supplied under appropriate flow rates, temperatures, and pressures, thereby growing InGaAs to form the contact layer 145, as shown in FIG. 3C.

[0037] Next, the use of a nitride semiconductor that does not contain Al as the material of the semiconductor layer 143 will be described with reference to FIG. 4B. FIG. 4B shows the reflectance measurement results when the material of the semiconductor layer is made of AlGaN and the surface of this semiconductor layer is subjected to the same As-treatment as described above. As shown in FIG. 4B, it was revealed that the reflectance hardly changes even when the surface of the semiconductor layer made of AlGaN is subjected to As-treatment. This suggests that the Al-N bond in the nitride semiconductor in which Al is a group III element is strong, and Al-N is hardly decomposed at a heat treatment temperature of around 700°C. For this reason, it is desirable that the material constituting the semiconductor layer to be subjected to As-treatment is GaN or InGaN or InN, which are materials in which the bond energy between the group III element and N is smaller than that.

[0038] The arsenic layer is formed by arsenating a nitride semiconductor. By forming the arsenic layer, the contact layer of the III-V compound semiconductor that does not contain nitrogen as a constituent element can be formed with good crystallinity, and the contact resistance of the electrode can be reduced.

[0039] Here, the presence of As in the As-doped layer and the thickness thereof can be measured by cross-sectional TEM observation or EDX analysis. However, it cannot be said that the same effects as those of the present invention can be obtained when a semiconductor layer of the same composition is grown by another crystal growth method. Therefore, it is considered to be almost impractical to clearly specify the structure of the As-doped layer that contributes to the effects of the present invention.

[0040] Next, a method for manufacturing the HEMT described with reference to Fig. 1 will be described with reference to Fig. 5A to Fig. 5F. First, as shown in Fig. 5A, a buffer layer 102, a back barrier layer 103, a channel layer 104, a barrier layer 105, and a cap layer 106 are grown in this order on a substrate 101 to form a transistor structure made of a nitride semiconductor on the substrate 101 (first step). In this type of transistor, the cap layer 106 is formed to a thickness of, for example, about several nm.

[0041] 5B, a part of the cap layer 106 in the thickness direction is converted to arsenic to form an arsenic layer 107 (second step). As described above, the cap layer 106 is converted to arsenic from the surface side by exposing it to an arsenic atmosphere and heating it. The cap layer 106 is made of an Al-free nitride semiconductor, and is the uppermost layer of the transistor structure where the electrodes are to be disposed.

[0042] 5C, InGaAs is grown on the As-doped layer 107 to form a contact layer 108 (third step). The contact layer 108 is a layer made of a III-V compound semiconductor containing As as a group V element. The contact layer 108 can be made of, for example, any of InAs, InGaAs, GaAs, GaAsSb, InGaAsSb, AlGaAs, InAsSb, AlAs, and AsAsSb.

[0043] Next, as shown in FIG. 5D, a source electrode 109 and a drain electrode 110 are formed on the contact layer 108 (fourth step). The source electrode 109 and the drain electrode 110 are formed so as to sandwich the gate formation region. The source electrode 109 and the drain electrode 110 are made of a metal having a low contact resistance with a III-V group compound semiconductor containing at least one of P, As, and Sb as a V group element such as InGaAs. There are many such metals, and these metals can obtain a low contact resistance without performing an alloying process with the contact layer 108. Examples of such metals include Ti / Pt / Au and Pt / Ti / Pt / Au. Depending on whether the contact resistance or heat resistance is important, an appropriate metal laminate structure can be selected. An alloying annealing process can also be performed within a range that does not significantly affect the element characteristics.

[0044] Next, the contact layer 108 and the As-doped layer 107 are selectively etched using the formed source electrode 109 and drain electrode 110 as a mask, thereby forming a first As-doped layer 107a, a second As-doped layer 107b, a first contact layer 108a, and a second contact layer 108b, as shown in FIG. 5E, and exposing the cap layer 106 in the gate formation region.

[0045] The above-mentioned etching can be performed by, for example, wet etching. For example, etching treatment using an etching solution such as hydrochloric acid, sulfuric acid, or citric acid can be used. GaN is hardly etched by these etching solutions. On the other hand, InGaAs and GaAs can be etched by these etching solutions, and the above-mentioned selective etching is possible.

[0046] Next, as shown in FIG. 5F, a gate electrode 111 that forms a Schottky contact is formed on the cap layer 106 in the exposed gate formation region.

[0047] Here, the thickness of the cap layer 106 to be subjected to the As conversion process will be described. The thickness of the cap layer 106 can be determined as follows. As shown by the results of the reflectance measurement described above, after a sufficient period of As conversion, the reflectance of the As conversion near the surface of the cap layer 106 shifts to a saturated state, and As conversion hardly progresses. Therefore, when the cap layer 106 is sufficiently thick, only a portion (near the surface) of the cap layer 106 from the surface in the thickness direction is converted to As.

[0048] In the etching step for exposing the cap layer 106 in the gate formation region, the As-converted layer 107 is removed, and the remaining cap layer 106 that is not As-converted remains directly below the gate electrode 111 and affects the device characteristics. Therefore, when designing a device, it is important to set the initial thickness (thickness at the time of formation) of the cap layer 106 in consideration of the thickness of the As-converted layer that is removed by etching.

[0049] For example, if the cap layer is thin before the As conversion process, the As conversion process converts almost the entire cap layer into As in the thickness direction. In this As conversion, the barrier layer 105 made of a nitride semiconductor containing Al as a constituent element is not converted into As. Therefore, the thickness of the As conversion layer can be controlled by making the cap layer 106 thinner than the maximum thickness at which the As conversion process forms the As conversion layer.

[0050] In this way, if the entire cap layer is converted to As to form an As-containing layer, and then a contact layer made of a III-V group compound semiconductor containing As as a group V element is formed on the cap layer, the cap layer will not remain in the gate formation region in the above-mentioned etching process. For this reason, it is important to determine the thickness of the cap layer (top layer) at the time of formation based on the maximum thickness of the As-containing layer formed in the nitride semiconductor not containing Al by Asification. For example, the thickness of the As-containing layer can be confirmed by EDX analysis in the observation of a cross-sectional TEM image, and the maximum thickness of the As-containing layer formed by Asification can be obtained by observing samples prepared under various conditions. In addition, if the cap layer is made to a thickness such that the entire layer is nitrided in this way, the AlGaN layer, which is easily oxidized, will be exposed, so care must be taken to prevent this.

[0051] Next, another method for manufacturing a HEMT will be described with reference to Figs. 6A to 6E. First, as shown in Fig. 6A, a buffer layer 102, a back barrier layer 103, a channel layer 104, a barrier layer 105, and a cap layer 106 are grown in this order on a substrate 101. Then, a mask pattern 201 is formed. Next, the cap layer 106, the barrier layer 105, and a part of the channel layer 104 in the thickness direction are patterned by an etching process using the formed mask pattern 201 as a mask. In this patterning, regions for forming a source electrode and a drain electrode are formed in the channel layer 104.

[0052] Next, the mask pattern 201 is removed, and then an As conversion process is performed to convert the exposed surface of the cap layer 106 and the surface of the channel layer 104 into As, thereby forming an As-converted layer 107' as shown in FIG. 6B.

[0053] Next, a III-V group compound semiconductor such as InGaAs doped with a high concentration of n-type impurities is grown to form a contact layer 108' as shown in FIG. ++ -It is made of InGaAs.

[0054] Next, a source electrode 109 and a drain electrode 110 are formed on the contact layer 108' with a gate formation region in between, and the contact layer 108' and the As-doped layer 107' are selectively etched using the source electrode 109 and the drain electrode 110 as a mask to expose the cap layer 106 in the gate formation region as shown in Fig. 6D. This forms a first As-doped layer 107'a and a second As-doped layer 107'b, and a first contact layer 108'a and a second contact layer 108'b are formed. Thereafter, a gate electrode 111 for Schottky contact is formed on the exposed cap layer 106 in the gate formation region as shown in Fig. 6E.

[0055] In this HEMT, the source electrode 109 and the drain electrode 110 are formed on the channel layer 104 via the arsenic layer and the contact layer, so that the contact resistance can be reduced compared to when they are formed on the barrier layer 105.

[0056] Next, another method for manufacturing a HEMT will be described with reference to Figures 7A to 7F. First, as shown in Figure 7A, a buffer layer 102, a back barrier layer 103, a channel layer 104, a barrier layer 105, and a cap layer 106 are grown in this order on a substrate 101. Next, a mask pattern 201 is formed.

[0057] Next, the cap layer 106, the barrier layer 105, and a part of the channel layer 104 in the thickness direction are patterned by etching using the formed mask pattern 201 as a mask. In this patterning, regions for forming source and drain electrodes are formed in the channel layer 104. Furthermore, n-type impurities having a high concentration are introduced on the barrier layer 105 and the channel layer 104 around the mesa of the cap layer 106 formed by patterning. + By regrowing -GaN, a first regrown layer 114a and a second regrown layer 114b are formed. The first regrown layer 114a and the second regrown layer 114b are formed in a state where they cover the side surfaces of the barrier layer 105 and the cap layer 106.

[0058] Next, mask pattern 201 is removed, and as shown in FIG. 7B, a groove is formed between first regrown layer 114a and second regrown layer 114b, with the upper surface of cap layer 106 exposed at the bottom of this groove.

[0059] Next, an As conversion process is performed to form an As conversion layer 107'' on the surfaces of the first regrown layer 114a and the second regrown layer 114b and on the surface (upper surface) of the cap layer 106, as shown in FIG. 7C.

[0060] Next, a III-V group compound semiconductor such as GaAs doped with a high concentration of n-type impurities is grown to form a contact layer 108″ as shown in FIG. 7D. In this example, the contact layer 108″ is ++ -It is assumed that the semiconductor device is made of GaAs.

[0061] Next, the contact layer 108" and the As-based layer 107" are selectively etched to expose the cap layer 106 in the gate formation region. As a result, as shown in FIG. 7E, a first As-based layer 107"a and a second As-based layer 107"b are formed, and a first contact layer 108"a and a second contact layer 108"b are formed. A source electrode 109 is formed on the first contact layer 108"a, and a drain electrode 110 is formed on the second contact layer 108"b. Thereafter, as shown in FIG. 7E, a gate electrode 111 for Schottky connection is formed on the exposed cap layer 106 in the gate formation region.

[0062] In this HEMT, since the barrier layer 105 is not exposed during the arsenic conversion process (FIG. 7E), no regions with poor crystal quality are formed.

[0063] Next, another method for manufacturing a HEMT will be described with reference to Figures 8A to 8E. In the above, the manufacturing method in which each nitride semiconductor layer is grown in the +c-axis direction on the substrate 101 has been described, but it is also possible to grow them in the -c-axis direction. By growing them in the -c-axis direction, the main surface of each nitride semiconductor layer becomes a group V polarity surface instead of a group III polarity surface.

[0064] It is possible to perform crystal growth so that the N-polarity plane is the main surface orientation by using a generally known technique. Examples include a crystal growth method using a nitrided sapphire substrate as a buffer layer, a growth method using a SiC substrate with the C-plane as the main surface orientation, or a method using a GaN substrate with the N-polarity plane as the main surface orientation. Alternatively, it is also possible to obtain an N-polarity plane by growing the crystal with the Ga-polarity plane as the main surface orientation and then inverting the epitaxial layer structure by substrate transfer.

[0065] 8A, a buffer layer 102, a back barrier layer 103, a channel layer 104, and a barrier layer 105 are grown in this order in the -c-axis direction on a substrate 101. In this case, a high concentration of two-dimensional electron gas is formed due to the polarization effect between the back barrier layer 103 and the channel layer 104.

[0066] Next, as shown in Fig. 8B, the barrier layer 105 and a part of the channel layer 104 are patterned in the thickness direction by etching using the mask pattern as a mask. In this patterning, regions for forming a source electrode and a drain electrode are formed in the channel layer 104. In this example, even if the barrier layer 105 is patterned, the two-dimensional electron gas is not lost.

[0067] Next, the mask pattern is removed, and then an As conversion process is performed to convert the exposed surface of the channel layer 104 into As, forming a first As conversion layer 117a and a second As conversion layer 117b sandwiching the barrier layer 105 made of AlGaN as shown in Fig. 8C. No As conversion layer is formed on the barrier layer 105 containing Al as a constituent element.

[0068] Next, a III-V group compound semiconductor such as InGaAs is grown to form a first contact layer 118a, a second contact layer 118b, and an amorphous layer 118c, as shown in Fig. 8D. In the region where the barrier layer 105 is exposed, the surface is not converted into As, so that amorphous InGaAs is deposited to form the amorphous layer 118c.

[0069] Thereafter, a source electrode and a drain electrode are formed on the first contact layer 118a and the second contact layer 118b, and a gate electrode for Schottky contact is formed on the exposed barrier layer 105, thereby completing a HEMT.

[0070] In the above-mentioned manufacturing method, since the barrier layer 105 is exposed in the As conversion process, the heat treatment is performed without converting it to As, which may cause a concern of degrading the crystal quality of the layer grown thereon. In contrast, by manufacturing as described below, the barrier layer 105 is not exposed in the As conversion process.

[0071] 8A and 8B, the barrier layer 105 and a part of the channel layer 104 are patterned in the thickness direction to form regions for forming a source electrode and a drain electrode in the channel layer 104. Next, GaN is regrown to form a cap layer 106' as shown in FIG.

[0072] Next, an arsenic conversion process is performed to convert the surface of the cap layer 106' into arsenic, forming an arsenic layer 107' as shown in Fig. 9B. Next, a III-V compound semiconductor such as InGaAs is grown to form a contact layer 108'.

[0073] Next, a source electrode 109 and a drain electrode 110 are formed on the contact layer 108' with a gate formation region in between, and the contact layer 108' and the As-doped layer 107' are selectively etched using the source electrode 109 and the drain electrode 110 as a mask to expose the cap layer 106' in the gate formation region as shown in Fig. 9C. This forms a first As-doped layer 107'a and a second As-doped layer 107'b, and a first contact layer 108'a and a second contact layer 108'b. Thereafter, a gate electrode 111 for Schottky contact is formed on the exposed cap layer 106' in the gate formation region.

[0074] In the above description, the contact layer is made of InGaAs doped with a high concentration of n-type impurities, but the present invention is not limited to this. The contact layer can be made of a p-type III-V group compound semiconductor. For example, the contact layer can be made of GaAs, AlGaAs, InGaAs, GaAsSb, InAsAsSb, InAsSb, InGaSb, GaSb, or InAs doped with C, Zn, or Be. In this way, a layer having an extremely low p-type contact resistance can be formed on a layer of a nitride semiconductor.

[0075] Next, a method for manufacturing the heterojunction bipolar transistor described with reference to Fig. 2 will be described with reference to Fig. 10A to Fig. 10F. First, as shown in Fig. 10A, a buffer layer 122, a sub-collector layer 123, a collector layer 124, a base layer 125, an emitter layer 126, and an emitter contact layer 127 are grown in this order on a substrate 121 to form a transistor structure made of nitride semiconductors on the substrate 121 (first step).

[0076] Next, an emitter electrode 128 is formed on the emitter contact layer 127, and the emitter contact layer 127 is etched using the formed emitter electrode 128 as a mask, thereby processing the emitter contact layer 127 into a first mesa shape as shown in Fig. 10B. The emitter electrode 128 is desirably made of an electrode material that can withstand a heat treatment at a high temperature of about 700°C in a later process. In addition, the emitter electrode 128 is desirably made of an electrode material that forms an ohmic contact with the emitter contact layer 127.

[0077] Next, a mask layer 202 is formed to cover the emitter contact layer 127 and the emitter electrode 128 formed in a mesa shape. Next, the emitter layer 126 is etched using the formed mask layer 202 as a mask, so that the emitter layer 126 is processed into a second mesa shape, as shown in FIG. 10C. The second mesa shape has a larger area in a plan view than the first mesa shape. This processing exposes the main surface of the base layer 125 around the emitter layer 126 formed into the second mesa shape.

[0078] Next, the main surface of the base layer 125 around the emitter layer 126 is converted to arsenic by an arsenic conversion process, forming an arsenic conversion layer 129 as shown in Fig. 10D (second step). As described above, the base layer 125 around the emitter layer 126 is converted to arsenic from the surface side by exposing it to an arsenic atmosphere and heating it. The base layer 125 around the emitter layer 126 is the uppermost layer of the transistor structure where the electrode (base electrode) is disposed.

[0079] Next, as shown in FIG. 10E, a highly p-type doped III-V compound semiconductor is grown on the As layer 107 to form a contact layer 108 (third step). For example, GaAsSb doped with a high concentration of carbon can be grown to form the contact layer 108. The contact layer 108 is a layer made of a III-V compound semiconductor containing As as a group V element.

[0080] 10F, a base electrode 131 is formed on the contact layer 108 (fourth step). The base electrode 131 can be made of an electrode material capable of forming an ohmic contact with the contact layer 108 made of GaAsSb. For example, the base electrode 131 can be a laminated electrode made of Ti, Pt, Au, or the like.

[0081] 10G, a heterojunction bipolar transistor is obtained by forming a collector electrode 132 on the back surface of the substrate 121. When assuming operation with a common emitter, the collector side is used with a reverse bias, so the collector electrode 132 does not need to form an ohmic contact. The collector electrode 132 can be configured to be connected to the substrate 121 via a Schottky contact.

[0082] As described above, according to the present invention, the uppermost layer of a transistor structure at the location where an electrode is to be disposed is provided with an As-containing layer formed by converting a portion of the uppermost layer into As. This makes it possible to reduce the contact resistance of the electrode in a semiconductor device using a nitride semiconductor.

[0083] It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention. [Explanation of symbols]

[0084] 101...substrate, 102...buffer layer, 103...back barrier layer, 104...channel layer, 105...barrier layer, 106...cap layer, 107a...first As-doped layer, 107b...second As-doped layer, 108a...first contact layer, 108b...second contact layer, 109...source electrode, 110...drain electrode, 111...gate electrode, 121...substrate, 122...buffer layer, 123...sub-collector layer, 124...collector layer, 125...base layer, 126...emitter layer, 127...emitter contact layer, 128...emitter electrode, 129...As-doped layer, 130...contact layer, 131...base electrode, 132...collector electrode.

Claims

1. A transistor structure made of a nitride semiconductor; an electrode connected to the transistor structure; an As-containing layer made of a III-V group compound semiconductor and formed by As-containing a portion of the top layer in a thickness direction, the As-containing layer being made of an Al-free nitride semiconductor and being disposed between the top layer of the transistor structure at a location where the electrode is disposed and the electrode; a contact layer disposed between the As layer and the electrode and made of a III-V compound semiconductor containing at least one of P, As, and Sb as a V group element; Equipped with the transistor structure is a heterojunction bipolar transistor having a collector layer, a base layer, and an emitter layer made of a nitride semiconductor; The electrode is a base electrode.

2. 2. The semiconductor device according to claim 1, The semiconductor device is characterized in that the uppermost layer and the As layer contain the same group III element.

3. A first step of forming a transistor structure made of a nitride semiconductor on a substrate; a second step of forming an As-containing layer by arsenizing a part of a thickness direction of a top layer of the transistor structure, the part being made of an Al-free nitride semiconductor and located at a position where an electrode is to be disposed; a third step of forming a contact layer made of a III-V compound semiconductor containing at least one of P, As, and Sb as a V group element on the As-doped layer; a fourth step of forming an electrode on the contact layer; Equipped with The second step comprises heating the uppermost layer in an atmosphere of a source gas containing As to convert the uppermost layer into As from the surface side.

4. 4. The method of manufacturing a semiconductor device according to claim 3, 2. A method for manufacturing a semiconductor device, wherein the contact layer is made of any one of InAs, InGaAs, GaAs, GaAsSb, InGaAsSb, AlGaAs, InAsSb, AlAs, and AsAsSb.

5. 5. The method for manufacturing a semiconductor device according to claim 3, further comprising the steps of: The thickness of the uppermost layer is determined based on the maximum thickness of the As-doped layer formed in the Al-free nitride semiconductor by As-doping.

4. A method for manufacturing a semiconductor device comprising the steps of:

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