Wideband low noise amplifier with noise rejection

Abstract

The low-noise amplifier has the requisite noise rejection to provide a low noise figure and operation over a frequency range of 0.5 GHz to 50 GHz. The amplifier amplifies the input signal, amplifying the noise while ensuring that the amplified signal and amplified noise are out of phase and in phase with their corresponding inputs, respectively. A feedback circuit, which is nonlinear with frequency, allows for constant amplification. A summing circuit combines the amplified signal with the noise to be rejected, so that the two combined noise signals to be added are 180 degrees out of phase with each other. An optional secondary amplification stage provides additional amplification. Preferably, the amplifier, auxiliary amplifier, and summing device utilize CMOS transistors located on an SOI substrate with impedance stabilization across the frequency range.

Description

[Technical field]

[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 16 / 399,599, filed April 30, 2019, and entitled "Low Noise Amplifier With Noise Cancellation."

[0002] The present invention relates to a wideband low noise amplifier with noise cancellation. [Background technology]

[0003] Embodiments of the present invention relate to a low noise amplifier with noise rejection suitable for, but not limited to, amplification of signals at mm-wave frequencies and implementation as a semiconductor device for ultra-wideband CMOS applications.

[0004] To minimize the presence of unwanted signals, especially in low frequency electronic devices, cancellation techniques have been employed. For example, to minimize the magnitude of an unwanted signal, a replica of the unwanted signal, which is 180° out of phase with the unwanted signal, can be combined or added to the unwanted signal. Under "perfect" conditions, where the replica signal is exactly 180° out of phase and has equal magnitude to the unwanted signal, adding these signals together results in virtually total cancellation.

[0005] Removal of unwanted signals using the techniques described above becomes much more difficult at higher microwave and millimeter wave frequencies. It becomes increasingly difficult to generate a "perfect" replica signal at higher frequencies due to the challenges in maintaining a perfect 180° phase relationship as well as an equal magnitude to the signal being removed. Even more challenges exist when the signal being removed is associated with an amplifier, especially when the amplifier operates over a substantial range of high frequencies. Summary of the Invention [Problem to be solved by the invention]

[0006] An objective of embodiments of the present invention is to fill the need for a low noise amplifier with noise rejection, particularly but not exclusively, an amplifier that operates over an extremely wide range from about 0.5 GHz up to full mmWave frequencies while providing a low noise figure. [Means for solving the problem]

[0007] Exemplary embodiments of the low noise amplifier are configured to provide a low noise figure and operation over the frequency range of 0.5 GHz to 50 GHz. integral The semiconductor amplifier amplifies the input signal and generates an amplified signal and an amplified noise, both out of phase and in phase with the corresponding inputs, respectively, and amplifies the noise. A feedback circuit, which is non-linear with frequency, allows constant amplification over a frequency range. An auxiliary semiconductor amplifier amplifies the same input and produces an amplified signal and an amplified noise, both out of phase with the input. A summing circuit combines all of these amplified signals such that the noise component is rejected, with the auxiliary amplifier providing the same amount of amplification as the amplifier, and the amplified noise signals being summed are 180 degrees out of phase with each other. An optional secondary amplification stage provides additional amplification. Preferably, the amplifier, auxiliary amplifier, and summing device utilize CMOS transistors located on an SOI substrate with impedance stabilization over the frequency range.

[0008] Features of the exemplary embodiments of the invention will become apparent from the description, the claims, and the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a simplified schematic diagram illustrating the concept of a low noise amplifier with noise cancellation according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic diagram of an embodiment of a low noise amplifier with noise cancellation in accordance with an embodiment of the present invention. [Diagram 3]1 is a graph showing predicted noise figure and gain for a 72 μm CMOS semiconductor device using 45 nm 12 SIO (silicon on insulator). [Figure 4] FIG. 2 is a more detailed schematic diagram of a low noise amplifier with noise cancellation according to an embodiment of the present invention, suitable for operation at mm-wave frequencies. [Diagram 5] 6 is a graph of the noise figure for the embodiment shown in FIG. 5 before and after device extraction, respectively. [Figure 6] 6 is a graph of the noise figure for the embodiment shown in FIG. 5 before and after device extraction, respectively. [Figure 7] 6 is a graph showing gain and input output return loss over the millimeter frequency range of 40-60 GHz for the embodiment shown in FIG. 5. [Figure 8] 6 is a graph illustrating third order distortion associated with the embodiment shown in FIG. 5. [Figure 9A] FIG. 1 is a schematic diagram of a low noise amplifier with noise rejection suitable for operation over a wide range of frequencies. [Figure 9B] FIG. 2 is a simplified schematic diagram of a low noise amplifier to aid in understanding the description including equations. [Figure 10] 9B is a graph showing the gain and input output return loss of the embodiment shown in FIG. 9A over a wide range of frequencies as shown. [Figure 11] 9B is a graph showing the noise figure of the embodiment shown in FIG. 9A over a wide range of frequencies shown. [Figure 12] 9B is a graph illustrating third order distortion associated with the embodiment shown in FIG. 9A. [Figure 13] FIG. 1 is a schematic diagram of a low noise amplifier with noise rejection including an additional amplification stage suitable for providing increased gain over a wide range of frequencies. [Figure 14] 14 is a graph illustrating the gain and input output return loss of the embodiment shown in FIG. 13. [Figure 15] 14 is a graph illustrating the noise figure of the embodiment shown in FIG. 13 over a wide range of frequencies as shown. [Figure 16] 14 is a graph illustrating third order distortion associated with the embodiment shown in FIG. 13. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] One aspect of an embodiment of the present invention is the recognition that by utilizing a secondary amplification stage and signal summing to achieve noise cancellation, thereby providing noise cancellation for the noise associated with the first amplification stage of the LNA, the noise at the output of the LNA circuit is primarily determined by only the noise associated with the secondary amplification stage and summing stage. The secondary and summing stages can be selected and configured to achieve a very low noise figure even at mm-wave operating frequencies.

[0011] Another aspect of an embodiment having an operating range of 0.5 GHz to 50 GHz is to reduce the inherent parasitic capacitances associated with the active devices involved in the noise elimination, such as the input capacitance C, such that the gain associated with the noise feedback signal remains substantially constant over a wide range of frequencies. gs , C ds and C gd This is accomplished by utilizing a frequency dependent circuit in the noise rejection feedback path that compensates for the effects of parasitic capacitance to maintain a substantially flat / constant gain for the noise rejection feedback signal over a wide range of frequencies.

[0012] 1 shows a simplified schematic diagram illustrating the concept of a low noise amplifier with noise cancellation according to an embodiment 100 of the present invention. A common source transistor 105 provides an amplification stage whose output Y is coupled to one input of a summing stage 110. An input X to the transistor 105 also provides an input to an inverting amplifier 115 whose output is connected to the other input of the summing stage 110. A resistor R s represents the resistance of the input signal source, resistor R is the feedback resistor, and the amplification provided by the amplifier stage is then given by Y=X*(1-g m *R). The noise amplification factor from node X to node Y is 1+R / Rs It is.

[0013] g m *If R is greater than 1, the input signal voltage V at X rf is amplified, and V rf is amplified to provide a voltage at Y that is 180° out of phase with the voltage V n represents the noise voltage that has the same phase at the input and output of transistor 105. The 180° phase inversion provided by amplifier 115 results in a signal V rf is the signal V at Y rf , and thus the signals are in phase and add in magnitude at the output of summer 110. However, the 180° phase inversion provided by amplifier 115 reduces the noise V from X to n is amplified, resulting in the noise at Y at the output of amplifier 115 being 180 degrees out of phase with the noise at Y. Thus, the noise signal combined at summing circuit 110 is subtracted, i.e., out of phase with the opposite magnitude, at the output of summing circuit 110. To maximize noise rejection, the amplification provided by amplifier 115 is −(1+R / R) such that the noise magnitude provided at the output of amplifier 115 is the same magnitude as the noise at Y but in opposite phase. s ) When the noise of the input amplifier stage 105 is removed, then the noise of the overall circuit is substantially determined only by the noise of the secondary stage, amplifier 115, and summing circuit 110. The summing circuit 110 may be a "Y" connection of three resistors or may use active devices such as transistors to combine the two signal paths.

[0014] 2 shows a more detailed schematic diagram of an embodiment 200 of a low noise amplifier with noise cancellation according to the present invention. The embodiment 200 utilizes the same basic principles of noise cancellation as described for embodiment 100. A matched amplifier Q1B is implemented as a resistive feedback inverter working in conjunction with amplifier Q1A to form an amplifier stage. The total transconductance gain of the amplifier stage is g m =gm.nmos +g m.pmos , i.e., the sum of the gains of Q1A and Q1B. As the size of the physically realized device increases, the drain-source resistance R ds It should be noted that, due to the reduced input capacitance, the noise signal leaks back into the channel and is not filtered out. Additionally, both active input amplifier devices exhibit input parasitic capacitance, resulting in frequency dependent noise signal leakage.

[0015] The combined secondary stage and summer 205 is implemented as a source follower Q3 on top of cascode common source amplifiers Q2A and Q2B. The noise voltage gain A(=-(1+R / R s )) is -g m2A / g m3 Therefore, the Q2A device must be physically sized A times larger than Q3 to achieve the correct gain, so that the noise signal coming from the drain of Q2B has the same magnitude as the noise signal coming from the source of Q3. This means that the output from the drain of amplifier Q1A has a gain of "A". If Q2A is sized too large compared to the input capacitance at the gates of Q1A and Q1B, then C gs2 (the gate to source capacitance of Q2A) affects the input match so sizing must be considered. A separate current source 215 can be used to help steer the current from the common source cascode devices Q2A and Q2B since it is much larger than the source follower Q3. The high pass filter, capacitor C and resistor R h filters the amplified signal coupled to the input gate of Q3. Bias voltages are not shown, but will be apparent to one skilled in the art in view of the embodiments described below.

[0016] 3 shows a graph showing noise figure 305 and gain 310, both in decibels, expected for a 72 μm CMOS semiconductor device using 45 nm 12 SIO (Silicon on Insulator) technology operating at 0.8v and 10mA for the frequencies as shown. Note that the noise figure is less than 3db at 60GHz and about 2db at 40GHz, lower than that at lower frequencies. The maximum gain at 40GHz is about 11db, dropping substantially linearly to approximately 10db or less at 60GHz. This demonstrates suitability for use in embodiments of the present invention.

[0017] FIG. 4 shows a more detailed schematic diagram of an embodiment 400 of a low noise amplifier with noise rejection suitable for operation over the millimeter wave frequency range, i.e., 40 GHz to 60 GHz. The embodiment 400 is substantially similar to the embodiment 200 and operates using the same principles. Therefore, only the differences between these embodiments will be primarily discussed. The five active devices in the embodiment 200 correspond to the five devices T1 to T5, respectively, in analogous circuit positions in the embodiment 400, with the respective transistors performing the corresponding functions. A matching network 405, together with a capacitor C1, forms an input matching network to provide impedance matching between a signal source 407 and the gate of the primary amplification stage provided by transistors T4 and T5. Similarly, a matching network 410, together with a capacitor C2, forms an output matching network to provide impedance matching between the amplified output, i.e., the source of transistor T3, and the next stage for receiving the amplified signal as represented by resistor RLOAD. In the exemplary embodiment 400, the amplifier is suitable for millimeter wave operation from 40 GHz to 60 GHz. A DC supply voltage source 415 is provided as shown to power the active devices. As will be appreciated, a DC bias voltage source 420 associated with the gate of transistor T2 will be set to an appropriate DC voltage to bias transistor T2 into the active linear region of operation.

[0018] The embodiment 400 provides an implementation of a current source 425 and input / output matching networks 405 and 410 that enhances wideband operation at millimeter wavelength (MMW) frequencies. A successful noise rejecting (NC) LNA for MMW applications with operation in the 20 GHz range is challenging. The gain selection of the auxiliary amplifier T1 / T3 is preferably based on the voltage amplification ratio of the noise signal at the input stage T4 / T5. If significant inter-stage impedance mismatch or noise current leakage exists, effective rejection of the noise from the input stage will not occur at the output. However, the implementation of a matching network at gigahertz frequencies offers complications such as adding parasitics. For example, inductors generally exhibit a self-resonant frequency (SRF) based on the inductance and parasitic capacitance values ​​of the inductor itself, similar to inductors implemented in CMOS technology. There are also resistive losses associated with the inductor. These factors can adversely affect the bandwidth (BW) of operation. From these considerations, it is preferable that the gain of the input amplifier stage is higher than the unloaded gain of the auxiliary amplifier, for example by a factor of 5. This is because the gain of the auxiliary amplifier (i.e., |1+R / R s |>g m2 / g m3 ) substantially larger R / R s This can be achieved by selecting a ratio (e.g., 5 times or more). Since T1 and T2 are the same size, the gain (g m1 / g m3 )=(g m2 / g m3 ) Increasing the input stage gain also reduces the noise contribution of the feedback resistor, R, because its noise is scaled down by the input stage gain.

[0019] The noise contribution of the input stage and feedback resistors is now minimized, so that the noise associated with the output stage (auxiliary amplifier plus summer) dominates the overall LNA noise. m1 and g m2Increasing the gm of transistors T1 and T2 can result in higher output stage gain and thereby reduce noise. One way to achieve this is to steer current from an external current source. Because transistors T1 and T2 have a higher gm value than transistor T3, transistors T1 and T2 can carry more DC current without interfering with the current through transistor T3. Therefore, an external current source can be used to supply current only to transistors T1 and T2. A simple current source that does not provide sufficient isolation from the auxiliary amplifier would result in degraded noise performance and frequency response at MMW frequencies. To overcome this, a cascode current source 425 with transistors T6-T9 and bypass capacitor C5 is used to reduce undesirable loading effects on the auxiliary amplifier.

[0020] Additional enhancements support more effective operation at MMW frequencies over an extended bandwidth. Specifically, inductive degeneration is incorporated into the output stage to enhance noise reduction. For example, the inductor L3 in series with the source of T1 and the amplifier stage internal input capacitance C gs The use of inductor L1 in series with T2 results in the desired real input impedance over most of the frequency bandwidth. The use of inductive degeneration with L3 results in improved performance over a wide frequency range. The appropriate choice of L3 is a balance between the one-handed input impedance and the broadband matching and noise figure (NF) performance. A parasitic reduction technique can be applied to the auxiliary amplifier by inserting inductor L4 between the source and drain of T3 of the common gate transistor T2. This reduces the overall series capacitance C gs For T2, dshas the effect of eliminating / reducing the noise. Inductor L4, with a value selected based on device size and parasitic capacitance L4, helps to achieve matching between T2 and T3, resulting in optimal current flow and increased gain in the system. In effect, inductor L4 transforms the highly capacitive output impedance (looking into the drain of T2) into a lower impedance value that allows current to flow more effectively between the two transistors. This compensation is preferably optimized so that frequency stability is not compromised as a result of the higher gain, nor is output return loss compromised. For example, for a 45 nm 12 SOI technology, depending on device size T1 / T2, L4 can be in the range of 80-150 pH for low power applications. To further reduce the noise figure as a result of the substage loading effect, a gate resistor R of several kilohms is used. h The drain of T4 / T5 and the C of T3 are used. gs and the series capacitance between h The combination of forms a high pass filter, which sets the low frequency of the desired operating frequency range. For MMW applications, low loss capacitor values ​​of fractions of a picofarad can be used.

[0021] Inductors are important in impedance matching, especially at MMW frequencies, and are preferably characterized for their inductance value, Q factor, and SRF. All inductors should preferably exhibit an SRF in excess of 100 GHz for amplifier operation in the 40 GHz to 60 GHz range. Furthermore, inductors in SOI technology are expected to suffer from less ohmic losses compared to inductors implemented in bulk silicon.

[0022] To further increase the operating frequency and BW, a wideband input matching network 405 should be used. Input and output DC blocking capacitors C1, C2 are preferably incorporated as part of the input and output matching networks. This is preferred because these capacitors are typically small at MMW frequencies, e.g., less than 1 pF, resulting in smaller parasitics and losses. The shunt inductor (L2=106 pH), series inductor (L1=100 pH), and shunt capacitor (C4=26.5×10 -15 The combination of 1000V to 1000V farads provides a broadband impedance transformation to the source impedance.

[0023] 5 and 6 are graphs 500 and 600 of noise diagrams for the embodiment shown in FIG. 5 before and after device extraction, respectively. Device extraction follows the integrated circuit layout of the device to determine the resistance, capacitance, and inductance at various nodes of the device. It better predicts the actual realizable behavior of the device. As shown in FIG. 6, the extraction was performed and the device capacitance and resistance at all significant nodes were calculated. As shown, a NF of 3 dB or less above 20 GHz from 40 GHz to 60 GHz is achieved.

[0024] FIG. 7 is a graph 700 showing gain 705, input return loss 710, and output return loss 715 over the millimeter frequency range of 40-60 GHz for the embodiment shown in FIG.

[0025] FIG. 8 is a graph 800 displaying the results of a simulated two-tone test for third-order distortion associated with the embodiment shown in FIG. 5. Graph 800 is a plot of a typical two-tone test. Two frequency signals f1 and f2 (with a frequency interval of 0.5 GHz) are injected into the input of the amplifier. The power of the signals f1 and f2 is increased and the power of the distortion products in the f1 signal, the f2 signal, 2f1-f2, and 2f2-f1 at the output of the amplifier is measured. The Output Third-order Intermodulation Product (OIP3) is arrived at from the intersection of the extrapolated power line slopes 805 and 810. The linear slopes of 805 and 810 are 1 and 3, respectively. The predicted value of 15 dBm for OIP3 is very good for low power applications at MMW frequencies.

[0026] Additional linearization techniques can be applied to the NCLNA circuit without adversely affecting the NF and input matching, e.g., Derivative Superposition (DS). DS exploits the complementary nature of T4 / T5 in the input amplification stage. By biasing the gates of the PMOS (T5) and NMOS (T4) differently and / or by adjusting the individual physical sizes of T4 vs. T5, both devices T4 / T5 share a common drain current, so that out-of-phase nonlinear transconductance coefficients (third-order derivatives of Id vs. Vgs) are generated and eliminated after summation. This results in further input third-order intermodulation products (IIP3) improvement as a measure of the reduction of the third-order nonlinearity coefficient in the drain current. IIP3s well above 5 dBm are achievable using the linearization techniques described above. Transistors T4, T5 and T1 share a common gate voltage as shown in Figure 4, but providing AC-only coupling of the T1 transistor to T4 / T5 (e.g., using a series capacitor) can enhance the DS linearization. This would of course require the addition of a bias resistor / circuit to provide an independent gate bias voltage to the T1 gate.

[0027] FIG. 9A shows a schematic diagram of a low noise amplifier 900 with noise rejection suitable for low noise operation over frequencies from 0.5 GHz to 40 GHz. This exemplary embodiment utilizes 12 SOI 45 nm CMOS technology, selected for its low noise figure and gain and the relative low cost available at this range of frequencies. Low noise amplifier 900 is substantially similar to amplifier 400, so the description of this circuit will focus on the differences between amplifier 900 and amplifier 400. As will be described in more detail with respect to FIG. 2, resistor R of amplifier 400 is a feedback element that controls the amplification of the noise signal and provides a constant gain factor.

[0028] The intrinsic input capacitance of the active device, C input or C in The presence of adds complexity to the noise rejection mechanism since the input impedance is frequency dependent. The following discussion is intended to explain why inductor L2 is useful. Refer to the circuit of Figure 2 where only a single feedback resistor R is used. Since the input impedance changes with frequency, the noise amplification changes with frequency. It can be shown that the input impedance of the feedback device is approximately equal to: Z in =1 / (g m +SC in ) where g m is the device transconductance, and S=jω=j2πf is the generally complex frequency.

[0029] When the input impedance becomes reactive, noise currents flow in the input capacitance, resulting in a lack of noise rejection as frequency increases. Thus, the noise voltage gain, i.e., the ratio of the noise voltages at the nodes at the drain and gate of Q1A, is frequency dependent and increases as frequency increases, as shown below:

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[0030] Figure 9B provides a simplified version of Figure 9A in which a more detailed mathematical expression and explanation of the ultra-wideband operation is presented. For noise analysis, C1 has been removed from the circuit and the noise contribution of Q1b has been neglected. The presence of L1 partially removes the input capacitance of the device, resulting in better input matching conditions and operation over a wider frequency range, as shown in the following equation.

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[0031] The inductor L4 is a parasitic capacitance (C gs , C for Q2B ds ) and provides matching between Q3 and Q2B. The inductor transforms the capacitive output impedance looking into the drain of Q2B to a lower impedance value, allowing a more effective flow of current between the two transistors.

[0032] g m2 / g m3 Since the ratio of (the gain of transistors 2 and 3) determines the gain of the sub-amplification provided by Q2 / Q3, the larger the size of the Q2 device, the higher the gain and the lower the device noise ratio due to the increased gain.

[0033] The output load is proportional to the impedance looking into the source follower Q3, which is inductive at low frequencies, so (Cgs The addition of capacitor C3 (in parallel with C1) contributes to the device bandwidth at low frequencies up to several gigahertz. To extend low frequency operation, the input and output DC blocking capacitors C1 and C4 should preferably be off-chip components to accommodate the size capacitance required for this frequency performance. The bypass capacitors as well as other matching networks can be realized in 45 nm SOI technology.

[0034] FIG. 10 is a graph showing gain 1005 and input return loss 1010 and output return loss 1015 for the embodiment shown in FIG. 9A over a wide range of frequencies shown extending from below 1 GHz to 40 GHz.

[0035] Figure 11 is a graph showing the noise figure 1105 for the embodiment shown in Figure 9A over the wide range of frequencies shown. While the noise figure for frequencies below 2 GHz is higher than that achieved for the remainder of the operating range, the circuit still provides significant gain and is operable at these lower frequencies.

[0036] FIG. 12 is a graph displaying simulated two-tone test results for third order distortion associated with the embodiment shown in FIG. 9A. The graph is a plot of a typical two-tone test. Two frequency signals, f1=30 GHz and f2=30.5 GHz, are injected into the input of the amplifier. The power of the signals f1 and f2 is increased and the power of the distortion products in the f1 signal, the f2 signal, 2f1-f2, and 2f2-f1 are measured at the output of the amplifier. The output third order intermodulation products (OIP3) are arrived at from the intersection of the extrapolated power line slopes 1205 and 1210. The linear slopes of 1205 and 1210 are 1 and 3, respectively. The 15 dBm prediction for OIP3 is very good for low power applications at MMW frequencies.

[0037] FIG. 13 is a schematic diagram of a low noise amplifier 1305 including a first stage 1310 with noise rejection and a further amplification stage 1315 suitable for providing additional gain over a wide range of frequencies. Stage 1310 is the same as amplifier 900 and therefore does not require additional discussion. Stage 1315 consists of cascode devices (Q4A and Q4B) and a source follower Q84 that provides a broadband match to a 50 ohm load. An active load Q5 for the cascode devices is utilized to reduce power consumption. Device Q4B improves the frequency stability of device Q4A over a wide frequency range by providing isolation for Q4A. A current mirror consisting of Q6 and Q7 provides bias for output device Q8 and part of the load for emitter follower Q8. The current mirror determines the current supplied to output device Q8 as controlled by bias resistor RB3. The low noise amplifier 1305 is suitable for use as a system-on-chip application, as an integrated microwave assembly, or as a standalone module such as in a communication receiver. Inductors L5 and L6 provide broadband impedance matching for Q4A and Q8, respectively.

[0038] Figure 14 is a graph showing gain 1405 and input return loss 1410 and output return loss 1415 for the embodiment shown in Figure 13. Note that the gain is substantially flat by only 20 dB or more from below 0.5 GHz to 50 GHz, i.e., the substantially flat gain does not vary by more than 2 dB over the frequency range.

[0039] FIG. 15 is a graph showing the noise figure 1505 for the embodiment shown in FIG. 13 over the wide range of frequencies shown. From 1 GHz to 50 GHz, the noise figure is below 2 dB, and from 3 GHz to 50 GHz, the noise figure remains below 1.6 dB. Note that the noise figure is higher below about 3 GHz, but the amplifier still functions and provides the same gain at the lower frequencies as at the higher frequencies in the range. Thus, even at these lower frequencies, it is suitable for operation for many applications.

[0040] FIG. 16 is a graph displaying the results of a simulated two-tone test for third-order distortion associated with the embodiment shown in FIG. 13. The graph is a plot of a typical two-tone test. Two frequency signals, f1=30 GHz and f2=30.5 GHz, are injected into the input of the amplifier. The power of the signals f1 and f2 is increased and the power of the distortion products in the f1 signal, the f2 signal, 2f1-f2, and 2f2-f1 are measured at the output of the amplifier. An output third-order intermodulation product (OIP3) of about 2 dBm was achieved from the intersection of the extrapolated power line slopes 1605 and 1610. The linear slopes of 1605 and 1610 are 1 and 3, respectively. A predicted IIP3 value of about -18 dBm is expected in view of the high gain. Linearity can be improved by increasing the size of the output stage device and linearity enhancement techniques.

[0041] While exemplary embodiments of the present invention have been shown and described in detail herein, it will be apparent to those skilled in the art that various modifications, additions, substitutions, and the like may be made without departing from the spirit of the invention. For example, all components of the exemplary embodiments are contemplated as being incorporated in a CMOS SOI substrate (except as specifically noted), although other semiconductor technologies may be used for implementations addressing similar or different operating frequencies.

Claims

1. A low noise amplifier circuit having a plurality of CMOS transistors forming an amplifier, an auxiliary amplifier, and a summing circuit, and a noise rejection circuit forming a feedback circuit and connected to the plurality of CMOS transistors, housed on a silicon on insulator substrate, and configured to operate over a frequency range of 0.5 GHz to 50 GHz, the amplifier uses one or more of the CMOS transistors to amplify a first signal and a first noise signal coupled to the input of the amplifier and generate corresponding amplified second signals and second noise signals at the output of the amplifier, respectively, the amplified second signal being 180 degrees out of phase with respect to the phase of the first signal, the amplified second noise signal having the same phase as the first noise signal, the first signal having a frequency in the range of 0.5 GHz to 50 GHz; the feedback circuit coupled to the amplifier controls an amount of amplification of the second signal and the second noise signal provided by the amplifier, the feedback circuit having a non-linear gain factor with respect to frequency, the gain factor increasing a gain applied to the amplifier with increasing frequency in the frequency range, the increase in the gain factor compensating for a decrease in gain applied to the amplifier with increasing frequency due to an internal capacitance associated with the amplifier to provide a constant amount of amplification of the second signal and the second noise signal across the frequency range; the auxiliary amplifier using one or more of the CMOS transistors is connected to the amplifier and receives the first signal and the first noise signal at an auxiliary input from the amplifier and produces at an auxiliary output a third signal which is an amplified version of the first signal and a fourth signal which is an amplified version of the first noise signal, the third signal and the fourth signal having a phase of 180 degrees relative to the phase of the first signal and the first noise signal, respectively, and an amount of amplification provided by the auxiliary amplifier is equal to an amount of amplification provided by the amplifier; the summing circuit is connected to the amplifier and the auxiliary amplifier, receives the second signal, the second noise signal, the third signal, and the fourth signal from the amplifier and the auxiliary amplifier, generates a resultant signal at a summing output, and transmits the resultant signal to the feedback circuit, the resultant signal including a first summation of the second signal and the third signal and a second summation of the second noise signal and the fourth signal, the second summation resulting in the cancellation of the second noise signal and the fourth signal because the second noise signal and the fourth signal are equal in amplitude but have 180 degree opposite phase; The CMOS transistors of the amplifier, the auxiliary amplifier, and the summing circuit and the feedback circuit are disposed on a single silicon on insulator substrate. Low noise amplifier circuit.

2. the resulting signal has an associated noise figure of less than 2 decibels from 20 GHz to 50 GHz and less than 1.6 dB from 3 GHz to 50 GHz; 2. The low noise amplifier circuit of claim 1.

3. the feedback circuit is connected between the drain and the gate of the amplifier; The auxiliary amplifier has an unloaded gain equal to the gain provided by the amplifier for the second noise signal.

2. The low noise amplifier circuit of claim 1.

4. the amplifier includes at least two CMOS transistors connected in cascode with their respective drains connected together as the output of the amplifier; the summing circuit includes at least one CMOS transistor; the auxiliary amplifier includes at least two CMOS transistors connected in cascode with each other and including one CMOS transistor connected in cascode with the at least one CMOS transistor of the summing circuit; A cascode current source having a high output impedance is connected to a node between the source of the at least one CMOS transistor and the drain of the one CMOS transistor in order to inject a current into one of the cascode-connected transistors of the auxiliary amplifier, and is configured such that the injected current flows through the at least two cascode-connected CMOS transistors but does not flow through the at least one CMOS transistor of the adder circuit.

2. The low noise amplifier circuit of claim 1.

5. a frequency matching network connected to the input of the amplifier and including at least one capacitor and an inductor configured to enhance impedance stability across the frequency range.

2. The low noise amplifier circuit of claim 1.

6. a high pass filter coupled to the summing circuit for high pass filtering the second signal and the second noise signal prior to receipt of the second signal and the second noise signal by the summing circuit.

2. The low noise amplifier circuit of claim 1.

7. and at least one inductor connected in the auxiliary amplifier between a source of one transistor and a drain of the other transistor and configured to provide feedback to stabilize impedance over the frequency range by compensating for internal capacitance associated with one or more transistors of the auxiliary amplifier.

2. The low noise amplifier circuit of claim 1.

8. 2. The low noise amplifier circuit of claim 1, wherein the feedback circuit includes at least one inductor in series with at least a first resistor.

9. 9. The low noise amplifier circuit of claim 8, wherein the feedback circuit includes a second resistor in parallel with at least one of the inductors.

10. 10. The low noise amplifier circuit of claim 9, wherein the second resistor and at least one of the inductors are each coupled to an output of the amplifier, and one terminal of the first resistor is coupled to the input of the amplifier.

11. 2. The low noise amplifier circuit of claim 1, further comprising a secondary amplification stage coupled to the summed output, the secondary amplification stage providing additional amplification at a final output.

12. 12. The low noise amplifier circuit of claim 11, wherein the amplifier, feedback circuit, auxiliary amplifier, summing circuit, and the secondary amplification stage are all formed as part of a single integrated silicon on insulator substrate utilizing 45 nm 12 SOI.

13. 12. The low noise amplifier circuit of claim 11, wherein the secondary amplification stage includes a cascode circuit having an input receiving the result signal from the summed output, the cascode circuit having a first CMOS device having a common source configuration coupled to a second CMOS device having a common gate configuration, the input of the cascode circuit being coupled to a gate of the first CMOS device, and the output from the cascode circuit being the drain of the second CMOS device.

14. 14. The low noise amplifier circuit of claim 13, further comprising a third CMOS device configured as a source follower, the gate of the third CMOS device coupled to the output from the cascode circuit, and the source of the third CMOS device further coupling the amplified signal to a load.

15. 15. The low noise amplifier circuit of claim 14, further comprising two CMOS devices coupled in a current mirror configuration with one of the two CMOS devices coupled to the source of the third CMOS device and establishing a bias for the third CMOS device.

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