Barrier layer for electrical contact area

Abstract

The power switching device includes a semiconductor layer structure having an active area and a non-active area, the active area comprising a plurality of unit cells, and the non-active area comprising a gate pad on the semiconductor layer structure and a gate bond pad on and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bond pad, and a barrier layer between the gate pad and the isolation layer.

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 16 / 863,642, filed April 30, 2020, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to semiconductor devices, and more particularly to power semiconductor switching devices. [Background technology]

[0003] A metal oxide semiconductor field effect transistor ("MOSFET") is a well-known type of semiconductor transistor that can be used as a switching device. A MOSFET is a three-terminal device that includes source and drain regions separated by a channel region, and a gate electrode disposed adjacent to the channel region. A MOSFET can be turned on or off by applying a gate bias voltage to the gate electrode. When a MOSFET is turned on (i.e., the MOSFET is in its "on-state"), current conducts between the source and drain regions through the MOSFET's channel region. When the bias voltage is removed from the gate electrode (or reduced below a threshold level), current stops conducting through the channel region. By way of example, an n-type MOSFET has n-type source and drain regions and a p-type channel. An n-type MOSFET therefore has an "npn" design. An n-type MOSFET turns on when a gate bias voltage is applied to the gate electrode that is sufficient to create a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and drain regions, thereby allowing bulk carrier conduction between the source and drain regions.

[0004] The gate electrode of a power MOSFET is typically separated from the channel region by a thin gate insulation pattern, such as a silicon oxide pattern. Because the gate electrode of a MOSFET is insulated from the channel region by the gate insulation pattern, a minimum gate current is required to maintain the MOSFET in its on state or to switch the MOSFET between its on state and its off state. The gate current is kept small during switching because the gate forms a capacitor with the channel region. Therefore, only minimal charge and discharge currents are required during switching, allowing for uncomplicated gate drive circuitry.

[0005] A bipolar junction transistor ("BJT") is another well-known type of semiconductor transistor that is also routinely used as a switching device. A BJT contains two pn junctions formed in close proximity to one another in a semiconductor material. In operation, charge carriers enter a first region (the emitter) of the semiconductor material adjacent to one of the pn junctions. Most of the charge carriers exit the device from a second region (the collector) of the semiconductor material adjacent to the other pn junction. The collector and emitter are formed in regions of semiconductor material that have the same conductivity type. A relatively thin third region of semiconductor material, known as the base, is positioned between the collector and emitter and has an opposite conductivity type to that of the collector and emitter. Thus, the two pn junctions of a BJT are formed where the collector meets the base and where the base meets the emitter. By passing a small current through the base of a BJT, a proportionally larger current passes from the emitter to the collector.

[0006] A BJT is a current-controlled device in that the BJT is "turned on" (i.e., biased so that current flows between the emitter and collector) by passing a current through the base of the transistor. For example, in an np-n BJT (i.e., a BJT having n-type collector and emitter regions and a p-type base region), the transistor is typically turned on by applying a positive voltage to the base to forward bias the base-emitter pn junction. When the device is so biased, hole current flowing into the base of the transistor is injected into the emitter. The holes are called the "majority carriers" because the base is a p-type region and holes are the "normal" charge carriers in such a region. In response to the hole current into the emitter, electrons are injected from the emitter into the base, where they diffuse towards the collector. These electrons are called the "minority carriers". This is because electrons are not the normal charge carriers in the p-type base region, and the device is called a "bipolar" device because the emitter-collector current contains both electron and hole current.

[0007] BJTs may require relatively large currents to maintain the device in its on state. Therefore, relatively complex external drive circuitry may be required to supply the relatively large base currents that high power BJTs can demand. Furthermore, the switching speed of BJTs can be significantly slower than that of power MOSFETs due to the bipolar nature of current conduction.

[0008] A third well-known type of semiconductor switching device is the insulated gate bipolar transistor (IGBT), which combines the high impedance gate of a power MOSFET with the low on-state conduction losses of a power BJT. An IGBT can be implemented, for example, as a Darlington pair containing a high voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, thereby allowing for simplified external drive circuitry.

[0009] There is an increasing demand for high power semiconductor switching devices, which can carry large currents in their "on" state and block large voltages (e.g., hundreds or even thousands of volts) in their reverse blocking state. To sustain high current densities and block such high voltages, power MOSFETs and IGBTs typically have vertical structures with sources and drains on opposing sides of a thick semiconductor layer structure to block higher voltage levels. In very high power applications, semiconductor switching devices are typically formed using wide band-gap semiconductor material systems (herein, the term "wide band-gap semiconductor" encompasses any semiconductor with a band gap of at least 1.4 eV), such as silicon carbide ("SiC"), which has several advantageous properties including, for example, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. For example, electronic devices formed using silicon carbide may be capable of operating at higher temperatures, higher power densities, higher speeds, higher power levels, and / or higher radiation densities compared to devices formed using other semiconductor materials, such as silicon. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] U.S. Patent Application Serial No. 15 / 699,149 Summary of the Invention [Means for solving the problem]

[0011] According to some embodiments of the present invention, a semiconductor device includes a semiconductor layer structure having an active area and a non-active area, the active area comprising a plurality of unit cells, the non-active area comprising a gate pad on the semiconductor layer structure and a gate bond pad on the gate pad and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bond pad, and a barrier layer between the gate pad and the isolation layer.

[0012] In some embodiments, the barrier layer is a first barrier layer and the semiconductor device further includes a second barrier layer over the gate pad and over the first barrier layer.

[0013] In some embodiments, at least a portion of the separation layer is between the first barrier layer and the second barrier layer.

[0014] In some embodiments, the barrier layer comprises multiple layers.

[0015] In some embodiments, the barrier layer comprises titanium (Ti) and / or tantalum (Ta).

[0016] In some embodiments, the barrier layer is a first barrier layer and the semiconductor device includes a gate finger over the active area and electrically connected to the gate bond pad, a second barrier layer over the gate finger, and Further includes:

[0017] In some embodiments, the second barrier layer is on the top surface and sidewalls of the gate fingers.

[0018] In some embodiments, the barrier layer is a first barrier layer and the semiconductor device comprises a source contact on the semiconductor layer structure, a second barrier layer on sidewalls and a bottom surface of the source contact, and a third barrier layer between the semiconductor layer structure and the second barrier layer. Further includes:

[0019] According to some embodiments of the present invention, a semiconductor device includes a semiconductor substrate, a gate pad on the semiconductor substrate, a gate bond pad on and electrically connected to the gate pad, a first barrier layer between the gate pad and a bottom portion of the gate bond pad in a first direction perpendicular to a top surface of the semiconductor substrate, and a second barrier layer between the gate pad and the first barrier layer in the first direction.

[0020] In some embodiments, the second barrier layer has a width in a second direction parallel to the top surface of the semiconductor substrate that exceeds a width of a portion of the first barrier layer between the second barrier layer and a bottom portion of the gate bond pad.

[0021] In some embodiments, the thickness of the second barrier layer is substantially uniform along the width of the second barrier layer in the second direction.

[0022] In some embodiments, the gate bond pad is coupled to the gate pad through a contact hole having opposing sidewalls, a portion of the first barrier layer is on the opposing sidewalls of the contact hole, and a width of the second barrier layer in a second direction parallel to the top surface of the semiconductor substrate is greater than a width of the contact hole in the second direction.

[0023] In some embodiments, the semiconductor device further includes an isolation layer, a portion of the isolation layer being between the second barrier layer and the gate bond pad.

[0024] In some embodiments, the second barrier layer comprises multiple layers.

[0025] In some embodiments, the second barrier layer comprises titanium (Ti) and / or tantalum (Ta).

[0026] In some embodiments, the second barrier layer is on the top surface and sidewalls of the gate pad.

[0027] In some embodiments, the material of the second barrier layer is different from the material of the first barrier layer.

[0028] In some embodiments, the semiconductor device further includes a semiconductor layer structure having an active area and a non-active area, the gate pad being on the non-active area, a gate finger on the active area and electrically connected to the gate pad, and a third barrier layer on the gate finger.

[0029] In some embodiments, the third barrier layer is on the top surface and sidewalls of the gate fingers.

[0030] According to some embodiments of the invention, a semiconductor device includes a semiconductor substrate, a gate pad on the semiconductor substrate, an isolation layer on the gate pad, a first barrier layer on the isolation layer and the gate pad, and a second barrier layer between the gate pad and the first barrier layer in a first direction, the second barrier layer having a width in the second direction that exceeds the width of the first barrier layer in the second direction.

[0031] In some embodiments, the semiconductor device further includes a gate bond pad overlying the gate pad and electrically connected to the gate pad through a contact hole in the isolation layer having opposing sidewalls, the first barrier layer having a first portion extending in a second direction between the opposing sidewalls of the contact hole, and a width of the second barrier layer in the second direction exceeds a width of the first portion of the first barrier layer in the second direction.

[0032] In some embodiments, a portion of the isolation layer is between the second barrier layer and the gate bond pad.

[0033] In some embodiments, the separation layer is on the top surface of the second barrier layer and on the sidewalls of the first barrier layer.

[0034] According to some embodiments of the present invention, a semiconductor device includes a semiconductor layer structure and a plurality of unit cell transistors electrically connected in parallel, each unit cell transistor having a gate finger extending in a first direction on a top surface of the semiconductor layer structure, the gate fingers being spaced apart from one another along a second direction; and an auxiliary gate electrode barrier layer on an upper surface of each of the gate fingers. Includes.

[0035] In some embodiments, the gate fingers comprise polysilicon.

[0036] In some embodiments, the auxiliary gate electrode barrier layer comprises titanium (Ti) and / or tantalum (Ta).

[0037] In some embodiments, an auxiliary gate electrode barrier layer is also on opposing sidewalls of each of the gate fingers.

[0038] In some embodiments, the semiconductor layer structure comprises a non-active area and an active area, the active area comprising a plurality of unit cell transistors, the non-active area comprising a gate pad on the semiconductor layer structure, a gate bond pad on the gate pad and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bond pad, an auxiliary gate pad barrier layer between the gate pad and the isolation layer, and Includes.

[0039] In some embodiments, an auxiliary gate pad barrier layer is on the top surface and sidewalls of the gate pad.

[0040] In some embodiments, the semiconductor device further includes a gate pad barrier layer between the auxiliary gate pad barrier layer and the gate bond pad.

[0041] In some embodiments, the auxiliary gate electrode barrier layer comprises multiple layers.

[0042] In some embodiments, the semiconductor device comprises a source contact on the semiconductor layer structure, a source barrier layer on sidewalls and a bottom surface of the source contact, and an auxiliary source barrier layer between the semiconductor layer structure and the source barrier layer. Further includes:

[0043] In some embodiments, the semiconductor device further comprises an isolation layer on the gate fingers, the auxiliary gate electrode barrier layer being between the isolation layer and the gate fingers. [Brief description of the drawings]

[0044] [Figure 1] 1 is a schematic plan view of a semiconductor wafer including a plurality of power switching devices according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a schematic plan view of one of the power switching devices contained on the semiconductor wafer of FIG. 1. [Figure 2B] FIG. 2B is a schematic plan view of the power switching device of FIG. 2A with source and gate metallization removed. [Figure 3A] FIG. 2C is a schematic cross-sectional view taken along line A-A' in FIG. 2B showing the unit cell structure in the active area and the gate pad in the non-active area of ​​a conventional device. [Figure 3B] FIG. 3B is a schematic cross-sectional view of portion A of FIG. 3A. [Figure 3C] FIG. 3B is a schematic cross-sectional view of portion B of FIG. 3A. [Figure 4A] FIG. 1 illustrates a semiconductor device according to some embodiments described herein. [Figure 4B]FIG. 4B is a schematic cross-sectional view of portion A of FIG. 4A. [Figure 4C] FIG. 2 illustrates a further semiconductor device according to some embodiments described herein. [Figure 5A] FIG. 2 illustrates a further semiconductor device according to some embodiments described herein. [Figure 5B] FIG. 2 illustrates a further semiconductor device according to some embodiments described herein. [Figure 6A] FIG. 2 illustrates a further semiconductor device according to some embodiments described herein. [Figure 6B] FIG. 6B is a schematic cross-sectional view of portion B of FIG. 6A. [Figure 6C] FIG. 2 illustrates a further semiconductor device according to some embodiments described herein. [Figure 6D] FIG. 2 illustrates a further semiconductor device according to some embodiments described herein. [Figure 6E] FIG. 2 illustrates a further semiconductor device according to some embodiments described herein. [Figure 7] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 8] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 9A] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 9B] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 9C] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 9D] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 10] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 11]1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. [Figure 12] 1 illustrates a method of manufacturing a semiconductor device according to some embodiments described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] Power silicon carbide MOSFETs are used today for applications requiring high voltage blocking, such as blocking voltages of 5,000 volts or more. By way of example, 10 A / cm MOSFETs will block voltages of at least 10 kV. 2 Silicon carbide MOSFETs with current density ratings of 1000 MHz or more are commercially available. To form such devices, a number of "unit cells" are typically formed, with each unit cell containing a MOSFET transistor. In high power applications, a large number (e.g., hundreds or thousands) of these unit cells are typically provided on a single semiconductor substrate, and a gate electrode pattern is formed on a top side of the semiconductor substrate that serves as the gate electrode for all of the unit cells. The opposing (bottom) side of the semiconductor substrate serves as a common drain for all of the device's unit cells. A number of source contacts are formed on source regions in the semiconductor layer structure and exposed in openings in the gate electrode pattern. These source contacts are in turn electrically connected to each other to serve as a common source. The resulting device has three terminals, a common source terminal, a common drain terminal, and a common gate electrode that serve as terminals for hundreds or thousands of individual unit cell transistors. It will be appreciated that the above description is for an n-type MOSFET and that the locations of the drain and source would be reversed for a p-type MOSFET.

[0046] A gate electrode pattern for a power MOSFET can be implemented by forming a patterned conductive layer that includes a number of elongated gate fingers that extend through the active area of ​​the device. The patterned conductive layer can comprise a semiconductor layer, such as a polysilicon layer and / or doped silicon (Si). The patterned conductive layer can also include a gate pad in the non-active area of ​​the device, and each gate finger can be connected to the gate pad either directly or by one or more gate buses and / or conductive vias.

[0047] This disclosure describes an approach to improve diffusion barrier protection between device layers and metallization layers while simultaneously modifying the conductivity and adhesion between the layers, which can be particularly useful for improving the gate contact region in power transistors (e.g., MOSFETs or IGBTs).

[0048] The embodiments described herein may add a material layer (e.g., TiN, other metal nitrides, and / or intermetallics) on top of a conductive layer, such as a gate pad and / or gate electrode (typically doped Si or silicide materials), source contact, and / or other layers requiring further contact, such as current or temperature sensing devices in a power device. The material layer may have properties of a diffusion barrier, enhanced conduction layer, and / or adhesion layer to the contact regions (insulating and / or conductive layers) above the material layer.

[0049] Metals, such as those used in metal layers, typically have large amounts of impurities that can adversely affect the semiconductor or metal-insulator-semiconductor interface, and therefore improved barrier performance can be useful for semiconductor devices.

[0050] Aspects of the present invention will now be discussed in more detail with reference to the accompanying drawings, in which example embodiments of the invention are shown.

[0051] FIG. 1 is a schematic plan view of a wafer 10 including a plurality of power switching devices, according to an embodiment of the present invention. Referring to FIG. 1, the wafer 10 can be a thin planar structure including a semiconductor layer structure having an insulating layer and / or other material layers, such as a metal layer formed on the insulating layer. The semiconductor layer structure can include a semiconductor substrate and / or multiple other semiconductor layers. A plurality of power switching devices 100 can be formed using the wafer 10. The switching devices 100 can be formed in rows and columns and spaced apart from one another so that the wafer 10 can later be singulated (e.g., diced) to separate the individual switching devices 100 for packaging and testing. The wafer 10 can, in some embodiments, include a silicon carbide substrate on which one or more silicon carbide layers are formed (e.g., by epitaxial growth). Other semiconductor layers (e.g., polysilicon layers), insulating layers, and / or metal layers can be formed on the silicon carbide semiconductor layer structure to form the power switching devices 100. The silicon carbide substrate and the silicon carbide layer formed thereon may be 4H silicon carbide in some embodiments.

[0052] Figure 2A is a schematic plan view of one of the power switching devices 100 contained on the semiconductor wafer 10 of Figure 1. Figure 2B is a schematic plan view of the power switching device 100 of Figure 2A with the source and gate metallization removed. In the following description, it is assumed that the power switching device 100 is an n-type power MOSFET 100.

[0053] As shown in FIG. 2A, a protective layer 110 covers a substantial portion of the top surface of the power MOSFET 100. The protective layer 110 may be formed of, for example, polyamide. Various bond pads may be exposed through openings 112 in the protective layer 110. The bond pads may include a gate bond pad 120 and one or more source bond pads 122. The configurations, shapes, and structures of the gate bond pad 120 and the source bond pad 122 shown in FIG. 2A are merely illustrative, and the embodiments described herein are not limited thereto. Two source bond pads 122-1, 122-2 are shown in FIG. 2A. Although not visible in FIG. 2A, a drain contact and / or bond pad 124 may be provided on the bottom side of the MOSFET 100. The bond pads 120, 122, 124 may be formed of a metal, such as aluminum, to which bond wires may be readily attached by conventional techniques, such as thermocompression or soldering. As discussed in more detail below, source contacts are provided that connect to the semiconductor layer structure of the MOSFET 100. The source contacts may be lower portions of a source metal pattern 123 that extends across most of the upper surface of the MOSFET 100 (e.g., all but the portion of the lower surface of the MOSFET 100 occupied by the gate bond pad 120). The source bond pads 122-1, 122-2 may constitute portions of the source metal pattern 123 that are exposed by the opening 112 in the protective layer 110. Bond wires 20 are shown in FIG. 2A that may be used to connect the gate bond pad 120 and the source bond pads 122-1, 122-2 to an external voltage source (not shown), such as terminals of other circuit elements.

[0054] As shown in Figure 2B, MOSFET 100 includes a semiconductor layer structure including active region 102 and non-active region 104. Active region 102 is the area of ​​the device that contains operational transistors (e.g., unit cell transistors as discussed herein), while non-active region 104 is the area that does not contain such operational transistors. Unit cell transistors 200 of MOSFET 100 are formed within active region 102. The location of one unit cell 200 is indicated by box 200 in Figure 2B to provide context.

[0055] The active area 102, in some embodiments, may generally correspond to the area under the source metal pattern 123. The non-active area 104 includes a gate pad portion 106 and a termination portion 108. The gate pad portion 106 of the non-active area 104 may generally correspond to the portion of the semiconductor layer structure under the gate pad 132. The termination portion 108 of the non-active area 104 may extend around the periphery of the MOSFET 100 and may include one or more termination structures, such as a guard ring and / or a junction termination extension, which may reduce electric field crowding that may occur around the edge of the device. The termination structures (shown as guard ring 109) may distribute the electric field along the periphery of the MOSFET 100, reducing electric field crowding. The edge termination structure can help increase the reverse blocking voltage at which a phenomenon known as "avalanche breakdown" occurs, in which an increase in electric field leads to runaway generation of charge carriers within a semiconductor device, resulting in a sudden increase in current that can damage or even destroy the device.

[0056] As further shown in FIG. 2B , a gate electrode pattern 130 may be provided, including a gate pad 132, a number of gate fingers 134, and one or more gate buses 136 electrically connecting the gate fingers 134 to the gate pad 132. The gate pad 132 of the gate electrode pattern 130 may underlie the gate bond pad 120 in the gate pad portion 106 of the non-active area 104, and the gate fingers 134 may extend (e.g., horizontally) across the active area 102. An insulating layer (not shown) may cover the gate fingers 134 and the gate bus(es) 136. A source metal pattern 123 may be provided over the gate fingers 134 and the insulating layer, with source contacts of the source metal layer contacting corresponding source regions in the semiconductor layer structure in openings between the gate fingers 134.

[0057] Figure 3A is a schematic cross-sectional view taken along line A-A' in Figure 2B showing a unit cell structure in the active area and a gate pad in the non-active area of ​​a conventional device. Figure 3B is a schematic cross-sectional view of portion A in Figure 3A. Figure 3C is a schematic cross-sectional view of portion B in Figure 3A.

[0058] 3A, the MOSFET device 100 may include a unit cell 200 that is a portion of the active area 102 of the MOSFET 100. The unit cell 200 may be one of a plurality of unit cells 200 that are electrically arranged in parallel.

[0059] The power MOSFET 100, and thus the unit cell 200, may include an n-type wide bandgap semiconductor substrate 210. The substrate 210 may comprise, for example, a single crystal 4H silicon carbide semiconductor substrate. The substrate 210 may be heavily doped with n-type impurities (i.e., n + The impurities may include, for example, nitrogen or phosphorus. The doping concentration of the substrate 210 may be, for example, 1×1018 atoms / cm 3 and 1×10 21 atoms / cm 3 , although other doping concentrations can be used. Substrate 210 can be of any suitable thickness (e.g., between 100 microns and 500 microns thick).

[0060] Lightly doped (n - 2.) An n-type silicon carbide drift region 220 may be provided on the substrate 210. The n-type silicon carbide drift region 220 may be formed, for example, by epitaxial growth on the silicon carbide substrate 210. The n-type silicon carbide drift region 220 may have a density of, for example, 1×10 16 ~5×10 17 Dopant / cm 3 The n-type silicon carbide drift region 220 may have a doping concentration of 100 μm to 300 μm. The n-type silicon carbide drift region 220 may be a thick region, for example having a vertical height above the substrate 210 of 3 to 100 μm. The upper portion of the n-type silicon carbide drift region 220 may, in some embodiments, comprise an n-type silicon carbide current spreading layer that is more highly doped than the lower portion of the n-type silicon carbide drift region 220.

[0061] The upper portion of the n-type silicon carbide drift region 220 can be doped p-type by ion implantation to form a p-well 240. The p-well 240 can be doped p-type by, for example, 5×10 16 / cm 3 and 5×10 19 / cm 3 The upper portion 242 of each p-well 240 may have a doping concentration between 2×10 18 / cm 3 and 1×10 20 / cm 3The p-well 240 (including its more heavily doped upper portion 242) can be formed by ion implantation. As known to those skilled in the art, ions such as n-type or p-type dopants can be implanted into a semiconductor layer or region by ionizing a desired ion species in an ion implantation target chamber and accelerating the ions with a predetermined kinetic energy as an ion beam toward the surface of the semiconductor layer. Based on the predetermined kinetic energy, the desired ion species can penetrate into the semiconductor layer to a particular depth.

[0062] In the active region 102, a heavily doped (n + A highly doped (n) silicon carbide source region 250 may be formed in an upper portion of the p-well 240 directly adjacent to and in contact with the more highly doped portion 242 of the p-well 240. The n-type source region 250 may also be formed by ion implantation. + ) N-type silicon carbide region 250 serves as a source region for unit cell transistor 200. Drift region 220 and substrate 210 together serve as a common drain region for unit cell transistor 200.

[0063] The n-type silicon carbide substrate 210 , the n-type silicon carbide drift region 220 , the p-wells 240 , 242 , and the n-type source region 250 formed within the p-well together may comprise the semiconductor layer structure of the MOSFET device 100 .

[0064] A gate insulation pattern 260 may be formed on the upper surface of the semiconductor layer structure, covering exposed portions of the drift region 220 between the p-well 240 and the n-type source region 250, and extending over the edges of the p-well 240 and the edges of the n-type source region 250. The gate insulation pattern 260 may comprise, for example, a silicon oxide layer, although other insulation materials may be used. A gate finger 134 is formed on the gate insulation pattern 260. It will be appreciated that the gate finger 134 may be part of a continuous gate electrode pattern 130 (see FIG. 2B ) that includes the gate pad 132, the plurality of gate fingers 134, and one or more gate buses 136. In some embodiments, the gate electrode pattern 130 may comprise, for example, a semiconductor pattern (e.g., polysilicon) and / or a metal gate pattern.

[0065] A source contact 280 may be formed on the n-type source region 250 and the more heavily doped portion 242 of the p-well. As described above with reference to Figures 2A-2B, the source contact 280 may be part of a continuous source metal pattern 123 that extends across the upper surface of the silicon carbide semiconductor layer structure. The remaining portions of the source metal pattern 123 (as well as an insulating layer electrically isolating the gate fingers 270 from the source metal pattern 123) are not shown in Figure 3A to simplify the drawing. The source contact 280 may comprise a metal, such as, for example, nickel, titanium, tungsten, or aluminum, or an alloy or thin layer stack of these or similar materials. As described above, the drain contact 124 may be formed on the lower surface of the substrate 210. The drain contact 124 may comprise, for example, a similar material as the source contact 280 to form an ohmic contact to the silicon carbide substrate. When a voltage is applied to gate finger 134 , current can flow from n-type source region 250 through drift region 220 beneath gate finger 134 .

[0066] Although MOSFET 100 is illustrated as an n-type device with source contact 280 on its upper surface and drain contact 124 on its lower surface, it will be recognized that in a p-type device, these locations are reversed. Thus, in certain parts of the following description (including the claims), source contacts and drain contacts may refer generally to source contacts or drain contacts.

[0067] As shown in FIG. 3A, in the gate pad portion 106 of the non-active area, the p-well 244 extends under most or all of the gate pad portion 106 of the non-active area. The p-well 244 may extend a significant distance in each horizontal direction under the gate pad portion 106, for example, a distance of 100-300 microns in each direction. A field insulation layer 264 is formed over the p-well 244 in the gate pad portion 106 of the non-active area 104. In some embodiments, the field insulation layer 264 may have a thickness in the vertical direction (i.e., perpendicular to the major surface of the substrate 210), for example, of 600-800 nanometers. The gate pad 132 is formed over the field insulation layer 264. As discussed above with reference to FIG. 2B, the gate pad 132 and the gate fingers 134 may be part of a continuous gate electrode pattern 130.

[0068] In some embodiments, the further source contact 284 penetrates the field isolation layer 264 to contact the p-well 244. The further source contact 284 can help manage the displacement current of the MOSFET device 100, as discussed in U.S. patent application Ser. No. 15 / 699,149 to Zhang et al., entitled “Power Switching Devices with DV / DT Capability and Methods of Making Such Devices,” filed Sep. 8, 2017, the entire contents of which are incorporated herein by reference. In some embodiments, the further source contact 284 can be omitted.

[0069] An isolation layer 230 may be formed on the gate fingers 134 and / or the gate pad 132. The isolation layer 230 may serve to isolate the gate electrode pattern 130 (including the gate fingers 134 and the gate pad 132) from the source metal pattern 123 (including the source contact 280 and the further source contact 284).

[0070] The gate barrier layer 310 can be disposed between the gate bond pad 120 and the gate pad 132. The gate barrier layer 310 can serve as a metallization barrier layer and / or an adhesion layer. Similarly, the source barrier layer 320 can be disposed between the source contact 280 and the source / drain region 250 and / or between the further source contact 284 and the p-well 244. The gate barrier layer 310 and / or the source barrier layer 320 can reduce and / or prevent diffusion from the respective contacts into the underlying material over which the barrier layer is disposed. For example, the gate barrier layer 310 can reduce diffusion of metallic material from the metal of the gate bond pad 120 into the polysilicon of the gate pad 132. Elements that diffuse into the polysilicon can further diffuse into the gate oxide and / or active area, impairing the performance of the MOSFET device 100.

[0071] 3B and 3C, in a conventional device, the gate contact and / or source contact are formed by etching a portion of the device (e.g., isolation layer 230) to form a contact hole 375. A barrier layer (e.g., gate barrier layer 310 and / or source barrier layer 320) can be formed in the contact hole 375. Metal for the contact can then be formed on the barrier layer. However, due to step coverage associated with the formation of the barrier layer, the corners of the contact hole 375 may have insufficient coverage. For example, referring to FIG. 3B, a region 385 of the gate barrier layer 310 may be thin between the gate bond pad 120 and the gate pad 132 at the corners of the contact hole 375. Similarly, referring to FIG. 3C, a region 386 of the source barrier layer 320 may be thin between the source contact 280 and the source region 250 at the corner regions of the contact hole 375. Due to the thickness of the corner regions 385 , 386 of the source and gate contact holes 375 , the conventional device may be susceptible to diffusion from the gate bond pad 120 and / or source contact 280 metal layers.

[0072] FIG. 4A illustrates a semiconductor device 400 according to some embodiments described herein. FIG. 4B illustrates a schematic cross-sectional view of portion A of FIG. 4A. FIG. 4C illustrates a further semiconductor device 400' according to some embodiments described herein. Descriptions of elements in FIG. 4A-4C that are the same as or similar to elements in FIG. 3A-3C are omitted for brevity. Thus, the description of FIG. 4A-4C focuses on the differences with respect to the devices described above.

[0073] 4A and 4B, a MOSFET device 400 according to some embodiments described herein may include additional barrier layers compared to conventional devices. For example, the MOSFET device 400 may include an auxiliary gate pad barrier layer 410 and an auxiliary gate electrode barrier layer 420.

[0074] The auxiliary gate pad barrier layer 410 may be formed on the gate pad 132, and may be on the upper surface 132a of the gate pad 132, and in some embodiments may cover the upper surface 132a. In FIG. 4B, the auxiliary gate pad barrier layer 410 is shown with separate shading to aid in distinguishing the auxiliary gate pad barrier layer 410 from the gate barrier layer 310, but this separate shading is not intended to limit the configuration of the auxiliary gate pad barrier layer 410 or the gate barrier layer 310. The auxiliary gate pad barrier layer 410 may be provided in addition to the gate barrier layer 310. As a result, a barrier layer will be present above (e.g., in the form of the gate barrier layer 310) and below (e.g., in the form of the auxiliary gate pad barrier layer 410) the isolation layer 230 that separates the device from the gate bond pad 120. In some embodiments, the gate barrier layer 310 may be on and / or in contact with the auxiliary gate pad barrier layer 410 in the portion of the MOSFET device 400 that is between the gate bond pad 120 and the gate pad 132 (e.g., vertically). In some embodiments, the isolation layer 230 may be between the auxiliary gate pad barrier layer 410 and the gate barrier layer 310 and / or the gate bond pad 120. In some embodiments, the isolation layer 230 may be on a top surface of a portion of the auxiliary gate pad barrier layer 410 and on the sidewalls of the gate barrier layer 310.

[0075] The presence of the auxiliary gate pad barrier layer 410 can improve barrier layer coverage in the bottom corner region 385 between the gate bond pad 120 and the gate pad 132. For example, the auxiliary gate pad barrier layer 410 can have a width in a direction parallel to the top surface of the substrate 210 (e.g., horizontally) that exceeds the width of the portion of the gate barrier layer 310 between the auxiliary gate pad barrier layer 410 and the bottom portion of the gate bond pad 120 (e.g., the portion of the gate barrier layer 310 that extends between the sidewalls of the contact hole connecting the gate bond pad 120 to the gate pad 132). Thus, even if the deposition of the gate barrier layer 310 in the bottom corner region 385 is not ideal, the layer below (here, the gate pad 132) can be protected from any elements in the contact metallurgy.

[0076] An auxiliary gate electrode barrier layer 420 may also be provided on the gate fingers 134 in the active area 102 of the MOSFET device 400. As with the auxiliary gate pad barrier layer 410, the auxiliary gate electrode barrier layer 420 may serve the purpose of a diffusion barrier for elements that may diffuse at the gate electrode interface with the material thereover, may improve layer conductivity, and / or may enhance adhesion of the gate fingers 134 to the dielectric layer above the gate fingers 134.

[0077] If the auxiliary gate electrode barrier layer 420 is present, a barrier layer will be present below (e.g., in the form of the auxiliary gate electrode barrier layer 420) and above (e.g., in the form of the source barrier layer 320) the isolation layer 230 that separates the gate finger 134 from the source metal pattern 123. In some embodiments, the auxiliary gate electrode barrier layer 420 may be between the upper surface 134a of the gate finger 134 and the isolation layer 230.

[0078] The auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can be applied in a variety of ways to produce a continuous or contiguous layer between 0.5 nm and 500 nm thick. In some embodiments, the thickness of the auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can be substantially uniform. The auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and other metal nitrides and / or intermetallic compounds including, for example, cobalt (Co), ruthenium (Ru), and the like. The auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can be a single layer (TiN, TaN, or similar material that has good thermodynamic stability and is electrically conductive) or a multi-layer stack of various elemental or compound materials in various stacking sequences. Thus, although Figures 4A-4B show single layers for the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420, the structures shown are also intended to show structures comprising multiple layers. In some embodiments, a conductive oxide can be used where adhesion to the dielectric layer is important. As will be appreciated by those skilled in the art, the materials used will depend on the process and application. The use of the auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can be applied as needed to improve diffusion barrier, conductivity, and / or adhesion properties.

[0079] In some embodiments, the materials and / or composition used for the auxiliary gate pad barrier layer 410 can be different from the materials and / or composition used for the auxiliary gate electrode barrier layer 420. In some embodiments, the materials and / or composition used for the auxiliary gate pad barrier layer 410 can be different from the materials and / or composition used for the gate barrier layer 310. In some embodiments, the materials and / or composition used for the auxiliary gate electrode barrier layer 420 can be different from the materials and / or composition used for the gate barrier layer 310.

[0080] In some embodiments, the auxiliary gate pad barrier layer 410 may be present and the auxiliary gate electrode barrier layer 420 may be omitted. For example, Figure 4C shows a MOSFET device 400' in which the auxiliary gate electrode barrier layer 420 is not present.

[0081] Figures 5A and 5B show further semiconductor devices according to some embodiments described herein. Descriptions of elements in Figures 5A and 5B that are the same as or similar to elements in figures described above will be omitted for brevity. Thus, the description of Figures 5A and 5B will focus on the differences with respect to these devices described above.

[0082] 5A, in a MOSFET device 500 according to some embodiments, the auxiliary gate pad barrier layer 410' extends over the top surface 132a and may extend over one or more side surfaces 132b of the gate pad 132. Thus, the auxiliary gate pad barrier layer 410' may extend uninterrupted over the top and side surfaces of the gate pad 132.

[0083] Similarly, the auxiliary gate electrode barrier layer 420' may extend onto one or more sidewalls 134b of the gate finger 134. Thus, the auxiliary gate electrode barrier layer 420' may extend uninterruptedly onto the top and side surfaces of the gate finger 134.

[0084] The use of the auxiliary gate pad barrier layer 410' and / or the auxiliary gate electrode barrier layer 420' can increase the diffusion barrier of the gate pad 132 and the gate fingers 134. Furthermore, the auxiliary gate pad barrier layer 410' and / or the auxiliary gate electrode barrier layer 420' can improve adhesion to the respective gate pad 132 and / or gate fingers 134.

[0085] As explained above, in some embodiments, the auxiliary gate pad barrier layer 410' may be present and the auxiliary gate electrode barrier layer 420' may be omitted. For example, Figure 5B illustrates a MOSFET device 500' in which the auxiliary gate electrode barrier layer 420' is absent.

[0086] FIG 6A illustrates a further semiconductor device 600 according to some embodiments described herein. FIG 6B is a schematic cross-sectional view of portion B of FIG 6A. FIG 6C-FIG 6E illustrate further semiconductor devices according to some embodiments described herein. Descriptions of those elements in FIG 6A-FIG 6E that are the same as or similar to elements in the figures described above will be omitted for brevity. Thus, the description of FIG 6A-FIG 6E will focus on the differences with respect to those devices described above.

[0087] 6A and 6B, the MOSFET device 600 can include an auxiliary source barrier layer 620. The auxiliary source barrier layer 620 can be formed on the semiconductor structure and can be formed on the n-type source region 250 and / or the more highly doped portion 242 of the p-well. The auxiliary source barrier layer 620 can be provided in addition to the source barrier layer 320. In FIG. 6B, the auxiliary source barrier layer 620 is shown with separate shading to aid in distinguishing the auxiliary source barrier layer 620 from the source barrier layer 320, but this separate shading is not intended to limit the configuration of the auxiliary source barrier layer 620 or the source barrier layer 320. In some embodiments, the source barrier layer 320 can be on and / or in contact with the auxiliary source barrier layer 620 in a portion of the MOSFET device 600 that is between the source contact 280 and the semiconductor structure that includes the highly doped n-type source region 250 and the more highly doped portion 242 of the p-well.

[0088] 6B, in some embodiments, the auxiliary source barrier layer 620 can extend beyond the source barrier layer 320 on the sidewalls of the source contact 280. In some embodiments, a portion of the isolation layer 230 can be between a portion of the auxiliary source barrier layer 620 and the source barrier layer 320. The use of the auxiliary source barrier layer 620 can provide additional diffusion protection between the source contact 280 and the semiconductor structure including the n-type source region 250 and / or the more heavily doped portion 242 of the p-well. For example, the corner region 686 of the source contact 280 can be strengthened through the use of the auxiliary source barrier layer 620.

[0089] 6A, a MOSFET device 600 may include, but is not limited to, the use of an auxiliary source barrier layer 620 in conjunction with the auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 shown in Figures 4A-4C. In some embodiments, the auxiliary source barrier layer 620 may be used independently of one or both of the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420.

[0090] Figure 6C illustrates an embodiment in which an auxiliary source barrier layer 620 is used in conjunction with the auxiliary gate pad barrier layer 410' and auxiliary gate electrode barrier layer 420' discussed herein with respect to Figures 5A and 5B. Figures 6A-6C illustrate the auxiliary source barrier layer 620 used in conjunction with the auxiliary gate electrode barrier layer 420, however, the embodiments described herein are not so limited. Figures 6D-6E illustrate the use of the auxiliary source barrier layer 620 with the auxiliary gate pad barrier layer 410, 410' in the absence of the auxiliary gate electrode barrier layer 420, 420'.

[0091] Thus, it will be understood that the auxiliary gate pad barrier layer 410', the auxiliary gate pad barrier layer 410, the auxiliary gate electrode barrier layer 420', the auxiliary gate electrode barrier layer 420, and the auxiliary source barrier layer 620 can be used independently of one another and in various combinations without departing from the scope of the embodiments described herein.

[0092] 7-12 illustrate a method of manufacturing a semiconductor device according to some embodiments described herein.

[0093] 7, a substrate 210 is provided and a drift region 220 is formed on the substrate 210 by epitaxial growth. In some embodiments, the substrate 210 is heavily doped (n + ) n-type silicon carbide, and the drift region 220 is lightly doped (n -) silicon carbide drift region 220. In some embodiments, an n-type silicon carbide current spreading layer may be formed comprising an upper portion of drift layer 220.

[0094] The p-wells 240 may be formed in what will be the active region 102 of the final device, and the p-wells 244 may be formed in what will be the non-active region 106 of the final device. In the active region 102, the upper portion 242 of each p-well 240 may be more heavily doped with a p-type dopant, and the heavily doped (n + A highly doped (n) n-type silicon carbide source region 250 may be formed in an upper portion of the p-well 240 directly adjacent to and in contact with the more highly doped portion 242 of the p-well 240. + ) N-type silicon carbide region 250 serves as a source region for unit cell transistor 200. In some embodiments, ion implantation can be used to form p-wells 240, 244 and n-type source region 250.

[0095] In the active area 102, a gate insulation layer may be formed on an upper surface of the semiconductor layer structure. The gate insulation layer may be patterned and etched to form a gate insulation pattern 260 covering exposed portions of the drift region 220 and extending over the edges of the p-well 240 and the edges of the n-type source region 250. In the non-active area 106, a field insulation layer 264 may be formed on the p-well 244.

[0096] A conductive material, such as polysilicon, may be formed over the field insulation layer 264 and the gate insulation pattern 260. The conductive material may be patterned and etched to form the gate pad 132 and the gate fingers 134. The gate pad 132 and the gate fingers 134 may be electrically coupled to each other.

[0097] 8, an auxiliary barrier layer 810 may be formed on the gate fingers 134 and the gate pad 132. In some embodiments, the auxiliary barrier layer 810 may extend on the sidewalls of each of the gate fingers 134 and the gate pad 132. In some embodiments, the auxiliary barrier layer 810 may be formed on the n-type source region 250 and the more heavily doped portion 242 of the p-well.

[0098] The auxiliary barrier layer 810 can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and other metal nitrides and / or intermetallic compounds including, for example, cobalt (Co), ruthenium (Ru), and the like. The auxiliary barrier layer 810 can be a single layer (TiN, TaN, or similar material that has good thermodynamic stability and is electrically conductive) or a multi-layer stack of various elemental or compound materials in various stacking sequences. Thus, although FIG. 8 shows a single layer for the auxiliary barrier layer 810, the structure shown is also intended to show a structure with multiple layers.

[0099] Although shown as covering both active area 102 and non-active area 106, it will be understood that embodiments of the present disclosure are not limited to this configuration. In some embodiments, auxiliary barrier layer 810 may only be formed in non-active area 106. In other words, in some embodiments, auxiliary barrier layer 810 may only be formed on gate pad 132.

[0100] The auxiliary barrier layer 810 may then be patterned and etched using standard techniques to form the auxiliary barrier layer according to various embodiments described herein. For example, referring to FIG. 9A, the auxiliary barrier layer 810 may be patterned and etched to remove all portions of the auxiliary barrier layer 810 except over the gate pad 132 and the gate fingers 134. Thus, the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420 as shown in FIG. 4A may be formed. In some embodiments, portions of the field insulation layer 264 may also be removed as part of forming the auxiliary gate pad barrier layer 410, although embodiments described herein are not limited thereto.

[0101] 9B, the auxiliary barrier layer 810 can alternatively be patterned and etched to remove all portions of the auxiliary barrier layer 810 except over the gate pad 132 and the gate fingers 134. As shown in FIG 9B, etching can be performed to leave portions of the auxiliary barrier layer 810 on the sidewalls of the gate pad 132 and the gate fingers 134. Thus, the auxiliary gate pad barrier layer 410' and the auxiliary gate electrode barrier layer 420' can be formed as shown in FIG 5A.

[0102] In some embodiments, the auxiliary barrier layer 810 or another layer may be patterned and etched to leave portions of the auxiliary barrier layer 810 over the n-type source region 250, the more heavily doped portion of the p-well 242, and / or the p-well 244. Thus, the auxiliary source barrier layer 620 as shown in FIG. 6A may be formed. FIG. 9C illustrates an embodiment in which the auxiliary barrier layer 810 is patterned and etched to form the auxiliary source barrier layer 620 together with the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420. FIG. 9D illustrates an embodiment in which the auxiliary barrier layer 810 is patterned and etched to form the auxiliary source barrier layer 620 together with the auxiliary gate pad barrier layer 410' and the auxiliary gate electrode barrier layer 420'.

[0103] In some embodiments, a further patterning step can be performed on the field insulation layer 264 to form the auxiliary source barrier layer 620. For example, referring again to FIG. 8, in some embodiments, predetermined portions of the field insulation layer 264 and the auxiliary barrier layer 810 can be patterned and etched to expose the n-type source region 250, the more heavily doped portion of the p-well 242, and / or the upper surface of the p-well 244. Further barrier layer material can then be deposited in the exposed areas to form the auxiliary source barrier layer 620. In some embodiments, the barrier layer material used to form the auxiliary source barrier layer 620 can be the same as the material used to form the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420, although the embodiments described herein are not limited thereto. Further mechanisms for forming the auxiliary gate pad barrier layer 410, the auxiliary gate electrode barrier layer 420, and the auxiliary source barrier layer 620 will be recognized by those skilled in the art, and the embodiments described herein are not limited to the embodiments shown in the figures.

[0104] Following the formation of the auxiliary barrier layer, further processing can be performed to create one or more of the MOSFET devices described herein. Figures 10-12 focus primarily on the process of forming the MOSFET device 400 shown with respect to Figure 4A. However, it will be understood that the processes described herein can be modified as necessary to achieve, without limitation, further embodiments of the devices described herein.

[0105] 10, isolation layer 230 may be formed on gate finger 134, gate pad 132, field insulation layer 264, auxiliary gate pad barrier layer 410, and auxiliary gate electrode barrier layer 420. Isolation layer 230 may be an IMD (inter-metal dielectric) layer or an ILD (inter-layer dielectric) layer. In some embodiments, isolation layer 230 may include the same or similar material as field insulation layer 264, although embodiments described herein are not limited thereto.

[0106] 11, the isolation layer 230 is patterned and etched to form a contact hole 1010 for a source contact and a contact hole 1020 for a gate bond pad. The contact hole 1020 can expose a predetermined portion of the auxiliary gate pad barrier layer 410. In some embodiments, the auxiliary gate pad barrier layer 410 can extend beyond the sidewalls of the contact hole 1020. The contact hole 1010 can expose a predetermined portion of the semiconductor structure, such as the n-type source region 250 and / or the more heavily doped portion 242 of the p-well 240. In embodiments where an auxiliary source barrier layer 620 is present (see, e.g., FIGS. 9C and 9D), the contact hole 1010 can expose the auxiliary source barrier layer 620.

[0107] 12, a barrier layer 1210 can be formed on the isolation layer 230 and in the contact holes 1010 and 1020. The barrier layer 1210 can be on the sidewalls and bottom of the contact holes 1010 and 1020. The barrier layer 1210 can also be formed on portions of the auxiliary gate pad barrier layer 410 exposed by the contact hole 1020. In embodiments where an auxiliary source barrier layer 620 is present (see, e.g., FIGS. 9C and 9D), the barrier layer 1210 can be formed on the auxiliary source barrier layer 620 exposed by the contact hole 1010.

[0108] 4A, a metal contact layer may be formed on the active areas 102 and the non-active areas 104. The metal contact layer may be patterned and etched to form the gate bond pad 120 and the source metal pattern 123. The etch of the metal contact layer may also separate the barrier layer 1210 into the gate barrier layer 310 and the source barrier layer 320.

[0109] Power switching devices according to embodiments disclosed herein can provide significantly improved performance: by reducing diffusion of materials into the active areas of the device and / or increasing adhesion between metal layers and other conductive portions of the device, the overall structure of the device can be improved and defects can be reduced and / or eliminated.

[0110] It will be appreciated that the specific layer structures, doping concentrations, materials, conductivity types, and the like shown in the figures and / or described herein are provided by way of example only to provide detailed structural illustrations of particular example embodiments, and as such, the specific details discussed below are not limiting to the present invention.

[0111] Herein, embodiments of the invention are described with respect to cross-sectional views showing one or two unit cells of a power switching device. It will be appreciated that actual implementations will typically include a much larger number of unit cells. However, it will be appreciated that the invention is not limited to such devices, and that the appended claims also cover, for example, MOSFETs and other power switching devices comprising a single unit cell. Furthermore, while the present disclosure focuses on silicon carbide devices, it will be appreciated that embodiments of the invention may also have applicability to devices formed using other wide bandgap semiconductors, such as, for example, gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductors.

[0112] Although some of the above figures show unit cell structures of n-channel MOSFETs, it will be appreciated that in accordance with further embodiments of the present invention, the polarity of each of the semiconductor layers within each device may be reversed to provide a corresponding p-channel MOSFET.

[0113] The present invention has been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it will be understood that the element or layer can be directly connected or coupled to the other element or layer, or that intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.

[0114] Although the terms first and second are used herein to describe various regions, layers, and / or elements, it will be understood that these regions, layers, and / or elements should not be limited by these terms. These terms are only used to distinguish one region, layer, or element from another region, layer, or element. Thus, a first region, layer, or element discussed below can be referred to as a second region, layer, or element, and similarly, a second region, layer, or element can be referred to as a first region, layer, or element without departing from the scope of the present invention.

[0115] Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if a device in the figures is flipped over, an element described as being on a "lower" side of another element would be oriented on an "upper" side of the other element. Thus, the exemplary term "lower" can encompass both an "lower" and an "upper" orientation, depending on the particular orientation of the figure. Similarly, if a device in one of the figures is flipped over, an element described as being "below" or "beneath" another element would be oriented "above" the other element. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

[0116] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, elements and / or components but do not exclude the presence or addition of one or more other features, elements, components and / or groups thereof.

[0117] Embodiments of the invention are described herein with reference to cross-sectional views, which are schematic illustrations. Thus, variations from the shapes of the illustrations, for example as a result of manufacturing techniques and / or tolerances, are expected. As such, embodiments of the invention should not be construed as limited to the particular shapes of regions shown herein, and include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and / or ion implantation concentration gradients at its edges, rather than a binary transition from implanted to unimplanted regions. As such, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device, and are not intended to limit the scope of the invention.

[0118] It will be understood that the embodiments disclosed herein may be combined, such that a feature depicted and / or described with respect to a first embodiment may also be included in a second embodiment, and vice versa.

[0119] Although the above embodiments are described with reference to certain figures, it is understood that some embodiments of the invention can include additional and / or intervening layers, structures, or elements, and / or certain layers, structures, or elements can be omitted. Although a few exemplary embodiments of the invention have been described, those skilled in the art will readily recognize that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the invention. Accordingly, all such modifications are intended to be included within the scope of the invention as defined in the claims. Accordingly, it is understood that the above is illustrative of the invention and is not to be construed as being limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, together with any equivalents of the claims contained within the scope of the claims.

Claims

1. 1. A semiconductor device comprising: a semiconductor layer structure comprising an active area and a non-active area, the active area comprising a plurality of unit cells, the non-active area comprising a gate pad on the semiconductor layer structure and a gate bond pad on and electrically connected to the gate pad; an isolation layer between the gate pad and the gate bond pad; a barrier layer between the gate pad and the isolation layer, the barrier layer being on a top surface and sidewalls of the gate pad; A semiconductor device comprising:

2. the barrier layer is a first barrier layer, and the semiconductor device comprises: a second barrier layer overlying the gate pad and overlying the first barrier layer; Further equipped with The semiconductor device of claim 1 , wherein at least a portion of the isolation layer is between the first barrier layer and the second barrier layer.

3. The barrier layer comprises a plurality of layers, The semiconductor device of claim 1 , wherein the barrier layer comprises titanium (Ti) and / or tantalum (Ta).

4. the barrier layer is a first barrier layer, and the semiconductor device comprises: a gate finger overlying the active area and electrically connected to the gate bond pad; a second barrier layer on the gate fingers; and Further equipped with 2. The semiconductor device of claim 1, wherein the second barrier layer is on a top surface and sidewalls of the gate fingers.

5. the barrier layer is a first barrier layer, and the semiconductor device comprises: a source contact on the semiconductor layer structure; a second barrier layer on the sidewalls and bottom surface of the source contact; a third barrier layer between the semiconductor layer structure and the second barrier layer; The semiconductor device of claim 1 , further comprising:

6. 1. A semiconductor device comprising: a semiconductor layer structure; a plurality of unit cell transistors electrically connected in parallel, each unit cell transistor comprising a gate finger extending in a first direction on a top surface of the semiconductor layer structure, the gate fingers being spaced apart from one another along a second direction; an auxiliary gate electrode barrier layer on an upper surface and opposing sidewalls of each of said gate fingers; Equipped with the semiconductor layer structure comprises a non-active area and an active area; the active area comprises the plurality of unit cell transistors; The inactive area is a gate pad on the semiconductor layer structure; a gate bond pad on and electrically connected to the gate pad; an isolation layer between the gate pad and the gate bond pad; an auxiliary gate pad barrier layer between the gate pad and the isolation layer; A semiconductor device comprising:

7. the gate finger comprises polysilicon; The semiconductor device of claim 6 , wherein the auxiliary gate electrode barrier layer comprises titanium (Ti) and / or tantalum (Ta).

8. 7. The semiconductor device of claim 6, further comprising a gate pad barrier layer between said auxiliary gate pad barrier layer and said gate bond pad.

9. A semiconductor device, comprising: a semiconductor layer structure; a plurality of unit cell transistors electrically connected in parallel, each unit cell transistor comprising a gate finger extending in a first direction on a top surface of the semiconductor layer structure, the gate fingers being spaced apart from one another along a second direction; an auxiliary gate electrode barrier layer on an upper surface and opposing sidewalls of each of said gate fingers; an isolation layer on the gate fingers; Equipped with the auxiliary gate electrode barrier layer is between the isolation layer and the gate finger.

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