Semiconductor manufacturing apparatus and method for manufacturing semiconductor device

JP7636954B2Active Publication Date: 2025-02-27KIOXIA CORP
View PDF 5 Cites 0 Cited by

Patent Information

Application Number
JP2021072536
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-04-22
Publication Date
2025-02-27
Estimated Expiration
2041-04-22

Smart Images

  • Figure 0007636954000001
    Figure 0007636954000001
  • Figure 0007636954000002
    Figure 0007636954000002
  • Figure 0007636954000003
    Figure 0007636954000003
Patent Text Reader

Abstract

To provide a semiconductor manufacturing device capable of suppressing chipping or dust occurring after a trimming step of an outer periphery part of a substrate, and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor manufacturing device 100 comprises a first laser irradiation unit 24, a second laser irradiation unit 26, and a separation unit 21. The first laser irradiation unit 24 forms a modified layer by irradiating the inside of a first substrate with a first laser beam from the first substrate side in an outer periphery part of a bonded substrate 5 including a first substrate and a second substrate bonded to each other. The second laser irradiation unit 26 peels the second substrate from a material layer by irradiating the material layer with a second laser beam from the second substrate side, the material layer provided between the first substrate and the second substrate and on the second substrate. The separation unit separates an outer peripheral part of the first substrate and an outer peripheral part of the material layer from the outer peripheral part of the bonded substrate.SELECTED DRAWING: Figure 1
Need to check novelty before this filing date? Find Prior Art

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device. [Background technology]

[0002] Hybrid bonding technology has been developed to bond multiple substrates on which semiconductor elements are formed. In this technology, after bonding multiple substrates together, a trimming process is carried out to remove part of the outer periphery (rounded portion) of the substrates in order to prevent chipping of the substrates.

[0003] However, if the device layer remains on the outer periphery of the substrate after the trimming process, there is a risk that the device layer will peel off from the substrate and cause chipping or dust in the subsequent grinding process and CMP (Chemical Mechanical Polishing) process. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Patent Publication No. WO2019 / 176589 Summary of the Invention [Problem to be solved by the invention]

[0005] A semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device are provided that can suppress chipping or dust that occurs after a process of trimming the outer periphery of a substrate. [Means for solving the problem]

[0006] The semiconductor manufacturing apparatus according to the present embodiment includes a first laser irradiation unit, a second laser irradiation unit, and a separation unit. The first laser irradiation unit irradiates a first laser beam from the first substrate side to the inside of the first substrate in the outer periphery of the bonded substrate including the first substrate and the second substrate bonded to each other, to form a modified layer. The second laser irradiation unit irradiates a material layer provided on the second substrate between the first substrate and the second substrate with a second laser beam from the second substrate side to separate the second substrate from the material layer. The separation unit separates the outer periphery of the first substrate and the outer periphery of the material layer from the outer periphery of the bonded substrate. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view showing an example of the configuration of a semiconductor manufacturing apparatus according to a first embodiment. [Diagram 2] FIG. 4 is a schematic cross-sectional view showing a configuration example of a modified layer forming unit. [Diagram 3] FIG. 4 is a schematic cross-sectional view showing a configuration example of a release layer forming unit. [Figure 4] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 5 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 4. [Figure 6] 6 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 5; [Figure 7] 7 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 6. [Figure 8] FIG. 11 is a plan view showing a configuration example of a semiconductor manufacturing apparatus according to a second embodiment; [Figure 9] FIG. 4 is a schematic cross-sectional view showing a configuration example of a modified layer-peeling layer forming unit. [Figure 10] 8A to 8C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 11] 11 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 10; [Figure 12] 10A to 10C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the third embodiment. [Figure 13] 13 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 12. [Figure 14] 14 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 13. [Figure 15] 15 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 14. [Figure 16] 16 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 15. [Figure 17] 17 is a schematic cross-sectional view showing an example of the manufacturing method of the semiconductor device following FIG. 16. [Figure 18] 18 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 17. [Figure 19] 19 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 18. [Figure 20] 19A to 19C are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device, following those shown in FIG. [Figure 21] 21 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 20. [Figure 22] 22 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 21. [Diagram 23] 23 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 22. [Figure 24] 24 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 23. [Diagram 25] 25 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device following FIG. 24. [Figure 26] 26 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 25. [Figure 27] 27 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 26. [Figure 28] 28 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 27. [Figure 29] 29 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 28. [Diagram 30] 29A to 29C are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device, following those shown in FIG. 29. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to this embodiment. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, elements similar to those described above with respect to the previous drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0009] (First embodiment) 1 is a plan view showing an example of the configuration of a semiconductor manufacturing apparatus 100 according to a first embodiment. The semiconductor manufacturing apparatus 100 includes a load port 14, a standby port 15, a first robot 16, a second robot 17, an inversion mechanism 18, a modified layer forming unit 19, a peeling layer forming unit 20, a separation unit 21, and a cleaning unit 22.

[0010] A wafer case that contains a bonded substrate 5 is set in the load port 14. The standby port 15 is an area for temporarily placing the bonded substrate 5 to be processed next or the bonded substrate 5 after processing. A first robot 16 moves the bonded substrate 5 between the wafer case of the load port 14 and the standby port 15. A second robot 17 has an inversion mechanism 18 that picks up the bonded substrate 5 and inverts the bonded substrate 5 upside down.

[0011] The bonded substrate 5 is a substrate including a first substrate 2 and a second substrate 4 bonded to each other. The first substrate 2 and the second substrate 4 are semiconductor substrates such as silicon substrates. A semiconductor element such as a memory cell array (not shown) is formed on the surface of the first substrate 2. The memory cell array may be a three-dimensional memory cell array in which memory cells are arranged three-dimensionally. A semiconductor element such as a CMOS (Complementary Metal Oxide Semiconductor) circuit (not shown) is formed on the surface of the second substrate 4. The CMOS circuit may be a controller that controls the memory cell array of the first substrate 2.

[0012] The modified layer forming unit 19 includes a first stage 23 that holds the bonded substrate 5, and a first laser irradiation section 24 that irradiates the bonded substrate 5 with a first laser beam. The peeling layer forming unit 20 includes a second stage 25 that holds the bonded substrate 5, and a second laser irradiation section 26 that irradiates the bonded substrate 5 with a second laser beam. The separation unit 21 includes a third stage 27 and a separation blade 11. The third stage 27 holds the bonded substrate 5. The separation blade 11 is formed in a disk shape and is inserted between the first substrate 2 and the second substrate 4 to separate the outer periphery of the first substrate 2 (see FIG. 6) of the bonded substrate 5 from the bonded substrate 5. The cleaning unit 22 includes a fourth stage 29 that holds the bonded substrate 5, and a two-fluid cleaning mechanism 30.

[0013] 2 is a schematic cross-sectional view showing an example of the configuration of the modified layer forming unit 19. The modified layer forming unit 19 includes a first stage 23 and a first laser irradiation section 24.

[0014] The first stage 23 is capable of holding the bonded substrate 5, and is configured to be rotatable about an axis as indicated by an arrow A.

[0015] The first laser irradiation unit 24 is configured to be movable to the outer periphery of the bonded substrate 5 on the first stage 23, and irradiates the first laser light 7 onto the outer periphery of the bonded substrate 5 from above in the Z direction of the bonded substrate 5. The first laser light 7 is laser light having a wavelength that is absorbed by the first substrate 2 (e.g., a silicon substrate) of the bonded substrate 5.

[0016] 3 is a schematic cross-sectional view showing an example of the configuration of the peeling layer forming unit 20. The peeling layer forming unit 20 includes a second stage 25 and a second laser irradiation section .

[0017] The second stage 25 is capable of holding the bonded substrate 5, and is configured to be rotatable about an axis as indicated by an arrow A.

[0018] The second laser irradiation unit 26 is configured to be movable to the outer periphery of the bonded substrate 5 on the second stage 25, and irradiates the outer periphery of the bonded substrate 5 with the second laser light 9 from above the bonded substrate 5 in the Z direction. That is, the first and second laser irradiation units 24, 26 irradiate the bonded substrate 5 with the first and second laser lights 7, 9, respectively, from the same direction (Z direction). The second laser light 9 is a laser light that transmits through the second substrate 4 (e.g., a silicon substrate) of the bonded substrate 5 and has a wavelength that is absorbed by at least one layer (e.g., a silicon oxide film) of a device layer provided between the first substrate 2 and the second substrate 4.

[0019] The memory cell array is covered with an insulating film such as a silicon oxide film on the first substrate 2. The CMOS circuit is covered with an insulating film such as a silicon oxide film on the second substrate 4. For example, any of insulating films such as a silicon oxide film, a silicon nitride film, a silicon carbide film, or a silicon carbonitride film is used as this insulating film. Note that, hereinafter, the device layer constituting the semiconductor elements such as the memory cell array and the CMOS circuit, and the insulating film covering the semiconductor elements are collectively referred to as a material layer.

[0020] 4 to 7 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. The direction perpendicular to the mounting surfaces of the stages 23 and 25 is the Z direction. One direction within the mounting surfaces of the stages 23 and 25 is the X direction, and the direction perpendicular to the X direction is the Y direction.

[0021] First, the first robot 16 of the semiconductor manufacturing apparatus 100 in Fig. 1 takes out the bonded substrate 5 from the wafer case 14 and places the bonded substrate 5 on the waiting port 15. Next, the second robot 17 places the bonded substrate 5 from the waiting port 15 onto the first stage 23 of the modified layer forming unit 19. The bonded substrate 5 is placed on the first stage 23 so that the first substrate 2 is upward in the Z direction. In the modified layer forming unit 19, the first stage 23 holds the bonded substrate 5 so that the first substrate 2 is upward in the Z direction, as shown in Fig. 4.

[0022] 4, the first laser irradiation unit 24 irradiates the outer periphery of the first substrate 2 with the first laser light 7 from the first substrate 2 side to form a modified layer 8 inside the first substrate 2. The modified layer 8 is formed so as to extend in the thickness direction (Z direction) of the first substrate 2. At this time, the first stage 23 rotates the bonded substrate 5 in the direction of arrow A in FIG. 2 to form the modified layer 8 in the first substrate 2 over the entire outer periphery of the first substrate 2.

[0023] Next, the second robot 17 picks up the bonded substrate 5 from the first stage 23, and while inverting the bonded substrate 5 with the inversion mechanism 18, places it on the second stage 25 of the peeling layer forming unit 20. The bonded substrate 5 is inverted so that the second substrate 4 faces upward and is held on the second stage 25.

[0024] 5, the second laser irradiation unit 26 irradiates the second laser light 9 from the second substrate 4 side, and irradiates the material layer 3 between the first substrate 2 and the second substrate 4 and provided on the second substrate 4 with the second laser light 9 from the second substrate 4 side. As a result, the material layer 3 of the second substrate 4 absorbs the second laser light 9 and is heated, and peels between the second substrate 4 and the material layer 3, or between films in the material layer 3, to form a peeling layer 10. At this time, the second stage 25 moves the second laser irradiation unit 26 in the X-axis direction while rotating the bonded substrate 5 in the direction of the arrow A in FIG. 2, thereby forming the peeling layer 10 over the entire outer periphery of the second substrate 4.

[0025] 1 picks up bonded substrate 5 from second stage 25, and places it on third stage 27 of separation unit 21 while inverting bonded substrate 5 using inversion mechanism 18. Bonded substrate 5 is again inverted so that first substrate 2 faces upward and is held on third stage 27.

[0026] Next, as shown in FIG. 6, a disk-shaped separation blade 11 is inserted between the first substrate 2 and the second substrate 4 while rotating in the direction of the arrow B to apply stress. At this time, the modified layer 8 breaks in the outer periphery of the first substrate 2, and the peeling layer 10 between the second substrate 4 and the material layer 3 is pulled away. As a result, as shown in FIG. 7, the outer periphery 2a of the first substrate 2, the outer periphery 1a of the material layer 1 on the first substrate 2, and the outer periphery 3a of the material layer 3 on the second substrate 4 are separated and removed from the bonded substrate 5. At this time, the outer periphery 4a of the second substrate 4 remains as it is, but all or at least a part of the outer peripheries 1a, 3a of the material layers 1, 3 thereon are removed. That is, in the outer periphery, the insulating film (e.g., silicon oxide film, silicon nitride film, silicon carbide film, silicon carbonitride film, etc.) and the wiring structure included in the material layers 1, 3 are removed together with the outer periphery of the first substrate 2.

[0027] Next, the second robot 17 picks up the bonded substrate 5 from the third stage 27 and places it on the fourth stage 29 of the cleaning unit 22. In the cleaning unit 22, the two-fluid cleaning mechanism 30 cleans the bonded substrate 5. Thereafter, the fourth stage 29 is rotated and dried.

[0028] Thereafter, the second robot 17 picks up the bonded substrate 5 from the fourth stage 29 and places it on the waiting port 15 of Fig. 1. The first robot 16 returns the bonded substrate 5 from the waiting port 15 to the wafer case 14.

[0029] In this embodiment, the peeling layer 10 is formed after the modified layer 8 is formed, but the modified layer 8 may be formed after the peeling layer 10 is formed. That is, in this embodiment, the first laser irradiation unit 24 irradiates the bonded substrate 5 with the first laser light 7, and then the second laser irradiation unit 26 irradiates the bonded substrate 5 with the second laser light 9. However, this order may be reversed, and the second laser irradiation unit 26 may irradiate the bonded substrate 5 with the second laser light 9, and then the first laser irradiation unit 24 may irradiate the bonded substrate 5 with the first laser light 7.

[0030] After that, the first substrate 2 is polished (back-ground) in a polishing process. Furthermore, after the outer peripheral portion 4a of the second substrate 4 is removed, the second substrate 4 is also polished. As a result, the material layer 1 and the material layer 3 are bonded to each other to form a semiconductor device. The bonded substrate 5 is diced into a plurality of individual semiconductor chips. The device layer (e.g., a memory cell array) of the material layer 1 and the device layer (e.g., a CMOS circuit) of the material layer 3 are electrically connected at the bonding surface between the material layer 1 and the material layer 3.

[0031] As described above, in this embodiment, the first laser light 7 is irradiated from the first substrate 2 side of the bonded substrate 5 to form the modified layer 8 extending in the Z direction inside the outer periphery of the first substrate 2. Then, the second laser light 9 is irradiated from the second substrate 4 side to form the peeling layer 10 extending in the X or Y direction between the second substrate 4 and the material layer 3, or between the films inside the material layer 3. Then, the outer periphery 2a of the first substrate 2 is separated from the modified layer 8, and at least a part of the outer periphery 1a of the material layer 1 and the outer periphery 3a of the material layer 3 is separated from the second substrate 4 along the peeling layer 10. This makes it possible to remove not only the first substrate 2 from the outer periphery of the bonded substrate 5, but also material layers such as the device layer and the insulating film. That is, the outer periphery of the first substrate 2 and the material layer between the first substrate 2 and the second substrate 4 are removed in advance from the outer periphery of the bonded substrate 5. Therefore, in the subsequent processing steps such as a grinding step and a CMP step, chipping of the outer periphery of the bonded substrate 5 or dust generated from the outer periphery of the bonded substrate 5 can be suppressed.

[0032] According to the present embodiment, the second laser light 9 is irradiated from the second substrate 4 on the opposite side to the first substrate 2 irradiated with the first laser light 7. An insulating film such as a silicon oxide film having a thickness of 50 nm or more is provided on the surface of the second substrate 4, but a device layer such as a semiconductor element is not provided. Therefore, the second laser light 9 is absorbed by the material layer 3 and heats the material layer 3. This makes it easier for the material layer 3 to peel off from the surface of the second substrate 4, or for the films in the material layer 3 to peel off. As a result, the peeling layer 10 is easily formed between the material layer 3 and the second substrate 4, or between the films in the material layer 3, and the outer periphery of the first substrate 2 and the material layer between the first substrate 2 and the second substrate 4 are easily removed from the outer periphery of the bonded substrate 5.

[0033] Second embodiment Fig. 8 is a plan view showing a configuration example of a semiconductor manufacturing apparatus 100 according to the second embodiment. Fig. 9 is a schematic cross-sectional view showing a configuration example of a modified layer / peeling layer forming unit 31. According to the second embodiment, the second robot 17 does not have an inversion mechanism 18, and the modified layer forming unit 19 and the peeling layer forming unit 20 are configured as one common modified layer / peeling layer forming unit 31. That is, in the second embodiment, the modified layer 8 and the peeling layer 10 are formed on the bonded substrate 5 in the modified layer / peeling layer forming unit 31 successively or simultaneously without inverting the bonded substrate 5.

[0034] The modified layer / peeling layer forming unit 31 includes a stage 32, a first laser irradiation section 24, and a second laser irradiation section .

[0035] Stage 32 is configured to be able to hold bonded substrate 5 and to be able to rotate around an axis as indicated by arrow A. As described above, first laser irradiator 24 is configured to be able to move to the outer periphery of bonded substrate 5 and irradiates first laser light 7 onto the outer periphery of bonded substrate 5 from above in the Z direction of bonded substrate 5. Second laser irradiator 26 is configured to be able to move to the outer periphery of bonded substrate 5 and irradiates second laser light 9 onto the outer periphery of bonded substrate 5 from below in the Z direction of bonded substrate 5.

[0036] Stage 32 has a diameter smaller than that of bonded substrate 5, and holds the bonded substrate such that the entire outer periphery of bonded substrate 5 extends beyond the outer edge of stage 32. For example, the outer diameter of bonded substrate 5 is about 300 mm, and the outer diameter of stage 32 is about 280 mm. In this case, the outer periphery of bonded substrate 5 extends beyond stage 32 by about 20 mm. This allows first and second laser irradiation units 24, 26 to irradiate first and second laser beams 7, 9, respectively, onto the front and back surfaces of bonded substrate 5 from opposite directions while bonded substrate 5 is held on the same stage 32.

[0037] The first laser irradiating section 24 irradiates the first laser light 7 from the first substrate 2 side of the bonded substrate 5. The second laser irradiating section 26 irradiates the second laser light 9 from the second substrate 4 side of the bonded substrate 5.

[0038] The first and second laser irradiation units 24, 26 may irradiate the first and second laser beams 7, 9 to substantially the same position in the XY plane. That is, the first and second laser irradiation units 24, 26 may face each other and substantially overlap when viewed from the Z direction. However, the first and second laser irradiation units 24, 26 do not necessarily irradiate the first and second laser beams 7, 9 to the same position in the XY plane, and may irradiate the first and second laser beams 7, 9 with a shift in the circumferential direction of the bonded substrate 5. Even if the first and second laser irradiation units 24, 26 are arranged with a shift in the circumferential direction of the bonded substrate 5, the stage 32 rotates the bonded substrate 5 in the direction of the arrow A, so that the modified layer 8 and the peeling layer 10 are formed on the outer periphery of the bonded substrate 5.

[0039] In addition, the first and second laser irradiation units 24, 26 may simultaneously irradiate the bonded substrate 5 with the first and second laser beams 7, 9. In this case, the modified layer 8 and the peeling layer 10 are simultaneously formed on the outer periphery of the bonded substrate 5. Thus, the modified layer 8 and the peeling layer 10 can be formed in a short time. On the other hand, the first and second laser irradiation units 24, 26 may irradiate the bonded substrate 5 with the first and second laser beams 7, 9 at different times. For example, as described below, first, the first laser irradiation unit 24 irradiates the outer periphery of the bonded substrate 5 with the first laser beam 7 to form the modified layer 8 on the bonded substrate 5. Next (successively), the second laser irradiation unit 26 may irradiate the outer periphery of the bonded substrate 5 with the second laser beam 9 to form the peeling layer 10 on the bonded substrate 5.

[0040] The bonded substrate 5 may be placed upside down on the stage 32, and the positions of the first laser irradiation unit 24 and the second laser irradiation unit 26 may be reversed accordingly. Even in this case, the first laser light 7 is irradiated from the first substrate 2 side, and a modified layer 8 can be formed inside the first substrate 2. The second laser light 9 is irradiated from the second substrate 4 side, and a peeling layer 10 can be formed by peeling between the second substrate 4 and the material layer 3, or between films in the material layer 3.

[0041] In the second embodiment, the reversing mechanism 18 is not required. Therefore, the cost of the apparatus 100 can be kept low. The modified layer forming unit 19 and the peeling layer forming unit 20 are integrated into one modified layer peeling layer forming unit 31. Therefore, the cost of the apparatus 100 can be further reduced, and the overall size of the apparatus 100 can be made smaller. The other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment. As a result, the second embodiment can also obtain the same effects as the first embodiment.

[0042] 10 and 11 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment.

[0043] First, the first robot 16 of the semiconductor manufacturing apparatus 100 in FIG. 8 takes out the bonded substrate 5 from the wafer case 14 and places the bonded substrate 5 on the waiting port 15. Next, the second robot 17 places the bonded substrate 5 from the waiting port 15 on the stage 32 of the modified layer peeling layer forming unit 31. The bonded substrate 5 is placed on the stage 32 so that the first substrate 2 is on the upper side in the Z direction. In the modified layer peeling layer forming unit 31, as shown in FIG. 10, the stage 32 holds the bonded substrate 5 so that the first substrate 2 is on the upper side in the Z direction. The stage 32 has a diameter smaller than that of the bonded substrate 5. Therefore, the first and second laser irradiation units 24, 26 can irradiate the outer periphery of the bonded substrate 5 protruding from the outer edge of the stage 32 with the first and second laser beams 7, 9 from opposite directions.

[0044] 10, the first laser irradiation section 24 irradiates the outer periphery of the first substrate 2 with the first laser light 7 from the first substrate 2 side to form a modified layer 8 inside the first substrate 2. The modified layer 8 is formed so as to extend in the thickness direction (Z direction) of the first substrate 2.

[0045] At this time, the first stage 23 rotates the bonded substrate 5 in the direction of arrow A in FIG. 9, thereby forming a modified layer 8 in the first substrate 2 over the entire outer periphery of the first substrate 2.

[0046] Next, with the bonded substrate 5 placed on the stage 32, the second laser irradiation unit 26 irradiates the second laser light 9 from the second substrate 4 side. The second laser irradiation unit 26 is located between the first substrate 2 and the second substrate 4, and irradiates the material layer 3 provided on the second substrate 4 with the second laser light 9 from the second substrate 4 side. As a result, the second laser light 9 is absorbed inside the material layer 3 of the second substrate 4 and heated, and the gap between the second substrate 4 and the material layer 3 or between films in the material layer 3 is peeled off to form a peeling layer 10.

[0047] 6 and 7, parts of outer periphery 12 (outer periphery 2a of first substrate 2, outer periphery 1a of material layer 1 on first substrate 2, and outer periphery 3a of material layer 3 on second substrate 4) are separated and removed from bonded substrate 5. Therefore, the second embodiment can obtain the same effect as the first embodiment.

[0048] The bonded substrate 5 may be placed upside down on the stage 32, and the positions of the first laser irradiation unit 24 and the second laser irradiation unit 26 may be reversed accordingly. Even in this case, the first laser light 7 is irradiated from the first substrate 2 side, and a modified layer 8 can be formed inside the first substrate 2. The second laser light 9 is irradiated from the second substrate 4 side, and a peeling layer 10 can be formed by peeling between the second substrate 4 and the material layer 3, or between films in the material layer 3.

[0049] Furthermore, when the first and second laser beams 7 and 9 are irradiated at different times, the first laser irradiation unit 24 may irradiate the bonded substrate 5 with the first laser beam 7, and then the second laser irradiation unit 26 may irradiate the bonded substrate 5 with the second laser beam 9. However, this order may be reversed. That is, the second laser irradiation unit 26 may irradiate the bonded substrate 5 with the second laser beam 9, and then the first laser irradiation unit 24 may irradiate the bonded substrate 5 with the first laser beam 7.

[0050] Furthermore, the first and second laser irradiation units 24, 26 may simultaneously irradiate the first and second laser beams 7, 9 onto the bonded substrate 5. This leads to a reduction in the time required to form the modified layer 8 and the peeling layer 10.

[0051] Furthermore, the second embodiment does not require the step of inverting the bonded substrate 5. Therefore, the time required to form the modified layer 8 and the release layer 10 is further reduced.

[0052] Third embodiment 12 to 30 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the third embodiment. The third embodiment is an embodiment in which the first or second embodiment is applied to a memory chip. Figs. 12 to 28 mainly show the manufacturing process of the structure of the outer periphery of the second substrate 4.

[0053] In the third embodiment, the material layer 3 on the second substrate 4 is preferably an insulating film that does not have a device layer such as a semiconductor element provided on the surface of the second substrate 4. For example, when the material layer 3 is a silicon oxide film, the thickness of the material layer 3 is preferably 50 nm or more. This makes it easier for the second laser light 9 to be absorbed by the material layer 3 without being reflected by the device layer, and the peeling layer 10 of FIG. 11 is easily formed between the material layer 3 and the second substrate 4, or between films in the material layer 3. That is, the material layer 3 can effectively function as an absorption layer for the second laser light 9. The material layer 3 may have an upper layer wiring structure provided above the second substrate 4. This is because the second laser light 9 can be sufficiently absorbed by the material layer 3 (for example, a silicon oxide film) between the upper layer wiring structure and the second substrate 4. Hereinafter, a method for manufacturing a semiconductor device will be described.

[0054] 12, a gate insulating film (e.g., a silicon oxide film) 33, a gate electrode film (e.g., a polysilicon film) 34, and an insulating film (e.g., a silicon nitride film) 35 are laminated in this order on a second substrate 4 (e.g., a silicon substrate). The thickness of the gate insulating film 33 is, for example, about 10 nm, the thickness of the gate electrode film 34 is, for example, about 90 nm, and the thickness of the insulating film 35 is, for example, about 30 nm.

[0055] 13, a resist film 36 is applied onto the insulating film 35 using a lithography technique, and the resist film 36 is removed from the element isolation formation region 37. At this time, the resist film 36 is left on the outer periphery (material layer formation region) 38 of the second substrate 4.

[0056] 14, the insulating film 35, the gate electrode film 34, the gate insulating film 33, and the second substrate 4 are processed by an etching technique such as RIE (Reactive Ion Etching) using the resist film 36 as a mask. As a result, a trench 39 is formed in the element isolation formation region 37. The depth of the trench 39 is, for example, about 350 nm.

[0057] After removing the resist film 36, an insulating film (e.g., a silicon oxide film) is deposited in the trench 39, and the insulating film is polished by a chemical mechanical polishing (CMP) method. As a result, as shown in FIG. 15, the insulating film is embedded in the trench 39, and an element isolation structure 40 is formed. Here, the element isolation structure 40 is not formed in the outer periphery (material layer formation region) 38 of the second substrate 4. As a result, the material layer 3 formed in a later process and the second substrate 4 are easily peeled off, and the peeling layer 10 is easily formed.

[0058] Next, as shown in Fig. 16, the insulating film 35 is removed. Next, as shown in Fig. 17, a metal silicide film (e.g., a tungsten silicide (WSi) film) 41 and a cap insulating film 42 (e.g., a silicon nitride film) are laminated on the gate electrode film 34. The metal silicide film 41 will be processed later as a gate electrode together with the gate electrode film 34. The thickness of the metal silicide film 41 is, for example, about 90 nm. The thickness of the cap insulating film 42 is, for example, 50 nm.

[0059] Next, a resist film 43 is applied onto the cap insulating film 42 using lithography technology, and the resist film 43 is removed from areas other than the gate electrode formation area. As a result, the resist film 43 is processed into a pattern of the gate electrodes of the transistors that constitute the CMOS circuit, as shown in Fig. 18. At this time, the resist film 43 from the outer periphery (material layer formation area) 38 of the second substrate 4 is also removed.

[0060] 19, the cap insulating film 42, the metal silicide film 41 and the gate electrode film 34 are processed into a gate electrode pattern by an etching technique such as RIE using the resist film 43 as a mask. As a result, the metal silicide film 41 and the gate electrode film 34 are formed as a gate electrode. Hereinafter, the metal silicide film 41 and the gate electrode film 34 are collectively referred to as the gate electrodes 34, 41.

[0061] 20, after removing the resist film 43, a material for the spacer layer 45 (for example, a silicon oxide film) is deposited above the second substrate 4. The material for the spacer layer 45 has a thickness of, for example, about 40 nm.

[0062] Next, the material of the spacer layer 45 is etched back using an etching technique, so that the spacer layer 45 remains on the side surfaces of the gate electrodes 34, 41, as shown in Fig. 21. Next, the material of the gate insulating film 33 is processed by an etching technique using the cap insulating film 42 and the spacer layer 45 as a mask. As a result, the gate insulating film 33 remains under the gate electrodes 34, 41 and the spacer layer 45, as shown in Fig. 21. Here, device structures such as the gate electrodes 34, 41 are not formed in the outer periphery (material layer formation region) 38.

[0063] Next, impurities are introduced using the spacer layer 45 and the cap insulating film 42 as a mask to form source / drain layers (not shown).

[0064] 22, insulating films 47 and 48 are laminated above the second substrate 4. The insulating film (liner layer) 47 is made of, for example, a silicon nitride film and has a thickness of, for example, about 30 nm. The insulating film 48 is made of, for example, a silicon oxide film and has a thickness of, for example, about 500 nm.

[0065] Next, the insulating film 48 is planarized by using a CMP method or the like, and then the insulating film 49 is deposited on the insulating film 48. The insulating film 49 is, for example, a silicon oxide film, and has a thickness of, for example, about 200 nm.

[0066] 22, a resist film 50 is applied onto the insulating film 49 by using a lithography technique, and the resist film 50 is removed from the contact formation region 51. At this time, the resist 50 is left behind in the outer periphery (material layer formation region) 38.

[0067] 23, the insulating films 49 and 48 are processed by an etching technique such as RIE using the resist film 50 as a mask to form a contact hole 52. After removing the resist film 50, the insulating film 47 and the cap insulating film 42 at the bottom of the contact hole 52 are further etched by an etching technique such as RIE using the insulating film 49 as a mask. As a result, the contact hole 52 reaches the second substrate 4 or the gate electrodes 34 and 41 as shown in FIG. 23. By removing the resist film 50, the structure shown in FIG. 24 is obtained.

[0068] Next, as shown in FIG. 25, a resist film 53 is applied using lithography, and the resist film 53 in a wiring formation region 54 is removed.

[0069] 26, using the resist film 53 as a mask, an upper portion of the insulating film 49 (for example, a portion up to 100 nm from the upper surface of the insulating film 49) is processed by an etching technique such as RIE to form a trench 55. The trench 55 passes over the contact hole 52 and extends, for example, in a direction perpendicular to the plane of the paper in FIG.

[0070] After removing the resist film 53, a metal film (e.g., a tungsten film) is formed so as to fill the contact hole 52 and the trench 55. Next, the metal film is polished by using the CMP method until the surface of the insulating film 49 is exposed. As a result, as shown in FIG. 27, the contact 56 and the wiring layer 57 are formed. At this time, in the outer periphery (material layer forming region) 38, a region 58 of the insulating films 48, 49 on the second substrate 4 where the wiring layer 57 is not provided functions as a material layer (absorption layer) that absorbs the second laser light 9. The thickness of the absorption layer 58 is, for example, 340 nm. Only the liner layer 47 exists between the absorption layer 58 and the second substrate 4.

[0071] Next, as shown in FIG. 28, an upper wiring structure 59 is formed on the insulating film 49 and the wiring layer 57.

[0072] In this manner, the material layer 3 is formed on the second substrate 4. The material layer 3 has a device layer (gate insulating film 33, gate electrode 34, metal silicide film 41) constituting a CMOS circuit in the central region of the second substrate 4. On the other hand, in the peripheral portion 38, the material layer 3 does not include a device layer, and insulating films 47 to 49, a wiring layer 57, and an upper wiring structure 59 are formed. In particular, the absorption layer 58 of the material layer 3 directly above the second substrate 4 is not provided with not only the device layer, but also the wiring layer 57 and the upper wiring structure 59. Therefore, the absorption layer 58 is composed of an insulating film such as a silicon oxide film that is relatively thicker than 50 nm, and can efficiently absorb the second laser light 9.

[0073] A material layer 1 is formed on the first substrate 2 separately from the second substrate 4. The material layer 1 includes a memory cell array 60 and an upper layer wiring structure 61. The reason for this will be described later. Note that a detailed description of the process of forming the material layer 1 will be omitted here.

[0074] As shown in FIG. 29, the first substrate 2 and the second substrate 4 are bonded at bonding surfaces 64, 65. The wiring layer of the upper wiring structure 61 of the first substrate 2 is exposed at the bonding surface 64. The wiring layer of the upper wiring structure 59 of the second substrate 4 is exposed at the bonding surface 65. When the bonding surfaces 64, 65 are bonded together, the wiring layer of the upper wiring structure 61 and the wiring layer of the upper wiring structure 50 are bonded together. This electrically connects the memory cell array 60 of the first substrate 2 and the CMOS circuit of the second substrate 4. The bonded substrate 5 is formed by bonding the first substrate 2 and the second substrate 4 together.

[0075] At this time, the outer edges of the first and second substrates 2, 4 are rounded with a certain curvature. Also, the outer periphery 38 of the material layers 1, 3 has an unbonded region (roll-off region) 66 due to the rounded portions of the outer edges of the first and second substrates 2, 4 and over-polishing by CMP or the like. Therefore, an unbonded region 66 that is not bonded at the bonding surface is generated in the outer periphery 38. In order to remove such an unbonded region 66, the following trimming process is performed.

[0076] Next, a laser trimming process is performed according to the first or second embodiment. For example, the first laser irradiation unit 24 irradiates the first laser light 7 from the first substrate 2 side to form a modified layer 8 on the outer periphery 38 of the first substrate 2. The second laser irradiation unit 26 irradiates the second laser light 9 from the second substrate 4 side to form a peeling layer 10 between the second substrate 4 and the absorption layer 58 of the material layer 3. Thereafter, a separation blade 11 is inserted between the first substrate 2 and the second substrate 4 to apply stress, and the modified layer 8 and the peeling layer 10 are broken. The first substrate 2 and the material layers 1 and 3 at the outer periphery 38 are separated. As a result, the first substrate 2 and the material layers 1 and 3 at the outer periphery 38 are removed from the bonded substrate 5, while the outer periphery of the second substrate 4 is left behind.

[0077] Here, the trimming region 67 to be removed by trimming includes the rounded portions and unbonded regions 66 at the ends of the first and second substrates 2, 4, and is set to a region included in the outer periphery 38. That is, as shown in FIG. 30, the length of the trimming region 67 in the X direction (radial direction of the bonded substrate 5) is longer than the unbonded regions 66 and shorter than the outer periphery 38. For example, the rounded portions and unbonded regions 66 of the first and second substrates 2, 4 are regions extending from the end of the bonded substrate 5 to a position approximately 2.0 mm inward. The outer periphery (material layer forming region) 38 is a region extending from the end of the bonded substrate 5 to a position 3.0 mm inward. The trimming region 67 is a region extending from the end of the bonded substrate 5 to a position 2.5 mm inward.

[0078] Thereafter, although not shown, the first substrate 2 may be thinned in a grinding process and a CMP process, after which electrodes are formed and a semiconductor device structure is formed thereon. Since the material layers 1 and 3 in the outer periphery 38 are removed in the trimming process, the occurrence of chipping and dust in the grinding process and the CMP process can be suppressed.

[0079] Moreover, the element isolation structure 40 is not provided in the outer periphery 38 of the second substrate 4. This makes it easier for the interface between the second substrate 4 and the material layer 3 to peel off, and makes it easier to form the peeling layer 10. This makes it possible to prevent the material layers 1 and 3 from remaining in the trimming region 67.

[0080] Furthermore, an absorption layer 58 (i.e., insulating films 48, 49) without a device layer or a wiring layer is provided in the material layer of the outer periphery 38. This can increase the absorption efficiency of the second laser light 9 and promote the formation of the peeling layer 10. This can prevent the material layers 1 and 3 from remaining in the trimming region 67.

[0081] In order to absorb the energy required for forming the peeling layer 10, the thickness of the absorbing layer 58 is preferably 50 nm or more. It is preferable that there is no film, such as a metal film, that reflects the second laser light 9 between the second substrate 4 and the absorbing layer 58. It is also preferable that no pattern is formed between the absorbing layer 58 and the second substrate 4 and the absorbing layer 58 in order to prevent scattering of the second laser light 9. That is, the absorbing layer 58 is preferably a single-layer film or a multilayer film that is a flat film along the surface of the second substrate 4. In order to simplify the manufacturing process, the absorbing layer 58 is preferably formed of a material that can be formed simultaneously with an interlayer insulating film of a semiconductor structure. For example, the absorbing layer 58 (i.e., the insulating films 48, 49) is preferably composed of a material such as a silicon oxide film, a silicon nitride film, a silicon carbide film, or a silicon carbonitride film.

[0082] Furthermore, in this embodiment, the absorption layer 58 is preferably provided on the second substrate 4 on which the CMOS circuit is formed. If the absorption layer 58 is to be provided on the first substrate 2 having the three-dimensional memory cell array 60, it is necessary to remove the memory cell array in the outer peripheral portion 38. In this case, a large step of 1 μm or more occurs at the boundary between the outer peripheral portion 38 and the memory cell array 60, and the unbonded region (roll-off region) 66 spreads due to over-polishing in the CMP process. As a result, there is a risk that the trimming region 67 needs to be expanded. Therefore, the absorption layer 58 is preferably provided on the second substrate 4, and the second laser light 9 is preferably irradiated from the second substrate 4 side.

[0083] The above embodiment can also be applied to a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0084] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0085] 10 semiconductor manufacturing apparatus, 18 inversion mechanism, 19 modified layer forming unit, 20 peeling layer forming unit, 21 separation unit, 22 cleaning unit, 23 first stage, 24 first laser irradiation unit, 25 second stage, 26 second laser irradiation unit, 5 bonded substrate

Claims

1. a first laser irradiation unit that irradiates a first laser beam from the first substrate side to the inside of the first substrate in an outer periphery of a bonded substrate including a first substrate and a second substrate bonded to each other to form a modified layer; a second laser irradiation unit that is between the first substrate and the second substrate and irradiates a material layer provided on the second substrate with a second laser light from the second substrate side to peel off the second substrate and the material layer; a separation unit that separates the outer periphery of the first substrate and the outer periphery of the material layer from the outer periphery of the bonded substrate.

2. a stage for holding the bonded substrate; and a reversing unit for reversing the bonded substrate.

2. The semiconductor manufacturing apparatus according to claim 1, wherein the first and second laser irradiating units irradiate the bonded substrate with the first and second laser beams from the same direction.

3. the first laser irradiation unit irradiates the first laser light onto an outer periphery of the first substrate; 3 . The semiconductor manufacturing apparatus according to claim 2 , wherein the second laser irradiation section irradiates the material layer with the second laser light after the reversing section has reversed the bonded substrate and placed it on the stage.

4. 2. The semiconductor manufacturing apparatus according to claim 1, wherein the first and second laser irradiating units irradiate the bonded substrate with the first and second laser beams in opposite directions to each other.

5. 5. The semiconductor manufacturing apparatus according to claim 4, further comprising a stage having a diameter smaller than a diameter of the bonded substrate and for holding the bonded substrate.

6. 6. The semiconductor manufacturing apparatus according to claim 4, wherein the first and second laser irradiating units irradiate the bonded substrate with the first and second laser beams simultaneously.

7. A method for manufacturing a semiconductor device using a semiconductor manufacturing apparatus including a first laser irradiation unit that irradiates a first laser onto an outer periphery of a bonded substrate including a first substrate and a second substrate bonded together, a second laser irradiation unit that irradiates a second laser onto the outer periphery of the bonded substrate, and a separation unit that separates the outer periphery of the bonded substrate, forming a modified layer by irradiating a first laser beam to an inside of the first substrate in an outer periphery of a bonded substrate including a first substrate and a second substrate bonded to each other; a second laser beam is irradiated onto a material layer disposed on the second substrate between the first substrate and the second substrate, thereby peeling off the material layer from the second substrate; separating an outer periphery of the first substrate and an outer periphery of the material layer from an outer periphery of the bonded substrate.

8. the first laser irradiation unit irradiates the first laser light from the first substrate side of the bonded substrate, The method according to claim 7 , wherein the second laser irradiating section irradiates the second laser light from a side of the bonded substrate facing the second substrate.

9. 9. The method of claim 7 or claim 8, wherein no device layer is provided within the material layer that reflects the second laser light.

Citation Information

Patent Citations

  • Laser processing method

    JP2014188581A

  • Processing device and processing method

    JP2020167303A

  • Substrate processing system, substrate processing method, and computer storage medium

    WO2019176589A1

  • Substrate processing system and substrate processing method

    WO2019208298A1

  • Substrate processing apparatus and substrate processing method

    WO2020105483A1