MOSFET Gate Engineering Using Dipolar Films

Abstract

A metal gate stack on a substrate includes an interfacial layer on the substrate, a high-k metal oxide layer on the interfacial layer, the high-k metal oxide layer including a dipole region adjacent the interfacial layer, the dipole region including niobium (Nb), a high-k metal oxide capping layer on the high-k metal oxide layer, a P-type metal oxide semiconductor (PMOS) work function material above the high-k metal oxide capping layer, and a gate electrode above the PMOS work function material, the dipole region being formed by driving Nb species of a Nb-based film into the high-k metal oxide layer to form the dipole region.

Description

[Technical field]

[0001]

[0001] Embodiments of the present disclosure generally relate to a niobium-containing dipole region formed from a niobium-based dipole film. In a particular embodiment, a high-k metal gate (HKMG) stack includes a high-k metal oxide layer including a dipole region and a work function material for PMOS (P-type metal oxide semiconductor). [Background technology]

[0002]

[0002] Integrated circuits have evolved into complex devices that may contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the feature size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased.

[0003]

[0003] As device dimensions shrink, device geometries and materials have become more difficult to maintain switching speeds without failure. Several new technologies have emerged that allow chip designers to continue to shrink device dimensions. Controlling the dimensions of device structures is a significant challenge for current and future technology generations.

[0004]

[0004] Microelectronic devices are fabricated on semiconductor substrates as integrated circuits in which various conductive layers are interconnected with each other, allowing electronic signals to propagate within the device. Examples of such devices include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) or MOSFETs (metal oxide semiconductor field effect transistors). A gate electrode is part of the integrated circuit. For example, a MOSFET includes a gate structure disposed between a source region and a drain region formed in a semiconductor substrate. The gate structure or stack generally includes a gate electrode and a gate dielectric. The gate electrode is disposed on top of the gate dielectric to control the flow of charge carriers in a channel region formed between the drain region and the source region below the gate dielectric.

[0005]

[0005] Threshold voltage (V t ) is conventionally tuned by inserting an interfacial dipole layer in the high-k / metal gate stack or by adding a work function tuning layer to the gate electrode. t The tuning methods may be incompatible with architectures for technology nodes below 10-15 nm.

[0006]

[0006] Therefore, as devices become smaller, the threshold voltage (V t What is needed is a system and method that can provide a device with Summary of the Invention

[0007]

[0007] One or more embodiments of the present disclosure are directed to a metal gate stack on a substrate, the metal gate stack including a P-type metal oxide semiconductor (PMOS) work function material above a high-k metal oxide capping layer, a high-k metal oxide layer, and an interfacial layer and below a gate electrode, the high-k metal oxide layer including a dipole region adjacent to the interfacial layer, the dipole region including niobium (Nb). The metal gate stack has an improved threshold voltage (V) compared to a comparative metal gate stack including a high-k metal oxide layer without a dipole region.t ).

[0008]

[0008] A further embodiment of the present disclosure is directed to a metal gate stack on a substrate, the metal gate stack including an interfacial layer on the substrate, a high-k metal oxide layer on the interfacial layer, the high-k metal oxide layer including a dipole region adjacent to the interfacial layer, the dipole region including niobium, a high-k metal oxide capping layer on the high-k metal oxide layer, a P-type metal oxide semiconductor (PMOS) work function material above the high-k metal oxide capping layer, and a gate electrode above the PMOS work function material.

[0009]

[0009] A further embodiment of the present disclosure is directed to a method of forming a dipole region, the method comprising forming an interfacial layer on a surface of a substrate, depositing a high-k metal oxide layer on the interfacial layer, forming a dipole film on the high-k metal oxide layer by exposing the surface of the substrate to a first precursor comprising niobium and optionally a second precursor comprising nitrogen, oxygen, or carbon using atomic layer deposition at a first substrate temperature ranging from 350°C to 500°C, depositing a first high-k metal oxide capping layer on the substrate, and exposing the substrate to a heat treatment at a second substrate temperature of at least 700°C to drive the dipole film into the high-k metal oxide layer and form a dipole region comprising niobium adjacent to the interfacial layer. The method may further comprise removing any remaining portion of the dipole film and the first high-k metal oxide capping layer.

[0010]

[0010] In order to understand the features of the present disclosure in detail, a more particular description of the present disclosure briefly summarized above can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the attached drawings illustrate only typical embodiments of the present disclosure, and the present disclosure may admit of other equally effective embodiments, and therefore the attached drawings should not be considered as limiting the scope of the present disclosure. [Brief description of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of a metal gate stack according to one or more embodiments of the present disclosure. [Diagram 2]

[0012] 1 is a flowchart of a method for forming a dipole region in accordance with one or more embodiments of the present disclosure. [Diagram 3]

[0013] 1 is a flowchart of a method for forming a metal gate stack in accordance with one or more embodiments of the present disclosure. [Figure 4]

[0014] 1 is a cluster tool in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0015] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of structure or process steps set forth in the following description as being capable of other embodiments and of being practiced or carried out in various ways.

[0013]

[0016] The term "substrate" as used herein and in the appended claims refers to a surface or a portion of a surface on which a process acts. It will also be appreciated by those skilled in the art that when reference is made to a substrate, it may refer to only a portion of the substrate unless the context clearly indicates otherwise. Furthermore, when reference is made to deposition on a substrate, it may refer to both a bare substrate and a substrate on which one or more films or features have been deposited or formed.

[0014]

[0017] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may undergo pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam (e-beam) cure, and / or bake the substrate surface. In addition to performing film processing directly on the substrate surface itself, the present disclosure also includes that any of the disclosed film processing steps are performed on an underlayer formed on the substrate, as described in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015]

[0018] Embodiments of the present disclosure provide superior PMOS performance, e.g., improved threshold voltage (V t Some embodiments of the present disclosure provide a metal gate stack having a high-k metal oxide layer that includes a dipole region that includes niobium (Nb) and / or titanium (Ti). The metal gate stack has an improved V t A comparative metal gate stack having a Ti / Nb / NiO2 film does not have such a dipole region. In some embodiments, the Ti and / or Nb are provided in the dipole region by forcing a niobium-based film into the high-k metal oxide layer.

[0016]

[0019] V in Nb-containing dipole regions t In performance experiments, V > +100mV t The results show an improvement in the equivalent oxide thickness (EOT) of 0.2 Å and no penalty in the equivalent oxide thickness (EOT) of 0.2 Å. 2 Hafnium oxide (HfO 2 ) was deposited on a high-k metal oxide layer containing NbCl at a substrate temperature of 450 °C. 5 and N.H. 3 Niobium nitride (NbN) films were deposited by atomic layer deposition using the precursor TiN. A high-k metal oxide capping layer of TiN was deposited in situ on the niobium-based film using PVD. The NbN film was driven into the high-k metal oxide layer by thermal treatment at a substrate temperature of at least 700 °C.

[0017]

[0020] Advantageously, the deposition of NbN and / or TiN by ALD was a linear process with stable and uniform growth, and advantageously, the step coverage of the silicon dioxide surface was greater than 95%.

[0018]

[0021] One or more embodiments of the present disclosure provide devices and methods of formation that are particularly useful in forming P-type metal oxide semiconductor (PMOS) integrated circuit devices and will be described in that context, although other devices and applications are within the scope of the invention.

[0019]

[0022] 1 illustrates a cross-sectional view of an exemplary PMOS metal gate stack device 100. The device 100 includes a substrate 110 that has a surface oxidized to form an interfacial layer 115. In some embodiments, the substrate 110 includes silicon and the interfacial layer 115 includes silicon dioxide. In some embodiments, the substrate includes additional electrical elements and materials, including, but not limited to, source regions, drain regions, conductive channels, and other electrical connectors.

[0020]

[0023] In accordance with one or more embodiments, the PMOS metal gate stack device 100 includes a gate dielectric or high-k metal oxide layer 120 having a dipole region 125, a high-k metal oxide capping layer 130, and a metal gate work function layer 140. As used herein, the metal gate work function layer 140 may also be referred to as a "PMOS work function material." The dipole region 125 is in the high-k metal oxide layer 120 adjacent to the interface layer 115.

[0021]

[0024] The high-k metal oxide layer 120 electrically insulates the metal gate workfunction layer 140 from the substrate 110. The high-k metal oxide layer 120 and the metal gate workfunction layer 140 together may be referred to herein as a metal gate stack. In some embodiments, the metal gate stack further includes a gate electrode 150 on the metal gate workfunction layer 140.

[0022]

[0025] In some embodiments, the gate dielectric 120 comprises a metal oxide. In some embodiments, the gate dielectric 120 comprises hafnium oxide (HfO 2 ).

[0023]

[0026] In some embodiments, the high-k capping layer 130 comprises or consists essentially of TiN. In some embodiments, the high-k capping layer comprises or consists essentially of TiSiN. As used in this context, "consists essentially of" means that the stated component is greater than 95%, greater than 98%, greater than 99%, or greater than 99.5% of the stated material on an atomic basis. For the avoidance of doubt, no stoichiometric ratio is implied by the identification of the materials disclosed herein. For example, a TiN material includes titanium and nitrogen. These elements may or may not be present in a 1:1 ratio.

[0024]

[0027] The high-k capping layer 130 may have any suitable thickness. In some embodiments, the thickness of the high-k capping layer 130 is in the range of 5 Å or more and 25 Å or less. In some embodiments, the thickness of the high-k capping layer is about 10 Å, including 10 ű10%, 10 ű5%, and / or 10 ű1%.

[0025]

[0028] In some embodiments, the high-k capping layer 130 comprises or consists essentially of TiN, hi some embodiments, the high-k capping layer 130 comprises or consists essentially of TiSiN.

[0026]

[0029] The PMOS workfunction material 140 includes any suitable material. The PMOS workfunction material 140 may have any suitable thickness. In some embodiments, the thickness of the PMOS workfunction material 140 ranges from 5 Å to 50 Å. In some embodiments, the thickness of the metal gate workfunction layer is about 15 Å, including 15 ű10%, 15 ű5%, and / or 15 ű1%.

[0027]

[0030] In some embodiments, the metal gate stack device 100 further includes a gate electrode 150. The gate electrode 150 may include multiple layers. In some embodiments, the gate electrode 150 includes a first layer including TiAl and a second layer including TiN. In some embodiments, the first layer has a thickness of 20 Å or more and 30 Å or less. In some embodiments, the first layer has a thickness of about 25 Å, including 25 ű10%. In some embodiments, the second layer has a thickness of about 500 Å, including 500 ű10%, 500 ű5%, and / or 500 ű1%. The first and second layers may be deposited by any suitable method.

[0028]

[0031] Threshold voltage (V t ) provides the properties of a metal gate stack. The inclusion of a Nb-containing dipole region (or a Ti-containing dipole region) in the high-k metal oxide layer of the metal gate stack increases V tIn one or more embodiments, the high-k metal oxide layer 120 is made of HfO 2 and Nb-containing dipole region (or Ti-containing dipole region), V t increases by more than +100mV.

[0029]

[0032] Equivalent oxide thickness (EOT) provides a characteristic of a metal gate stack. In one or more embodiments, a metal gate stack including a Nb-containing dipole region (or a Ti-containing dipole region) formed from a NbN dipole film (or a TiN dipole film) has an EOT of 0.2 Å or less compared to a comparable metal gate stack without a Nb-containing dipole region (or a TiN dipole region).

[0030]

[0033] In some embodiments, the p dipole metal comprises or consists essentially of titanium aluminum nitride (TiAlN). In some embodiments, the p dipole capping layer comprises or consists essentially of titanium silicon nitride (TiSiN). In some embodiments, there is no intentional air break between the deposition of TiAlN and TiSiN. In some embodiments, there is no amorphous silicon capping layer prior to annealing the p dipole layer and the p dipole cap.

[0031]

[0034] 2, another embodiment of the present disclosure relates to a method 200 of forming a dipole region. The method 200 begins in operation 210 by providing a substrate to a processing chamber.

[0032]

[0035] In operation 215, an interface layer is formed on the substrate. The formation of the interface layer is achieved by using nitrous oxide (N 2 The thermal oxidation process may include a suitable thermal oxidation process, such as an enhanced in situ steam generation (eISSG) process utilizing 203 gas. In one or more embodiments, the interfacial layer (e.g., 115 in FIG. 1) is a thin amorphous silicon oxide (SiO 2 ) layer having a thickness between about 3 Å and about 10 Å, e.g., about 5 Å, corresponding to one or more monolayers of silicon oxide.2 In some embodiments, the interface layer is a H 2 and O 2 In-situ steam generation (ISSG) process using gas, or NH 3 and O 2 It may be formed by a gas-based rapid thermal oxidation (RTO) process. The interfacial layer may act as a nucleation layer for a high-k gate dielectric layer (e.g., 120 in FIG. 1) that is deposited thereon.

[0033]

[0036] In operation 220, a high-k metal oxide layer is deposited on the interfacial layer. The high-k gate metal oxide layer is typically hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), ytterbium oxide (Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), high-k dielectric materials such as HfZrO, HfLaO xThe high-k dielectric film may be formed of a ternary high-k dielectric film having a third element doped into an existing metal oxide high-k dielectric host material such as HfTiO. The deposition process may include an atomic layer deposition (ALD) process. In the ALD process, a metal-containing precursor and an oxygen-containing precursor are alternately delivered to the interfacial layer. In some embodiments, the metal-containing precursor is purged before delivering the oxygen-containing precursor. The metal may be a transition metal such as hafnium (Hf), zirconium (Zr), or titanium (Ti), a rare earth metal such as lanthanum (La), ytterbium (Yb), or yttrium (Y), an alkaline earth metal such as strontium (Sr), or another metal such as aluminum (Al). For the oxidizer, any oxygen-containing precursor that may react with the metal may be used. For example, the oxygen-containing precursor may be or may include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen- and oxygen-containing precursor, plasma-enhanced oxygen, including locally or remotely enhanced oxygen, or any other material containing oxygen that may be incorporated into a metal to produce a layer of oxide of the metal on the interfacial layer. In one embodiment, the metal-containing precursor is hafnium tetrachloride (HfCl 4 ) and the oxidant is water (H 2 O) and hafnium dioxide (HfO 2 The ALD process may be performed at a temperature between 200° C. and about 400° C., such as about 270° C. The metal oxide layer deposited by the ALD process may be amorphous and may have a thickness between about 10 Å and about 30 Å.

[0034]

[0037] In operation 230, a dipole film is formed on the high-k metal oxide layer. In one or more embodiments, the dipole film is a niobium-containing film, such as a niobium nitride (NbN) film (or a titanium nitride film). The niobium-containing film (or titanium-containing film) is deposited by atomic layer deposition (ALD) at a substrate temperature ranging from 350° C. to 500° C. The ALD cycle is repeated to obtain a desired thickness of the NbN film (or TiN film), such as 5 Å to 10 Å. In some embodiments, the deposition of the dipole film is performed by blanket deposition of the dipole film over the entire exposed surface of the high-k gate dielectric layer, and subsequent lithography and etching processes to pattern the dipole film (i.e., to form a dipole film in some areas of the semiconductor structure and not form a dipole film in other areas of the semiconductor structure). In a subsequent thermal treatment (in operation 250), eg, an annealing process, the dopant species, eg, Nb, from the dipole film diffuses and becomes incorporated into the underlying high-k gate dielectric layer to form the dipole regions.

[0035]

[0038] In one or more embodiments, a dipole film is formed on a high dielectric constant metal oxide layer by exposing a surface of the substrate to a first precursor comprising niobium and optionally a second precursor comprising nitrogen, oxygen, or carbon using atomic layer deposition at a first substrate temperature ranging from 350° C. to 500° C. Generally, any suitable niobium precursor may be used. For NbN films, the niobium precursor may be, but is not limited to, NbCl. 5 , NbB 5 , NbBr 5 , NbI 5 , NbF 5 , organic niobium compounds, and combinations thereof. Nitrogen precursors may include, but are not limited to: NH 3 , N 2 , N 2 H 2 , N 2 H 4 , nitrogen-containing plasmas, and combinations thereof. Generally, any suitable titanium precursor may be used. For TiN films, titanium precursors include, but are not limited to, TiCl 5 , TiBr5 , TiI 5 , TiF 5 , organotitanium compounds, and combinations thereof. Nitrogen precursors include, but are not limited to, NH 3 , N 2 , N 2 H 2 , N 2 H 4 , nitrogen-containing plasma, and combinations thereof.

[0036]

[0039] In one or more embodiments, the first precursor comprises a first compound selected from the group consisting of: NbCl 5 , NbB 5 , NbBr 5 , NbI 5 , NbF 5 , NbOCl 3 , organic niobium compounds, and combinations thereof. In one or more embodiments, the first precursor comprises a first compound selected from the group consisting of: TiCl 5 , TiB 5 , TiBr 5 , TiI 5 , TiF 5 , TiOCl 3 , organotitanium compounds, and combinations thereof.

[0037]

[0040] In one or more embodiments, the second precursor comprises a second compound selected from the group consisting of: NH 3 , N 2 , N 2 H 2 , N 2 H 4 , nitrogen-containing plasma, and combinations thereof.

[0038]

[0041] In one or more embodiments, the second precursor is H 2 O, H 2 O 2 , O 3 , ethanol, and combinations thereof.

[0039]

[0042] In one or more embodiments, the second precursor comprises a second compound selected from the group consisting of: CH 4 , ethanol, and H 2 It is.

[0040]

[0043] In one or more embodiments, the second precursor comprises a combination of two or more second compounds selected from the group consisting of: NH 3 , C.H. 4 , ethanol, H 2 It is.

[0041]

[0044] In one or more embodiments, the first precursor is NbCl 5 and the second precursor is NH 3 In one or more embodiments, the first precursor comprises TiCl 5 and the second precursor is NH 3 Includes.

[0042]

[0045] In operation 240, a high-k metal oxide capping layer is deposited on the dipole film. In one or more embodiments, the high-k metal oxide capping layer is deposited by atomic layer deposition (ALD). In one or more embodiments, the high-k metal oxide capping layer comprises titanium nitride (TiN). An exemplary process for depositing TiN includes exposing the substrate to a first precursor comprising Ti and then exposing the substrate to a second precursor comprising a nitrogen source to provide a TiN film. In some embodiments, the substrate is repeatedly exposed to the precursors to obtain a predetermined film thickness. In some embodiments, the substrate is maintained at a temperature of about 200° C. to about 700° C. during the ALD process.

[0043]

[0046] In optional operation 245, a sacrificial silicon cap layer comprising an amorphous silicon (a-Si) material is deposited on the substrate. The sacrificial silicon cap layer may physically and chemically protect the underlying high-k metal oxide layer and the first high-k metal oxide capping layer during a subsequent thermal treatment process in operation 250. The sacrificial silicon cap layer is formed of amorphous silicon, such as hydrogenated amorphous silicon (a-Si:H). Amorphous silicon may have less atomic diffusion compared to polycrystalline silicon, where grain boundaries provide a pathway for diffusion. The deposition process in block 245 may be an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In that case, the semiconductor structure on which the first high-k metal oxide capping layer is to be formed is exposed to a silicon precursor. An example of a silicon precursor is polysilane (Si x H y For example, polysilanes include disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ), isotetrasilane, neopentasilane (Si 5 H 12 ), cyclopentasilane (Si 5 H 10 ), hexasilane (C 6 H 14 ), cyclohexasilane (Si 6 H 12 ), or generally, Si x H y where x=2 or more. x H y , and combinations thereof. The sacrificial silicon cap layer may have a thickness between about 30 Å and about 50 Å.

[0044]

[0047] In operation 250, the substrate is thermally treated to drive the dipole film into the high-k metal oxide layer and form dipole regions in the high-k metal oxide layer. The thermal treatment is performed to diffuse niobium (Nb) dopant species (or titanium dopant species) into the underlying high-k gate metal oxide layer. In one or more embodiments, the thermal treatment of operation 250 includes a post cap anneal (PCA) process. The PCA process is performed to harden and densify the first high-k metal oxide capping layer. Crystallization of the as-deposited first high-k metal oxide capping layer and any as-deposited sacrificial silicon cap layer may occur. The PCA process may include an anneal process. The anneal process may be performed in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif., using nitrogen (N 2 ) and a thermal annealing process in an inert atmosphere, such as an argon (Ar) atmosphere.

[0045]

[0048] The thermal treatment of operation 250 may be performed for between about 1 second and about 30 seconds, at a temperature between about 600° C. and about 1000° C., for example about 900° C., and at a pressure between about 0.1 Torr and 100 Torr.

[0046]

[0049] In operation 260, according to one or more embodiments, any remaining portions of the bipolar film are removed along with the high-k metal oxide capping layer. The removal process may include a dry plasma etching process. The resulting structure including the high-k metal oxide layer with doped regions may then be further processed to suit a desired application.

[0047]

[0050] Aspects herein include a method of forming a dipole region, the method including forming an interfacial layer on a surface of a substrate, depositing a high-k metal oxide layer on the interfacial layer, forming a dipole film on the high-k metal oxide layer by exposing the surface of the substrate to a first precursor comprising niobium (or titanium) and optionally a second precursor comprising nitrogen, oxygen, or carbon using atomic layer deposition at a first substrate temperature ranging from 350° C. to 500° C., depositing a first high-k metal oxide capping layer on the substrate, and exposing the substrate to a heat treatment at a second substrate temperature of at least 700° C. to drive the dipole film into the high-k metal oxide layer and form a dipole region comprising niobium (or titanium) adjacent the interfacial layer.

[0048]

[0051] In one or more embodiments, the method further includes removing any remaining portions of the bipolar film and the first high dielectric constant metal oxide capping layer.

[0049]

[0052] Referring to FIG. 3, another embodiment of the present disclosure relates to a method 300 of forming a metal gate stack device 100. The method 300 begins at 310 by providing a substrate in a first processing chamber. In operation 315, an interface layer is formed on the substrate, following operation 215 described with respect to FIG. 2. In operation 320, a high-k metal oxide layer is deposited on the interface layer, following operation 220 described with respect to FIG. 2. In operation 330, a dipole film is formed on the high-k metal oxide layer, following operation 230 described with respect to FIG. 2. In operation 340, a high-k metal oxide capping layer is deposited on the dipole film, following operation 240 described with respect to FIG. 2.

[0050]

[0053] In one or more embodiments, a high dielectric constant metal oxide capping layer is deposited on the bipolar film in situ, in that the same processing (first) chamber is used for both operations 330 and 340 .

[0051]

[0054] In optional operation 345, a sacrificial silicon cap layer comprising amorphous silicon (a-Si) material is deposited over the substrate, following operation 245 described with respect to FIG.

[0052]

[0055] After deposition of the high-k metal oxide capping layer, according to one or more embodiments, the substrate is transferred to a different (second) processing chamber for operation 350. In some embodiments, the first and second processing chambers are integrated. In some embodiments, method 300 is performed without breaking vacuum or exposure to ambient air.

[0053]

[0056] In operation 350, the substrate is heat treated to drive the dipole film into the high-k metal oxide layer and form a dipole region in the high-k metal oxide layer. In operation 360, any remaining portions of the dipole film are removed along with the high-k metal oxide capping layer. Then, in operation 370, another (second) high-k metal oxide capping layer is deposited on the high-k metal oxide layer. In operation 380, a PMOS work function material is deposited on the second high-k metal oxide capping layer. In operation 390, a gate material is deposited on the PMOS work function material.

[0054]

[0057] Many precursors are within the scope of the present invention. Precursors can be plasmas, gases, liquids, or solids at ambient temperature and pressure. However, in the ALD chamber, the precursors volatilize. Organometallic compounds or complexes include any chemical that contains a metal and at least one organic group, such as alkyl, alkoxyl, alkylamide, and anilide groups. Precursors can consist of organometallic and inorganic / halogen compounds.

[0055]

[0058] Generally, any suitable titanium precursor may be used for the high dielectric constant capping layer. Thus, titanium precursors include, but are not limited to, TiCl 4 , TiBr 4 , TiI 4 , TiF 4Additionally, any suitable nitrogen source precursor may be used. Examples include, but are not limited to, nitrogen gas, ammonia gas, N 2 H 2 , or N 2 H 4 Includes.

[0056]

[0059] Aspects herein are directed to a method of manufacturing a metal gate stack. The method includes forming an interfacial layer on a surface of a substrate in a first processing chamber; depositing a high-k metal oxide layer on the interfacial layer in the first processing chamber; forming a dipole film on the high-k metal oxide layer by exposing the surface of the substrate to a first precursor comprising niobium (or titanium) and optionally exposing to a second precursor comprising nitrogen, oxygen, or carbon in the first processing chamber using atomic layer deposition at a first substrate temperature in the range of 350° C. to 500° C.; depositing a first high-k metal oxide capping layer on the substrate in the first processing chamber; transferring the substrate to a second processing chamber; exposing the substrate to a thermal treatment in the second processing chamber at a second substrate temperature in the range of 700° C. to 1050° C. to drive the dipole film into the high-k metal oxide layer and form a dipole region comprising niobium (or titanium) adjacent the interfacial layer; and removing the first high-k metal oxide capping layer and any remaining portions of the dipole film.

[0057]

[0060] In one or more embodiments, the method further includes depositing a second high dielectric constant metal oxide capping layer over the substrate.

[0058]

[0061] In one or more embodiments, the method further includes depositing a PMOS work function material over the substrate.

[0059]

[0062] In one or more embodiments, the method further includes depositing a gate material onto the substrate.

[0060]

[0063] In one or more embodiments, the first high-k metal oxide capping layer comprises titanium nitride (TiN) and the high-k metal oxide layer comprises hafnium oxide (HfO 2 ), and the interface layer is silicon dioxide (SiO 2 ).

[0061]

[0064] In one or more embodiments, the method further includes depositing a second high dielectric constant metal oxide capping layer comprising TiN.

[0062]

[0065] In one or more embodiments, forming the interfacial layer includes oxidizing the surface of the substrate prior to depositing the high dielectric constant metal oxide layer.

[0063]

[0066] The order in which the substrate is exposed to the precursors can be varied. The exposures may be repeated in a deposition cycle. Further, the exposure to the precursors may be repeated within a single deposition cycle.

[0064]

[0067] In some embodiments, a process for forming a MOSFET includes 1) forming a gate dielectric (e.g., interlayer dielectric / high-k dielectric); 2) depositing a p-dipole metal layer comprising TiAlN that is deposited on the gate dielectric by ALD or other process; 3) transferring the wafer from the ALD chamber to include an intentional air break to allow oxygen to react with the TiAlN; 4) depositing a dipole capping layer comprising TiSiN by ALD or other technique; 5) thermal anneal by RTP at 700-900° C. (without a-Si cap); and 6) stripping the capping layer.

[0065]

[0068] Some embodiments of the present disclosure are directed to a metal gate stack on a substrate, the metal gate stack including a P-type metal oxide semiconductor (PMOS) work function material above a high-k metal oxide capping layer, a high-k metal oxide layer, and an interfacial layer, and below a gate electrode. The high-k metal oxide layer includes a dipole region adjacent to the interfacial layer. The dipole region includes titanium aluminum nitride (TiAlN). The metal gate stack then has an improved threshold voltage (V) compared to a comparable metal gate stack including a high-k metal oxide layer without a dipole region. t ).

[0066]

[0069] Further embodiments of the present disclosure are directed to a method of forming a dipole region, the method including forming an interfacial layer on a surface of a substrate, depositing a high-k metal oxide layer on the interfacial layer, forming a dipole film on the high-k metal oxide layer by exposing the surface of the substrate to a first precursor comprising titanium and optionally a second precursor comprising nitrogen, oxygen, or carbon using atomic layer deposition at a first substrate temperature ranging from 350° C. to 500° C., depositing a first high-k metal oxide capping layer on the substrate, and exposing the substrate to a heat treatment at a second substrate temperature of at least 700° C. to drive the dipole film into the high-k metal oxide layer and form a dipole region comprising titanium adjacent the interfacial layer.

[0067]

[0070] The methods of the present disclosure may be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is transferred from a first chamber to a separate second chamber for further processing. The substrate may be transferred directly from the first chamber to another processing chamber, or may be transferred from the first chamber to one or more transfer chambers and then to another processing chamber. Thus, a suitable processing apparatus may include multiple chambers in communication with a transfer station. This type of apparatus may be referred to as a "cluster tool" or a "cluster system", etc.

[0068]

[0071] Generally, a cluster tool is a modular system with multiple chambers that perform various functions, including center detection and orientation, degassing, annealing, deposition, and / or etching of the substrate. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber may house a robot capable of transferring substrates to and from the processing chambers and the load lock chambers. The transfer chamber is typically maintained at reduced pressure and provides an intermediate stage for transferring substrates to and from one chamber to another chamber and / or the load lock chamber located at the front end of the cluster tool. Two well-known cluster tools that may be adapted for the present disclosure are the Centura® and Endura®, both available from Applied Materials, Inc., Santa Clara, Calif. However, the exact arrangement and combination of chambers may be altered for the purposes of performing the specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal processing such as RTP, plasma nitridation, annealing, alignment, hydroxylation, and other substrate processing. By performing processing in a chamber on a cluster tool, surface contamination of the substrate from airborne impurities can be avoided without oxidation prior to depositing a subsequent film.

[0069]

[0072] In some embodiments, the first processing chamber and the second processing chamber are part of the same clustered processing tool. Thus, in some embodiments, the method is an in-situ integrated method.

[0070]

[0073] In some embodiments, the first processing chamber and the second processing chamber are different processing tools, and thus, in some embodiments, the method is an ex-situ integrated method.

[0071]

[0074] According to one or more embodiments, the substrate is continuously under reduced pressure or "load-lock" conditions and is not exposed to ambient air when it is transferred from one chamber to the next. The transfer chamber is therefore under reduced pressure and is "pumped down" to reduced pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent the transfer of reactants from the deposition chamber to the transfer chamber and / or further processing chambers. Thus, a flow of inert gas forms a curtain at the outlet of the chamber.

[0072]

[0075] Substrates may be processed in a single substrate deposition chamber where a single substrate is loaded, processed, and unloaded before another substrate is processed. Substrates may also be processed in a continuous manner similar to a conveyor system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The geometry of the chamber and associated conveyor system may form a linear or curved path. Additionally, the processing chamber may be a carousel, where multiple substrates move around a central axis and undergo deposition, etching, annealing, and / or cleaning processes throughout the carousel path.

[0073]

[0076] The substrate can also be stationary or rotated during the process. A rotating substrate can be rotated continuously or in non-continuous steps. For example, the substrate can be rotated throughout the entire process, or the substrate can be rotated in small increments between exposures to various reactive or purge gases. Rotating the substrate (either continuously or in steps) during processing can, for example, minimize the effects of local variability in gas flow profiles, helping to produce a more uniform deposition or etching.

[0074]

[0077] In an atomic layer deposition chamber, a substrate can be exposed to a first and a second precursor in a spatially or temporally separated process. Temporal ALD is a conventional process in which a first precursor is flowed into the chamber and reacts with the surface. Before flowing the second precursor, the first precursor is purged from the chamber. In spatial ALD, the first and second precursors are both flowed into the chamber at the same time, but are spatially separated such that there is a region between the flows that prevents the precursors from mixing. In spatial ALD, the substrate is moved relative to the gas distribution plate or vice versa.

[0075]

[0078] In embodiments where one or more of the method parts are carried out in one chamber, the process may be a spatial ALD process. Although one or more of the above chemical properties may be incompatible (i.e., resulting in reaction other than on the substrate surface and / or deposition on the chamber), the spatial separation ensures that the reagents in the gas phase are not exposed to each other. For example, temporal ALD involves purging of the deposition chamber. However, in practice, it may sometimes be impossible to purge excess reagents out of the chamber before flowing in additional reagents. Thus, any remaining reagents in the chamber may react. With spatial separation, there is no need to purge excess reagents, limiting cross contamination. Furthermore, it may take a lot of time to purge a chamber, and therefore, eliminating the purge step may increase throughput.

[0076]

[0079] Referring to FIG. 4, further embodiments of the present disclosure are directed to a processing system 900 for performing the methods described herein. FIG. 4 illustrates a system 900 that may be used to process substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910 having a robot 912 therein. The robot 912 is shown as a single blade robot, but one of ordinary skill in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers coupled to the central transfer station 910.

[0077]

[0080] At least one pre-clean / buffer chamber 920 is coupled to the central transfer station 910. The pre-clean / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-clean / buffer chamber 920 may be used as a holding area for individual semiconductor substrates or for a cassette of wafers for processing. The pre-clean / buffer chamber 920 may perform a pre-clean process or may pre-heat the substrate for processing, or may simply be a staging area for a processing sequence. In an embodiment, there are two pre-clean / buffer chambers 920 coupled to the central transfer station 910.

[0078]

[0081] 4, a pre-clean chamber 920 may act as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 for moving substrates from a cassette to the pre-clean / buffer chamber 920. A robot 912 may then move the substrate from the pre-clean / buffer chamber 920 to other chambers in the system 900.

[0079]

[0082] A first processing chamber 930 may be connected to the central transfer station 910. The first processing chamber 930 may be configured for thermal oxidation to form an interface layer on the substrate. The substrate may be moved by a robot 912 to and from the processing chamber 930 through a shutoff valve 914.

[0080]

[0083] Processing chambers 940 may also be connected to the central transfer station 910. In some embodiments, the processing chambers 940 include atomic layer deposition chambers for depositing a high-k gate metal oxide layer and are in fluid communication with one or more reactive gas sources to provide a flow of reactive gas to the processing chambers 940. In some embodiments, the processing chambers 940 include atomic layer deposition chambers for depositing a dipole film and are in fluid communication with one or more reactive gas sources to provide a flow of reactive gas to the processing chambers 940. In some embodiments, the processing chambers 940 include atomic layer deposition chambers for depositing a high-k gate metal oxide capping layer and are in fluid communication with one or more reactive gas sources to provide a flow of reactive gas to the processing chambers 940. Substrates may be moved to and from the processing chambers 940 by the robot 912 through the shutoff valves 914.

[0081]

[0084] In some embodiments, a processing chamber 960 is connected to the central transfer station 910 and configured to thermally process substrates.

[0082]

[0085] In some embodiments, other processing chambers may be configured to perform further portions of the processing method, including removing any remaining dipole film and first high-k metal oxide capping layer, depositing a second high-k capping layer, depositing a PMOS work function material, and depositing a gate electrode material. Those skilled in the art will recognize that the number and arrangement of individual processing chambers on a tool can vary, and the embodiment shown in FIG. 4 represents just one possible configuration.

[0083]

[0086] In some embodiments, the processing system 900 includes one or more metrology stations. For example, a metrology station may be located within the pre-clean / buffer chamber 920, the central transfer station 910, or within any of the individual processing chambers. The metrology station may be any location within the system 900 that is capable of measuring the recessed distance without exposing the substrate to an oxidizing environment.

[0084]

[0087] At least one controller 950 is coupled to one or more of the central transfer station 910, the pre-clean / buffer chamber 920, the processing chambers 930, 940, or 960. In an embodiment, there are two or more controllers 950 connected to individual chambers or stations, and a main control processor is connected to each of the individual processors to control the system 900. The controller 950 may be one of any form of general purpose computer processor, microcontroller, microprocessor, etc. that may be used in an industrial environment to control various chambers and sub-processors.

[0085]

[0088] At least one controller 950 may include a processor 952, a memory 954 coupled to the processor 952, input / output devices 956 coupled to the processor 952, and support circuits 958 for communicating between various electronic components. The memory 954 may include one or more of a transient memory (e.g., random access memory) and a non-transient memory (e.g., a storage device).

[0086]

[0089] The processor's memory 954 or computer readable medium may be one or more of readily available memory, such as random access memory (RAM), read only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The memory 954 may hold a set of instructions executable by the processor 952 to control parameters and components of the system 900. The support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. For example, the circuits may include cache, power supplies, clock circuits, input / output circuits, subsystems, and the like.

[0087]

[0090] The process may generally be stored in memory as a software routine. When executed by a processor, the software routine causes the process chamber to perform the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the process may be implemented in software and implemented in hardware using a computer system, for example as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into a special-purpose computer (controller) that controls the chamber operation to perform the process.

[0088]

[0091] In some embodiments, controller 950 has one or more configurations for executing individual processes or sub-processes to perform the method. Controller 950 may be connected or configured to operate intermediate components to perform the functions of the method. For example, controller 950 may be connected and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum controls, etc.

[0089]

[0092] The controller 950 in some embodiments includes one or more of the following: a configuration for moving a substrate on a robot between multiple processing chambers and a metrology station, a configuration for loading and / or unloading a substrate to / from the system, a configuration for forming an interface layer on a surface of a substrate, a configuration for depositing a high-k metal oxide layer, a configuration for depositing a niobium-containing (e.g., NbN) film, a configuration for depositing a first high-k metal oxide capping layer, a configuration for heat treating the substrate to drive the Nb-containing film into the high-k metal oxide layer, a configuration for removing any remaining Nb-containing film and the first high-k metal oxide capping layer, a configuration for depositing a second high-k metal oxide capping layer, a configuration for depositing a PMOS work function material, and / or a configuration for depositing a gate electrode.

[0090]

[0093] References throughout this specification to "one embodiment," "certain embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0091]

[0094] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the present invention cover such modifications and variations as come within the scope of the appended claims and their equivalents.

Claims

1. A metal gate stack on a substrate, the metal gate stack comprising a P-type metal oxide semiconductor (PMOS) work function material above a high-k metal oxide capping layer, a high-k metal oxide layer, and an interfacial layer and below a gate electrode, the high-k metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb), the metal gate stack exhibiting an improved threshold voltage (V t ), wherein an increase in equivalent oxide thickness (EOT) of the metal gate stack including the high-k metal oxide layer including the dipole region containing Nb is +0.2 Å or less compared to the metal gate stack including the comparative high-k metal oxide layer without the dipole region.

2. The above V t The metal gate stack of claim 1 , wherein the metal gate stack improves by more than +100 mV.

3. The high-k metal oxide capping layer comprises titanium nitride (TiN), and the high-k metal oxide layer comprises hafnium oxide (HfO 2 ), and the interface layer comprises silicon dioxide (SiO 2 2. The metal gate stack of claim 1, comprising:

4. A metal gate stack on a substrate, comprising: an interface layer on the substrate; a high dielectric constant metal oxide layer on the interfacial layer, the high dielectric constant metal oxide layer including a dipole region adjacent the interfacial layer, the dipole region including niobium (Nb); a high dielectric constant metal oxide capping layer on said high dielectric constant metal oxide layer; a P-type metal oxide semiconductor (PMOS) work function material over the high dielectric constant metal oxide capping layer; and A gate electrode above the PMOS work function material Including, A metal gate stack, wherein an increase in equivalent oxide thickness (EOT) of the metal gate stack including the high dielectric constant metal oxide layer including the dipole region containing Nb is +0.2 Å or less compared to a comparison metal gate stack including a high dielectric constant metal oxide layer without the dipole region.

5. The high-k metal oxide capping layer comprises titanium nitride (TiN), and the high-k metal oxide layer comprises hafnium oxide (HfO 2 ), and the interface layer comprises silicon dioxide (SiO 2 5. The metal gate stack of claim 4, comprising:

6. The metal gate stack has a threshold voltage (V) in the range of +100 mV or more compared to the comparison metal gate stack including a high-k metal oxide layer without the dipole region. t 5. The metal gate stack of claim 4 having the improvement:

7. 1. A method of forming a dipole region, comprising the steps of: forming an interface layer on a surface of a substrate; depositing a high dielectric constant metal oxide layer over said interfacial layer; forming a dipole film on the high dielectric constant metal oxide layer by exposing the surface of the substrate to a first precursor comprising niobium and optionally to a second precursor comprising nitrogen, oxygen, or carbon using atomic layer deposition at a first substrate temperature in the range of 350° C. to 500° C.; depositing a first high dielectric constant metal oxide capping layer over the substrate; and exposing the substrate to a heat treatment at a second substrate temperature of at least 700° C. to drive the dipole film into the high dielectric constant metal oxide layer and form a dipole region comprising niobium adjacent the interfacial layer.

8. The method of claim 7 further comprising removing any remaining portions of the dipole film and the first high dielectric constant metal oxide capping layer.

9. 9. The method of claim 8, further comprising depositing a second high dielectric constant metal oxide capping layer on the substrate after removing the first high dielectric constant metal oxide capping layer and any remaining portions of the dipole film.

10. The first high-k metal oxide capping layer comprises titanium nitride (TiN), and the high-k metal oxide layer comprises hafnium oxide (HfO 2 ), and the interface layer comprises silicon dioxide (SiO 2 8. The method of claim 7, comprising:

11. The first precursor is NbCl 5 , NbB 5 , NbBr 5 , NbI 5 , NbF 5 , NbOCl 3 8. The method of claim 7, comprising a first compound selected from the group consisting of: an organo-niobium compound, an organoniobium compound, and combinations thereof.

12. The second precursor is NH 3 , N 2 , N 2 H 2 , N 2 H 4 12. The method of claim 11, comprising a second compound selected from the group consisting of a nitrogen-containing plasma, a nitrogen-containing plasma, and combinations thereof.

13. The second precursor is H 2 O, H 2 O 2 , O 3 12. The method of claim 11, further comprising a second compound selected from the group consisting of: ethanol, and combinations thereof.

14. The second precursor is CH 4 , ethanol, and H 2 12. The method of claim 11 , comprising a second compound selected from the group consisting of:

15. The second precursor is NH 3 , C.H. 4 , ethanol, H 2 12. The method of claim 11, comprising a combination of two or more second compounds selected from the group consisting of:

16. The first precursor is NbCl 5 and the second precursor comprises NH 3 The method of claim 11 , comprising:

17. 8. The method of claim 7, wherein depositing the first high-k metal oxide capping layer and forming the dipole film on the high-k metal oxide layer both occur in a first chamber.

18. The method of claim 9 , further comprising depositing a PMOS work function material on the substrate.

19. The method of claim 18 , further comprising depositing a gate material onto the substrate.

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