High electron mobility transistor structure, its manufacturing method and use

Abstract

This application discloses a high electron mobility transistor structure and its manufacturing method and application. The high electron mobility transistor structure comprises an epitaxial structure, a source, a drain and a gate, the epitaxial structure comprises a first semiconductor layer and a second semiconductor layer, a carrier channel is formed between the first semiconductor layer and the second semiconductor layer, the source and the drain are electrically connected through the carrier channel, and the overlap rate between the orthogonal projection of the grid foot of the gate on the first semiconductor layer and the orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more. The GaN electronic device structure of this application does not have an access region between the gate-source and the gate-drain, and effectively regulates the entire carrier channel with the gate, and is advantageous in realizing the reduction of velocity saturation and device knee-point voltage. GS The nonlinear effects induced by resistive degradation can be eliminated.

Description

[Technical field]

[0001] The present application relates to the technical field of semiconductor devices, specifically to a high electron mobility transistor structure and its manufacturing method and applications. [Background technology]

[0002] Gallium nitride (GaN), a new generation broadband semiconductor material, has high breakdown voltage (3.1MV / cm), high electron mobility (~1500cm 2 / V·s) and the polarization effect allows GaN-based heterostructures (e.g. AlGaN / GaN, AlInGaN / GaN, AlN / GaN, etc.) to form high density 2DEG (two-dimensional electron gas) without intentional doping, making them the best choice for lateral HEMTs (high-electron-mobility transistors), a new generation of electronic devices. GaN HEMTs have great features such as high current density, high voltage resistance, and high frequency, and are being applied to 5G core infrastructure such as base stations as RF power amplifiers (PAs), gradually replacing conventional silicon-based LDMOS (lateral double-diffused metal-oxide-semiconductor) devices, and will continue to play an important role in the overall 5G communication technology.

[0003] In the more promising field of consumer electronics, silicon-based GaN HEMTs for RF (Radio Frequency, RF) / MM Wave (Milimeter Wave) applications, with their low cost advantages, are also attractive products. Compared with conventional gallium arsenide (GaAs) HBTs (Heterojunction Bipolar Transistors), GaN HEMTs achieve higher output power and better heat dissipation performance, which gives them an essential advantage in 5G communication services that require higher power, and they are expected to be adopted for the transmit PA of mobile phone RF front-end modules. However, GaN RF HEMTs for mobile terminals have not yet appeared. The reason is that conventional GaN HEMTs have access regions between the device gate-source and gate-drain along the channel direction, which creates a large proportion of series resistance R ac As shown in Figure 1, the introduction of drastically reduces the voltage applied to both sides of the channel under the gate, physically restricting the saturation behavior of the device output current, causing pinch-off saturation to occur prior to velocity saturation, and the device V knee The operating voltage of mobile phones is generally low, at 3 to 5 V, so the large V knee (generally 2 to 3 V) significantly limits low-voltage applications and does not take full advantage of its high power density. On the other hand, the conventional GaN HEMT structure has a channel resistance R GS Inevitably, under the action of high electric fields, nonlinear effects closely related to electron mobility degradation will occur, degrading the output current and linearity, greatly limiting the application of PAs to mobile smart terminals. In addition, with the current device structure and process technology, it is very difficult to fabricate GaN HEMTs for RF applications.

[0004] To solve the above problems, a practical solution is to make the source-drain spacing as short as possible, as long as semiconductor process technology allows. This allows a high electric field to be built between the source and drain with a small source-drain voltage, so that pinch-off saturation occurs prior to velocity saturation, effectively lowering the knee-point voltage. At present, some researchers can fabricate GaN HEMTs with a source-drain spacing of 130 nm by sidewall process technology, and some researchers can fabricate short-channel (<500 nm) GaN HEMTs by traditional photolithography and electron beam exposure processes. However, the devices fabricated by the above solutions all cannot avoid the access regions between the gate-source and gate-drain, so the linearity degradation at high output currents is more serious.

[0005] On the other hand, it is very difficult to manufacture enhancement-type GaN HEMTs for RF (and mmWave) with conventional solutions, and due to the practical requirements of simplifying the system and reducing the chip area, the enhancement-type operation mode of PA is necessary for the RF front-end of mobile smart terminals. Currently, only Intel manufactures enhancement-type GaN RF HEMTs worldwide using slow etching technology with potential barrier layers, but this technology has very high requirements for etching precision and controllability, which are difficult to realize. In addition, other researchers have proposed p-NiO gate technology to develop enhancement-type GaN RF HEMTs, but there are problems with the difficulty of p-type NiO growth and poor thermal stability. Summary of the Invention [Problem to be solved by the invention]

[0006] The main objective of the present application is to provide a T-shaped grid near-total grid control high electron mobility transistor structure, in which a composite layer consisting of a heavily doped ohmic contact layer and a high resistance layer is used as a support layer, and spatial isolation is realized by using air and the heavily doped ohmic contact layer, and a manufacturing method and application thereof, in order to overcome the shortcomings of the prior art. [Means for solving the problem]

[0007] In order to achieve the objectives of the above application, the present application adopts the following technical solutions: One aspect of the present application provides a high electron mobility transistor structure, an epitaxial structure including a heterojunction composed of a first semiconductor layer and a second semiconductor layer, in which a carrier channel is formed between the first semiconductor layer and the second semiconductor layer; a source, a drain and a gate electrically connected through the carrier channel and interdigitated with the epitaxial structure; The overlap rate between the orthogonal projection of the grid foot of the gate on the first semiconductor layer and the orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more.

[0008] An aspect of the present application provides another high electron mobility transistor structure, comprising an epitaxial structure and a source, a drain and a gate interdigitated with the epitaxial structure, the epitaxial structure includes a heterojunction, a carrier channel is formed within the heterojunction, the carrier channel is distributed within an area covered by an orthogonal projection of the gate on the epitaxial structure, the epitaxial structure further includes a heavily doped region and a highly resistive region, the heavily doped region is disposed on the heterojunction and forms an ohmic contact with the carrier channel, both the source and drain form ohmic contacts with the heavily doped region, the highly resistive region is disposed on the heavily doped region, and the source and gate, and the drain and gate are separated by the highly resistive region.

[0009] Another aspect of the present application provides a method for manufacturing a high electron mobility transistor structure, comprising: fabricating an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; a source, drain and gate interconnected with said epitaxial structure, said source and drain being electrically connected through said carrier channel; The step of manufacturing a gate includes setting a size of the grid foot of the gate to satisfy a condition that an overlap rate between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more, i.e., the orthogonal projection of the grid foot on the first semiconductor layer covers most of the orthogonal projection of the second semiconductor layer on the first semiconductor layer.

[0010] Another aspect of the present application provides a method for manufacturing a high electron mobility transistor structure, comprising: forming a heterojunction by sequentially providing a first semiconductor layer and a second semiconductor layer, and distributing carrier channels in the heterojunction within an area covered by an orthogonal projection on an epitaxial structure of a gate; forming a heavily doped region and a highly resistive region on the heterojunction, providing the highly resistive region on the heavily doped region, and making an ohmic contact between the heavily doped region and the carrier channel to form an epitaxial structure; forming a source, a drain and a gate interfacing with the epitaxial structure, the source and drain both forming ohmic contacts with heavily doped regions, and the source and gate, and the drain and gate, being separated by highly resistive regions.

[0011] Another aspect of the present application provides the use of said high electron mobility transistor structure in the manufacture of power amplifiers, RF devices, communication devices or electronic devices.

[0012] Another aspect of the present application provides a power amplifier having the above-described high electron mobility transistor structure. Effect of the Invention

[0013] Compared with the prior art, the present invention has the following beneficial effects: 1) The high electron mobility transistor structure provided by the embodiments of the present application does not have access regions between the gate-source and gate-drain, and effectively regulates the entire two-dimensional electron gas carrier channel with the gate, thereby eliminating the nonlinear effect induced by RGS resistance degradation in realizing the reduction of velocity saturation and device knee-point voltage. 2) The high electron mobility transistor structures provided by the embodiments of the present application have high reliability, stability and transconductance, which contribute to a significant increase in the power gain of RF power amplifiers. 3) The manufacturing method of the high electron mobility transistor structure provided in the embodiments of the present application adopts a self-alignment process and secondary epitaxial technology, uses a composite material made of a heavily doped layer and a highly resistive layer as a supporting layer, and uses air and a heavily doped ohmic contact layer to isolate the space, and directly constructs a T-shaped grid between the source and drain, thereby manufacturing a high electron mobility transistor structure that realizes a short channel, near total grid control, series resistance with almost no access area, and low parasitic effect, which can effectively reduce the device knee-point voltage and improve the device linearity, while at the same time improving the frequency characteristics, output efficiency and reliability of the device. 4) The high electron mobility transistor structure provided by the embodiment of the present application is B By adopting a heterojunction epitaxial structure with a thin potential barrier without requiring a gate etching process, an enhancement-mode device can be manufactured. The thin potential barrier material structure gives the device a large mutual conductance, which can contribute to improving the gain of RF power amplifiers. [Brief description of the drawings]

[0014] In order to more clearly describe the technical solutions in the embodiments of the present application or the prior art, the necessary drawings used in the description of the embodiments or the prior art will be briefly described. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative labor.

[0015] [Figure 1] FIG. 1 is a schematic diagram showing a high electron mobility transistor structure in the prior art. [Diagram 2] FIG. 1 is a schematic diagram showing a structure of a near-total grid control GaN RF HEMT according to a representative embodiment of the present application. [Figure 3a] FIG. 1 is a schematic diagram showing a GaN HEMT epitaxial structure according to a first embodiment of the present application. [Figure 3b] FIG. 3b is a schematic diagram showing the case where a T-shaped grid foot size is defined in the epitaxial structure shown in FIG. 3a using an HSQ electrophotoresist in Example 1 of the present application. [Figure 3c] FIG. 3B is a schematic diagram showing the HSQ electrophotoresist in FIG. 3A of Example 1 of the present application after annealing and hardening treatment; [Figure 3d] FIG. 4 is a schematic diagram showing the device structure shown in FIG. 3c in Example 1 of the present application after etching source-drain ohmic contact regions. [Figure 3e] FIG. 3C is a schematic diagram showing the device structure shown in FIG. 3D of Example 1 of the present application after secondary epitaxy of an ohmic contact layer. [Figure 3f] FIG. 3C is a schematic diagram showing the device structure shown in FIG. 3E of Example 1 of the present application after removing the hardened HSQ electrophotoresist. [Figure 3g] FIG. 3C is a schematic diagram showing the device structure of Example 1 of the present application after the active region is isolated as shown in FIG. 3F. [Figure 3h] FIG. 3C is a schematic diagram showing the device structure shown in FIG. 3g of Example 1 of the present application after a dielectric layer has been deposited on the device structure. [Figure 3i]FIG. 3H is a schematic diagram showing the device structure of Example 1 of the present application after a T-shaped grid is formed on the device structure shown in FIG. 3H. [Figure 3j] FIG. 3i is a schematic diagram showing the device structure of Example 1 of the present application after a source and a drain are formed. [Figure 4a] FIG. 4 is a schematic diagram showing the device structure shown in FIG. 3c of Example 2 of the present application after a dielectric layer has been deposited on the device structure shown in FIG. 3c. [Figure 4b] FIG. 4B is a schematic diagram showing the case after forming a dielectric sidewall on the sidewall of the cured HSQ electrophotoresist in FIG. 4A of Example 2 of the present application. [Figure 4c] FIG. 4C is a schematic diagram showing the device structure of Example 2 of the present application after etching the source-drain ohmic contact regions shown in FIG. 4B. [Figure 4d] FIG. 4C is a schematic diagram showing an ohmic contact layer on the device structure shown in FIG. 4C of Example 2 of the present application after secondary epitaxy. [Figure 4e] FIG. 4C is a schematic diagram showing the device structure of FIG. 4D in Example 2 of the present application after the active region is isolated. [Figure 4f] FIG. 4E is a schematic diagram showing the device structure of the second embodiment of the present application after a source and a drain are formed on the device structure shown in FIG. 4E. [Figure 4g] FIG. 4C is a schematic diagram showing the device structure shown in FIG. 4F of Example 2 of the present application after a sacrificial layer is spin-coated onto the device structure. [Figure 4h] FIG. 4C is a schematic diagram showing the sacrificial layer on the device structure shown in FIG. 4G of Example 2 of the present application after thinning by CMP. [Figure 4i] FIG. 4G is a schematic diagram showing the device structure in Example 2 of the present application after removing the HSQ electrophotoresist. [Figure 4j] FIG. 4i is a schematic diagram of the device structure of Example 2 of the present application after depositing a gate on the device structure shown in FIG. 4i. [Figure 4k] FIG. 4j is a schematic diagram showing the device structure after removing a sacrificial layer in the device structure shown in FIG. 4j in Example 2 of the present application. [Diagram 5]FIG. 1 is a schematic diagram showing a high electron mobility transistor structure according to one representative embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram illustrating another high electron mobility transistor structure according to a representative embodiment of the present application. [Figure 7a] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7b] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7c] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7d] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7e] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7f] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7g] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7h] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7i] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7j] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 7k] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to the third embodiment of the present application. [Figure 8a] FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to Example 4 of the present application. [Figure 8b]FIG. 6 is a schematic diagram showing a flow of manufacturing the high electron mobility transistor structure shown in FIG. 5 according to Example 4 of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] In view of the shortcomings of the prior art, the applicant has obtained the technical solution of the present application after a long period of research and extensive experiments, which provides a high electron mobility transistor structure, and a composite layer of a heavily doped layer and a high resistance layer is grown by secondary epitaxial growth; on the other hand, the heavily doped region formed by the heavily doped layer can effectively reduce the source-drain ohmic contact resistance; on the other hand, the high resistance material layer between the gate source and gate drain can effectively reduce the parasitic capacitance and suppress the gate leakage, thereby improving the frequency characteristics of the device and at the same time improving the reliability of the device.

[0017] One aspect of an embodiment of the present application provides a high electron mobility transistor structure, e.g., a GaN electronic device structure, comprising: an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; a source, a drain and a gate electrically connected through the carrier channel and interdigitated with the epitaxial structure; The overlap rate between the orthogonal projection of the grid foot of the gate on the first semiconductor layer and the orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more, preferably 90% or more, more preferably 95% or more, even more preferably 99% or more, and particularly preferably 100%.

[0018] That is, an orthogonal projection of the grid foot of the gate onto the first semiconductor layer and an orthogonal projection of the second semiconductor layer onto the first semiconductor layer are substantially overlapped. Preferably, an orthogonal projection of the grid foot onto the first semiconductor layer and an orthogonal projection of the second semiconductor layer onto the first semiconductor layer are overlapped.

[0019] In some embodiments, the gate includes a first portion and a second portion sequentially distributed along a direction away from the second semiconductor layer, the first portion being a grid foot and having a radial size equal to or smaller than the radial size of the second portion. In particular, the gate includes a first portion and a second portion, the radial size of the first portion being smaller than the radial size of the second portion. In particular, the first portion and the second portion may be integrally formed.

[0020] In some specific embodiments, the gate is a T-shaped grid, but is not limited to this, and may be, for example, a G-shaped gate, a trapezoidal gate, etc.

[0021] In some embodiments, the second semiconductor layer is thin and the gate and the second semiconductor layer are separated by a dielectric layer to form an enhancement mode device, although of course the second semiconductor layer can be thick to form a depletion mode device without the need for a dielectric layer between the gate and the second semiconductor layer.

[0022] In some embodiments, an insertion layer is further provided between the first and second semiconductor layers.

[0023] In some embodiments, a cap layer is further distributed between the dielectric layer and the second semiconductor layer.

[0024] In some embodiments, the epitaxial structure further comprises an ohmic contact layer, the ohmic contact layer contacting a carrier channel, and the source and drain are disposed on the ohmic contact layer and form ohmic contacts with the ohmic contact layer.

[0025] Furthermore, the ohmic contact layer is provided on the first semiconductor layer and in contact with the carrier channel.

[0026] In some embodiments, the ohmic contact layer forms an ohmic contact with the carrier channel.

[0027] In some embodiments, a groove is provided between the source and drain regions on the ohmic contact layer. B At least the bottom of the grid foot and the second semiconductor layer are both B Furthermore, the entire grid foot of the gate is disposed within the groove. B It may also be provided within

[0028] Furthermore, the group B The sidewall of the groove and the surface of the first semiconductor layer form an angle of 60 to 90°, and more preferably an angle of 90°. B The sidewalls are approximately perpendicular to the surface of the first semiconductor layer.

[0029] Further, the gate cap of the gate is B Cover the top.

[0030] In some embodiments, the gate and the ohmic contact layer are electrically insulated by a dielectric layer, the dielectric layer disposed between the gate and the ohmic contact layer being defined as a dielectric sidewall, or the gate and the heavily doped ohmic contact layer are insulated by air.

[0031] More preferably, the epitaxial structure employs a thin potential barrier structure, although in some cases the epitaxial structure may employ a thick potential barrier structure.

[0032] More preferably, the radial size of the grid foot of the gate may be set to 10 nm to 500 nm.

[0033] In some embodiments, the epitaxial structure may further include a P-type layer disposed on the second semiconductor layer, and a gate may be disposed on the P-type layer to form a P-type gate enhancement device.

[0034] In some embodiments, the ohmic contact layer further includes a sacrificial layer, and at least some regions of the source, drain and gate are exposed through the sacrificial layer. The sacrificial layer may be made of, but is not limited to, PI rubber, BCB rubber (Benzo Cyclo Butene), SOG (Spin-on-glass) or other low-k dielectric materials, and may be removed by process means, and is spatially isolated from the heavily doped ohmic contact layer by air.

[0035] Furthermore, the material of the epitaxial structure includes a III-V compound. For example, the first semiconductor layer is understood to be a channel layer, and the first semiconductor The material of the layer includes GaN, etc. The second semiconductor layer is understood as a potential barrier layer, and the material of the second semiconductor layer includes AlGaN, AlN, AlInN, or AlInGaN, etc. The material of the cap layer includes GaN, etc. The material of the ohmic contact layer includes n-type GaN, etc., particularly heavily doped n-type GaN. The material of the insertion layer includes AlN, etc.

[0036] In some embodiments, the material of the dielectric layer includes Al2O3, SiO2, HfO2, AlON, silicon nitride, and the like, or combinations thereof, including, but not limited to, composite grid dielectrics such as Al2O3 / AlN, Al2O3 / HfO2, and the like.

[0037] In some embodiments, the GaN electronic device structure includes, but is not limited to, a nitrogen-polar (N-polar) HEMT device structure or a HEMT device structure having a back barrier structure.

[0038] In some embodiments, the high electron mobility transistor structure further comprises a substrate, and the epitaxial structure is formed on the substrate. The substrate may be made of, but is not limited to, silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, etc. Furthermore, the epitaxial structure may include a nucleation layer, a buffer layer, etc., sequentially grown on the substrate, which are well known in the art and will not be described in detail herein.

[0039] The above embodiments of the present application directly construct a gate (e.g., a T-shaped grid) between the source and drain, and further form a short channel, total grid control, and a GaN electronic device structure with almost no access area and series resistance, which can effectively reduce the device knee-point voltage and improve the device linearity. Moreover, this GaN electronic device structure is perfectly suitable for depletion-mode and enhancement-mode HEMT devices. In particular, when using a heterojunction epitaxial structure with a thin potential barrier, the group B An enhancement-mode device can be realized without the need for a gate etching process and at the same time have a large transconductance, which can significantly improve the PA power gain of the device.

[0040] Some embodiments of the present application further provide a method for manufacturing a high electron mobility transistor structure, the method comprising: fabricating an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; and fabricating a source, a drain and a gate electrically connected through the carrier channel and interfacing with the epitaxial structure; In the step of manufacturing the gate, a grid foot size of the gate is set so that an overlap rate between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more, more preferably 90% or more, even more preferably 95% or more, still more preferably 99% or more, and particularly preferably 100%. That is, the orthogonal projection of the grid foot on the first semiconductor layer almost covers the orthogonal projection of the second semiconductor layer on the first semiconductor layer.

[0041] The manufacturing method described in some embodiments specifically includes the steps of: forming a first semiconductor layer and a second semiconductor layer on a substrate by sequentially growing the first semiconductor layer and the second semiconductor layer; providing a mask on a gate region of the second semiconductor layer, the mask having a radial size that matches a radial size of the grid foot; Etching away unmasked areas of the second semiconductor layer until an etching depth reaches or penetrates the surface of the first semiconductor layer; growing an ohmic contact layer on at least the source region and the drain region of the first semiconductor layer such that a surface height of the second semiconductor layer is equal to or lower than a surface height of the ohmic contact layer, and contacting the ohmic contact layer with a carrier channel; The method includes the steps of forming a gate on the second semiconductor layer after removing the mask, forming the source and drain on the source and drain regions of the ohmic contact layer, respectively, and forming ohmic contacts between the source and drain and the ohmic contact layer, respectively.

[0042] More preferably, the ohmic contact layer forms an ohmic contact with the carrier channel.

[0043] In some embodiments, the method further comprises growing an ohmic contact layer on a surface of the first semiconductor layer in a region not covered by the second semiconductor layer, such that a surface of the ohmic contact layer is higher than a surface of the second semiconductor layer, and forming a groove in the ohmic contact layer. B After forming the gate, the mask is removed to form the gate, and at least the bottom of the grid foot is bonded to the group. B The method further comprises distributing the

[0044] In some embodiments, the manufacturing method includes, after growing and forming the ohmic contact layer, first removing the mask, forming a continuous dielectric layer on the ohmic contact layer and the second semiconductor layer, forming the gate on the dielectric layer, opening a window in the dielectric layer, and forming the source and drain in the window.

[0045] Here, the step of manufacturing the gate may be performed before or after the step of manufacturing the source and drain.

[0046] In some embodiments, the method includes growing and forming the ohmic contact layer, first forming the source and drain on the ohmic contact layer, forming a sacrificial layer continuous with the ohmic contact layer, embedding the source and drain in the sacrificial layer, exposing at least the mask surface from the sacrificial layer, and then removing the mask. Q and forming a gate on the second semiconductor layer.

[0047] Here, after the source, drain, and mask are completely embedded in the sacrificial layer, the mask portions are exposed from within the sacrificial layer by processes such as grinding and polishing (for example, CMP, chemical mechanical polishing process).

[0048] After fabricating the source, drain and gate, the sacrificial layer can be removed and spatially isolated from the heavily doped ohmic contact layer by air, or the sacrificial layer can be retained and used as a support layer for the gate, etc.

[0049] The manufacturing method described in some embodiments specifically includes the steps of forming the mask on a gate region of the second semiconductor layer, forming a dielectric layer on at least a sidewall of the mask, and then sequentially performing an etching operation on the second semiconductor layer and an operation of growing the ohmic contact layer on the first semiconductor layer.

[0050] In some embodiments, the method further comprises performing an operation of isolating the epitaxial structure from an active region, which can be performed in a manner well known in the art.

[0051] In some embodiments, the gate includes a grid foot and a gate cap sequentially distributed along a direction away from the second semiconductor layer, and the radial size of the grid foot is equal to or smaller than the radial size of the gate cap. Preferably, the gate includes, but is not limited to, a T-shaped grid.

[0052] In the above embodiments of the present application, the mask is formed of a photoresist or a dielectric film, etc., and may be formed by a patterning process such as exposure and development as is well known in the art, or may be removed by wet etching as is well known in the art.

[0053] In the above embodiments of the present application, each structural layer in the epitaxial structure can be grown by physical and / or chemical vapor deposition techniques well known in the art, such as MOCVD, ALD, PECVD, etc.

[0054] In the above embodiments of the present application, the dielectric layer may be formed by ALD or other physical or chemical vapor deposition methods.

[0055] In the above embodiments of the present application, the sources, drains, gates, etc. are formed by various means well known in the art, such as sputtering, evaporation, metal lift-off processes, and the like.

[0056] In a more preferred embodiment of the present application, based on a thin potential barrier heterojunction GaN HEMT epitaxial structure, the GaN electronic device structure is fabricated with the aid of secondary epitaxial growth ohmic technology, which is defined as a near-total grid control short channel device, and the GaN electronic device structure can realize both low knee-point voltage and enhancement type operation mode, and meets the RF front-end PA application scenario. Compared with the conventional GaN RF HEMT, the GaN electronic device structure does not have the access region between the gate-source and gate-drain, and effectively regulates the entire short channel with the gate, realizing velocity saturation and eliminating the nonlinear effect induced by RGS resistance degradation. In particular, for realizing the enhancement type operation mode, the epitaxial structure of the GaN electronic device structure adopts a thin potential barrier and does not require processes such as dry etching, so that it is different from the conventional group. B This avoids etching damage during the manufacturing process of gate-enhanced HEMT devices, greatly improving the reliability and stability of device manufacturing. As for suppressing parasitic effects, the T-gate structure, which spatially isolates the heavily doped ohmic contact layer by air, greatly suppresses high-frequency parasitic effects. At the same time, the thin potential barrier means a large gate capacitance, which greatly improves the transconductance of this GaN electronic device structure, ultimately contributing to increasing the power gain of the PA.

[0057] Some embodiments of the present application further provide applications of the GaN electronic device structures in the manufacture of power amplifiers, RF devices, communication devices or electronic devices, the power amplifiers being, but not limited to, RF band power amplifiers, or millimeter wave or terahertz band power amplifiers, the electronic devices being, but not limited to, mobile phones, tablet computers or other smart devices.

[0058] Another aspect of the present application further provides a high electron mobility transistor structure comprising an epitaxial structure and a source, a drain and a gate interdigitated with the epitaxial structure, the epitaxial structure including a heterojunction, a carrier channel formed within the heterojunction, the carrier channel distributed within an area covered by an orthogonal projection of the gate on the epitaxial structure, the epitaxial structure further comprising a heavily doped region and a highly resistive region, the heavily doped region disposed at the heterojunction and forming an ohmic contact with the carrier channel, both the source and drain forming an ohmic contact with the heavily doped region, the highly resistive region formed on the heavily doped region, the source and gate, and the drain and gate being separated by the highly resistive region.

[0059] It should be noted that the heavily doped and highly resistive regions can be considered as highly doped ohmic contact layers.

[0060] In some embodiments, the top surface of the heavily doped region is higher than a surface of the carrier channel.

[0061] Here, the material of the heavily doped region can be, but is not limited to, GaN, or any one or more combinations of InGaN, AlInGaN, or AlGaN, and the material of the highly resistive region can be, but is not limited to, GaN, or any one or more combinations of SiN, AlN, InGaN, AlInGaN, or AlGaN.

[0062] In some embodiments, the heterojunction is mainly composed of a first semiconductor layer and a second semiconductor layer provided on the first semiconductor layer, the heavily doped region includes a first heavily doped region blended with a source and a second heavily doped region blended with a drain, the first heavily doped region and the second heavily doped region are respectively disposed on both sides of the second semiconductor layer, the high resistance region includes a first highly resistive region blended with a source and a second highly resistive region blended with a drain, at least a portion of the source and drain form ohmic contacts with the first heavily doped region and the second heavily doped region after passing through the first highly resistive region and the second highly resistive region, the first heavily doped region together with the first highly resistive region forms a source contact region of the high electron mobility transistor structure, and the second heavily doped region together with the second highly resistive region forms a drain contact region of the high electron mobility transistor structure.

[0063] Here, the first semiconductor layer is a first semiconductor layer of the high electron mobility transistor structure, the first semiconductor layer has a thickness of 5 to 200 nm, and is made of a GaN material, and the second semiconductor layer is a second semiconductor layer of the high electron mobility transistor structure, the second semiconductor layer has a thickness of 1 to 100 nm, and is made of one or a combination of AlGaN-based, AlN-based, AlInN-based, and AlInGaN-based materials, but is not limited to these.

[0064] In some embodiments, the carrier channel is a two-dimensional electron gas channel and the heavily doped region is n-type, or the carrier channel is a two-dimensional hole gas channel and the heavily doped region is p-type.

[0065] In some embodiments, the material of the epitaxial structure may be a Ga-polar surface or an N-polar surface, and a device structure having a two-dimensional electron gas channel formed in a Ga-polar surface is consistent with a device structure having a two-dimensional hole gas channel formed in an N-polar surface, and a device structure having a two-dimensional hole gas channel formed in a Ga-polar surface is consistent with a device structure having a two-dimensional electron gas channel formed in an N-polar surface.

[0066] In some embodiments, the first semiconductor layer includes a first region and a second region, a protrusion is formed in the first region, the second semiconductor layer is formed in the protrusion, and the first heavily doped region and the second heavily doped region are formed on the second region and distributed on both sides of the protrusion.

[0067] In some embodiments, the epitaxial structure further comprises a cap layer disposed on the second semiconductor layer, the cap layer having a thickness of 0-100 nm and made of, but not limited to, a GaN material or SiN.

[0068] In some embodiments, the epitaxial structure further comprises an insertion layer distributed between the first semiconductor layer and the second semiconductor layer, the insertion layer having a thickness of 0-10 nm and being made of, but not limited to, AlN material.

[0069] In some embodiments, the epitaxial structure further comprises a buffer layer distributed between the substrate and the first semiconductor layer.

[0070] In some embodiments, the buffer layer may be selectively doped.

[0071] In some embodiments, the epitaxial structure further comprises a back barrier layer distributed between the buffer layer and the first semiconductor layer, and the material of the back barrier layer can be, but is not limited to, AlN, AlGaN, etc.

[0072] In some embodiments, the gate may be a T-shaped grid, including a gate cap and a grid foot arranged along an axial direction, the gate cap being arranged on and supported by a high resistance region, the grid foot being arranged within the epitaxial structure, the size of the gate cap along a source drain channel direction being larger than the size of the grid foot along the source drain channel direction, the carrier channel being distributed directly under the grid foot, and the size of the grid foot along the source drain channel direction being equal to or smaller than the length of the two-dimensional electron gas channel.

[0073] In some more preferred embodiments, a sidewall dielectric layer is further provided between the sidewall of the grid foot and the high resistance region, the material of which may be, but is not limited to, SiN, and the sidewall dielectric layer may be formed by LPCVD growth method.

[0074] In some embodiments, there is further provided a dielectric layer between the gate and the heterojunction, the material of which may be one or more of SiO2, HfO2, Al2O3, AlN, AlON, SiN, etc., and the dielectric layer may be formed by ALD growth method, but is not limited thereto.

[0075] In some embodiments, the dielectric layer extends further to cover the surface of the epitaxial structure, and the source and drain interface with the epitaxial structure through windows opened in the dielectric layer.

[0076] In some embodiments, the dielectric layer is used to separate the gate and the high resistance region, or the gate and the high resistance region are directly insulated by air.

[0077] In some embodiments, the highly resistive region may be epitaxially formed on the heavily doped region by secondary epitaxy, or may be formed by conversion of a portion of the heavily doped region material into a highly resistive material, for example by thermal diffusion, ion implantation, plasma treatment, or any other method capable of forming a layer of highly resistive material.

[0078] In the above embodiments, the interface between the heavily doped region and the high resistance region may be a mutational dope modulation or incremental dope modulation, as long as it is ensured that the surface of the heavily doped region is higher than the surface of the carrier channel.

[0079] In some embodiments, the high electron mobility transistor structure further comprises isolation regions formed in the epitaxial structure for isolating active regions of the high electron mobility transistor structure, the isolation regions being distributed on opposite sides of the epitaxial structure and extending axially from a surface of the epitaxial structure to at least below the first semiconductor layer.

[0080] In some embodiments, implantation energies of 100 to 400 keV, 10 12 ~10 17 / cm 2 The isolation region is formed by an N ion implantation technique with an implantation amount of N ions of 1000 nm to an implantation depth equal to or less than the first semiconductor layer. The isolation region may be formed by an etching method that etches the epitaxial layer outside the active region to the first semiconductor layer.

[0081] Another aspect of the present application further provides a method for manufacturing the high electron mobility transistor structure, the method comprising: forming a heterojunction by sequentially providing a first semiconductor layer and a second semiconductor layer, and distributing carrier channels in the heterojunction within an area covered by an orthogonal projection on an epitaxial structure of a gate; forming a heavily doped region and a highly resistive region on the heterojunction, the highly resistive region being disposed on the heavily doped region, and the heavily doped region being in ohmic contact with the carrier channel to form an epitaxial structure; forming a source, a drain and a gate interfacing with the epitaxial structure, the source and drain making ohmic contacts with heavily doped regions, and the source and gate and the drain and gate being separated by highly resistive regions.

[0082] Further, the manufacturing method specifically comprises: Sequentially growing a first semiconductor layer and a second semiconductor layer on a substrate; A mask is provided on a surface of the second semiconductor layer in a region corresponding to a gate, and a source contact region and a drain contact region of the second semiconductor layer are entirely removed. semiconductor etching the second semiconductor layer and the first semiconductor layer using the mask until removing a portion of a source contact region and a drain contact region of the layer, forming a region of the first semiconductor layer corresponding to a gate as a protrusion, and distributing a remaining portion of the second semiconductor layer on the protrusion; forming the epitaxial structure by growing a heavily doped layer on a remaining portion of the source contact region and the drain contact region of the first semiconductor layer to form a heavily doped region, and then growing a highly resistive layer on the heavily doped layer to form a highly resistive region, such that a surface of the heavily doped region is higher than a surface of the carrier channel; or growing a heavily doped layer on remaining portions of the source contact region and the drain contact region of the first semiconductor layer, and then converting a semiconductor material from a surface of the heavily doped layer to a predetermined depth within the heavily doped layer into a highly resistive material to form a highly resistive region and a heavily doped region within the heavily doped layer, the predetermined depth being higher than a surface of the carrier channel, to form the epitaxial structure; Removing the mask to form the gate, source and drain.

[0083] In some embodiments, the source and drain materials may be Ti / Al / Ni / Au or other metal systems capable of forming ohmic contacts with the heavily n-type or heavily p-type doped regions, and the gate material may be Ni / Au or a material system capable of forming a Schottky contact with the second semiconductor layer, such as Ni / Pt / Au, Ni / Pt, or P-GaN.

[0084] In some embodiments, the method of manufacturing further specifically comprises forming a dielectric layer between the gate and the heterojunction.

[0085] In some embodiments, the method further specifically includes forming a sidewall dielectric layer between the grid foot and the high resistance region of the gate.

[0086] It is not necessary to form the dielectric layer or the sidewall dielectric layer under conditions that allow the growth shape of the ohmic contact region composed of the high resistance region and the heavily doped region to be controlled.

[0087] In some embodiments, the method further specifically includes forming a buffer layer between the substrate and the first semiconductor layer.

[0088] In some embodiments, the material of the substrate is any one selected from the group consisting of, but not limited to, silicon, sapphire, silicon carbide, gallium nitride, and aluminum nitride.

[0089] In some more specific embodiments, the manufacturing method may include the following steps. Step 1) A buffer layer, a first semiconductor layer, an insertion layer, a second semiconductor layer and a cap layer are epitaxially grown in sequence on a substrate, and a carrier channel is formed under the surface of the first semiconductor layer near the insertion layer. Step 2) By using an electrophotoresist, a grid foot size of the T-shaped grid, i.e., a gate length L GDefined as ≒ 50~500nm. Step 3), harden the electrophotoresist through an annealing process, and the annealing temperature is about 400°C. Step 4), after depositing a sidewall dielectric layer on the device surface formed in step 3), the cap layer and the sidewall dielectric layer on the top of the electrophotoresist are etched away by a self-aligned etching technique. Step 5) Using the hardened electrophotoresist as a mask, etch the source contact region and the drain contact region, and remove the cap layer, the second semiconductor layer, the insertion layer and a part of the first semiconductor layer in the source contact region and the drain contact region. Step 6), using the hardened electrophotoresist as a mask, epitaxially grow a heavily doped layer on the etched source contact region and drain contact region to form a heavily doped region, and set the thickness and doping concentration of the heavily doped region to form a good ohmic contact with the carrier channel, and then epitaxially grow a high resistance layer on the heavily doped region to form a high resistance region. Step 7) Remove the electrophotoresist. Step 8) forming isolation regions of active regions on both sides of the epitaxial structure; Step 9) depositing a dielectric layer on the surface of the device formed in step 8). Step 10), the high resistance layer is used as a support layer for a T-shaped grid cap to form the T-shaped grid. Step 11) opening windows on the grid dielectric layer and the high resistance layer, forming sources and drains in the windows, and forming ohmic contacts with the source, drain and the heavily doped layer.

[0090] In some more specific embodiments, step 6) uses the hardened electrophotoresist as a mask to epitaxially grow a heavily doped layer on the source contact region and the drain contact region after etching to form a heavily doped region, and sets the thickness and doping concentration of the heavily doped region to ensure that it forms a good ohmic contact with the carrier channel, and then converts the semiconductor material from the surface of the heavily doped layer to a predetermined depth in the heavily doped layer into a high resistance material, forming a high resistance region and a heavily doped region in the heavily doped layer, and the predetermined depth is higher than the surface of the carrier channel.

[0091] Another aspect of the present application further provides a power amplifier having the above-described high electron mobility transistor structure.

[0092] In some embodiments, the power amplifier includes an RF, mmWave, or terahertz power amplifier.

[0093] Hereinafter, the technical solutions of the present application will be described clearly and completely with reference to the drawings and specific examples, but obviously, the described examples are only some of the examples of the present application, and are not all of the examples. Based on the examples of the present application, other examples obtained by those skilled in the art without creative labor are all included in the scope of protection of the present application. Unless otherwise specified, the manufacturing process of the following examples of the present application adopts the existing process in the field, so the process parameters are omitted here.

[0094] Referring to FIG. 2, the GaN electronic device structure in the representative embodiment of the present application is a near-total grid control GaN HEMT structure, which includes a buffer layer 20, a channel layer 30, an insertion layer 50, a potential barrier layer 60, a cap layer 70, etc., which are sequentially grown on a substrate 10. An n-type layer (i.e., the ohmic contact layer) is further grown on the surface of the channel layer 30, and the n-type layer contacts the insertion layer 50, the potential barrier layer 60, the cap layer 70, etc. to form an epitaxial structure. The channel layer 30, the insertion layer 50, and the potential barrier layer 60 form a heterojunction, and a two-dimensional electron gas channel 40 is formed between the channel layer 30 and the insertion layer 50.

[0095] In this embodiment, the n-type layer is B The insertion layer 50, the potential barrier layer 60, and the cap layer 70 are all formed in the group. B The gate 104 is a T-shaped grid, the grid foot of which is also distributed in the group. B A gate cap is provided on the n-type layer, and a source 102 and a drain 103 are provided on the n-type layer and form ohmic contacts with the n-type layer.

[0096] The epitaxial structure has active area isolation structures formed, such as by ion implantation, while a continuous dielectric layer 101 is further formed between the n-type and capping layers 70 and the gate 104 to form an enhancement type device.

[0097] In this embodiment, the epitaxial structure is preferably a thin potential barrier design. Such a design allows the fabrication of short channel devices where nearly the entire channel is effectively controlled by the gate (i.e., the gate length L G ≒ Source-drain distance L DS ), there is no access area between the gate-source and gate-drain, which greatly reduces the difficulty of obtaining a low knee-point voltage for the device. At the same time, R GSThe problem of device linearity degradation caused by high magnetic field nonlinear behavior can be effectively suppressed, while the thin potential barrier epitaxial structure is adopted and the gate can regulate the electron concentration in the entire channel, making it easy to realize the fabrication of enhancement-type devices without the need for complicated processes. At the same time, the thin potential barrier means a large gate capacitance, which helps improve the device transconductance and ultimately contributes to the PA power gain.

[0098] Referring to FIG. 5, an n-type channel high electron mobility transistor structure provided by an embodiment of the present application includes a substrate 10, an epitaxial structure provided on the substrate 10, a source 102, a drain 103 and a gate 104 integrated with the epitaxial structure, the epitaxial structure includes a GaN buffer layer 20, a GaN first semiconductor layer 30, an AlN insertion layer 50, an AlGaN second semiconductor layer 60 and a GaN cap layer 70 sequentially formed on the sapphire substrate 10, the GaN first semiconductor layer 30 including a first region and a second region. a protrusion is formed in the first region, and the AlN insertion layer 50, the AlGaN second semiconductor layer 60 and the GaN cap layer 70 are sequentially formed on the protrusion, wherein the GaN first semiconductor layer 30, the AlN insertion layer 50 and the AlGaN second semiconductor layer 60 form a heterojunction, and a two-dimensional electron gas channel 40 is formed under the surface of the GaN first semiconductor layer 30 near the AlN insertion layer 50, and the two-dimensional electron gas channel 40 is distributed within the area covered by the orthogonal projection of the gate 104 on the epitaxial structure.

[0099] Furthermore, the epitaxial structure further comprises a heavily doped region and a highly resistive region, the heavily doped region including a first heavily doped region 801 aligned with the source 102 and a second heavily doped region 802 aligned with the drain 103, the first heavily doped region 801 and the second heavily doped region 802 being disposed on the second region of the GaN first semiconductor layer 30 and forming a good ohmic contact with the two-dimensional electron gas channel 40, and the highly resistive region includes a first highly resistive region 901 aligned with the source 102 and a second highly doped region 902 aligned with the drain 103. The source 102 and the drain 103 include a first high resistance region 901 and a second high resistance region 902, and a portion of the source 102 and the drain 103 form ohmic contacts with the first heavily doped region 801 and the second heavily doped region 802 after passing through the first high resistance region 901 and the second high resistance region 902, respectively, the source 102 and the gate 104, and the drain 103 and the gate 104 are separated by the first high resistance region 901 and the second high resistance region 902, respectively, and the surfaces of the first heavily doped region 801 and the second heavily doped region 802 are higher than the surface of the two-dimensional electron gas channel 40.

[0100] Here, the first heavily doped region 801 and the second heavily doped region 802 are made of an n-type heavily doped GaN material, and the first highly resistive region 901 and the second highly resistive region 902 are made of a highly resistive GaN material.

[0101] Specifically, the gate 104 is a T-shaped grid, and includes a gate cap and a grid foot arranged along the axial direction, both ends of the gate cap are respectively arranged on the first high resistance region 901 and the second high resistance region 902 and supported by the first high resistance region 901 and the second high resistance region 902, a grid foot is arranged in the epitaxial structure, a diameter of the gate cap is larger than a diameter of the grid foot, the two-dimensional electron gas channel 40 is distributed directly below the grid foot, and a diameter of the grid foot is equal to or larger than a length of the two-dimensional electron gas channel 40, thereby realizing a near-total grid control high electron mobility transistor structure.

[0102] Specifically, a SiN sidewall dielectric layer 100 is further provided between the grid foot of the gate 104 and the first and second high resistance regions 901 and 902, and an Al2O3 dielectric layer 101 is further provided between the gate 104 and the surface of the epitaxial structure.

[0103] Next, referring to FIG. 6 , the n-type channel high electron mobility transistor structure with an N-polarity plane provided by the embodiment of the present application is different from the n-type channel high electron mobility transistor structure shown in FIG. 5 in that a two-dimensional electron gas channel 40 is formed on the surface of the GaN first semiconductor layer 30 close to the AlN insertion layer 50, and an AlGaN second semiconductor layer 60 is provided below the GaN first semiconductor layer 30.

[0104] The technical solution of the present application will be described in more detail below with reference to examples and drawings. The present examples are implemented under the premise of the technical solution of the present application, and detailed embodiments and specific operation procedures are described. However, the scope of protection of the present application is not limited to the following examples.

[0105] Example 1 The GaN HEMT structure (hereinafter referred to as device) provided in this embodiment is basically the same as the GaN electronic device structure shown in Figure 1, and the ohmic contact layer formed by secondary epitaxial is directly used as the T-shaped grid support layer. The fabrication method of this device includes the following steps: S1, as shown in FIG. 3a, epitaxially grow a thin second semiconductor layer heterojunction-based device epitaxial structure by MOCVD (metal organic chemical vapor deposition). In this epitaxial structure, the second semiconductor layer is Al 0.2 Ga 0.8 The GaN cap layer is about 2 nm thick, the AlN insertion layer is about 1 nm thick, and the GaN first semiconductor layer is 5 to 200 nm thick. S2, as shown in Figure 3b, the grid foot size of the T-shaped grid ("T-shaped grid") of the device is determined using HSQ (Hydrogen Silsesquioxane) electrophotoresist or other photoresist, i.e., the gate length LG Define the L of the T-shaped grid. G ≒50nm~250nm. S3, as shown in Fig. 3c, the HSQ electrophotoresist is cured by annealing process, and the annealing temperature is about 400 °C. S4, etch the source-drain ohmic contact region, as shown in Figure 3d. Etch the gate to the source-drain ohmic contact region by chlorine ICP (Inductive Coupled Plasma) etching technology with the cured HSQ electrophotoresist as a mask, and control the etching rate at 1-20 nm / min. S5, forming a secondary epitaxial ohmic contact layer. As shown in Fig. 3e, using the HSQ electrophotoresist after MOCVD (Metal-organic Vapor Deposition) and hardening treatment as a mask, epitaxially grow n-type heavily doped layer n++ GaN to form an ohmic contact layer, and set its doping concentration and thickness to form a good ohmic contact with the channel electrons. S6, Remove the HSQ electrophotoresist. As shown in Figure 3f, the HSQ electrophotoresist is removed using a BOE solution (or HF solution). S7, Isolate the active region. As shown in FIG. 3g, isolation is performed by N ion implantation technology, the ion implantation energy is 150-400 KeV ion implantation, the implanted ion dosage is 10 12 ~10 14 / cm 2 , the implantation depth exceeds the buffer layer by about 50 to 250 nm. S8, Deposit grid dielectric. As shown in Figure 3h, a dielectric layer (abbreviated as "grid dielectric") is deposited by ALD (Atom Layer Deposition) technology, and the thickness of the Al2O3 dielectric layer is 1-5 nm. S9, fabricate a T-shaped grid (abbreviated as “T-shaped grid”). As shown in Figure 3i, with the secondary epitaxial ohmic contact layer as the T-shaped grid supporting layer, use the photofinish process and electron beam evaporation technology to form a Ni / Au T-shaped grid with a thickness of 50 nm / 250 nm. S10, fabricate the source and drain. After the window process of the source and drain ohmic contacts, the source and drain are formed by electron beam evaporation technology to form the ohmic contact layer and the ohmic contact. As shown in Figure 3j, the source and drain are Ti / Au ohmic contact electrodes with thicknesses of 50nm / 250nm. The knee point voltage of the GaN HEMT device of this embodiment can reach 1V or less.

[0106] Example 2 The GaN HEMT structure (hereinafter referred to as device) provided in this embodiment is similar to the GaN electronic device structure shown in Figure 1, except that a dielectric sacrificial layer is used as the support layer for the T-shaped grid. The fabrication method of this device is similar to that of Example 1, and includes the following steps: S1 to S3: As shown in FIG. 3c, similar to steps S1 to S3 in the device manufacturing method of Example 1, the grid feet of the T-shaped grid are defined by HSQ electrophotoresist, and then annealing hardening is performed. S4, deposit a dielectric layer. As shown in Figure 4a, a dielectric layer is deposited by ALD technology. For example, a silicon nitride dielectric layer with a thickness of 1 to 5 nm can be deposited. S5, Form dielectric sidewall. As shown in Fig. 4b, the silicon nitride dielectric layer is etched by fluorine RIE (Reactive Ion Etch) to form the dielectric sidewall. In particular, the dielectric sidewall is responsible for preventing short circuit between the electrodes of the device while maintaining the stability of the HSQ electrophotoresist in the later process. S6, Etch the source-drain ohmic contact region. As shown in Figure 4c, the gate is etched against the source-drain ohmic contact region by chlorine ICP etching technology using the cured HSQ electrophotoresist as a mask, and the etching rate is controlled at 1-20 nm / min. S7, forming a secondary epitaxial ohmic contact layer. As shown in Fig. 4d, by MOCVD, using the hardened HSQ electrophotoresist as a mask, n-type heavily doped n++ GaN is epitaxially grown as an ohmic contact layer, and its doping concentration and thickness are set to form a good ohmic contact with the channel electrons. S8, Isolate the active region. As shown in Figure 4e, isolation is performed by N ion implantation technology, the ion implantation energy is 150-400 KeV ion implantation, the implanted ion agent amount is 10 12~ 10 14 / cm 2 , the implantation depth exceeds the buffer layer by about 50 to 250 nm. S9, fabricate source and drain. By electron beam deposition technology, the source and drain are formed to form an ohmic contact layer and an ohmic contact. As shown in Fig. 4f, the source and drain are Ti / Au electrodes with a thickness of 50nm / 250nm. S10, Spin-coat the sacrificial layer. Spin-coat the sacrificial layer PI rubber (Polyimide) by spin-coating. Set the thickness of the spin-coat to graphically cover the surface of the wafer (i.e., at least higher than the height of the HSQ electrophotoresist, source drain) as shown in Figure 4g. S11: Chemical Mechanical Polishing (CMP) is performed. As shown in Figure 4h, the sacrificial layer is CMPed to expose the hardened HSQ electrophotoresist. S12, Remove HSQ electrophotoresist. As shown in Figure 4i, BOE solution (or HF solution) is used to remove HSQ electrophotoresist. S13, fabricate a T-shaped grid. As shown in Figure 4j, with the sacrificial layer as the supporting layer, a Ni / Au T-shaped grid is formed by photoprocess and e-beam evaporation technology, with a thickness of 50 nm / 250 nm. S14: Remove the sacrificial layer. As shown in Fig. 4k, the sacrificial layer is removed using organic solvent or plasma ashing, and the T-gate structure is spatially isolated from the heavily doped ohmic contact layer by air. The knee-point voltage of the GaN HEMT device of this embodiment can reach 1V or less.

[0107] Although the device presented in this example is a depletion mode device, enhancement mode devices may also be fabricated by providing a dielectric layer between the gate and the cap layer.

[0108] Example 3 A method for fabricating the high electron mobility transistor structure of this embodiment shown in FIG. 5 may include the following steps. Step 1), as shown in FIG. 7a, a GaN buffer layer 20 having a thickness of 1500 nm, a GaN first semiconductor layer 30 having a thickness of 150 nm, an AlN insertion layer 50 having a thickness of 1 nm, an AlGaN second semiconductor layer 60 having a thickness of 5 nm, and a GaN cap layer 70 having a thickness of 2 nm are epitaxially grown in sequence on a sapphire substrate 10, and a two-dimensional electron gas channel 40 is formed under the surface of the GaN first semiconductor layer 30 near the AlN insertion layer 50. Step 2) As shown in FIG. 7b, a HSQ (hydrosesquioxane) electrophotoresist 106 is used to deposit the grid foot size of the T-shaped grid, i.e., the gate length L G Define ≒50~500nm. Step 3), as shown in FIG. 7c, the HSQ electrophotoresist 106 is cured by annealing process, and the annealing temperature is about 400° C. Step 4), as shown in FIG. 7d, a 5 nm thick SiN sidewall dielectric layer is deposited on the surface of the device formed in step 3) by using low pressure chemical vapor deposition technique (LPCVD), and then the GaN cap layer 70 and the SiN sidewall dielectric layer on top of the HSQ electrophotoresist are etched away by self-aligned etching technique, as shown in FIG. 7e. Step 5), as shown in FIG. 7f, by using the cured HSQ electrophotoresist 106 as a mask, etch the source contact region and the drain contact region by inductively coupled plasma etching technology (ICP), to remove the GaN cap layer 70, the AlGaN second semiconductor layer 60, the AlN insertion layer 50 and a part of the GaN first semiconductor layer 30 in the source contact region and the drain contact region, so that the region corresponding to the GaN first semiconductor layer 30 and the gate 104 becomes a protrusion, and the remaining AlN insertion layer 50, the AlGaN second semiconductor layer 60 and the GaN cap layer 70 are distributed on the protrusion. Step 6), as shown in FIG. 7g, using the hardened HSQ electrophotoresist 106 as a mask, epitaxially grow n-type heavily doped GaN material layer on the etched source contact region and drain contact region by metal organic chemical vapor deposition (MOCVD) to form a first heavily doped region 801 and a second doped region 802, and set the thickness (supposing that the surface of the first heavily doped region 801 and the second doped region 802 is higher than the surface of the two-dimensional electron gas channel 40) and doping concentration of the first heavily doped region 801 and the second doped region 802 to form a good ohmic contact with the two-dimensional electron gas channel 40, and then epitaxially grow a high resistance GaN material layer on the first heavily doped region 801 and the second doped region 802 to form a first high resistance region 901 and a second high resistance region 902. Step 7), as shown in FIG. 7h, remove the HSQ electrophotoresist 106 using BOE solution or HF solution. Step 8), as shown in FIG. 7i, form active region isolation regions 105 on both sides of the epitaxial structure by N ion implantation technology, and the N ion implantation energy is 100-400 keV, and the N ion implantation dose is 1012 ~10 15 / cm 2 , the implantation depth exceeds the GaN buffer layer 20 by about 50 to 250 nm. Step 9), as shown in FIG. 7j, a 1 nm thick Al2O3 dielectric layer 101 is grown on the surface of the device formed in step 8) by atomic layer deposition (ALD). Step 10), as shown in FIG. 7k, the first high resistance region 901 and the second high resistance region 902 are used as a support layer for the gate cap of the gate 104 to form the gate 104, which is made of Ni / Au and has a thickness of 50 nm / 250 nm. Step 11), opening windows in the Al2O3 dielectric layer 101, the first high resistance region 901 and the second high resistance region 902, and forming a source 102 and a drain 103 in the windows by electron beam deposition technology, where the source and drain are made of Ti / Au with a thickness of 50nm / 250nm, thereby manufacturing a high electron mobility transistor structure as shown in FIG.

[0109] It should be noted that the process steps in this embodiment can be adjusted according to the actual situation as long as the final device structure can be realized, which is well known to those skilled in the art, so redundant description will be omitted.

[0110] Example 4 The method of manufacturing the high electron mobility transistor structure shown in FIG. 5 in this embodiment is basically the same as the method of manufacturing in the first embodiment, but differs in the following respects. Step 6) As shown in FIG. 8a, first, use the hardened HSQ electrophotoresist 106 as a mask to epitaxially grow n-type heavily doped GaN material layer in the source contact region and drain contact region after etching to form a first heavily doped region 801 and a second heavily doped region 802, and set the thickness and doping concentration of the first heavily doped region 801 and the second heavily doped region 802 to form good ohmic contact with the two-dimensional electron gas channel 40, and then convert the n-type heavily doped GaN material from the surface of the first heavily doped region 801 and the second heavily doped region 802 to a predetermined depth inside into a GaN high resistance material to form a first highly resistive region 901 and a second highly resistive region 902, and the predetermined depth is higher than the surface of the two-dimensional electron gas channel 40, as shown in FIG. 8b.

[0111] In the above embodiment of the present application, by using the self-alignment process and secondary epitaxial technology, the heavily doped layer and the high resistance layer composite material are used as the supporting layer to directly construct a T-shaped grid between the source and drain, forming a short channel, realizing near total grid control, realizing a high electron mobility transistor structure with no access area series resistance and low parasitic effect, effectively reducing the device knee-point voltage, improving the device linearity, and at the same time improving the frequency characteristics, output efficiency and reliability of the device. At the same time, the high electron mobility transistor structure provided by the present application adopts a heterojunction epitaxial structure based on a thin potential barrier, and the group B No gate etching process is required, and enhancement-mode devices can be fabricated. The thin potential barrier material structure gives the devices large transconductance, contributing to improved gain in RF power amplifiers.

[0112] Furthermore, the high electron mobility transistor structure provided by the embodiments of the present application can be applied to GaN HEMT devices having a back barrier structure or other structures on the back surface, and to GaN HEMT devices having various polar faces such as Ga face and N face.

[0113] Additionally, applicant has tested other raw materials, process operations and process conditions as described in the above examples and specification, and in each case has obtained ideal results.

[0114] It should be noted that the technical solutions of the present application are not limited to the above specific embodiments, and as long as they do not deviate from the spirit and scope of the present application, all technical modifications made based on the technical solutions of the present application are included in the protection scope of the present application.

[0115] (Additional Note) (Appendix 1) An epitaxial structure including a heterojunction mainly composed of a first semiconductor layer and a second semiconductor layer, in which a carrier channel is formed between the first semiconductor layer and the second semiconductor layer; a high electron mobility transistor structure comprising a source, a drain and a gate electrically connected through said carrier channel and interdigitated with said epitaxial structure, a ratio of an orthogonal projection of the grid foot of the gate on the first semiconductor layer to an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more.

[0116] (Appendix 2) an orthogonal projection of the grid foot on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer overlap each other; and / or the carrier channel is distributed within an area covered by a orthogonal projection of the gate on the epitaxial structure.

[0117] (Appendix 3) The epitaxial structure further comprises an ohmic contact layer, the ohmic contact layer contacting a carrier channel, and the source and drain are both disposed on the ohmic contact layer and form ohmic contacts with the ohmic contact layer; Preferably, the ohmic contact layer and the carrier channel form an ohmic contact.

[0118] (Appendix 4) A groove is formed in a region of the ohmic contact layer corresponding to the gate. B is further distributed, and at least the bottom of the grid foot and the second semiconductor layer are both B Located within and / or the gate and the ohmic contact layer are electrically insulated by a dielectric layer, or the gate and the ohmic contact layer are insulated by air.

[0119] (Appendix 5) The group B the sidewall and the surface of the first semiconductor layer form an angle of 60 to 90°; and / or the gate cap of said gate is B 5. The high electron mobility transistor structure of claim 4, further comprising a dielectric layer overlying said first insulating layer.

[0120] (Appendix 6) 4. The high electron mobility transistor structure of claim 3, wherein the ohmic contact layer comprises a heavily doped region and a highly resistive region, the heavily doped region being disposed at the heterojunction and forming an ohmic contact with the carrier channel, the source and drain both forming ohmic contacts with the heavily doped region, the highly resistive region being disposed in the heavily doped region, and the source and gate, and the drain and gate are both separated by the highly resistive region.

[0121] (Appendix 7) an upper surface of the heavily doped region is higher than a surface of the carrier channel; and / or the heavily doped region includes a first heavily doped region blended with the source and a second heavily doped region blended with the drain, the first heavily doped region and the second heavily doped region being disposed on either side of the second semiconductor layer, the high resistance region includes a first highly resistive region blended with the source and a second highly resistive region blended with the drain, and at least a portion of the source and drain form ohmic contacts with the first heavily doped region and the second heavily doped region through the first highly resistive region and the second highly resistive region.

[0122] (Appendix 8) 8. The high electron mobility transistor structure of claim 7, wherein the carrier channel is a two-dimensional electron gas channel, the second semiconductor layer is disposed on the first semiconductor layer, and the heavily doped region is n-type; or the carrier channel is a two-dimensional hole gas channel and the heavily doped region is p-type.

[0123] (Appendix 9) 9. The high electron mobility transistor structure of claim 8, wherein the first semiconductor layer includes a first region and a second region, a protrusion is formed in the first region, the second semiconductor layer is provided on the protrusion, and the first heavily doped region and the second heavily doped region are provided on the second region and distributed on both sides of the protrusion.

[0124] (Appendix 10) a cap layer is distributed between the gate and the second semiconductor layer; Preferably, the gate and cap layer are electrically insulated by a dielectric layer; and / or the epitaxial structure further comprises an insertion layer distributed between the first semiconductor layer and the second semiconductor layer.

[0125] (Appendix 11) 11. The high electron mobility transistor structure of claim 10, wherein the epitaxial structure has a Ga-polar or N-polar surface.

[0126] (Appendix 12) the gate includes a gate cap and a grid foot, the gate cap being disposed on and supported by the high resistance region, the grid foot being disposed within the epitaxial structure, the carrier channel being distributed beneath the grid foot; and / or the size of the gate cap along the source / drain channel direction is larger than the size of the grid foot along the source / drain channel direction, and the size of the grid foot along the source / drain channel direction is equal to or smaller than the length of the carrier channel; Preferably, the gate is a T-shaped grid and / or the gate and the second semiconductor layer are electrically insulated by a dielectric layer; 7. The high electron mobility transistor structure of claim 6, further comprising a sidewall dielectric layer between a sidewall of the grid foot and the high resistance region.

[0127] (Appendix 13) a dielectric layer is provided between the gate and the heterojunction; and / or the dielectric layer further separates the gate and the high resistance region, or the gate and the high resistance region are directly insulated by air; and / or the dielectric layer extends further to cover a surface of the epitaxial structure, and the source and drain are integrated with the epitaxial structure through corresponding windows in the dielectric layer.

[0128] (Appendix 14) The high resistance region is formed by secondary epitaxial growth or by being transformed from a portion of the heavily doped region; and / or the interface between the heavily doped region and the highly resistive region is mutationally doped or incrementally doped.

[0129] (Appendix 15) 7. The high electron mobility transistor structure of claim 6, further comprising an isolation region formed in the epitaxial structure for isolating an active region.

[0130] (Appendix 16) the material of the epitaxial structure is made of a III-V compound, and / or the high electron mobility transistor structure comprises a nitrogen polarity HEMT device structure or a HEMT device structure having a back barrier structure; and / or the high electron mobility transistor structure is a depletion mode device structure or an enhancement mode device structure; and / or the high electron mobility transistor structure further comprises a substrate, the epitaxial structure being formed on the substrate; and / or the epitaxial structure further comprises a buffer layer distributed between the substrate and the first semiconductor layer.

[0131] (Appendix 17) fabricating an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; a source and drain electrically connected through said carrier channel, said source and drain being integrated with said epitaxial structure, said source and drain being electrically connected through said carrier channel, and said method for fabricating said high electron mobility transistor structure comprising the steps of: a step of manufacturing a gate comprising: setting a size of a grid foot of the gate so as to satisfy a condition that an overlap rate between an orthogonal projection of a grid foot of the gate on a first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more.

[0132] (Appendix 18) specifically, forming a first semiconductor layer and a second semiconductor layer on a substrate by sequentially growing the first semiconductor layer and the second semiconductor layer; providing a mask on a gate region of the second semiconductor layer, and matching a radial size of the mask with a radial size of the grid foot; Etching away unmasked areas of the second semiconductor layer until an etching depth reaches or penetrates the surface of the first semiconductor layer; growing an ohmic contact layer on at least the source region and the drain region of the first semiconductor layer such that a surface height of the second semiconductor layer is equal to or lower than a surface height of an ohmic contact layer and the ohmic contact layer is in contact with a carrier channel; After removing the mask, fabricating a gate on the second semiconductor layer, and forming the source and drain on the source and drain regions of the ohmic contact layer, respectively, so that both the source and drain form ohmic contacts with the ohmic contact layer; Preferably, the ohmic contact layer forms an ohmic contact with the carrier channel.

[0133] (Appendix 19) an ohmic contact layer is grown on a region of the surface of the first semiconductor layer that is not covered by the second semiconductor layer such that the surface of the ohmic contact layer is higher than the surface of the second semiconductor layer; B After forming the grid foot, at least the bottom of the grid foot is B 19. The method of claim 18, further comprising removing the mask and forming the gate such that the mask is distributed within the gate.

[0134] (Appendix 20) 20. The method of claim 18 or 19, further comprising the steps of: after growing and forming the ohmic contact layer, first removing the mask; forming a continuous dielectric layer on the ohmic contact layer and the second semiconductor layer; forming the gate on the dielectric layer; opening a window on the dielectric layer; and forming the source and drain in the window.

[0135] (Appendix 21) After the ohmic contact layer is grown and formed, the source and drain are first formed on the ohmic contact layer, a sacrificial layer is formed continuously on the ohmic contact layer, the source and drain are embedded in the sacrificial layer, at least the mask surface is exposed from the sacrificial layer, and then the mask is Q and forming a gate on the second semiconductor layer; 20. The method according to claim 18 or 19, wherein the gate and the ohmic contact layer are directly insulated by air.

[0136] (Appendix 22) Specifically, the manufacturing method described in Appendix 21 includes the steps of forming the mask on a gate region of the second semiconductor layer, forming a dielectric layer at least on a sidewall of the mask, and then sequentially performing an etching operation on the second semiconductor layer and an operation of growing the ohmic contact layer on the first semiconductor layer.

[0137] (Appendix 23) forming a heavily doped region and a highly resistive region on the heterojunction, the highly resistive region being disposed on the heavily doped region, and the heavily doped region being in ohmic contact with the carrier channel, thereby forming the epitaxial structure; forming ohmic contacts between the source and drain and heavily doped regions, and isolating the source and gate, and the drain and gate, respectively, by highly resistive regions; Preferably, the carrier channel in the heterojunction is distributed within an area covered by a positive projection of the gate on the epitaxial structure.

[0138] (Appendix 24) in particular, growing a first semiconductor layer and a second semiconductor layer on a substrate; A mask is provided on a region of the surface of the second semiconductor layer corresponding to a gate, and all of the source contact region and the drain contact region of the second semiconductor layer are removed. conductor etching the second semiconductor layer and the first semiconductor layer using the mask until a source contact region and a drain contact region of the layer are partially removed, forming a protrusion in a region of the first semiconductor layer corresponding to a gate, and distributing a remaining portion of the second semiconductor layer on the protrusion; growing a heavily doped layer on a remaining portion of the source contact region and the drain contact region of the first semiconductor layer to form a heavily doped region, such that an upper surface of the heavily doped region is above a surface of the carrier channel, and then growing a highly resistive layer on the heavily doped layer to form a highly resistive region, forming the epitaxial structure; or or growing a heavily doped layer on remaining portions of the source contact region and the drain contact region of the first semiconductor layer, converting a semiconductor material from a surface of the heavily doped layer to a predetermined depth in the heavily doped layer into a high resistance material, forming a high resistance region and a heavily doped region in the heavily doped layer such that the predetermined depth is higher than a surface of the carrier channel, and further forming the epitaxial structure; and removing the mask to form the source, drain, and gate.

[0139] (Appendix 25) Specifically, the method further includes forming a dielectric layer between the gate and the heterojunction; and / or the gate includes a grid foot and a gate cap sequentially distributed along a direction away from the second semiconductor layer, and a radial size of the grid foot is equal to or smaller than a radial size of the gate cap, preferably the gate includes a T-shaped grid; And / or the manufacturing method specifically further includes the step of forming a sidewall dielectric layer between the grid foot of the gate and the high resistance region, or directly insulating the gate and the high resistance region by air; And / or the manufacturing method specifically further includes forming a buffer layer between the substrate and the first semiconductor layer; And / or the manufacturing method according to claim 17 or 24, further comprising forming an isolation region in the epitaxial structure to isolate an active region.

[0140] (Appendix 26) 17. Use of a high electron mobility transistor structure according to any one of claims 1 to 16 in the manufacture of a power amplifier, an RF device, a communications device or an electronic device.

[0141] (Appendix 27) 17. A power amplifier comprising a high electron mobility transistor structure according to any one of claims 1 to 16.

[0142] (Appendix 28) 28. The power amplifier according to claim 27, comprising an RF band, a millimeter wave band, or a terahertz band power amplifier.

Claims

1. an epitaxial structure including a heterojunction mainly composed of a first semiconductor layer and a second semiconductor layer, in which a carrier channel is formed between the first semiconductor layer and the second semiconductor layer; a high electron mobility transistor structure comprising a source, a drain and a gate electrically connected through said carrier channel and interdigitated with said epitaxial structure, an overlapping ratio between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more; The epitaxial structure further comprises an ohmic contact layer, the ohmic contact layer contacting a carrier channel, and the source and drain are both disposed on the ohmic contact layer and form ohmic contacts with the ohmic contact layer; Preferably, the ohmic contact layer and the carrier channel form an ohmic contact, a groove is further distributed in a region of the ohmic contact layer corresponding to the gate, and at least a bottom of the grid foot and the second semiconductor layer are both disposed within the groove; 2. A high electron mobility transistor structure, comprising: a gate and an ohmic contact layer, the gate and the ohmic contact layer being insulated by air.

2. an orthogonal projection of the grid foot on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer overlap each other; 2. The high electron mobility transistor structure of claim 1, wherein the carrier channel is distributed within an area covered by an orthogonal projection of the gate onto the epitaxial structure.

3. a sidewall of the groove and a surface of the first semiconductor layer form an angle of 60 to 90 degrees; 2. The high electron mobility transistor structure of claim 1, wherein: and / or a gate cap of the gate covers a dielectric layer over the groove.

4. the material of the epitaxial structure is made of a III-V compound, and / or the high electron mobility transistor structure includes a nitrogen polarity HEMT device structure or a HEMT device structure having a back barrier structure; and / or the high electron mobility transistor structure is a depletion mode device structure or an enhancement mode device structure; and / or the high electron mobility transistor structure further comprises a substrate, the epitaxial structure being formed on the substrate; 10. The high electron mobility transistor structure of claim 1, wherein the epitaxial structure further comprises a buffer layer distributed between the substrate and the first semiconductor layer.

5. an epitaxial structure including a heterojunction mainly composed of a first semiconductor layer and a second semiconductor layer, in which a carrier channel is formed between the first semiconductor layer and the second semiconductor layer; a high electron mobility transistor structure comprising a source, a drain and a gate electrically connected through said carrier channel and interdigitated with said epitaxial structure, an overlapping ratio between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more; The epitaxial structure further comprises an ohmic contact layer, the ohmic contact layer contacting a carrier channel, and the source and drain are both disposed on the ohmic contact layer and form ohmic contacts with the ohmic contact layer; Preferably, the ohmic contact layer and the carrier channel form an ohmic contact, the ohmic contact layer comprises a heavily doped region and a highly resistive region, the heavily doped region being disposed at the heterojunction and forming an ohmic contact with the carrier channel, the source and drain both forming ohmic contacts with the heavily doped region, the highly resistive region being disposed in the heavily doped region, and the source and gate, and the drain and gate are both separated by the highly resistive region.

6. an upper surface of the heavily doped region is higher than a surface of the carrier channel; and / or the heavily doped region includes a first heavily doped region blended with the source and a second heavily doped region blended with the drain, the first heavily doped region and the second heavily doped region being disposed on both sides of the second semiconductor layer, the high resistance region includes a first highly resistive region blended with the source and a second highly resistive region blended with the drain, and at least a portion of the source and drain form ohmic contacts with the first heavily doped region and the second heavily doped region through the first highly resistive region and the second highly resistive region.

7. 7. The high electron mobility transistor structure of claim 6, wherein the carrier channel is a two-dimensional electron gas channel, the second semiconductor layer is disposed on the first semiconductor layer, and the heavily doped region is n-type; or the carrier channel is a two-dimensional hole gas channel, and the heavily doped region is p-type.

8. 8. The high electron mobility transistor structure of claim 7, wherein the first semiconductor layer includes a first region and a second region, a protrusion is formed in the first region, the second semiconductor layer is provided on the protrusion, and the first heavily doped region and the second heavily doped region are provided on the second region and distributed on both sides of the protrusion.

9. a cap layer is distributed between the gate and the second semiconductor layer; Preferably, the gate and cap layer are electrically insulated by a dielectric layer; 7. The high electron mobility transistor structure of claim 6, wherein the epitaxial structure further comprises an insertion layer distributed between the first and second semiconductor layers.

10. 10. The high electron mobility transistor structure of claim 9, wherein the epitaxial structure has a Ga-polar or N-polar surface.

11. the gate includes a gate cap and a grid foot, the gate cap being disposed on and supported by the high resistance region, the grid foot being disposed within the epitaxial structure, the carrier channel being distributed beneath the grid foot; and / or the size of the gate cap along the source / drain channel direction is larger than the size of the grid foot along the source / drain channel direction, and the size of the grid foot along the source / drain channel direction is equal to or smaller than the length of the carrier channel; Preferably, the gate is a T-shaped grid and / or the gate and the second semiconductor layer are electrically insulated by a dielectric layer; 6. The high electron mobility transistor structure of claim 5, further comprising a sidewall dielectric layer preferably provided between a sidewall of said grid foot and said high resistance region.

12. a dielectric layer is provided between the gate and the heterojunction; and / or the dielectric layer further separates the gate and the high resistance region, or the gate and the high resistance region are directly insulated by air; and / or the dielectric layer further extends to cover a surface of the epitaxial structure, and the source and drain are integrated with the epitaxial structure through corresponding windows opened in the dielectric layer.

13. The high resistance region is formed by secondary epitaxial growth or by being transformed from a portion of the heavily doped region; 6. A high electron mobility transistor structure according to claim 5, characterized in that the interface between the heavily doped region and the highly resistive region is mutationally doped or incrementally doped.

14. 6. The high electron mobility transistor structure of claim 5, further comprising isolation regions formed in the epitaxial structure for isolating active regions.

15. Use of a high electron mobility transistor structure according to any one of claims 1 to 14 in the manufacture of power amplifiers, RF devices, communication devices or electronic devices.

16. A power amplifier comprising a high electron mobility transistor structure according to any one of claims 1 to 14.

17. 17. The power amplifier according to claim 16, comprising an RF band, a millimeter wave band, or a terahertz band power amplifier.

18. fabricating an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; a source and drain electrically connected through said carrier channel, said source and drain being integrated with said epitaxial structure, said source and drain being electrically connected through said carrier channel, and said method for fabricating said high electron mobility transistor structure comprising the steps of: The step of manufacturing a gate includes setting a size of the grid foot of the gate so as to satisfy a condition that an overlap rate between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more; specifically, forming a first semiconductor layer and a second semiconductor layer on a substrate by sequentially growing the first semiconductor layer and the second semiconductor layer; providing a mask on a gate region of the second semiconductor layer, and matching a radial size of the mask with a radial size of the grid foot; Etching away unmasked areas of the second semiconductor layer until an etching depth reaches or penetrates the surface of the first semiconductor layer; growing an ohmic contact layer on at least the source region and the drain region of the first semiconductor layer such that a surface of the second semiconductor layer is equal to or lower than a surface of an ohmic contact layer and the ohmic contact layer is in contact with a carrier channel; After removing the mask, fabricating a gate on the second semiconductor layer, and forming the source and drain on the source and drain regions of the ohmic contact layer, respectively, so that both the source and drain form ohmic contacts with the ohmic contact layer; Preferably, the ohmic contact layer forms an ohmic contact with the carrier channel; after growing and forming the ohmic contact layer, first removing the mask, forming a continuous dielectric layer on the ohmic contact layer and the second semiconductor layer, forming the gate on the dielectric layer, opening a window in the dielectric layer, and forming the source and drain in the window.

19. fabricating an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; a source and drain electrically connected through said carrier channel, said source and drain being integrated with said epitaxial structure, said source and drain being electrically connected through said carrier channel, and said method for fabricating said high electron mobility transistor structure comprising the steps of: The step of manufacturing a gate includes setting a size of the grid foot of the gate so as to satisfy a condition that an overlap rate between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more; specifically, forming a first semiconductor layer and a second semiconductor layer on a substrate by sequentially growing the first semiconductor layer and the second semiconductor layer; providing a mask on a gate region of the second semiconductor layer, and matching a radial size of the mask with a radial size of the grid foot; Etching away unmasked areas of the second semiconductor layer until an etching depth reaches or penetrates the surface of the first semiconductor layer; growing an ohmic contact layer on at least the source region and the drain region of the first semiconductor layer such that a surface of the second semiconductor layer is equal to or lower than a surface of an ohmic contact layer and the ohmic contact layer is in contact with a carrier channel; After removing the mask, fabricating a gate on the second semiconductor layer, and forming the source and drain on the source and drain regions of the ohmic contact layer, respectively, so that both the source and drain form ohmic contacts with the ohmic contact layer; Preferably, the ohmic contact layer forms an ohmic contact with the carrier channel; After growing and forming the ohmic contact layer, the method further includes the steps of first forming the source and drain on the ohmic contact layer, forming a sacrificial layer continuous with the ohmic contact layer, embedding the source and drain in the sacrificial layer, exposing at least the mask surface from the sacrificial layer, and then removing the mask to form a gate on the second semiconductor layer; Preferably, the gate and the ohmic contact layer are directly insulated by air.

20. Specifically, the method of claim 19 includes the steps of forming the mask on a gate region of the second semiconductor layer, forming a dielectric layer at least on a sidewall of the mask, and then sequentially performing an etching operation on the second semiconductor layer and an operation of growing the ohmic contact layer on the first semiconductor layer.

21. 20. The method of claim 18, further comprising the steps of growing an ohmic contact layer on a region of the surface of the first semiconductor layer that is not covered by the second semiconductor layer such that a surface of the ohmic contact layer is higher than a surface of the second semiconductor layer, and after forming grooves in the ohmic contact layer, removing the mask and forming the gate such that at least a bottom of the grid foot is distributed within the groove.

22. fabricating an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; a source and drain electrically connected through said carrier channel, said source and drain being integrated with said epitaxial structure, said source and drain being electrically connected through said carrier channel, and said method for fabricating said high electron mobility transistor structure comprising the steps of: The step of manufacturing a gate includes setting a size of the grid foot of the gate so as to satisfy a condition that an overlap rate between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more; forming a heavily doped region and a highly resistive region on the heterojunction, the highly resistive region being disposed on the heavily doped region, and the heavily doped region being in ohmic contact with the carrier channel, thereby forming the epitaxial structure; forming ohmic contacts between the source and drain and heavily doped regions, and isolating the source and gate, and the drain and gate, respectively, by highly resistive regions; Preferably, the carrier channels in the heterojunction are distributed within the area covered by the orthogonal projection of the gate onto the epitaxial structure.

23. in particular, growing a first semiconductor layer and a second semiconductor layer on a substrate; providing a mask on a region of the surface of the second semiconductor layer corresponding to a gate, and etching the second semiconductor layer and the first semiconductor layer using the mask until the source contact region and the drain contact region of the second semiconductor layer are entirely removed and the source contact region and the drain contact region of the first semiconductor layer are partially removed, so that the region of the first semiconductor layer corresponding to the gate becomes a protrusion and the remaining portion of the second semiconductor layer is distributed on the protrusion; growing a heavily doped layer on a remaining portion of the source contact region and the drain contact region of the first semiconductor layer to form a heavily doped region, such that an upper surface of the heavily doped region is above a surface of the carrier channel, and then growing a highly resistive layer on the heavily doped layer to form a highly resistive region, forming the epitaxial structure; or or growing a heavily doped layer on remaining portions of the source contact region and the drain contact region of the first semiconductor layer, converting a semiconductor material from a surface of the heavily doped layer to a predetermined depth in the heavily doped layer into a high resistance material, forming a high resistance region and a heavily doped region in the heavily doped layer such that the predetermined depth is higher than a surface of the carrier channel, and further forming the epitaxial structure; 23. The method of claim 22, further comprising the step of: removing the mask to form the source, drain and gate.

24. fabricating an epitaxial structure including a heterojunction including a first semiconductor layer and a second semiconductor layer, the heterojunction having a carrier channel formed between the first semiconductor layer and the second semiconductor layer; a source and drain electrically connected through said carrier channel, said source and drain being integrated with said epitaxial structure, said source and drain being electrically connected through said carrier channel, and said method for fabricating said high electron mobility transistor structure comprising the steps of: The step of manufacturing a gate includes setting a size of the grid foot of the gate so as to satisfy a condition that an overlap rate between an orthogonal projection of the grid foot of the gate on the first semiconductor layer and an orthogonal projection of the second semiconductor layer on the first semiconductor layer is 80% or more; Specifically, the method further includes forming a dielectric layer between the gate and the heterojunction; and / or the gate includes a grid foot and a gate cap sequentially distributed along a direction away from the second semiconductor layer, and a radial size of the grid foot is equal to or smaller than a radial size of the gate cap, preferably the gate includes a T-shaped grid; And / or the manufacturing method specifically further includes the step of forming a sidewall dielectric layer between the grid foot of the gate and the high resistance region, or directly insulating the gate and the high resistance region by air; And / or the manufacturing method specifically further includes forming a buffer layer between the substrate and the first semiconductor layer; And / or the method for manufacturing a high electron mobility transistor structure further comprises the step of forming an isolation region in the epitaxial structure for isolating an active region.

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