Semiconductor Device

Abstract

To provide a semiconductor device having stable characteristics and suitable for miniaturization and a method for manufacturing the same.SOLUTION: An electric fuse element EH has a first portion P1, a second portion P2 located at one end of the first portion P1, and a third portion P3 located at the other end of the first portion P1. The resistive element RS is located separately from the electric fuse element EH. Each of the electric fuse element EH and the resistive element RS has a material of silicon metal or nickel-chromium. The electric fuse element EH and the resistive element RS are arranged in the upper layer of the first wiring FI and in the lower layer of the second wiring SI. The wiring widths W2 of the second portion P2 and W3 of the third portion P3 are larger than the wiring width W1 of the first portion P1.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. Place Regarding. [Background technology]

[0002] A semiconductor device having a structure in which the resistance value does not vary even when stress is applied is disclosed, for example, in Japanese Patent Laid-Open Publication No. 2011-155192 (Patent Document 1). In Patent Document 1, a metal resistive element layer is formed in the region between the passivation film and the top aluminum wiring. This makes it possible to realize a high-precision resistive element with little variation in resistance value due to molding stress after the packaging process, and to form a high-precision analog circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-155192 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in semiconductor devices incorporating various elements, there is a demand for further stabilization of characteristics and miniaturization.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to a semiconductor device of one embodiment, a first metal film has a first portion, a second portion disposed at one end of the first portion, and a third portion disposed at the other end of the first portion. The second metal film is disposed separately from the first metal film. The material of each of the first metal film and the second metal film includes silicon metal or nickel chromium. The first metal film and the second metal film are disposed in an upper layer of the first wiring and in a lower layer of the second wiring. At least one of the second portion and the third portion has a wiring width larger than that of the first portion.

[0007] In a semiconductor device according to another embodiment, the material of the electrical fuse element that can be the target for melting and removing when replacing the specific circuit section with the redundant circuit section includes a silicon metal film or nickel chrome.

[0008] A method for manufacturing a semiconductor device according to one embodiment includes the following steps. A first wiring is formed. A first metal film having a first portion, a second portion disposed at one end of the first portion, and a third portion disposed at the other end of the first portion is formed in an upper layer of the first wiring. A second metal film separated from the first metal film is formed in an upper layer of the first wiring. A second wiring is formed in an upper layer of the first metal film and the second metal film. The material of each of the first metal film and the second metal film includes silicon metal or nickel chromium. The first metal film is formed so that at least one of the second portion and the third portion has a wiring width wider than the first portion. The first metal film and the second metal film are formed simultaneously. Effect of the Invention

[0009] According to the above embodiment, a semiconductor device having stable characteristics and suitable for miniaturization is provided. Place It can be achieved. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to an embodiment in a chip state; [Diagram 2] FIG. 1 is a plan view illustrating a schematic configuration of a semiconductor chip in which a redundant circuit is formed. [Diagram 3] FIG. 1 is a diagram showing a circuit configuration having an electrical fuse. [Figure 4] 5A and 5B are cross-sectional views showing the configuration of a semiconductor device of one embodiment, in which (A) is a cross-sectional view taken along line IVA-IVA in FIG. 5A, and (B) is a cross-sectional view taken along line IVB-IVB in FIG. 5B. [Diagram 5] FIG. 1A is a diagram showing a configuration of a semiconductor device according to an embodiment, and is a plan view showing a configuration of a resistance element, and FIG. 1B is a plan view showing a configuration of an electrical fuse element. [Figure 6] 6 is a diagram showing a state in which the second wiring is omitted from FIG. 5 and a first wiring FI8 is added, in which (A) is a plan view showing the configuration of a resistance element and (B) is a plan view showing the configuration of an electrical fuse element. FIG. [Figure 7] FIG. 2 is a plan view showing a configuration in which resistance elements are connected in parallel. [Figure 8] 11 is a cross-sectional view showing a configuration in which a resistance element and an electrical fuse element are each electrically connected to a second wiring. FIG. [Figure 9] 1 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 4 is a cross-sectional view showing a second step of the method for manufacturing a semiconductor device according to the embodiment. [Figure 11] 5 is a cross-sectional view showing a third step of the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 12] 4 is a cross-sectional view showing a fourth step of the method for manufacturing a semiconductor device according to the embodiment. FIG. [Figure 13] 5 is a cross-sectional view showing a fifth step of the method for manufacturing a semiconductor device according to the embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and redundant descriptions will not be repeated. In addition, in the drawings, the configuration or manufacturing method may be omitted or simplified for convenience of explanation. In addition, at least a part of the embodiment and each modified example may be combined with each other in any desired manner.

[0012] In addition, the semiconductor device in the embodiments described below is not limited to a semiconductor chip, but may be a semiconductor wafer before being divided into semiconductor chips, or may be a semiconductor package in which a semiconductor chip is sealed with resin. In addition, in this specification, a plan view means a viewpoint seen from a direction perpendicular to the surface of a semiconductor substrate.

[0013] <Configuration of Semiconductor Device in Chip State> First, the configuration of a chip as a configuration of a semiconductor device according to this embodiment will be described with reference to FIG.

[0014] As shown in FIG. 1, the semiconductor device SC in this embodiment is, for example, a microcomputer. The semiconductor device SC is, for example, in a chip state, and has a semiconductor substrate. Electrical elements are arranged on the surface and above the semiconductor substrate. The semiconductor device SC has, for example, a RAM (Random Access Memory) region RA, a redundant circuit region RB, a power supply circuit region RC, a CPU (Central Processing Unit) region RD, and a peripheral circuit region RE. The power supply circuit region RC has, for example, an oscillator circuit region RF. The semiconductor device SC has a plurality of pad electrodes PD. Each of the plurality of pad electrodes PD is electrically connected to an electrical element arranged in the semiconductor device SC.

[0015] An oscillator circuit is disposed in the oscillator circuit region RF. The oscillator circuit generates an output signal with a predetermined oscillation period by an oscillation operation, for example, by repeatedly charging and discharging a capacitance element. The oscillator circuit is, for example, a high-speed on-chip oscillator (HOCO) circuit, but may also be a low-speed on-chip oscillator (LOCO) circuit, or may include both a HOCO circuit and a LOCO circuit.

[0016] The oscillator circuit has a constant current circuit that outputs a signal of a constant voltage level, and the constant current circuit includes a resistive element. The oscillator circuit also has a differential amplifier circuit, and the differential amplifier circuit also includes a resistive element. Resistive elements are also included in other circuits.

[0017] A spare redundant circuit section is arranged in the redundant circuit area RB. The spare redundant circuit section has the same function as a specific circuit section having a predetermined function. An electric fuse that is blown and removed is provided to replace the specific circuit section with the redundant circuit section.

[0018] <Configuration and Function of Redundant Circuit and Electrical Fuse> Next, the configurations and functions of the redundant circuit section and the electrical fuses will be described with reference to FIGS.

[0019] As shown in Fig. 2, a plurality of blocks (specific circuit parts) N1, N2, ..., Nm are arranged in the semiconductor device SC. Each of the plurality of blocks N1, N2, ..., Nm has the same function as each other. Each of the plurality of blocks N1, N2, ..., Nm is composed of a plurality of memory cells in the RAM area RA (Fig. 1), for example.

[0020] A blowable fuse H1, H2, ..., Hm is formed to inactivate each of the multiple blocks N1, N2, ..., Nm. A spare redundant block (redundant circuit section) RED having the same function as any of the inactivated blocks N1, N2, ..., Nm is also arranged so that it can replace the inactivated blocks. The redundant block RED is arranged in a redundant circuit area RB (FIG. 1).

[0021] The potential of the ground power supply GD is applied to the gate electrode of the MOS (Metal Oxide Semiconductor) transistor TR via the fuse Hs, so that the MOS transistor TR is held in a non-conductive state, and the redundant block RED is thus electrically isolated within the semiconductor device SC.

[0022] Further, in order to detect defects in each of the plurality of blocks N1, N2, . . . , Nm, test pad electrodes PDa and PDb are arranged.

[0023] Next, a functional test of the semiconductor device configured as above will be described, in which a fuse is blown and removed by energizing the device.

[0024] First, an electrical signal is applied from a functional testing device (hereinafter also referred to as a tester) (not shown) through the test pad electrodes PDa and PDb. If the semiconductor device SC is normal, an expected signal corresponding to the applied electrical signal is output from the test pad electrodes PDa and PDb. At this time, the tester judges whether the semiconductor device SC is good or bad based on the correlation between the electrical signal applied to the semiconductor device SC and the electrical signal output from the tester. If any of the blocks N1, N2, ..., Nm is judged to be bad, the bad block is replaced with a redundant block RED. This allows the semiconductor device SC to fulfill the functions that it should originally achieve, which creates the possibility that the semiconductor device SC will be a good product.

[0025] The replacement of the defective block with the redundant block RED is performed as follows: When a defect in, for example, block N1 is detected by the above-mentioned functional test, fuses H1 and Hs are blown and removed by energization. The blowing of fuse H1 electrically isolates the defective block N1 within the semiconductor device SC.

[0026] On the other hand, when the fuse Hs is blown, the voltage of the power supply PV is applied to the gate electrode of the MOS transistor TR through the resistor RR, which causes the MOS transistor TR to become conductive, and the defective block N1 is replaced by the redundant block RED.

[0027] Next, the melting and removal of the electrical fuse element, which is melted and removed by energization, will be described with reference to FIG.

[0028] 3, the electrical fuse element EH is a fuse that is blown by passing a current through it, rather than by irradiation with a laser beam. A blower transistor CT is provided as a switching element for passing a current through the electrical fuse element EH.

[0029] One end of the electrical fuse element EH is electrically connected to a power supply voltage (Vdd). The other end of the electrical fuse element EH is electrically connected to a drain D of the breaker transistor CT. The source S of the breaker transistor CT is connected to a ground potential (GND).

[0030] A level shifter LS is electrically connected to the gate G of the fusing transistor CT. The level shifter LS inputs a signal for turning the fusing transistor CT on and off to the gate G of the fusing transistor CT. A core part CO is electrically connected to the other end of the electrical fuse element EH and the drain of the fusing transistor CT.

[0031] If any of the blocks N1, N2, ..., Nm (Fig. 2) is determined to be defective, the level shifter LS turns on the cutoff transistor CT. This causes a current to flow through the electrical fuse element EH, which is then blown and removed. The core part CO is a determination circuit that determines the state of the electrical fuse element EH, and if it is determined to have been blown and removed, replacement is performed based on this determination result.

[0032] <Configuration of Resistance Element and Electrical Fuse Element> Next, the configurations of the resistance element and the electrical fuse element included in the semiconductor device in this embodiment will be described with reference to Figures 4 to 8. As described above, the resistance element is arranged, for example, in the oscillation circuit region RF (Figure 1), but is not limited thereto and may be arranged in another region.

[0033] As shown in Figures 4(A) and 4(B), the first wiring FI is disposed on an interlayer insulating layer (not shown). The first wiring FI is made of a conductor, for example, a metal (including an alloy). The first wiring FI is made of, for example, aluminum (Al), copper (Cu), aluminum-copper (AlCu), etc. The first wiring FI is an electric wiring that transmits an electric signal. However, the first wiring FI may be a dummy wiring. The dummy wiring is a wiring that is electrically isolated from other electric elements and does not transmit an electric signal.

[0034] As shown in FIG. 4A, an interlayer insulating layer I1 is disposed so as to cover the first wiring FI. The upper surface of the interlayer insulating layer I1 is planarized. A via hole Va1 is provided in the interlayer insulating layer I1. The via hole Va1 extends from the upper surface of the interlayer insulating layer I1 to the first wiring FI. A via conductive layer Vca1 is embedded in the via hole Va1. The via conductive layer Vca1 is made of, for example, tungsten (W).

[0035] A resistor element RS (second metal film) is disposed on the upper surface of the interlayer insulating layer I1. The resistor element RS is made of, for example, a metal (including an alloy), such as silicon metal, nickel chromium (NiCr), etc. The silicon metal is, for example, silicon chromium (SiCr) or silicon chromium doped with carbon (SiCrC).

[0036] Each of one end and the other end of the resistor element RS is electrically connected to the first wiring FI through the via conductive layer Vca1. Specifically, one end of the resistor element RS is electrically connected to the first wiring FI1 through the via conductive layer Vca1, and the other end of the resistor element RS is electrically connected to the first wiring FI4 through the via conductive layer Vca1.

[0037] An interlayer insulating layer I2 is disposed so as to cover the resistor element RS. The upper surface of the interlayer insulating layer I2 is planarized. A via hole V2 is provided so as to extend from the upper surface of the interlayer insulating layer I2 through the interlayer insulating layers I2 and I1 to the first wiring FI. A via conductive layer Vc2 is embedded in the via hole V2. The via conductive layer Vc2 is made of, for example, tungsten.

[0038] The second wiring SI is disposed on the upper surface of the interlayer insulating layer I2. The second wiring SI is made of a conductor, for example, a metal (including an alloy). The second wiring SI is made of, for example, aluminum, copper, or aluminum-copper. The second wiring SI is an electric wiring that transmits an electric signal. However, the second wiring SI may be a dummy wiring that is electrically isolated from other electric elements and does not transmit an electric signal.

[0039] One of the multiple second wirings SI is electrically connected to the first wiring FI through the via conductive layer Vc2. Specifically, the second wiring SI1 is electrically connected to the first wiring FI4 through the via conductive layer Vc2. An interlayer insulating layer I3 is disposed so as to cover the second wiring SI. The upper surface of the interlayer insulating layer I3 is flattened.

[0040] 4B, a via hole Vb1 is provided in the interlayer insulating layer I1. The via hole Vb1 extends from the upper surface of the interlayer insulating layer I1 to the first wiring FI. A via conductive layer Vcb1 is embedded in the via hole Vb1. The via conductive layer Vcb1 is made of, for example, tungsten.

[0041] An electrical fuse element EH (first metal film) is disposed on the upper surface of the interlayer insulating layer I1. The electrical fuse element EH is made of, for example, a metal (including an alloy), such as silicon metal, nickel chrome, etc. The silicon metal is, for example, silicon chrome, or silicon chrome doped with carbon.

[0042] Each of one end and the other end of the electrical fuse element EH is electrically connected to the first wiring FI through the via conductive layer Vcb1. Specifically, one end of the electrical fuse element EH is electrically connected to the first wiring FI6 through the via conductive layer Vcb1, and the other end of the electrical fuse element EH is electrically connected to the first wiring FI7 through the via conductive layer Vcb1.

[0043] An interlayer insulating layer I2 is disposed so as to cover the electrical fuse element EH. The upper surface of the interlayer insulating layer I2 is planarized. A second wiring SI may be disposed on the upper surface of the interlayer insulating layer I2. However, it is preferable that the second wiring SI is not disposed in the region directly above the electrical fuse element EH. This is because, if the electrical fuse element EH is blown and removed, the second wiring SI located directly above the electrical fuse element EH may be damaged by the blown and removed. An interlayer insulating layer I3 is disposed on the interlayer insulating layer I2. The upper surface of the interlayer insulating layer I3 is planarized as described above.

[0044] 4A and 4B, each of the resistance element RS and the electrical fuse element EH is disposed in an upper layer of the first wiring FI and in a lower layer of the second wiring SI. The resistance element RS and the electrical fuse element EH are disposed in the same layer and have the same composition.

[0045] 5A, the resistance element RS may have, for example, a plurality of resistance parts RSa, RSb, RSc, RSd (a plurality of metal parts). Each of the plurality of resistance parts RSa to RSd is made of, for example, a metal (including an alloy), such as silicon metal, nickel chrome, or the like. The silicon metal is, for example, silicon chrome, or silicon chrome doped with carbon. Note that the resistance element RS is not limited to the four resistance parts RSa to RSd, and may have two, three, five or more resistance parts.

[0046] The resistor portions RSa to RSd may be connected in series, for example in the order of resistor portion RSa, resistor portion RSb, resistor portion RSc, and resistor portion RSd.

[0047] Specifically, one longitudinal end of the resistor RSa is electrically connected to one longitudinal end of the resistor RSb via the first wiring FI1. The other longitudinal end of the resistor RSb is electrically connected to one longitudinal end of the resistor RSc via the first wiring FI2. The other longitudinal end of the resistor RSc is electrically connected to one longitudinal end of the resistor RSd via the first wiring FI3.

[0048] The resistor element RS is preferably arranged so as to meander in a planar view. The longitudinal directions of the resistor sections RSa to RSd are, for example, along the same direction and parallel to each other. In this arrangement, the longitudinal ends of adjacent resistor sections are electrically connected to each other via the first wirings FI1 to FI3 as described above, so that the resistor element RS is configured to meander in a planar view.

[0049] If the resistance element RS is meandering in a plan view, the longitudinal directions of the plurality of resistance portions RSa to RSd do not have to be along the same direction.

[0050] In plan view, the other end in the longitudinal direction of the resistor portion RSa is electrically connected to the second wiring SI1 via the first wiring FI4, and in plan view, the other end in the longitudinal direction of the resistor portion RSd is electrically connected to the second wiring SI2 via the first wiring FI5.

[0051] 5B, the electrical fuse element EH is disposed separately from the resistance element RS. The electrical fuse element EH has a first portion P1, a second portion P2, and a third portion P3. The second portion P2 is disposed at one end of the first portion P1. The third portion P3 is disposed at the other end of the first portion P1. The first portion P1 is sandwiched between the second portion P2 and the third portion P3.

[0052] At least one of the second portion P2 and the third portion P3 has a wiring width W2, W3 larger than the wiring width W1 of the first portion P1. In this embodiment, each of the maximum wiring width W2 of the second portion P2 and the maximum wiring width W3 of the third portion P3 is larger than the wiring width W1 of the first portion P1.

[0053] The second portion P2 has a tapered portion TP2 and a pad portion PD2 in a plan view. The tapered portion TP2 is connected to the first portion P1. The pad portion PD2 is connected to the tapered portion TP2. The tapered portion TP2 is disposed between the first portion P1 and the pad portion PD2. The tapered portion TP2 is configured such that the wiring width gradually increases from the first portion P1 toward the pad portion PD2 in a plan view. The pad portion PD2 has, for example, a rectangular shape in a plan view.

[0054] The third portion P3 has a tapered portion TP3 and a pad portion PD3 in a plan view. The tapered portion TP3 is connected to the first portion P1. The pad portion PD3 is connected to the tapered portion TP3. The tapered portion TP3 is disposed between the first portion P1 and the pad portion PD3. The tapered portion TP3 is configured such that the wiring width gradually increases from the first portion P1 toward the pad portion PD3 in a plan view. The pad portion PD3 has, for example, a rectangular shape in a plan view. The tapered portions TP2 and TP3 may not be present, and the pad portions PD2 and PD3 may be directly connected to the first portion P1.

[0055] The pad portion PD2 is electrically connected to the first wiring FI6 through a via hole Vb1. The pad portion PD3 is electrically connected to the first wiring FI7 through a via hole Vb1.

[0056] 5A and 5B, the wiring width W1 of the first portion P1 in the electrical fuse element EH is smaller than the wiring width WB of each of the multiple resistance parts RSa to RSd. Note that the wiring widths WB of each of the multiple resistance parts RSa to RSd are preferably the same as each other, but may be different from each other.

[0057] As shown in Figures 4A and 4B, the wiring length LB of the electrical fuse element EH is smaller than the wiring length LA of the resistance element RS. As shown in Figures 5A and 5B, when the resistance element RS is composed of a plurality of resistance parts RSa to RSd connected in series, the wiring length LB of the electrical fuse element EH is smaller than the sum of the wiring lengths LA of the plurality of resistance parts RSa to RSd.

[0058] As shown in Fig. 6(B), the area of ​​the region where the first wiring FI and the electrical fuse element EH overlap in a plan view (the hatched area in the figure) is smaller than the area of ​​the region where the first wiring FI and the resistance element RS overlap in a plan view (the hatched area in the figure) as shown in Fig. 6(A). By reducing the area of ​​the first wiring FI8 that overlaps with the electrical fuse element EH in a plan view in this way, the electrical fuse element EH becomes less likely to dissipate heat and more likely to melt.

[0059] 6A, when there are multiple overlapping regions between the resistor RS and the first wiring FI, the sum of the areas of the multiple overlapping regions is compared with the area of ​​the overlapping region between the first wiring FI and the electrical fuse element EH. Similarly, when there are multiple overlapping regions between the first wiring FI and the electrical fuse element EH, the sum of the areas of the multiple overlapping regions is compared with the area of ​​the overlapping region between the first wiring FI and the resistor RS.

[0060] 6B shows a configuration in which the first wiring FI8 is provided below the electrical fuse element EH in order to clarify the overlapping region between the electrical fuse element EH and the first wiring FI. However, the first wiring FI8 does not have to be provided in the region directly below the electrical fuse element EH as shown in FIGS. 4B and 5B.

[0061] As shown in FIG. 7, when the resistance element RS is composed of a plurality of resistance parts RSa to RSd, the plurality of resistance parts RSa to RSd may be connected in parallel to each other. In this case, the longitudinal directions of the plurality of resistance parts RSa to RSd are, for example, along the same direction and are parallel to each other. In this arrangement, one ends of the plurality of resistance parts RSa to RSd are electrically connected to each other by a first wiring FI11 through a via hole V1. The other ends of the plurality of resistance parts RSa to RSd are electrically connected to each other by another first wiring FI12 through the via hole V1. The first wiring FI11 is electrically connected to a second wiring SI11 through a via hole V2. The first wiring FI12 is electrically connected to a second wiring SI12 through a via hole V2.

[0062] If the plurality of resistor portions RSa to RSd are connected in parallel with one another, the longitudinal directions of the plurality of resistor portions RSa to RSd do not have to be along the same direction.

[0063] 8, each of the resistance element RS and the electrical fuse element EH may be electrically connected to the second wiring SI. In this case, the resistance element RS is electrically connected to the second wiring SI by a via conductive layer Vca3 that fills a via hole Va3 provided in the interlayer insulating layer I2. Also, the electrical fuse element EH is electrically connected to the second wiring SI by a via conductive layer Vcb3 that fills a via hole Vb3 provided in the interlayer insulating layer I2.

[0064] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

[0065] First, a semiconductor substrate (not shown) is prepared, and electrical elements (not shown) such as MOS transistors are formed on the surface of the semiconductor substrate. An interlayer insulating layer is formed on the surface of the semiconductor substrate so as to cover the electrical elements formed on the surface of the semiconductor substrate. Wiring is formed on the interlayer insulating layer. By repeatedly forming interlayer insulating layers and wiring in this manner, a multilayer wiring structure is formed.

[0066] 9(A) and 9(B), a first wiring FI is formed as one wiring of a multilayer wiring structure. The first wiring FI is formed, for example, by forming a metal (aluminum, copper, aluminum and copper, etc.) on an interlayer insulating layer and then patterning it by photolithography technology, etching technology, etc.

[0067] 10A and 10B, an interlayer insulating layer I1 is formed so as to cover the first wiring FI. The interlayer insulating layer I1 is made of, for example, silicon oxide (SiO 2 ) is formed. Then, CMP (Chemical Mechanical Polishing) is performed, which flattens the upper surface of the interlayer insulating layer I1.

[0068] Thereafter, via holes Va1 and Vb1 are formed in the interlayer insulating layer I1 by photolithography. Each of the via holes Va1 and Vb1 is formed so as to reach the first wiring FI from the upper surface of the interlayer insulating layer I1.

[0069] Thereafter, a conductive layer is formed on the upper surface of the interlayer insulating layer I1 so as to fill each of the via holes Va1 and Vb1. The conductive layer is, for example, tungsten. A barrier metal layer may be formed between the conductive layer and the interlayer insulating layer. The barrier metal layer is, for example, titanium nitride (TiN).

[0070] Then, CMP is performed on the upper surface of the buried conductive layer. This exposes the upper surface of the interlayer insulating layer I1, and the buried conductive layer remains inside each of the via holes Va1 and Vb1. The buried conductive layer remaining inside each of the via holes Va1 and Vb1 forms via conductive layers Vca1 and Vcb1.

[0071] 11(A) and 11(B), a metal layer SM is formed on the upper surface of the interlayer insulating layer I1 by, for example, sputtering. The metal layer SM is made of, for example, silicon metal (SiCr, SiCrC), nickel chromium, or the like.

[0072] As shown in Figures 12(A) and 12(B), a photoresist (organic photosensitive film) PR is applied onto the metal layer SM. The photoresist PR is patterned into a predetermined shape by exposure and development. The metal layer SM is etched using the patterned photoresist PR as a mask.

[0073] The metal layer SM is patterned by this etching, and the resistance element RS and the electrical fuse element EH are simultaneously formed from the metal layer SM. The resistance element RS and the electrical fuse element EH are formed so as to be separated from each other. As a result, the resistance element RS and the electrical fuse element EH are formed in the same layer and with the same composition.

[0074] The resistance element RS is formed so as to be electrically connected to the first wiring FI through the via conductive layer Vca1 that fills the via hole Va1. The electrical fuse element EH is formed so as to be electrically connected to the first wiring FI through the via conductive layer Vcb1 that fills the via hole Vb1. After that, the photoresist PR is removed by ashing or the like.

[0075] As shown in Figures 13(A) and 13(B), an interlayer insulating layer I2 is then formed on the interlayer insulating layer I1 so as to cover the resistor element RS and the electrical fuse. The interlayer insulating layer I2 is made of, for example, silicon oxide. Then, CMP is performed on the upper surface of the interlayer insulating layer I2. This flattens the upper surface of the interlayer insulating layer I2.

[0076] Thereafter, a via hole V2 is formed in the interlayer insulating layers I1 and I2 by photolithography and etching techniques. The via hole V2 is formed so as to reach the first wiring FI from the upper surface of the interlayer insulating layer I2.

[0077] Thereafter, a conductive layer is formed on the upper surface of the interlayer insulating layer I2 so as to fill the via hole V2. The conductive layer is, for example, tungsten. A barrier metal layer may be formed between the conductive layer and the interlayer insulating layer. The barrier metal layer is, for example, titanium nitride.

[0078] Then, CMP is performed on the upper surface of the buried conductive layer. This exposes the upper surface of the interlayer insulating layer I2, and the buried conductive layer remains inside the via hole V2. The buried conductive layer remaining inside the via hole V2 forms a via conductive layer Vc2.

[0079] 4(A) and 4(B), the second wiring SI is formed on the upper surface of the interlayer insulating layer I2 as one of the wirings in the multilayer wiring structure. The second wiring SI is formed by forming a metal (aluminum, copper, aluminum-copper, etc.) on the interlayer insulating layer I2 and then patterning it by photolithography, etching, etc.

[0080] An interlayer insulating layer I3 is formed so as to cover the second wiring SI. The interlayer insulating layer I3 is formed of, for example, silicon oxide. Then, CMP is performed on the upper surface of the interlayer insulating layer I3. This flattens the upper surface of the interlayer insulating layer I3.

[0081] In this manner, the semiconductor device according to this embodiment shown in FIGS. 4(A) and 4(B) is manufactured.

[0082] <Effects> In this embodiment, silicon metal (silicon chrome) used as the material for the metal films EH and RS has a sheet resistance of 300 to 1300 Ω / □ and a melting point of 1306°C. Nickel chrome used as the material for the metal films EH and RS has a sheet resistance of 5 to 200 Ω / □ and a melting point of 1400°C. On the other hand, polycrystalline silicon has a sheet resistance of 360 Ω / □ and a melting point of 1414°C. Due to the above characteristics, silicon metal (silicon chrome) and nickel chrome can be cut off with a smaller cutting current than polycrystalline silicon.

[0083] According to this embodiment, as shown in Fig. 5(B), each of the second portion P2 and the third portion P3 of the metal film EH has a width wider than that of the first portion P1. This allows the metal film EH to be used as, for example, an electrical fuse element EH. As described above, silicon metal or nickel chromium can be blown with a smaller blowing current than polycrystalline silicon. Therefore, by using the metal film EH as, for example, the electrical fuse element EH, the fusing transistor CT (Fig. 3) can be made smaller. Therefore, the semiconductor device SC of this embodiment is suitable for miniaturization.

[0084] As shown in Figures 5(A) and 5(B), the metal film RS is separated from the metal film EH. Therefore, the metal film RS can be used as an element other than the electrical fuse element EH. Silicon metal or nickel chrome has a smaller temperature dependency of resistance than polycrystalline silicon. Therefore, by using the metal film RS as, for example, a resistor element RS, the characteristics such as resistance are stabilized.

[0085] In addition, silicon metal has a higher sheet resistance than polycrystalline silicon, which means that by using the metal film RS as a resistor element RS, for example, a large resistance can be obtained with a short wiring length, which also makes it possible to reduce the size.

[0086] Furthermore, the metal film EH and the metal film RS are disposed between the first wiring FI and the second wiring SI. During resin sealing, stress acts on the metal film EH and the metal film RS due to the difference in thermal expansion coefficient between the sealing resin and the semiconductor substrate, but the first wiring FI and the second wiring SI function as a buffer to relieve the stress. Therefore, the stress caused by the difference in thermal expansion coefficient between the sealing resin and the semiconductor substrate during resin sealing is less likely to act on the metal films RS and EH. This prevents the characteristics of the elements constituted by the metal film RS and the elements constituted by the metal film EH from fluctuating due to the influence of stress, and stable characteristics can be obtained.

[0087] As a result, a semiconductor device having stable characteristics and suitable for miniaturization can be realized.

[0088] According to the present embodiment, the metal film EH is the electrical fuse element EH, and the metal film RS is the resistance element RS, thereby making it possible to realize stable characteristics and miniaturization in the semiconductor device SC having the electrical fuse element EH and the resistance element RS.

[0089] Furthermore, according to this embodiment, as shown in FIG. 5(A) or FIG. 7, the resistance element RS has a plurality of resistance portions RSa to RSd, which are connected in series or in parallel.

[0090] 5A, the resistor elements RSa to RSd are connected in series, and the resistor elements RS are arranged in a zigzag pattern in plan view, thereby making it possible to reduce the wiring width and ensure a long resistor length while occupying a small planar area.

[0091] 6A and 6B, in this embodiment, the area where the first wiring FI8 and the electrical fuse element EH overlap in a plan view is smaller than the area where the first wirings FI9 and FI10 overlap with the resistance element RS. The electrical fuse element EH is a portion to be blown and removed. Therefore, by reducing the area of ​​the first wiring FI8 that overlaps with the electrical fuse element EH in a plan view, the electrical fuse element EH is less likely to dissipate heat and is more likely to be blown.

[0092] 4A and 4B, according to this embodiment, the wiring length LB of the electrical fuse element EH is smaller than the wiring length LA of the resistance element RS. This makes it easy to increase the wiring resistance of the resistance element RS. Also, it makes it easy to identify the portion of the electrical fuse element EH that is to be blown and removed.

[0093] 5A and 5B, the wiring width W1 of the electrical fuse element EH is smaller than the wiring width WB of the resistance element RS, which makes it easier to blow and remove the electrical fuse element EH.

[0094] 5(A) and 5(B), the electrical fuse element EH and the resistance element RS are disposed in the same layer and have the same composition. This allows the electrical fuse element EH and the resistance element RS to be formed simultaneously from the same layer. This simplifies the manufacturing process compared to when the electrical fuse element EH and the resistance element RS are formed separately.

[0095] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0096] CO core section, CT transistor for disconnection, D drain, EH electric fuse element (metal film), FI, FI1 to FI12 first wiring, G gate, GD ground power supply, H1, H2, Hm, Hs fuse, I1, I2, I3 interlayer insulating layer, LS level shifter, N1 block, P1 first section, P2 second section, P3 third section, PD pad electrode, PD2, PD3 pad section, PDa, PDb test pad electrode, PR photoresist, PV power supply, RA RAM area, RB redundant circuit area, RC power supply circuit area, RD CPU area, RE peripheral circuit area, RED redundant block, RF oscillator area, RR resistor, RS resistor element (metal film), RSa, RSb, RSc, RSd resistor section, S source, SC semiconductor device, SI, SI1, SI2 second wiring, SM metal layer, TP2, TP3 taper section, TR Transistors, V2, Va1, Vb1 via holes, Vc2, Vca1, Vcb1 via conductive layers.

Claims

1. A first wiring; A second wiring; a first metal film having a first portion, a second portion disposed at one end of the first portion, and a third portion disposed at the other end of the first portion; a second metal film disposed separately from the first metal film; the first metal film and the second metal film each have a material selected from the group consisting of silicon metal and nickel chromium; the first metal film and the second metal film are disposed in an upper layer of the first wiring and in a lower layer of the second wiring; At least one of the second portion and the third portion has a wiring width larger than that of the first portion; A semiconductor device, wherein the wiring length of the first metal film is shorter than the wiring length of the second metal film.

2. 2. The semiconductor device according to claim 1, wherein said first metal film is a fuse element, and said second metal film is a resistor element.

3. The resistor element has a plurality of resistor portions, The semiconductor device according to claim 2 , wherein the plurality of resistance sections are connected in series or in parallel.

4. The semiconductor device according to claim 3 , wherein said plurality of resistance portions are connected in series, and said resistance elements are arranged in a meandering manner in a plan view.

5. 2 . The semiconductor device according to claim 1 , wherein an area where said first wiring and said first metal film overlap in a plan view is smaller than an area where said first wiring and said second metal film overlap.

6. 2. The semiconductor device according to claim 1, wherein a wiring width of said first metal film is smaller than a wiring width of said second metal film.

7. 2. The semiconductor device according to claim 1, wherein said first metal film and said second metal film are disposed in the same layer and have the same composition.

8. A first wiring; A second wiring; a first metal film having a first portion, a second portion disposed at one end of the first portion, and a third portion disposed at the other end of the first portion; a second metal film disposed separately from the first metal film; the first metal film and the second metal film each have a material selected from the group consisting of silicon metal and nickel chromium; the first metal film and the second metal film are disposed in an upper layer of the first wiring and in a lower layer of the second wiring; At least one of the second portion and the third portion has a wiring width larger than that of the first portion; a first wiring and a second metal film overlapping each other in a plan view, the first wiring and the second metal film overlapping each other in a plan view, the first wiring and the second metal film overlapping each other in a plan view, the second metal film and the second metal film overlapping each other in a plan view, the second metal film and the first wiring ...

9. A first wiring; A second wiring; a first metal film having a first portion, a second portion disposed at one end of the first portion, and a third portion disposed at the other end of the first portion; a second metal film disposed separately from the first metal film; the first metal film and the second metal film each have a material selected from the group consisting of silicon metal and nickel chromium; the first metal film and the second metal film are disposed in an upper layer of the first wiring and in a lower layer of the second wiring; At least one of the second portion and the third portion has a wiring width larger than that of the first portion; A semiconductor device, wherein the wiring width of the first metal film is smaller than the wiring width of the second metal film.

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