Semiconductor wafer and method for manufacturing the same

Abstract

To inhibit chipping or cracking during dicing of a wafer.SOLUTION: A semiconductor wafer 101 is diced along a plurality of dicing lines 41 and 42 in a first direction and a second direction different from the first direction so that a chip 12 can be cut out of an effective region 10. The semiconductor wafer 101 comprises a deposition pattern 3. The at least one dicing line included in the plurality of dicing lines 41 and 42 is an on-pattern dicing line 43, the overall length or partial length of which overlaps the deposition pattern 3.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to semiconductor wafers and methods for manufacturing semiconductor wafers. [Background technology]

[0002] In the dicing process, the wafer is fixed to a chuck table (CT) with UV tape and cut into chips with a blade. If the wafer is warped or distorted, the stress inherent in the wafer will be released during dicing, causing chipping or cracks in the chips.

[0003] Incidentally, the chipping or cracking that occurs during dicing is also pointed out in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2016-105463 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the conventional technology, it is unavoidable to press or fix a warped or distorted wafer onto the flat surface of a chuck table, so the stress inherent in the wafer dissipates within the effective area during dicing, resulting in chipping or cracks on the side or bottom of the device, which can lead to potential defects.

[0006] In addition, when wafers are diced with a blade, the impact on the wafer is large, and as a result, dicing often proceeds in an unstable state due to variations in conditions such as the amount of warping or distortion of the wafer, the adhesion and retention strength of the UV tape on the chuck table, or the grinding performance of the blade, which can lead to concerns that chipping or cracking of devices will be promoted and occur frequently.

[0007] The present disclosure has been made to solve the above problems, and aims to suppress chipping or cracking during wafer dicing. [Means for solving the problem]

[0008] The present disclosure One The semiconductor wafer is diced along a plurality of dicing lines in a first direction and a second direction different from the first direction, so that chips are cut out from an effective area. The semiconductor wafer has a deposition pattern. At least one dicing line included in the plurality of dicing lines is an on-pattern dicing line whose entire length or a portion of its length overlaps the deposition pattern. The on-pattern dicing lines are five or less dicing lines among the multiple dicing lines in the first direction, in order of the earliest cutting in the dicing process. Effect of the Invention

[0009] According to the semiconductor wafer of the present disclosure, at least a portion of the dicing line overlaps with the deposition pattern, which makes it possible to suppress chipping or cracking during dicing of the semiconductor wafer. [Brief description of the drawings]

[0010] [Figure 1] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Diagram 2] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Diagram 3] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 4] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Diagram 5] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 6]11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 7] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 8] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 9] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 10] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 11] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 12] 11 is a plan view of a semiconductor wafer showing an example of the arrangement of on-pattern DLs and on-pattern DL portions. FIG. [Figure 13] FIG. 2 is a plan view showing a unit pattern of the first photomask. [Figure 14] FIG. 2 is a plan view showing a first photomask in which unit patterns are arranged in two rows and two columns. [Figure 15] FIG. 4 is a plan view showing a unit pattern of a second photomask. [Figure 16] FIG. 13 is a plan view showing a second photomask in which unit patterns are arranged in two rows and two columns. [Figure 17] FIG. 4 is a plan view showing a unit pattern of a third photomask. [Figure 18] FIG. 13 is a plan view showing a third photomask in which unit patterns are arranged in two rows and two columns. [Figure 19] FIG. 13 is a diagram showing the arrangement of a photomask with respect to a base wafer with little warpage. [Figure 20] FIG. 13 is a diagram showing the arrangement of a photomask with respect to a base wafer having a large warpage. [Figure 21] FIG. 2 is a plan view of a semiconductor wafer on which a film formation pattern is formed. [Figure 22] 1 is a cross-sectional view of a semiconductor wafer on which a film formation pattern is formed. [Diagram 23] FIG. 2 is a diagram showing a configuration of a deposition pattern. [Figure 24] FIG. 2 is a diagram showing a configuration of a deposition pattern. [Diagram 25] FIG. 2 is a diagram showing a configuration of a deposition pattern. [Figure 26] FIG. 2 is a diagram showing a configuration of a deposition pattern. [Figure 27] FIG. 2 is a diagram showing a configuration of a deposition pattern. [Figure 28] FIG. 2 is a diagram showing a configuration of a deposition pattern. [Figure 29] FIG. 2 is a diagram showing a configuration of a deposition pattern. [Diagram 30] FIG. 13 is a diagram showing a deposition pattern having a flat upper surface and a single layer. [Diagram 31] FIG. 1 shows a two-layer film formation pattern in which the entire upper surface is flat. [Diagram 32] FIG. 13 is a diagram showing a deposition pattern of a single layer whose entire upper surface is inclined. [Diagram 33] FIG. 13 is a diagram showing a deposition pattern of a single layer whose entire upper surface is inclined. [Diagram 34] FIG. 13 is a diagram showing a two-layer film formation pattern in which the entire upper surface is inclined. [Diagram 35] FIG. 13 is a diagram showing a two-layer film formation pattern in which the entire upper surface is inclined. [Diagram 36] FIG. 13 is a diagram showing a deposition pattern of a single layer having a partially inclined upper surface. [Figure 37] FIG. 13 is a diagram showing a two-layer film formation pattern with a part of the upper surface being inclined. [Figure 38] FIG. 13 is a diagram showing a deposition pattern of a single layer having a partially inclined upper surface. [Figure 39] FIG. 13 is a diagram showing a two-layer film formation pattern with a part of the upper surface being inclined. [Diagram 40] 1 is a cross-sectional view of a semiconductor wafer showing a deposition pattern provided apart from a chip end portion. [Diagram 41] 1 is a cross-sectional view of a semiconductor wafer in which the DL is entirely covered with a deposition pattern. [Diagram 42] 1 is a cross-sectional view of a semiconductor wafer in which a portion of a chip end portion is covered with a deposition pattern. [Diagram 43] 1 is a cross-sectional view of a semiconductor wafer in which the entire surface of a chip is covered with a film pattern. [Diagram 44] FIG. 13 is a plan view showing a film formation pattern formed continuously in the longitudinal direction of the DL. [Diagram 45] FIG. 11 is a plan view showing deposition patterns arranged at equal intervals in the longitudinal direction of the DL. [Figure 46] FIG. 13 is a plan view showing a deposition pattern that is divided into small parts and arranged in the longitudinal direction of the DL. [Figure 47] 1A to 1C are diagrams showing a combination of a cross-sectional form and a planar form of a deposition pattern. [Figure 48] FIG. 11 is a plan view showing a film formation pattern disposed obliquely with respect to a chip pattern. [Figure 49] FIG. 2 is a plan view showing a film formation pattern constituting the TEG. [Figure 50] 3 is a cross-sectional view showing a film formation pattern constituting the TEG. [Figure 51] FIG. 2 is a plan view showing a film formation pattern constituting the TEG. [Figure 52] FIG. 2 is a plan view showing a film formation pattern constituting the TEG. [Figure 53] FIG. 2 is a plan view showing a film formation pattern constituting the TEG. [Figure 54] FIG. 2 is a plan view showing a film formation pattern constituting the TEG. [Figure 55] FIG. 2 is a plan view showing a film formation pattern that constitutes an alignment mark. [Figure 56] FIG. 2 is a plan view showing a film formation pattern that constitutes an alignment mark. [Figure 57] FIG. 2 is a plan view showing a film formation pattern that constitutes an alignment mark. [Figure 58] FIG. 2 is a plan view showing a film formation pattern constituting a target. [Figure 59] 1 is a plan view showing a deposition pattern constituting a reference marking; [Figure 60] FIG. 2 is a plan view showing a deposition pattern constituting a monitor pattern. [Figure 61] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 62] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 63] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 64] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 65] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 66] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 67] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 68] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 69] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 70] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 71] It is a plan view showing a film-forming pattern constituting a monitor pattern. [Figure 72] It is a plan view showing a film-forming pattern with a name drawn. [Figure 73] It is a plan view showing a film-forming pattern with a design or logo mark drawn. [Figure 74] It is a plan view showing a film-forming pattern with a design or logo mark drawn. [Figure 75] It is a plan view showing a film-forming pattern with a design or logo mark drawn. [Figure 76] It is a plan view showing a film-forming pattern with an administrative number drawn.

Mode for Carrying Out the Invention

[0011] <A. Embodiment 1> FIG. 1 is a plan view of the semiconductor wafer 101 according to Embodiment 1. In FIG. 1, the vertical direction of the paper surface is the x-axis, and the horizontal direction of the paper surface is the y-axis. The directions of these axes are the same in other plan views described later.

[0012] The semiconductor wafer 101 is cut in the x direction and the y direction along a plurality of dicing lines (hereinafter also referred to as DLs). In FIG. 1, the DL 41 in the x direction is represented by a dashed arrow, and the illustration of the DL in the y direction is omitted. In actuality, the DL is a region on the semiconductor wafer 101, but in FIG. 1 and the following figures, for easy understanding of the direction of the DL, the dashed arrows representing the DL 41 etc. are extended outside the semiconductor wafer 101.

[0013] The semiconductor wafer 101 includes an effective region 10 where chips 12 cut out by dicing exist, and an invalid region 11 other than that.

[0014] A film formation pattern is formed on the semiconductor wafer 101 according to Embodiment 1. At least one of the plurality of DLs for cutting the semiconductor wafer 101 is a pattern-on DL 43 that overlaps the film formation pattern in its entire length or a partial length. And the portion of the pattern-on DL 43 that overlaps the film formation pattern is referred to as a pattern-on DL portion 44.

[0015] In the example of FIG. 1, three of the plurality of DLs 41 in the x direction are pattern-on DLs 43, and all of the pattern-on DLs 43 are pattern-on DL portions 44.

[0016] Hereinafter, the layout of the pattern-on DL 43 and the pattern-on DL portion 44 in the semiconductor wafer 101 will be described.

[0017] <A-1-1. Arrangement of the pattern-on DL portion 44> The following are assumed for the arrangement of the pattern-on DL portion 44.

[0018] (1) As shown in FIG. 1, the DL portion 44 on the pattern may be arranged in the effective region 10 and the invalid region 11 among the DLs 41 in the x direction.

[0019] (2) As shown in FIG. 2, the DL portion 44 on the pattern may be arranged only in the chip 12 in the outermost effective region 10 of the semiconductor wafer 101.

[0020] <A-1-2. Number of DLs 43 on the pattern> The following are assumed for the number of DLs 43 on the pattern.

[0021] (1) The DL 43 on the pattern may be the first one or the first and second ones among the DLs in the x direction. Here, the first DL means the DL that is first cut into the semiconductor wafer 101 in the dicing process, and the second DL means the DL that is first cut into the semiconductor wafer 101 in the dicing process. Hereinafter, the number of DLs is counted in the order in which the semiconductor wafer 101 is cut in the dicing process.

[0022] FIG. 3 shows a state where the first DL 41 in the x direction is the DL 43 on the pattern. FIG. 4 shows a state where the first and second DLs 41 in the x direction are the DL 43 on the pattern.

[0023] (2) The DL 43 on the pattern may be the DL 41 from the first to the third, from the first to the fourth, or from the first to the fifth in the x direction. FIG. 5 shows a state where the DL 41 from the first to the third in the x direction is the DL 43 on the pattern. FIG. 6 shows a state where the DL 41 from the first to the fifth in the x direction is the DL 43 on the pattern.

[0024] (3) The on-pattern DL43 may be the first to third, first to fourth, or first to fifth DL41 in the x direction, and the first to third, first to fourth, or first to fifth DL42 in the y direction. Fig. 7 shows a state where the first to third DL41 in the x direction and the first to third DL42 in the y direction are the on-pattern DL portion 44. In Fig. 7, the DL42 in the y direction is represented by a dashed arrow.

[0025] <A-1-3. Length of the on-pattern DL portion> The following is assumed for the length of the on-pattern DL portion 44.

[0026] The on-pattern DL portion 44 is part or all of the on-pattern DL43. That is, the length of the on-pattern DL portion 44 is part or all of the total length of the on-pattern DL43.

[0027] Fig. 8 shows a state where all of the two on-pattern DL43 in the x direction are the on-pattern DL portion 44. That is, in Fig. 8, the length of the on-pattern DL portion 44 is the total length of the on-pattern DL43 in the x direction.

[0028] Fig. 9 shows a state where all of the first on-pattern DL43 in the x direction and part of the second on-pattern DL43 in the x direction are the on-pattern DL portion 44. Among the second on-pattern DL43, only the portion with the same length as the first on-pattern DL43 is the on-pattern DL portion 44. That is, in Fig. 9, the length of the on-pattern DL portion 44 is part or all of the total length of the on-pattern DL43 in the x direction.

[0029] Fig. 10 shows a state where, among the two on-pattern DL43 in the x direction, the portion that is 1 / 2 of the total length of each on-pattern DL43 is the on-pattern DL portion 44. That is, in Fig. 10, the length of the on-pattern DL portion 44 is 1 / 2 of the total length of the two on-pattern DL43 in the x direction.

[0030] In the examples of FIGS. 8 to 10, the DL portion 44 on the pattern was arranged regardless of the active region 10 and the inactive region 11. In contrast, in the following examples, the DL portion 44 on the pattern is arranged only in the inactive region 11.

[0031] In the example of FIG. 11, it shows that only the portion of the inactive region 11 among the two DLs 43 on the pattern in the x direction is the DL portion 44 on the pattern. That is, in FIG. 11, the length of the DL portion 44 on the pattern is the length of the portion arranged in the inactive region 11 among the two DLs 43 on the pattern in the x direction.

[0032] In the example of FIG. 12, it shows that only the portion of the inactive region 11 among the two DLs 43 on the pattern in the x direction and the two DLs 43 on the pattern in the y direction is the DL portion 44 on the pattern. That is, in FIG. 12, the length of the DL portion 44 on the pattern is the length of the portion arranged in the inactive region 11 among the two DLs 43 on the pattern in the x direction and the two DLs 43 on the pattern in the y direction.

[0033] <A-2. Effect> The semiconductor wafer 101 of Embodiment 1 is diced along a plurality of dicing lines 41, 42 in the x direction and the y direction, whereby the chip 12 is cut out from the active region 10. The semiconductor wafer 101 includes a film formation pattern 3. At least one dicing line included in the plurality of dicing lines 41, 42 is a dicing line 43 on the pattern whose entire length or partial length overlaps with the film formation pattern 3. Thereby, chipping or cracking during dicing due to the warpage or internal stress of strain of the semiconductor wafer 101 can be reduced.

[0034] By forming the film formation pattern 3 on the DL 43 on the pattern, the following effects are achieved.

[0035] (A) The amount of chipping or cracking spreading from the side surface to the lower surface of the semiconductor wafer 101 can be reduced.

[0036] (a) Conventionally, the size of chipping or cracking on the underside of semiconductor wafer 101 was about half the size of chipping or cracking on the side of semiconductor wafer 101, but this size can be made smaller.

[0037] (c) The amount of chipping on the upper surface of the semiconductor wafer 101 can be reduced.

[0038] Moreover, the warpage stress inherent in the semiconductor wafer 101 only needs to be dissipated once at one of the locations (mainly the outer periphery of the wafer) where warpage or distortion exists within the semiconductor wafer 101. The location where the warpage stress inherent in the semiconductor wafer 101 is to be dissipated can be specified by the number and direction of the DLs 43 on the pattern and the length of the DL portion 44 on the pattern.

[0039] In other words, by providing a film formation pattern in the vicinity of a defective product determined by electrical characteristics or appearance inspection in the invalid area 11 or valid area 10 on the outer periphery of the semiconductor wafer 101, even if it is only for a few DLs 41, 42 that are first cut into the semiconductor wafer 101, the amount of chipping or cracking can be reduced without affecting the product chip 12.

[0040] When the semiconductor wafer 101 is diced using two dicing blades, by providing a film formation pattern on one of the DLs 41 and 42 in the semiconductor wafer 101, the amount of chipping (cracks) can be reduced.

[0041] If 1 / 2 or more of the DL length is cut in the DL that is first cut into the semiconductor wafer 101, the size of chipping (cracks) will decrease rapidly thereafter. Therefore, in the DLs 41 and 42 on the outermost periphery of the semiconductor wafer 101, if about 1 / 2 to 2 / 3 of the total DL length is made the DL portion 44 on the pattern, it is possible to halve chipping (cracks).

[0042] The length of chipping (crack) according to the warp amount of the semiconductor wafer 101 is generally understood. If a maximum of five DLs are used as the DL portion 44 on the pattern, the amount of chipping (crack) can be reduced.

[0043] According to the semiconductor wafer 101 of Embodiment 1, by arranging the DL portion 44 on the pattern in the region where defective products are located in either the invalid region 11 or the valid region 10, a high yield after dicing can be obtained.

[0044] <B. Embodiment 2> <B-1. Photomask> In Embodiment 2, the manufacturing process of the semiconductor wafer 101 of Embodiment 1 will be described. In the pre-process of semiconductor manufacturing, a film-forming pattern is formed on the DL 43 on the pattern of the semiconductor wafer 101. Hereinafter, the state of the semiconductor wafer 101 before the pattern of the chip 12 or the film-forming pattern is formed is referred to as the base wafer BW. Hereinafter, the photomask used in the photolithography process for forming the film-forming pattern on the base wafer BW will be described.

[0045] FIG. 13 shows the unit pattern of the first photomask FM1. FIG. 14 shows the first photomask FM1 in which the unit patterns are combined in two rows and two columns. The first photomask FM1 includes a chip pattern region 51 for drawing the pattern of the chip 12 on the semiconductor wafer 101 and a DL pattern region 52 for forming DLs 41 and 42 on the semiconductor wafer 101. The DL pattern region 52 extends in the x direction and the y direction. The portion of the DL pattern region 52 extending in the x direction is also referred to as the first portion, and the portion extending in the y direction is also referred to as the second portion. In the first photomask FM1, there is no pattern 53 for the film-forming pattern for drawing the film-forming pattern on the semiconductor wafer 101 in the DL pattern region 52.

[0046] FIG. 15 shows the unit pattern of the second photomask FM2. FIG. 16 shows the second photomask FM2 in which the unit patterns are combined in a 2×2 matrix. The second photomask FM2 is obtained by providing a film-forming pattern pattern 53 in all the DL pattern regions 52 in the first photomask FM1.

[0047] FIG. 17 shows the unit pattern of the third photomask FM3. FIG. 18 shows the third photomask FM3 in which the unit patterns are combined in a 2×2 matrix. The third photomask FM3 is obtained by providing a film-forming pattern pattern 53 in either the DL pattern region 52 extending in the x direction or the DL pattern region 52 extending in the y direction in the first photomask FM1.

[0048] <B-2. Photolithography Process> In the photolithography process, the first to third photomasks FM1 - 3 are used in combination according to the degree of warpage or distortion of the base wafer BW.

[0049] When the warpage or distortion of the base wafer BW is small, as shown in FIG. 19, the second photomask FM2 or the third photomask FM3 is drawn in one row from the outer periphery of the base wafer BW, and the first photomask FM1 is drawn in the remaining central portion. Thereby, a film-forming pattern is formed on the outer peripheral portion of the base wafer BW, and no film-forming pattern is formed in the central portion.

[0050] When the warpage or distortion of the base wafer BW is large, the range for drawing the second photomask FM2 or the third photomask FM3 is increased according to the degree of warpage or distortion. In the example of FIG. 20, two rows from the outer periphery of the base wafer BW are defined as the outer peripheral portion, the second photomask FM2 or the third photomask FM3 is drawn in the outer peripheral portion, and the first photomask FM1 is drawn in the remaining central portion. That is, the larger the warpage of the base wafer BW, the larger the width of the outer peripheral portion of the base wafer BW on which the second photomask FM2 or the third photomask FM3 is drawn.

[0051] <B-3. Effect> The method for manufacturing a semiconductor wafer according to Embodiment 2 includes: (a) a step of drawing a first photomask FM1 on the central portion of a semiconductor substrate 17; and (b) a step of drawing a second photomask FM2 or a third photomask FM3 on the outer peripheral portion surrounding the central portion of the semiconductor substrate (17). The first, second, and third photomasks FM1, FM2, and FM3 include a chip pattern region 9 where a chip pattern is formed and a dicing line pattern region 2 where patterns of a plurality of dicing lines 41 and 42 are formed. The dicing line pattern region 2 surrounds the chip pattern region 9 and has a first portion extending in a first direction and a second portion extending in a second direction. In the dicing line pattern region 2 of the second photomask FM2, a film-forming pattern pattern 53 for drawing a film-forming pattern in the first portion and the second portion is formed. In the dicing line pattern region 2 of the third photomask FM3, a film-forming pattern pattern 53 is formed in either one of the first portion and the second portion. The larger the warp of the semiconductor substrate 17, the larger the width of the outer peripheral portion.

[0052] Therefore, according to the method for manufacturing a semiconductor wafer of Embodiment 2, by properly using the first to third photomasks FM1 to FM3 according to the location of the semiconductor wafer 101, the formation location of the film-forming pattern 3 in the semiconductor wafer 101 can be specified. Therefore, a film-forming pattern can be freely formed at a location with warp or distortion on the semiconductor wafer 101. Also, by arranging the film-forming pattern to a minimum, clogging of the dicing blade due to the film-forming pattern can be minimized.

[0053] <C. Embodiment 3> In Embodiment 3, a detailed configuration of the film-forming pattern in the semiconductor wafer 101 of Embodiment 1 will be described.

[0054] <C-1. Configuration> Fig. 21 is a plan view of a semiconductor wafer 101 on which a film formation pattern 3 is formed. Fig. 22 is a cross-sectional view of the semiconductor wafer 101 taken along line AA' in Fig. 21. In Fig. 21, the film formation pattern 3 is continuously formed along DL43 on the x-direction pattern, but may be formed intermittently. Note that the semiconductor wafer 101 may also have a film formation pattern 3 in the y-direction, but since the film formation patterns 3 in the x and y directions have the same configuration, only the film formation pattern 3 in the x direction will be described below.

[0055] The width W1 of the film formation pattern 3 is smaller than the width W2 of the DL 43 on the pattern and is larger than the width W3 of the dicing blade.

[0056] The film quality of the film formation pattern 3 is of a type that can be manufactured in a wafer pre-process, and is used to form the product chip 12. The film formation pattern 3 is made up of a single layer or multiple layers.

[0057] When dicing, the semiconductor wafer 101 is fixed on a UV tape 14 as shown in FIG. 22. The semiconductor wafer 101 is configured to include a semiconductor base material 17 and various layers formed on the semiconductor base material 17 in a wafer pre-process. The semiconductor base material 17 is also called a base wafer BW. The semiconductor base material 17 is Si, SiC, or GaN. In FIG. 22, reference numeral 15 denotes a crack that spreads from the side surface of the chip 12 to the back surface.

[0058] In the wafer pre-processing, other films 166, field film 165, interlayer film 164, electrode 163, glass coat 162, and polyimide film 161 are formed on semiconductor substrate 17. Glass coat 162 is made of an oxide film, a nitride film, or the like. Electrode 163 is made of Al, AlSi, Poly-Si, or the like. Field film 165 and other films 166 are oxide films.

[0059] Therefore, the deposition pattern 3 can have any one of the following configurations (1) to (9). (1) Lamination of polyimide film, glass coating, electrodes and interlayer film (2) Lamination of polyimide film, glass coating and electrodes (3) Lamination of polyimide film and glass coating (4) Glass coating and electrode lamination (5) Lamination of electrodes and interlayer films (6) Electrodes only (7) Interlayer film only (8) Lamination of polyimide film, glass coating, and interlayer film (9) Polyimide film only

[0060] 23 to 29 show the thickness of the film formation pattern 3 in the above configurations (1) to (9). The film formation pattern 3 is a film constituting a product (device) with a thickness that can be manufactured in a wafer pre-process. FIG. 23 shows the case where the film formation pattern 3 is a single layer made of a polyimide film 161. FIG. 24 shows the case where the film formation pattern 3 is a single layer made of a polyimide film 161 or an electrode. FIG. 25 shows the case where the film formation pattern 3 is a two-layered pattern made of an electrode 163 and an interlayer film 164. FIG. 26 shows the case where the film formation pattern 3 is a two-layered pattern made of a glass coat 162 and an electrode 163. FIG. 27 shows the case where the film formation pattern 3 is a two-layered pattern made of a polyimide film 161 and a glass coat. FIG. 28 shows the case where the film formation pattern 3 is a three-layered pattern made of a polyimide film 161, a glass coat 162, and an interlayer film 164, or a three-layered pattern made of a polyimide film 161, a glass coat 162, and an electrode 163. FIG. 29 shows a case where the film pattern 3 is made up of four layers: a polyimide film 161 , a glass coat 162 , an electrode 163 and an interlayer film 164 .

[0061] Figures 30 to 39 show the shape of the upper surface of the film formation pattern 3. Figures 30 and 31 show an example in which the upper surface of the film formation pattern 3 is flat like the film that constitutes the chip 12. The film formation pattern 3 in Figure 30 is a single layer, and the film formation pattern 3 in Figure 31 is two layers.

[0062] Figures 32 to 35 show examples in which the entire upper surface of the film formation pattern 3 is inclined. The film formation pattern 3 in Figures 32 and 33 is a single layer, while the film formation pattern 3 in Figures 34 and 35 is a two-layer. Figures 32 and 34 show a film formation pattern 3 with a small inclination angle of the upper surface, while Figures 33 and 35 show a film formation pattern 3 with a large inclination angle of the upper surface.

[0063] Figures 36 to 39 show examples in which a part of the upper surface of the film formation pattern 3 is inclined. The film formation pattern 3 in Figures 36 and 37 has one inclined surface, and the film formation pattern 3 in Figures 38 and 39 has two inclined surfaces. The film formation pattern 3 in Figures 36 and 38 is a single layer, and the film formation pattern 3 in Figures 27 and 39 is two layers.

[0064] 40 to 43 are cross-sectional views of the semiconductor wafer 101 showing the relationship between the film formation pattern 3 and the chip end portion 121 as the cross-sectional form of the film formation pattern 3. The following four patterns are assumed for the relationship between the film formation pattern 3 and the chip end portion 121.

[0065] (1) As shown in Fig. 40, the film formation pattern 3 is disposed at an appropriate interval so as not to come into contact with the film constituting the chip end portion 121 adjacent to the DL43 on the pattern. This planar form is called "island-like" in Fig. 47. The width W1 of the film formation pattern 3 is smaller than the width W2 of the DL43 on the pattern, and the film formation pattern 3 does not come into contact with the chip 12 adjacent to the DL43 on the pattern.

[0066] (2) As shown in Fig. 41, the film formation pattern 3 covers the entire DL 43 on the pattern and contacts the side of the interlayer film 164 constituting the chip terminal portion 121, i.e., the side of the chip 12. In other words, the width W1 of the film formation pattern 3 is equal to the width W2 of the DL 43 on the pattern. This planar form is referred to as "full DL coverage" in Fig. 47.

[0067] (3) As shown in Fig. 42, the film formation pattern 3 covers the entire pattern DL 43, and also covers part of the side and upper surfaces of the interlayer film 164 and polyimide film 161 that constitute the chip terminal end 121. In other words, the width W1 of the film formation pattern 3 is larger than the width W2 of the pattern DL. This planar form is referred to as "chip terminal end coverage" in Fig. 47.

[0068] (4) As shown in FIG. 43, the film-formed pattern 3 covers the entire DL43 on the pattern, and covers the entire surface of the chip 12 adjacent to the DL43 on the pattern except for the opening 18. That is, the width W1 of the film-formed pattern 3 is larger than the width W2 of the DL43 on the pattern. In the opening 18, the film-formed pattern 3, the polyimide film 161, and the glass coat 162 are locally removed, and the electrode 163 is exposed. The opening 18 is provided to electrically connect the electrode 163 to the outside of the chip 12 by wire bonding or the like. This planar form is referred to as "covering the entire chip" in FIG. 47.

[0069] In any of the above patterns, it is desirable that the width W1 of the film formation pattern 3 is larger than the width W3 of the dicing blade 8 in order to reduce chipping or cracking of the semiconductor wafer 101 during dicing.

[0070] Specifically, it is desirable that the ratio W1 / W3 of the width W1 of the film pattern 3 to the width W3 of the dicing blade 8 be greater than 1.0 and less than 2.4 for patterns (1) and (2), and greater than or equal to 2.4 for patterns (3) and (4).

[0071] By defining the relationship between the width W1 of the deposition pattern 3 and the width W3 of the dicing blade 8 as described above, the remainder of the deposition pattern 3 remains in a part of the DL on the chip after dicing. Therefore, it becomes easy to tell from the appearance, etc., that this configuration is adopted at an early stage of product analysis.

[0072] In pattern (1) where the film formation pattern 3 is arranged in an island shape within DL43 on the pattern, the film formation pattern 3 does not contact the chip end portion 121 and may be a conductive film. In other patterns (2), (3), and (4), the film formation pattern 3 contacts the chip end portion 121 and must be a non-conductive film.

[0073] In addition, in the patterns (3) and (4), instead of forming an additional film on the pattern DL43 in the wafer pre-process, the film formation pattern 3 may be formed by utilizing an existing protective film. That is, the film formation pattern 3 may be formed by extending an existing protective film such as the polyimide film 161 or glass coat 162, which conventionally extends only up to the chip end portion 121, into the pattern DL43.

[0074] The planar configuration of the film formation pattern 3 is assumed to be as follows.

[0075] (1) As shown in Fig. 44, the deposition pattern 3 covers the entire DL 43 on the pattern in the longitudinal direction. This planar form is called "full coverage" in Fig. 47. With "full coverage", the area of ​​the deposition pattern 3 becomes large, and the effect of reducing chipping is improved.

[0076] (2) As shown in Fig. 45, the deposition patterns 3 are intermittently arranged in the longitudinal direction of the DL43 on the pattern. The interval L2 between two adjacent deposition patterns 3 in the longitudinal direction of the DL43 on the pattern is equal to the length L1 of the deposition pattern 3. The number of deposition patterns 3 arranged in the longitudinal direction of one DL43 on the pattern is two or three. This planar form is referred to as "equally spaced division" in Fig. 47.

[0077] (3) As shown in FIG. 46, the deposition patterns 3 are intermittently arranged in the longitudinal direction of the DL43 on the pattern. The number of deposition patterns 3 arranged in the longitudinal direction of one DL43 on the pattern is four or more. The interval L2 between two adjacent deposition patterns 3 in the longitudinal direction of the DL43 on the pattern is arbitrary. This planar form is referred to as "subdivision" in FIG. 47.

[0078] FIG. 47 shows possible combinations of the cross-sectional and planar forms of the film-forming pattern 3. When the planar form of the film-forming pattern 3 is "entire surface coverage", the possible cross-sectional forms of the film-forming pattern 3 are any of "island shape", "DL full coverage", "chip end portion coverage", or "entire chip coverage". When the planar form of the film-forming pattern 3 is "equally spaced division" or "fine division", the possible cross-sectional forms of the film-forming pattern 3 are "island shape" or "DL full coverage".

[0079] As shown in FIG. 48, the longitudinal direction of the film-forming pattern 3 may have an angle θ with respect to the longitudinal direction of the DL43 on the pattern. However, the angle θ is defined within a range where the film-forming pattern 3 does not deviate from the DL43 on the pattern.

[0080] FIG. 48 shows the film-forming pattern 3 having a planar form of "entire surface coverage", but the same applies to the film-forming pattern 3 having a planar form of "equally spaced division" or "fine division". That is, in the case of the film-forming pattern 3 having a planar form of "equally spaced division" or "fine division", the arrangement direction of the film-forming pattern 3 on the DL43 on the pattern is set to have an angle θ with respect to the longitudinal direction of the DL43 on the pattern.

[0081] <C-2. Effect> In the semiconductor wafer 101 of Embodiment 3, the chip 12 includes a semiconductor substrate 17, an interlayer film 164, an electrode 163, and a surface protection film formed on the semiconductor substrate 17, and the film-forming pattern 3 is composed of the same material as at least one of the interlayer film 164, the electrode 163, and the surface protection film. Thus, according to the semiconductor wafer 101, the film-forming pattern 3 can be covered with the films constituting the chip 12. Therefore, it is not necessary to add a special photolithography process to form the film-forming pattern 3 within the DL43 on the pattern, and an increase in man-hours can be avoided. Further, by selecting one film from the plurality of films constituting the chip 12 or combining a plurality of films and adopting them for the film-forming pattern 3, an appropriate effect of reducing chipping can be obtained according to the degree of warping or distortion of the semiconductor wafer 101.

[0082] <D. Embodiment 4> In Embodiment 4, the function of the film formation pattern 3 on the semiconductor wafer 101 will be described.

[0083] <D-1. TEG> FIG. 49 is a plan view showing a film formation pattern 3 having the function of a TEG (Test Element Group). FIG. 50 is a cross-sectional view of the film formation pattern 3 corresponding to FIG. 49. The film formation pattern 3 having the function of a TEG includes a measurement target element 20, a wiring 21, a pad 22, and a protective film 23. The wiring 21 is a routing wiring obtained by forming a conductive layer such as Al, AlSi, or poly-Si. The pad 22 is a place where a probe needle for measuring electrical characteristics hits. The protective film is polyimide or glass coat or the like.

[0084] A plurality of pads 22 are arranged at regular intervals on the semiconductor substrate 17 on the pattern DL43. A measurement target element 20 is arranged between adjacent pads 22. The wiring 21 connects the pad 22 and the measurement target element 20. Although the protective film 23 is not shown in FIG. 49, as shown in FIG. 50, except for the opening 18 of the pad 22, it covers the entire pad 22, the wiring 21, and the measurement target element 20.

[0085] As shown in FIG. 51, a plurality of pads 22 may be connected by the wiring 21 to form one electrode.

[0086] The size of the pad 22 is arbitrary. FIG. 52 shows an example in which the pad 22 is made larger and longer than FIG. 49. The shape, size, and number of the openings 18 of the pad 22 are arbitrary.

[0087] As shown in FIGS. 53 and 54, the wiring 21 connecting the pad 22 and the measurement target element 20 may be extended long and folded back a plurality of times with the same width as the pad 22. The folding width of the wiring 21 may be larger than the width W3 of the dicing blade as shown in FIG. 53, or may be the same as the width W3 of the dicing blade as shown in FIG. 54.

[0088] <D-2. Marks The following describes a film-forming pattern having a function as a mark.

[0089] Figures 55 to 57 show a film-forming pattern 3 that functions as an alignment mark.

[0090] Figure 58 shows a film-forming pattern 3 that functions as a target.

[0091] Figure 59 shows a film-forming pattern 3 that functions as a reference marking.

[0092] The film-forming pattern 3 shown in Figures 55 to 59 is a film-forming pattern mainly used in the photolithography process of the pre-wafer process to improve the overlay accuracy between the film formed in the previous stage and the photomask.

[0093] <D-3. Monitor Pattern The following describes a film-forming pattern having a function as a monitor pattern.

[0094] Figure 60 shows a film-forming pattern 3 as a monitor pattern for measuring film thickness, concentration, reflectance, refractive index, etc.

[0095] Figures 61 and 62 show a film-forming pattern 3 as a monitor pattern for overlay inspection.

[0096] Figures 63 to 65 show a film-forming pattern 3 as a monitor pattern for the shape of contact holes, etc.

[0097] Figures 66 and 67 show a film-forming pattern 3 as a monitor pattern for measuring the dimensions of a photolithography pattern.

[0098] Figures 68 and 69 show a film-forming pattern 3 as a monitor pattern for measuring the length of the cut or remaining part of a photolithography pattern.

[0099] Figure 70 shows the film-forming pattern 3 as a monitor pattern for the grain size in a metal film such as aluminum.

[0100] Figure 71 shows the film-forming pattern 3 as a monitor pattern for observing the finish such as color or gloss.

[0101] The film-forming pattern 3 as the monitor pattern described above is mainly a film-forming pattern for various measurements, inspections, and observation of the finish, etc., when forming product chips by repeating film formation, impurity diffusion, and photolithography processes, etc., in the pre-wafer process.

[0102] <D-4. Name, etc.> Hereinafter, the film-forming pattern with a name, etc., drawn will be described.

[0103] Figure 72 shows the film-forming pattern 3 with a name such as a company name or a manufacturer name drawn.

[0104] Figures 73 to 75 show the film-forming pattern 3 with a design or a logo mark drawn.

[0105] Figure 76 shows the film-forming pattern 3 with a management number such as an ID, S / N, or other alphanumeric characters drawn.

[0106] In addition, the film-forming pattern 3 may have a registered trademark drawn.

[0107] In this embodiment, the film-forming pattern 3 having various functions or with a name, etc., drawn has been described. However, the film-forming pattern 3 may not have these functions and may not have a name drawn.

[0108] In addition, in Embodiment 3, it was described that the film formation pattern 3 employs films constituting the chip 12, which are of types manufacturable in the pre-wafer process. However, the film formation pattern 3 is not essential for the configuration of the chip 12 and may be newly added.

[0109] <D-5. Effect> According to the semiconductor wafer 101 of Embodiment 4, the film formation pattern 3 can be used in combination with other functions such as TEG for purposes other than reducing chipping.

[0110] It should be noted that the embodiments can be freely combined, or each embodiment can be appropriately modified or omitted.

Explanation of Reference Numerals

[0111] 3 Film formation pattern, 8 Dicing blade, 10 Active region, 11 Inactive region, 12 Chip, 14 UV tape, 17 Semiconductor substrate, 18 Opening, 20 Element to be measured, 21 Wiring, 22 Pad, 23 Protective film, 41, 42 Dicing line, 43 Dicing line on pattern, 44 Portion of dicing line on pattern, 51 Chip pattern region, 52 Dicing line pattern region, 53 Pattern for film formation pattern, 101 Semiconductor wafer, 121 Chip end portion, 161 Polyimide film, 162 Glass coat, 163 Electrode, 164 Interlayer film, 165 Field film, BW Base wafer, FM1 First photomask, FM2 Second photomask, FM3 Third photomask.

Claims

1. A semiconductor wafer is diced along a plurality of dicing lines in a first direction and a second direction different from the first direction, so that chips are cut out from an effective area, the semiconductor wafer has a deposition pattern; At least one dicing line included in the plurality of dicing lines is a pattern dicing line whose entire length or a part of its length overlaps the deposition pattern, the dicing lines on the pattern are five or less dicing lines in the order of the earliest cutting in a dicing process among the plurality of dicing lines in the first direction; Semiconductor wafer.

2. A semiconductor wafer in which chips are cut out from an effective area by dicing along a plurality of dicing lines in a first direction and a second direction different from the first direction, the semiconductor wafer has a deposition pattern; At least one dicing line included in the plurality of dicing lines is a pattern dicing line whose entire length or a part of its length overlaps the deposition pattern, the dicing lines on the pattern are 3 to 5 dicing lines in descending order of cutting speed in a dicing process among the plurality of dicing lines in the first direction, and 3 to 5 dicing lines in descending order of cutting speed in a dicing process among the plurality of dicing lines in the second direction, Semiconductor wafer.

3. A semiconductor wafer in which chips are cut out from an effective area by dicing along a plurality of dicing lines in a first direction and a second direction different from the first direction, the semiconductor wafer has a deposition pattern; At least one dicing line included in the plurality of dicing lines is a pattern dicing line whose entire length or a part of its length overlaps the deposition pattern, a dicing line portion on the pattern, which is a portion of each of the dicing lines on the pattern that overlaps the deposition pattern, has a length that is half the total length of each of the dicing lines on the pattern; Semiconductor wafer.

4. A semiconductor wafer in which chips are cut out from an effective area by dicing along a plurality of dicing lines in a first direction and a second direction different from the first direction, the semiconductor wafer has a deposition pattern; At least one dicing line included in the plurality of dicing lines is a pattern dicing line whose entire length or a part of its length overlaps the deposition pattern, a dicing line portion on the pattern, which is a portion of each of the dicing lines on the pattern that overlaps with the deposition pattern, is present only in an invalid area, which is an area other than the valid area of ​​the semiconductor wafer; Semiconductor wafer.

5. The chip comprises: A semiconductor substrate; An interlayer film, an electrode, and a surface protective film formed on the semiconductor substrate, the deposition pattern is made of the same material as at least one of the interlayer film, the electrode, and the surface protection film; The semiconductor wafer according to any one of claims 1 to 4.

6. the width of the deposition pattern is smaller than the width of the dicing line on the pattern; The deposition pattern does not contact the chip adjacent to the dicing line on the pattern. The semiconductor wafer according to any one of claims 1 to 5.

7. the width of the deposition pattern is equal to the width of the dicing line on the pattern, the deposition pattern contacts a side surface of the chip adjacent to a dicing line on the pattern; The semiconductor wafer according to any one of claims 1 to 5.

8. the width of the deposition pattern is greater than the width of the dicing line on the pattern, the deposition pattern covers an end portion of the chip adjacent to a dicing line on the pattern; The semiconductor wafer according to any one of claims 1 to 5.

9. the width of the deposition pattern is greater than the width of the dicing line on the pattern, the deposition pattern covers the top surface of the chip, except for an opening provided in the chip for electrically connecting the electrode to the outside of the chip; The semiconductor wafer according to claim 5 .

10. The width of the film formation pattern is larger than the width of a dicing blade for dicing the semiconductor wafer. The semiconductor wafer according to any one of claims 1 to 9.

11. The deposition pattern covers the entire longitudinal direction of the dicing line on the pattern. The semiconductor wafer according to any one of claims 1 to 10.

12. The deposition patterns are arranged intermittently in a longitudinal direction of the dicing lines on the pattern. The semiconductor wafer according to any one of claims 1 to 7.

13. a longitudinal direction or an arrangement direction of the deposition pattern has an angle with respect to a longitudinal direction of the dicing line on the pattern within a range in which the deposition pattern does not deviate from the dicing line on the pattern; The semiconductor wafer according to any one of claims 1 to 12.

14. The deposition pattern has a function as an alignment mark, a target, or a reference marking. The semiconductor wafer according to any one of claims 1 to 13.

15. The deposition pattern has a function as a monitor pattern. The semiconductor wafer according to any one of claims 1 to 13.

16. The deposition pattern is a pattern on which a name, a logo mark, or a control number is drawn. The semiconductor wafer according to any one of claims 1 to 13.

17. The semiconductor material of the semiconductor wafer is Si, SiC, or GaN; The semiconductor wafer according to any one of claims 1 to 16.

18. A method for manufacturing a semiconductor wafer, the semiconductor wafer being diced along a plurality of dicing lines in a first direction and a second direction different from the first direction to cut out chips from an effective area, the method comprising the steps of: forming a film pattern on the semiconductor wafer; and at least one dicing line included in the plurality of dicing lines is a patterned dicing line whose entire length or a portion of its length overlaps with the film pattern, the method comprising the steps of: (a) imaging a first photomask onto a central portion of a semiconductor workpiece; (b) drawing a second photomask or a third photomask on a periphery surrounding the central portion of the semiconductor substrate; Equipped with the first, second and third photomasks each include a chip pattern region in which a pattern of the chip is formed, and a dicing line pattern region in which a pattern of the plurality of dicing lines is formed; the dicing line pattern region surrounds the chip pattern region and has a first portion extending in the first direction and a second portion extending in the second direction; a pattern for a deposition pattern for drawing the deposition pattern in the first portion and the second portion is formed in the dicing line pattern region of the second photomask; the deposition pattern is formed in either the first portion or the second portion in the dicing line pattern region of the third photomask; The greater the warp of the semiconductor substrate, the greater the width of the outer periphery. A method for manufacturing a semiconductor wafer.

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