Method for manufacturing silicon carbide semiconductor device

Abstract

To suppress the warpage of a SiC wafer by a method different from a method of forming a groove for warpage correction.SOLUTION: Before ion implantation is performed, a fracture layer 1a is formed on the rear surface side of an SiC wafer 1 to generate warpage in a downward convex direction. As a result, even when warpage in an upward convex direction is generated by ion implantation, forming the fracture layer 1a in advance allows the cancellation by the warp in the downward convex direction, and the warpage in the upward convex direction can be reduced. Therefore, in each step of the manufacturing process of the SiC semiconductor device, the SiC wafer 1 is prevented from being hindered in transportation due to the influence of the warpage, and the SiC wafer 1 can be transported accurately.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a silicon carbide (hereinafter referred to as SiC) semiconductor device. [Background technology]

[0002] In recent years, SiC has been considered as a material for power devices that can obtain high electric field breakdown strength. SiC wafers are thinner than Si wafers and are prone to warping. In particular, repeated ion implantation for semiconductor device formation expands the upward convex warp, in which the center of the wafer protrudes above the outer edge, i.e., toward the front side of the wafer. In addition, when trenches are formed, the trench formation generates a downward convex warp, in which the center of the wafer protrudes below the outer edge, i.e., toward the back side of the wafer. If the upward convex warp becomes too large before that, it may cause problems in transportation. For example, the orientation flat may not be recognized properly when searching for the wafer before transportation due to the influence of the warp, making it impossible to transport the wafer, or the wafer alignment may not be performed properly, making it impossible to transport the wafer. In addition, when the wafer is mounted on a vacuum suction chuck or vacuum suction stage, the warp may make it impossible to vacuum suction.

[0003] Therefore, Patent Document 1 proposes a method for correcting the warpage of a semiconductor substrate, which corrects the warpage of a SiC wafer. + A semiconductor substrate made of single crystal SiC is - The warping of the semiconductor substrate is corrected by forming multiple grooves in a lattice pattern on a SiC substrate having a laminated type epitaxial layer and a p-type epitaxial layer, and then performing heat treatment. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 10-125905 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the warpage correction method of Patent Document 1 can reduce the warpage after the formation of the multiple grooves, but cannot reduce the warpage before that, and cannot deal with cases where the warpage causes problems with transportation in the previous processes. In addition, it is necessary to determine the semiconductor element layout and chip layout taking into account the layout of the multiple grooves.

[0006] In view of the above, an object of the present invention is to provide a method for manufacturing a SiC semiconductor device that suppresses warpage of a SiC wafer using a method different from the method of forming grooves for correcting warpage. [Means for solving the problem]

[0007] In order to achieve the above object, claim 1 、4、7 The invention described in is a method for manufacturing a SiC semiconductor device, which includes preparing a SiC wafer (1) having a front and back surface, and forming semiconductor elements on the front surface side of the SiC wafer by carrying out a semiconductor element formation process including at least one ion implantation, and by forming a fractured layer (1a) on the back surface side of the semiconductor wafer prior to the ion implantation, a downward convex warp is generated in which the central side of the SiC wafer protrudes more toward the back surface side than the outer edge side.

[0008] In this way, a downward convex warp is generated by forming a fracture layer on the back side of the SiC wafer before ion implantation. Therefore, even if an upward convex warp is generated by ion implantation, the downward convex warp generated by forming the fracture layer in advance can cancel it, and the upward convex warp can be reduced. Therefore, in each process of the manufacturing process of the SiC semiconductor device, the influence of the warp on the transportation of the SiC wafer is suppressed, and the SiC wafer can be transported accurately.

[0009] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0010] [Figure 1] 1A to 1C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0012] (First embodiment) A first embodiment will be described. Here, a method for manufacturing a SiC semiconductor device in which a MOSFET with a trench gate structure is formed as a semiconductor element will be described as an example, but a SiC semiconductor device in which other semiconductor elements are formed may also be used. In addition, since the MOSFET formation process itself in the manufacturing process of a SiC semiconductor device may be the same as a publicly known method, the process related to suppression of warpage will mainly be described here.

[0013] First, as shown in FIG. 1(a), a SiC wafer 1 is prepared. For example, in the case of an n-type channel MOSFET, a SiC wafer 1 composed of a high concentration of n-type is prepared. The thickness of the SiC wafer 1 is arbitrary, but is set to, for example, about 350 μm. Then, a SiC wafer 1 composed of a low concentration of n-type is prepared. - After the step of forming the epitaxial layer constituted by the mold and the like are performed, or before the step of forming the epitaxial layer, the steps shown in FIGS. 1(b) to (g) are performed.

[0014] That is, as shown in Fig. 1(b), a protective tape 2 is attached to the front surface side of the SiC wafer 1. Any protective tape 2 may be used as long as it can protect the front surface of the SiC wafer 1 and can be easily peeled off in a later process. For example, a backgrinding tape used in backgrinding performed in the final stage after element formation of a SiC semiconductor device can be used as the protective tape 2.

[0015] In this state, as shown in FIG. 1(c), the front and back sides of the SiC wafer 1 are inverted, the protective tape 2 side faces downward, and the back side of the SiC wafer 1 to which the protective tape 2 is not attached faces upward. Then, the back side of the SiC wafer 1 is ground using a grinder (not shown) or the like, to form a fractured layer 1a on the back side of the SiC wafer 1, as shown in FIG. 1(d). By forming such a fractured layer 1a, it is possible to generate a downwardly convex warp such that the center side of the SiC wafer 1 protrudes downward from the outer edge side. The fractured layer 1a is formed by grinding the back side to roughen it, which causes transitions in the SiC single crystal or amorphization.

[0016] The amount of grinding of the SiC wafer 1 and the surface roughness of the crushed layer 1a at this time are arbitrary, but are set to be suitable for suppressing warpage of the SiC wafer 1. For example, a grindstone of No. 2000 is used for the grinder, and the crushed layer 1a is formed by grinding about 50 μm. Of course, the grit of the grindstone is arbitrary, and other grits may be used, or a combination of grits of multiple grits may be used, for example, grinding with a No. 2000 grindstone followed by grinding with a No. 10000 grindstone. The surface roughness of the crushed layer 1a can be appropriately adjusted according to the grit of the grindstone used. Then, the amount of warpage in the downward convex direction can be set according to the amount of grinding of the SiC wafer 1 when forming the crushed layer 1a and the surface roughness of the crushed layer 1a. The amount of warpage is expressed, for example, as the difference in height between the center position and the outer peripheral end of the SiC wafer 1 relative to the diameter of the SiC wafer 1, based on a flat surface.

[0017] Next, as shown in Fig. 1(e), the front and back sides of the SiC wafer 1 are again inverted so that the protective tape 2 faces up, and then, as shown in Fig. 1(f), the protective tape 2 is peeled off from the SiC wafer 1. Then, as shown in Fig. 1(g), the front surface of the SiC wafer 1 is cleaned.

[0018] After this, if the epitaxial layer formation process has not yet been performed, it is performed, and then various processes for constructing a MOSFET are performed. For example, a process for forming a p-type base region for forming a channel region, a process for forming a high-concentration n-type MOSFET on the base region, and so on are performed. + Type source region and high concentration p + A step of forming a contact region of the mold is performed by ion implantation or the like. In addition, a step of forming a trench that penetrates the source region and the base region and reaches the epitaxial layer, a step of forming a gate insulating film on the inner wall surface of the trench, and a step of forming a gate electrode on the gate insulating film in the trench are performed to form a trench gate structure. In addition, a step of forming an interlayer insulating film that covers the gate electrode, a step of forming a contact hole in the interlayer insulating film, a step of forming a source electrode connected to the source region and the contact region through the contact hole, a protective film forming step, and the like are performed. This completes various steps on the front side of the SiC wafer 1. Then, the back side of the SiC wafer 1 is further ground and polished by CMP (Chemical Mechanical Polishing) or the like to thin the SiC wafer 1 to a predetermined thickness, for example, 200 μm, and then a drain electrode is formed. In this way, the MOSFET is formed, and then the SiC wafer 1 on which the MOSFET is formed is diced to be divided into chip units, and the SiC semiconductor device is completed.

[0019] The manufacturing process of the SiC semiconductor device as described above includes a process of forming impurity layers, for example, in a source region, a contact region, etc., by ion implantation. By performing this ion implantation, particularly by performing it repeatedly, an upward convex warp occurs in the SiC wafer 1 such that the center side protrudes above the outer edge side.

[0020] However, in this embodiment, before ion implantation, a fractured layer 1a is formed on the back side of the SiC wafer 1 to generate a downward convex warp. Therefore, even if an upward convex warp is generated by ion implantation, the fractured layer 1a is formed in advance to cancel the downward convex warp, and the upward convex warp can be reduced. Therefore, in each step of the manufacturing process of the SiC semiconductor device, the influence of the warp on the transportation of the SiC wafer 1 is suppressed, and the SiC wafer 1 can be transported accurately. For example, it is assumed that an upward convex warp of about 50 μm occurs due to ion implantation, but it has been confirmed that even if an upward convex warp of about 200 μm occurs, the warp can be reduced accurately.

[0021] It is not necessary that the amount of downward warpage of the SiC wafer 1 due to the formation of the fractured layer 1a and the amount of upward warpage of the SiC wafer 1 due to ion implantation are the same. If downward warpage can be generated in the SiC wafer 1 due to the formation of at least the fractured layer 1a, the upward warpage of the SiC wafer 1 due to ion implantation can be reduced.

[0022] In addition, in this embodiment, a SiC semiconductor device is provided with a MOSFET having a trench gate structure, and a trench is formed, which causes downward warping, and if a heat treatment is performed after the trench formation, the downward warping becomes even larger. For example, a heat treatment after the trench formation may be a heat treatment for activating the implanted ions, and if a heat treatment is performed at a temperature exceeding 1000° C., the downward warping becomes even larger.

[0023] Therefore, by forming the trench, it becomes possible to further cancel the upward convex warpage caused by ion implantation.

[0024] Here, the relationship between the upward convex warp and the downward convex warp will be described. As described above, the upward convex warp can be generated by performing ion implantation. On the other hand, the downward convex warp can be generated by forming the fracture layer 1a. After the trench is formed, the downward convex warp can be generated based on the trench formation and heat treatment.

[0025] Whether or not it interferes with transportation depends on the equipment used to manufacture the SiC semiconductor device. For example, (1) upward convex warping interferes with transportation, but downward convex warping does not interfere with transportation, (2) downward convex warping also interferes with transportation, but the amount of downward warping is acceptable even if it is greater than the amount of upward warping. Also, (3) downward convex warping interferes with transportation to the same extent as upward convex warping, but does not interfere with transportation much if the amount of downward warping is smaller than the amount of upward warping caused by ion implantation.

[0026] In any of the cases (1) to (3), if the crushed layer 1a is formed to cause a downward convex warp, it is possible to cancel at least a part of the upward convex warp caused by ion implantation.

[0027] For example, in the case of (1), since the downward warp does not interfere with transportation, if the amount of downward warp due to the formation of the crushed layer 1a is equal to or greater than the amount of warp due to ion implantation, the upward warp can be completely cancelled. Also, in this case, even if the amount of downward warp is less than the amount of warp due to ion implantation, a part of the upward warp can be cancelled.

[0028] In addition, in (2) and (3), if the downward warpage may cause problems during transportation, the grinding amount of the SiC wafer 1 when forming the crushed layer 1a and the surface roughness of the crushed layer 1a are adjusted so that the warpage is not so large as to cause problems. In this case, even if the amount of downward warpage caused by the formation of the crushed layer 1a is smaller than the amount of upward warpage caused by ion implantation, the downward warpage can cancel a part of the upward warpage.

[0029] In this way, in any of the cases (1) to (3), if the crushed layer 1a is formed to generate a downward convex warp, at least a part of the upward convex warp caused by ion implantation can be canceled. Therefore, the warp of the SiC wafer 1 can be suppressed by a method different from the method of forming grooves for warp correction, and more accurate transportation can be performed.

[0030] In addition, when a trench is formed, a downward convex warp is generated based on the trench formation and heat treatment. In the case of (1), the influence of the downward convex warp does not need to be considered, but in the cases of (2) and (3), the downward convex warp based on the formation of the crushed layer 1a can be adjusted by taking into account the downward convex warp based on the trench formation and heat treatment.

[0031] For example, in the cases of (2) and (3), the downward convex warp amount based on the formation of the fractured layer 1a is set to a level that reduces the upward convex warp caused by ion implantation and does not interfere with transportation. In addition, the downward convex warp amount based on the formation of the fractured layer 1a is set so that when the downward convex warp amount based on the trench formation and heat treatment is added, the downward convex warp amount becomes too large and does not interfere with transportation. However, in this case, the downward convex warp is canceled by the upward convex warp caused by ion implantation. Therefore, it is sufficient to subtract the canceled amount and set the downward convex warp amount when the amount based on the formation of the fractured layer 1a and the amount based on the trench formation and heat treatment are added to a level that does not interfere with transportation.

[0032] In addition, in consideration of the occurrence of downward warpage due to trench formation and heat treatment, the crushed layer 1a can be adjusted, for example, before heat treatment after ion implantation or trench formation. In other words, the grinding amount when forming the crushed layer 1a or the surface roughness of the crushed layer 1a can be adjusted to reduce the amount of downward warpage due to the formation of the crushed layer 1a compared to before adjustment.

[0033] Furthermore, since the formation of the trench causes a downward convex warp, a process of removing the fractured layer 1a may be performed after the formation of the trench. The removal method may be any method, such as grinding or wet etching. As described above, the back side of the SiC wafer 1 is ground and polished before the formation of the drain electrode. However, if a heat treatment is performed at a high temperature after the formation of the trench, the downward convex warp becomes larger, so it is preferable to remove the fractured layer 1a before the heat treatment. In this case, even if the fractured layer 1a is removed, the warp is canceled by the upward convex warp caused by the ion implantation and the downward convex warp caused by the formation of the trench and the heat treatment.

[0034] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0035] For example, in the above embodiment, the fracture layer 1a is formed by grinding, but the fracture layer 1a may be formed by a method other than grinding. As an example, instead of grinding, the fracture layer 1a may be formed by performing a blasting process on the back surface of the SiC wafer 1.

[0036] In the above embodiment, the formation of the fractured layer 1a before the ion implantation has been described, but the formation of the fractured layer 1a may be divided into multiple stages. For example, after the fractured layer 1a is formed, one or more ion implantations are performed, and then the grinding amount when forming the fractured layer 1a and the surface roughness of the fractured layer 1a are adjusted. Then, when adjusting the grinding amount when forming the fractured layer 1a and the surface roughness of the fractured layer 1a, the adjustment is performed taking into consideration the amount of warping in the upward convex direction based on the ion implantation performed thereafter. In this way, the downward convex warping and the upward convex warping are repeatedly generated little by little, so that even if the downward convex warping or the upward convex warping occurs in each process, the amount of warping can be made small.

[0037] In the above embodiment, a MOSFET with a trench gate structure has been described as an example of a SiC semiconductor device in which a trench is formed. However, even if a trench is not formed, an upward convex warp occurs due to ion implantation or heat treatment, so the present invention can be applied to a SiC semiconductor device in which a trench is not formed. In addition, a trench other than a trench gate structure, for example, a trench that recesses the outer peripheral region may be formed to form a mesa structure in which a cell region in which an element is formed protrudes from the outer peripheral breakdown voltage region. The trench that constitutes such a mesa structure also causes a downward convex warp, so it is preferable to adjust the downward convex warp based on the formation of the crushed layer 1a by taking this into consideration.

[0038] That is, in a method for manufacturing a SiC semiconductor device in which a SiC wafer 1 is prepared and a process for forming a semiconductor element including ion implantation is performed on the SiC wafer 1, the effects shown in the above embodiment can be obtained by forming the fractured layer 1a before the ion implantation. When the ion implantation is performed multiple times, the fractured layer 1a may be formed multiple times alternately with the ion implantation. It is sufficient to perform at least one ion implantation after the formation of the fractured layer 1a, and the order may be such that the ion implantation is performed first, the fractured layer 1a is formed, and then the ion implantation is performed again. [Explanation of symbols]

[0039] 1. SiC wafer 1a Crushed layer 2 Protective tape

Claims

1. A method for manufacturing a silicon carbide semiconductor device, comprising: Providing a silicon carbide wafer (1) having a front surface and a back surface; and performing a semiconductor element formation process including at least one ion implantation on the front surface side of the silicon carbide wafer to form the semiconductor element; Prior to the ion implantation, a fractured layer (1a) is formed on the back surface side of the silicon carbide wafer, thereby generating a downward convex warp in which the central side of the silicon carbide wafer protrudes further toward the back surface side than the outer edge side; In the process of forming the semiconductor element, the ion implantation is performed a plurality of times, and the downwardly convex warpage is generated before at least one of the plurality of ion implantations; A method for manufacturing a silicon carbide semiconductor device, comprising alternately repeating the generation of the downward convex warp and the execution of one or a plurality of the ion implantations.

2. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the downwardly convex warpage is generated by grinding a back surface side of the silicon carbide wafer to form the fractured layer.

3. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the generation of the downward convex warpage is achieved by performing a blasting treatment on a back surface side of the silicon carbide wafer to form the fractured layer.

4. A method for manufacturing a silicon carbide semiconductor device, comprising the steps of: Providing a silicon carbide wafer (1) having a front surface and a back surface; and performing a semiconductor element formation process including at least one ion implantation on the front surface side of the silicon carbide wafer to form the semiconductor element; Prior to the ion implantation, a fractured layer (1a) is formed on the back surface side of the silicon carbide wafer, thereby generating a downward convex warp in which the central side of the silicon carbide wafer protrudes further toward the back surface side than the outer edge side; the generating of the warpage in the downward convex direction comprises forming the fractured layer by grinding a back surface side of the silicon carbide wafer.

5. A method for manufacturing a silicon carbide semiconductor device as described in claim 4, wherein, in the formation process of forming the semiconductor element, the ion implantation is performed multiple times and the downward convex warping is generated before at least one of the multiple ion implantations.

6. forming the semiconductor element includes forming a trench on a front surface side of the silicon carbide wafer; The method for manufacturing a silicon carbide semiconductor device according to claim 1 , further comprising the step of removing the fracture layer after forming the trench.

7. A method for manufacturing a silicon carbide semiconductor device, comprising: Providing a silicon carbide wafer (1) having a front surface and a back surface; and performing a semiconductor element formation process including at least one ion implantation on the front surface side of the silicon carbide wafer to form the semiconductor element; Prior to the ion implantation, a fractured layer (1a) is formed on the back surface side of the silicon carbide wafer, thereby generating a downward convex warp in which the central side of the silicon carbide wafer protrudes further toward the back surface side than the outer edge side; forming the semiconductor element includes forming a trench on a front surface side of the silicon carbide wafer; The method for manufacturing a silicon carbide semiconductor device further comprises removing the fracture layer after forming the trench.

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