Semiconductor device manufacturing method

Abstract

To perform ion implantation using a resist by solving trade-off for which heat resistance of the resist is required, while suppressing generation of a crystal defect.SOLUTION: Ion implantation is performed after forming a hard layer 2a by performing UV irradiation on a resist 2. Thus, even at a high temperature in the case of the ion implantation, the hard layer 2a is capable of suppressing blowout of degassing. More specifically, the hard layer 2a is formed by performing the UV irradiation at a higher temperature than a temperature during the ion implantation, such that a shape of the hard layer 2a can be maintained without deforming it even at a high temperature in the case of the ion implantation. Therefore, even at a high temperature in the case of the ion implantation, degassing can be confined in the resist 2 by the hard layer 2a, and blowout of degassing to the outside of the resist 2 can be suppressed. Thus, even if the general resist 2 is used as a mask, the high-temperature ion implantation capable of suppressing a crystal defect can be performed.SELECTED DRAWING: Figure 1C

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device that uses silicon carbide (hereinafter referred to as SiC) or the like as a semiconductor material. [Background technology]

[0002] In the manufacturing process of SiC semiconductor devices, such as power semiconductors, it is necessary to perform ion implantation with a high impurity concentration to establish contact between the SiC substrate and the electrodes, but ion implantation is performed at high temperatures to prevent crystal defects from occurring due to ion implantation. For example, when forming a contact p-type layer for electrically connecting the p-type base region and source electrode in a MOSFET, ion implantation with a high impurity concentration is performed at high temperatures.

[0003] When performing ion implantation at high temperature, high impurity concentration, and high energy, an oxide film, for example, a SiO2 film, is generally used as a mask, but the mask process using an oxide film increases the number of steps, making it a high-cost process. For this reason, in order to suppress the increase in costs associated with the increase in the number of steps, it has been considered to use a resist mask instead. However, in order to create a resist mask for ion implantation at a high impurity concentration, it is necessary to solve the trade-off between the need to perform ion implantation at high temperature to suppress the occurrence of crystal defects, and the need for heat resistance of the resist.

[0004] In response to this, Patent Document 1 shows that a resist with a heat-resistant temperature of 1000°C can be used as a mask for high-temperature aluminum (Al) ion implantation by baking the resist in a nitrogen atmosphere at a temperature equivalent to that of ion implantation after resist formation. By using this technology, a resist with a heat-resistant temperature of 1000°C can be used to create a resist mask even for high-temperature ion implantation. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2017-97378 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, when using a resist that is not generally used in semiconductor manufacturing processes, such as a resist with a heat resistance of 1000°C, the number of types of resist is increased, which is not preferable because it can cause problems such as waste liquid from the developer used during development and complicate process management. For this reason, when a resist that is generally used in semiconductor manufacturing processes, such as a resist with a heat resistance of 300°C, was used and heated in a nitrogen atmosphere as in Patent Document 1, it was found that the resist shape was distorted and could not be used as a mask.

[0007] In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device that resolves the trade-off between suppressing the occurrence of crystal defects and the need for heat resistance of the resist, thereby enabling ion implantation using a resist. [Means for solving the problem]

[0008] In order to achieve the above object, the invention described in claim 1 is a manufacturing method for a semiconductor device in which an impurity layer (3) is formed in a semiconductor substrate (1) by ion implantation, the method comprising the steps of preparing a semiconductor substrate, forming a resist (2) having a desired pattern on the semiconductor substrate, irradiating the resist with ultraviolet light (hereinafter referred to as UV) at a temperature equal to or higher than the ion implantation temperature, and, after the UV irradiation, performing ion implantation using the resist as a mask to form the impurity layer in the semiconductor substrate. Specifically, the impurity layer is formed by using Al as the ion species in the ion implantation, setting the temperature of the semiconductor substrate during the ion implantation to 200° C. or higher, and setting the dose to 1.0×10 14 cm -2 That is all.

[0009] In this way, a hardened layer can be formed on the resist by irradiating the resist with UV light. Then, ions are implanted after the hardened layer is formed. Therefore, even if the temperature is high during ion implantation, the hardened layer can suppress the blowing out of degassing. More specifically, since the hardened layer is formed by irradiating the resist with UV light at a temperature higher than the temperature during ion implantation, the hardened layer can maintain its shape without collapsing even if the temperature is high during ion implantation. Therefore, even if the temperature is high during ion implantation, the hardened layer can confine degassing within the resist, and the blowing out of the degassing to the outside of the resist can be suppressed.

[0010] This makes it possible to perform ion implantation at high temperatures that can suppress crystal defects even when a general resist is used as a mask. This solves the trade-off between suppressing the occurrence of crystal defects and the need for heat resistance of the resist, and makes it possible to perform ion implantation using a general resist.

[0011] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0012] [Figure 1A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 1B] 1B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 1A. [Figure 1C] 1C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 1B. [Figure 1D] 1D is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 1C. [Figure 1E] 1D; FIG. [Diagram 2] FIG. 1D is a cross-sectional view showing a state after ion implantation in FIG. 1C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0014] (First embodiment) A first embodiment will be described. In this embodiment, a method for manufacturing a SiC semiconductor device including a step of forming an impurity layer by ion implantation into a SiC substrate constituting a semiconductor element will be described. The semiconductor element formed in the SiC semiconductor device may be any type, such as a vertical MOSFET or an IGBT, and the structure of the semiconductor element will be omitted here. The impurity layer formed in the SiC substrate may be not only an impurity layer for constituting the semiconductor element itself, such as a vertical MOSFET or an IGBT, but also any impurity layer formed by ion implantation. In particular, it is preferable to apply the method to an impurity layer formed by high-temperature, high-impurity-concentration, high-energy ion implantation.

[0015] [Step shown in FIG. 1A] First, a SiC substrate 1 for forming a semiconductor element is prepared. The SiC substrate 1 here means a sample that has been subjected to the process before the formation of an impurity layer by ion implantation. For example, in the case of a vertical MOSFET, a n-type SiC substrate is prepared. + On the main surface of the n-type substrate - After epitaxial growth of the n-type drift layer, - On top of the p-type drift layer, a p-type base region and an n-type + Then, the n-type source region is formed in the p-type base region. + A contact p-type layer is formed in a surface layer at a position different from the position where the n-type source region is disposed, to locally increase the p-type impurity concentration. When the impurity layer formed by ion implantation is a contact p-type layer, the p-type base region and the n-type source region are formed in the contact p-type layer. +The SiC substrate 1 shown in FIG. 1A is the one that has been subjected to the process of forming the n-type source region. Of course, it is also possible to form impurity layers in other parts by ion implantation. For example, if the impurity layer formed by ion implantation is + In the case of a p-type source region, the process up to the formation of a p-type base region is carried out to obtain the SiC substrate 1 shown in FIG. 1A.

[0016] Then, after forming a film of resist 2 on the SiC substrate 1, a photolithography process is performed to pattern the resist 2 into a desired pattern so that the area other than the area where the contact p-type layer is to be formed is covered with the resist 2. As the resist 2, a commonly used photoresist having a heat resistance of about 300°C and not as high as 1000°C, such as PFI89 manufactured by Sumitomo Chemical Co., Ltd., is used. The thickness of the resist 2 may be arbitrarily determined depending on the dose amount and acceleration energy of the ion implantation, but here it is adjusted to a range of 1.7 μm ±10%.

[0017] [Step shown in FIG. 1B] A UV curing process is performed in which the resist 2 is irradiated with UV light. Specifically, the sample on which the resist 2 is patterned is mounted on a stage in a chamber of a UV curing device (not shown), and the stage is heated to raise the temperature of the sample, and UV curing is performed in that state. The temperature of the sample at this time is set to a temperature higher than the temperature of the ion implantation performed later, and is set to 200°C or higher, for example, 200 to 250°C. The UV curing time is arbitrary, but is performed for several tens to several hundreds of seconds. This UV curing forms a hardened layer 2a in the surface layer of the resist 2, which is the part irradiated with UV light.

[0018] The hardened layer 2a formed at this time is formed with a thickness according to the UV curing time. For example, if the UV curing time is 100 seconds, the thickness of the hardened layer 2a is 100 nm, and if it is 200 seconds, it is 250 nm. The longer the UV curing time, the thicker the hardened layer 2a becomes. The hardened layer 2a also plays a role of protecting the SiC substrate 1 from ions being implanted during the subsequent ion implantation, but also plays a role of trapping degas generated inside the hardened layer 2a due to the high temperature during ion implantation and preventing it from being blown out to the outside. Taking these roles into consideration, the thickness of the hardened layer 2a is set based on the dose amount, acceleration energy, and temperature during ion implantation. Here, for example, the UV curing time is set to 100 seconds, and the thickness of the hardened layer 2a is set to about 100 nm. Note that, although an example of the UV curing time is given here, it is sufficient that the hardened layer 2a is formed with a thickness that fulfills the above role, so the UV curing time can be adjusted appropriately.

[0019] [Step shown in FIG. 1C] By performing ion implantation using the resist 2 with the hardened layer 2a formed thereon as a mask, an impurity layer 3 such as a contact p-type layer is formed in the portion of the SiC substrate 1 that is not covered with the resist 2. For example, a sample of the SiC substrate 1 with the resist 2 formed thereon is mounted on a stage in a chamber of an ion implantation device (not shown), and the temperature of the SiC substrate 1 is raised to 200°C or higher by heating the stage. In this state, ion implantation is performed using a p-type impurity, for example, Al (aluminum), as the ion species. For example, when forming the impurity layer 3 with a high impurity concentration such as a contact p-type layer, a concentration of 1.0×10 14 cm -2 Ion implantation is performed with a dose of 1.0×10 or more. However, since there is an error in the dose, the target value is set to 1.0×10 14 cm -2 Ion implantation is performed within ±15% of the above. The acceleration energy is set to 200 keV.

[0020] At this time, degassing may occur within the resist 2 due to the high temperature during ion implantation, but even if this gas tries to blow out of the resist 2, the hardened layer 2a is formed and guards against this, preventing it from blowing out. If degassing blows out of the resist 2, abnormal discharge may occur during ion implantation, so by preventing the blowing out of degassing, the occurrence of abnormal discharge can be prevented, enabling stable ion implantation.

[0021] When ions are implanted in this manner, the hardened layer 2a becomes harder, and as shown in FIG. 2, Al remains in the resist 2, particularly in the hardened layer 2a.

[0022] [Step shown in FIG. 1D] The SiC substrate 1 with the impurity layer 3 formed thereon is placed in the ashing device 10, and the resist 2 is removed by high-temperature ashing. In this figure, the SiC substrate 1 is shown in a wafer state, so the impurity layer 3 is not shown, but in reality, the impurity layer 3 is formed at the desired position. Specifically, the resist 2 remaining on the SiC substrate 1 is removed by O2 plasma ashing. At this time, it was confirmed that the Al remaining in the resist 2 including the hardened layer 2a is changed to a non-volatile oxide (Al2O3) during O2 plasma ashing. Since this oxide is non-volatile, it is difficult to remove it by O2 plasma ashing, and if O2 plasma ashing is only performed, it will remain as a residue on the surface of the SiC substrate 1. For this reason, the next step shown in FIG. 1E is performed.

[0023] [Step shown in FIG. 1E] An oxide removal process is performed using HF (hydrogen fluoride) cleaning. As described above, non-volatile oxides remain as residues on the surface of the SiC substrate 1 if O2 plasma ashing is only performed. For this reason, HF cleaning is performed to change the non-volatile oxides into AlOF, which has high solubility, and dissolve them. This makes it possible to remove the residues on the surface of the SiC substrate 1.

[0024] In this manner, the impurity layer 3 can be formed by ion implantation in the surface layer portion of the SiC substrate 1. Although not shown, thereafter, a manufacturing process for a SiC semiconductor device can be performed to manufacture a SiC semiconductor device including a semiconductor element such as a vertical MOSFET or an IGBT.

[0025] As described above, in this embodiment, a commonly used resist 2 with a heat-resistant temperature of about 300° C. is used as a mask for ion implantation, and the resist 2 is irradiated with UV light to form a hardened layer 2a before ion implantation. Therefore, even if the temperature is high during ion implantation, the hardened layer 2a can suppress the blowing out of degassing. More specifically, since the hardened layer 2a is formed by irradiating UV light at a temperature higher than the temperature during ion implantation, the hardened layer 2a can maintain its shape without collapsing even if the temperature is high during ion implantation. Therefore, even if the temperature is high during ion implantation, the hardened layer 2a can confine degassing within the resist 2, and the blowing out of the resist 2 can be suppressed.

[0026] This makes it possible to perform ion implantation at high temperatures that can suppress crystal defects even when a general resist 2 is used as a mask. This solves the trade-off between suppressing the occurrence of crystal defects and the need for heat resistance of the resist 2, and makes it possible to perform ion implantation using a general resist 2. In particular, when the impurity layer 3 has a high impurity concentration, ion implantation is performed at a high dose. In such cases, the resist 2 is prone to collapse, but by using the manufacturing method of this embodiment, stable ion implantation can be performed without the resist 2 collapsing.

[0027] Furthermore, the manufacturing method of this embodiment can provide the following effects.

[0028] (1) When Al is used as the ion species, Al remains in the resist 2 including the hardened layer 2a during ion implantation, so that non-volatile oxides remain as residues on the surface of the SiC substrate 1 if O2 plasma ashing is only performed. In order to remove this residue, an HF cleaning process is performed after O2 plasma ashing. This makes it possible to eliminate the residues on the surface of the SiC substrate 1.

[0029] (2) In this embodiment, the substrate temperature during ion implantation is set to 200° C. or higher, and the dose is set to 1.0×10 14 cm -2 When performing ion implantation at high temperature, high impurity concentration, and high energy to achieve a tolerance of ±15% or more, a general resist 2 is used as a mask. When performing ion implantation at high temperature, high impurity concentration, and high energy, an oxide film is generally used as a mask, but if ion implantation can be performed using general resist 2 in such cases, a high effect can be obtained, particularly in terms of suppressing the increase in costs associated with an increase in the number of processes.

[0030] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0031] (1) For example, in the above embodiment, a vertical MOSFET or an IGBT is given as an example of a semiconductor element, and the case of forming the impurity layer 3 of one of these components is described. However, this is merely an example, and the present invention can be applied to ion implantation when forming an impurity layer that will be a component of other semiconductor elements, or an impurity layer other than a semiconductor element, such as an impurity layer formed in a peripheral voltage-withstanding region.

[0032] (2) In the above embodiment, a manufacturing method is described for the effective area of ​​a wafer that is extracted as a chip when manufacturing a SiC semiconductor device. However, it is preferable to use a manufacturing method that takes into account unnecessary areas located on the outer edge of the wafer that are not extracted as chips.

[0033] Specifically, when the resist 2 is formed, the resist 2 is formed thicker in the unnecessary area of ​​the outer edge of the wafer than in the effective area inside the unnecessary area due to the influence of surface tension. Therefore, if the resist 2 in the unnecessary area is left as it is, even if the hardened layer 2a is formed by UV irradiation, the hardened layer 2a may collapse during ion implantation due to the thick thickness of the resist 2, and degassing may occur. Therefore, when the resist 2 is patterned, at least the entire area of ​​the unnecessary area of ​​the outer edge of the wafer where the film thickness of the resist 2 is thicker than that of the effective area is removed. In this way, it is possible to suppress degassing from the outer edge of the wafer during ion implantation, which causes abnormal discharge.

[0034] (3) In the above embodiment, Al is used as an example of the ion species used for ion implantation. However, the present invention can also be applied to cases where other impurity ion species, such as N (nitrogen), P (phosphorus), or B (boron), are used.

[0035] (4) In the above embodiment, PFI89 is used as an example of a general resist 2 that is not highly heat resistant, but of course, other materials may be used. In other words, other materials may be used as long as they are general resists that are used in other processes, not resists that are highly heat resistant and not used in other processes. In addition, a resist with a heat resistance of about 300° C. is used as an example, but this is not limited to this.

[0036] (5) In the above embodiment, the case where SiC is used as the semiconductor material is taken as an example, and the impurity layer 3 is formed in the SiC substrate 1. However, the present invention can be applied even if the semiconductor material is something other than SiC, so long as the impurity layer is formed by ion implantation into the semiconductor substrate using a general resist 2 that is not alternating heat. [Explanation of symbols]

[0037] 1. SiC substrate 2. Resist 2a hardened layer 3 Impurity layer

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: forming an impurity layer (3) in a semiconductor substrate (1) by ion implantation, providing the semiconductor substrate; forming a resist (2) having a desired pattern on the semiconductor substrate; irradiating the resist with ultraviolet light at a temperature equal to or higher than the temperature of the ion implantation; and performing the ion implantation using the resist as a mask after the irradiation of the ultraviolet light to form the impurity layer in the semiconductor substrate. In forming the impurity layer, Al is used as an ion species in the ion implantation, the temperature of the semiconductor substrate during the ion implantation is 200° C. or higher, and a dose amount is 1.0×10 14 cm −2 or higher.

2. After forming the impurity layer, removing the resist by O 2 plasma ashing; 2. The method for manufacturing a semiconductor device according to claim 1, further comprising removing said aluminum oxide film formed during said O2 plasma ashing with hydrogen fluoride.

3. preparing the semiconductor substrate includes preparing a wafer of the semiconductor substrate; 3. The method for manufacturing a semiconductor device according to claim 1, wherein forming the resist includes forming the resist in the desired pattern by removing a portion formed on an outer edge of the wafer.

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