Clock and data recovery circuit and receiver

Abstract

To regenerate a clock signal based on a received data signal according to a channel characteristic.SOLUTION: A regeneration circuit 23 includes a phase detector 201 for outputting phase characteristic data D3 from a digital data signal D2, and an adjustment circuit 202 for adjusting the phase characteristic data D3. An adjustment value is set to the adjustment circuit 202 by a monitor circuit 203 which calculates the adjustment value of the phase characteristic data D3 while varying the phase of a reference clock signal BCL to be adjusted by a phase interpolation circuit 208 based on offset data D6 outputted from an offset output circuit 205, in a training period before starting communication.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a circuit for regenerating a clock signal for sampling received data and a receiver including the circuit. [Background technology]

[0002] In a communication system, it is necessary to synchronize the frequency and phase of a clock signal between a transmitter and a receiver. A clock and data recovery circuit (CDR circuit) in the receiver recovers a clock signal based on a random data signal sent from the transmitter. An analog-to-digital converter in the receiver samples the data signal based on the clock signal recovered by the CDR circuit.

[0003] The clock recovery circuit in the following Patent Document 1 uses a clock signal and a clock signal obtained by inverting the clock signal by 180 degrees to determine the phase difference between input data and a recovered clock. In addition, a method has been proposed in which a clock signal that has been oversampled twice is used to determine the phase difference between a clock signal on the transmitter side and a clock signal on the receiver side. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-120214 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, using a clock signal that is oversampled twice or a clock signal whose phase is inverted by 180 degrees to construct an analog circuit that determines the phase difference between a clock signal on the transmitter side and a clock signal on the receiver side increases the manufacturing cost of the circuit. Therefore, a phase detector that digitally processes the process of determining the phase difference between input data and a recovered clock may be used. For example, a Mueller-Muller phase detector is known as a phase detector.

[0006] A phase detector is a circuit that detects phase shifts in a received data sequence, and the detection result depends on the quality of the received data. In other words, the detection result of the phase detector is affected by the characteristics of the channel. For this reason, depending on the characteristics of the channel, the receiver may not be able to achieve frequency lock.

[0007] An object of the present invention is to recover a clock signal based on a received data signal depending on the characteristics of the channel. [Means for solving the problem]

[0008] A clock data recovery circuit according to one aspect of the present invention includes a phase interpolation circuit that adjusts the phase of a reference clock signal generated by a reference clock generation circuit and generates a reception clock signal, a phase detector that operates in synchronization with the reception clock signal generated by the phase interpolation circuit, inputs a reception digital data signal output from an analog-to-digital converter that converts a reception analog data signal into a reception digital data signal, and outputs phase characteristic data from the reception digital data signal, and Ta The adjustment circuit to be adjusted and the phase characteristic data output from the adjustment circuit are monitored, and the adjustment circuit is set based on the phase characteristic data. Ru tone Adjustment Valuea loop filter that outputs adjustment data for generating phase data to be set in the phase interpolation circuit based on the phase characteristic data output from the adjustment circuit, and an offset output circuit that outputs offset data for generating the phase data to be set in the phase interpolation circuit, and during a training period before starting communication, the phase of the reference clock signal adjusted in the phase interpolation circuit is changed based on the offset data output from the offset output circuit, while Techo Adjustment Value By calculating the Ru tone Adjustment Value Lock.

[0009] A receiver according to another aspect of the present invention includes the above clock data recovery circuit, a reference clock generation circuit, and an analog-to-digital converter. Effect of the Invention

[0010] According to the present invention, a clock signal can be recovered based on the received data signal depending on the characteristics of the channel. [Brief description of the drawings]

[0011] [Figure 1] 1 is an overall view of a communication system. [Diagram 2] 1 is a block diagram of a receiver showing an internal configuration of a clock data recovery circuit according to an embodiment of the present invention; [Diagram 3] FIG. 2 is a circuit diagram of an adjustment circuit according to the present embodiment. [Figure 4] 1 is a circuit diagram of a monitor circuit according to an embodiment of the present invention; [Diagram 5] FIG. 13 is a diagram for explaining MM characteristic values. [Figure 6] FIG. 13 is a diagram showing an S curve of MM output. [Figure 7] FIG. 13 is a diagram showing MM output. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Next, a clock data recovery circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0013] (1) Communication System Configuration FIG. 1 is an overall diagram of a communication system NS. The communication system NS includes a master 1 and a slave 2. The master 1 and the slave 2 are connected by a communication line NC. That is, in this embodiment, the master 1 and the slave 2 perform high-speed wired communication. The master 1 and the slave 2 may be installed in the same facility or in different facilities. Alternatively, the master 1 and the slave 2 may be installed in a vehicle such as an automobile. The master 1 and the slave 2 perform communication using, for example, TCP / IP. In this embodiment, the master 1 operates as a transmitter and the slave 2 operates as a receiver, so that the master 1 will be described below as a transmitter 1 and the slave 2 as a receiver 2. However, each device (each terminal) may have the functions of both the master 1 and the slave 2 described in the following embodiment. That is, each device (each terminal) may function as a transmitter and a receiver.

[0014] The transmitter 1 includes a digital-to-analog converter (DAC) 11 and a reference clock generating circuit 12. The digital-to-analog converter 11 converts a data signal to be transmitted into an analog signal based on a reference clock signal generated by the reference clock generating circuit 12, and outputs the analog signal to a communication line NC. The reference clock generating circuit 12 includes, for example, a crystal oscillator, a PLL (Phase Lock Loop) circuit, and the like.

[0015] The receiver 2 includes an analog-to-digital converter (ADC) 21, a reference clock generation circuit 22, and a clock data recovery circuit (CDR circuit) 23. The analog-to-digital converter 21 uses a reception clock signal MCL generated in the clock data recovery circuit 23 to digitally convert a data signal received via a communication line NC. The reference clock generation circuit 22 includes, for example, a crystal oscillator and a PLL circuit, and generates a reference clock signal BCL. The clock data recovery circuit 23 adjusts the phase of the reference clock signal BCL based on the digitally converted data signal, and generates a reception clock signal MCL.

[0016] (2) Receiver configuration including clock and data recovery circuit 2 is a block diagram of the receiver 2 showing the internal configuration of the clock data recovery circuit 23. The receiver 2 includes an analog-to-digital converter 21, a reference clock generation circuit 22, and a clock data recovery circuit 23, as shown in FIG.

[0017] The analog-to-digital converter 21 converts an analog data signal D1 received via a communication line NC into a digital data signal D2. The analog-to-digital converter 21 samples the data signal D2 based on a reception clock signal MCL generated by a phase interpolation circuit 208. The reference clock generation circuit 22 generates a reference clock signal BCL. The phase interpolation circuit 208 inputs the reference clock signal BCL output from the reference clock generation circuit 22. The phase interpolation circuit 208 adjusts the phase of the reference clock signal BCL based on phase data D8 generated by a clock data recovery circuit 23, and generates a reception clock signal MCL.

[0018] As shown in FIG. 2, the clock data recovery circuit 23 includes a phase detector 201, an adjustment circuit 202, a monitor circuit 203, a loop filter 204, an offset output circuit 205, a selector 206, an integration circuit 207, and a phase interpolation circuit 208.

[0019] The phase detector 201 receives the digital data signal D2 output from the analog-to-digital converter 21. The phase detector 201 calculates phase characteristic data D3 based on the data signal D2. In this embodiment, a case where a Mueller-Muller phase detector is used as the phase detector 201 will be described as an example. The phase detector 201 outputs a Mueller-Muller characteristic value (hereinafter referred to as an MM characteristic value) as the phase characteristic data D3 based on the data signal D2.

[0020] FIG. 5 is a diagram for explaining the MM characteristic value. In FIG. 5, the horizontal axis indicates time, and the vertical axis indicates the signal value of the data signal D2. Time t2 in the diagram indicates a sampling point. Times t1 and t3 are times before and after the sampling point t2, and the time interval between t1 and t2 and the time interval between t2 and t3 are the same. At time t1, the data signal D2 has a value "a," and at time t3, the data signal D2 has a value "b." The MM characteristic value is a value proportional to ba, and when ba=0, the MM characteristic value is 0. In other words, the MM characteristic value increases as the sampling point t2 shifts from the peak of the data signal D2.

[0021] 2, the adjustment circuit 202 receives the phase characteristic data D3 (MM characteristic value) output by the phase detector 201. The adjustment circuit 202 is a circuit that adjusts the offset and gain of the phase characteristic data D3.

[0022] 3 is a circuit diagram showing the adjustment circuit 202. The adjustment circuit 202 includes a calculation circuit 31 and a multiplier 32. The calculation circuit 31 receives the phase characteristic data D3 output by the phase detector 201. The calculation circuit 31 also receives the average value data D11 output by the monitor circuit 203. The calculation circuit 31 subtracts the average value data D11 from the phase characteristic data D3 to output subtraction data. The average value data D11 is used as an offset adjustment value for the phase characteristic data D3. The subtraction data is data in which the offset of the phase characteristic data D3 has been adjusted.

[0023] The multiplier 32 receives the subtraction data output by the arithmetic circuit 31. The multiplier 32 also receives the gain adjustment data D12 output by the monitor circuit 203. The multiplier 32 multiplies the subtraction data by the gain adjustment data D12 to output phase characteristic data D4. The gain adjustment data D12 is used as a gain adjustment value for the phase characteristic data D3. The phase characteristic data D4 is data in which the offset and gain of the phase characteristic data D3 have been adjusted. In other words, the phase characteristic data D4 is an MM characteristic value in which the offset and gain have been adjusted.

[0024] 2, the monitor circuit 203 receives the phase characteristic data D4 output by the adjustment circuit 202. The monitor circuit 203 is a circuit that operates during a training period before the start of communication.

[0025] 4 is a circuit diagram showing the monitor circuit 203. The monitor circuit 203 includes a square calculation circuit 41, an average value calculation circuit 42, an average value calculation circuit 43, a square calculation circuit 44, a calculation circuit 45, and a gain table 46. The square calculation circuit 41 receives the phase characteristic data D4 output by the adjustment circuit 202. The square calculation circuit 41 performs a calculation to square the value of the phase characteristic data D4. The average value calculation circuit 42 accumulates the calculation result of the square calculation circuit 41 for a predetermined period and calculates an average value.

[0026] The average value calculation circuit 43 receives the phase characteristic data D4 output by the adjustment circuit 202. The average value calculation circuit 43 accumulates the phase characteristic data D4 for a predetermined period and calculates an average value. The square calculation circuit 44 performs a square calculation of the average value output from the average value calculation circuit 43. The average value calculated by the average value calculation circuit 43 is provided to the adjustment circuit 202 as average value data D11.

[0027] The calculation circuit 45 receives the output of the average value calculation circuit 42 and the output of the square calculation circuit 44. The calculation circuit 45 subtracts the output value of the square calculation circuit 44 from the output value of the average value calculation circuit 42 to obtain a variance value of the phase characteristic data D4. The gain table 46 is a table that associates the variance value of the phase characteristic data D4 with the gain adjustment data D12. The gain table 46 receives the variance value output from the calculation circuit 45, and outputs the corresponding gain adjustment data D12. The gain adjustment data D12 is provided to the adjustment circuit 202.

[0028] 2, the loop filter 204 receives the phase characteristic data D4 output by the adjustment circuit 202. The loop filter 204 includes an averaging circuit and an integrating circuit. The loop filter 204 averages the phase characteristic data D4 in the averaging circuit. The loop filter 204 calculates adjustment data D5 by integrating the averaged phase characteristic data D4 in the integrating circuit. The loop filter 204 provides the adjustment data D5 to the selector 206.

[0029] The offset output circuit 205 is a circuit that operates during a training period before communication starts. The offset output circuit 205 provides the offset data D6 to the selector 206. The selector 206 receives a control signal C1 from a control device (not shown). When the selector 206 receives "0" as the control signal C1, it outputs the adjustment data D5 provided from the loop filter 204 as the adjustment data D7. When the selector 206 receives "1" as the control signal C1, it outputs the offset data D6 provided from the offset output circuit 205 as the adjustment data D7.

[0030] The integration circuit 207 integrates the adjustment data D7 output from the selector 206, and outputs phase data D8. The integration circuit 207 provides the phase data D8 to the phase interpolation circuit 208.

[0031] The phase interpolation circuit 208 receives the phase data D8 output from the integration circuit 207. The phase interpolation circuit 208 adjusts the phase of the reference clock signal BCL based on the phase data D8 to generate a reception clock signal MCL. The phase interpolation circuit 208 provides the reception clock signal MCL to the analog-to-digital converter 21. For example, consider a case where the phase of the reception clock signal MCL output from the phase interpolation circuit 208 is adjusted with an angular frequency ω. In this case, if the offset data D6 is Ω and the sample interval is Ts, then Ω=ω*Ts. By adding Ω for each sample in the integration circuit 207, the value integrated in the integration circuit 207 for one second becomes ω.

[0032] (3) Behavior during training The operation of the clock data recovery circuit 23 during the training period before the start of communication will be described. During the training period, the selector 206 shown in FIG. 2 is provided with a control signal C1 of "1". The selector 206 provides the offset data D6 output from the offset output circuit 205 to the integration circuit 207 as adjustment data D7. The integration circuit 207 integrates the adjustment data D7 and provides the phase data D8 to the phase interpolation circuit 208. As a result, the phase interpolation circuit 208 sequentially receives the phase data D8, the value of which gradually increases while the adjustment data D7 is added. In response to this, the phase interpolation circuit 208 sequentially adjusts the phase of the reference clock signal BCL based on the phase data D8. The phase interpolation circuit 208 outputs a reception clock signal MCL whose phase sequentially changes. The analog-to-digital converter 21 digitally converts the data signal D1 in synchronization with the reception clock signal MCL whose phase sequentially changes, and outputs a data signal D2.

[0033] The phase detector 201 receives the data signal D2 output by the analog-to-digital converter 21. The phase detector 201 outputs phase characteristic data D3 (MM characteristic value) based on the data signal D2. The phase detector 201 outputs the phase characteristic data D3 (MM characteristic value) corresponding to the received clock signal MCL whose phase changes sequentially. FIG. 6 is a graph showing the phase difference vs. output characteristic of the MM characteristic value. The phase difference vs. output characteristic of the MM characteristic value is called the S-curve of the MM characteristic value. In FIG. 6, the horizontal axis represents the phase difference, and the vertical axis represents the MM characteristic value. In the example shown in FIG. 6, the MM characteristic value has a maximum value of 0.3 The maximum value is around -0.2, and the minimum value is around -0.2, which is offset to the positive side. In other words, in the example of Figure 6, the MM characteristics are offset to the positive side due to the channel characteristics.

[0034] The adjustment circuit 202 receives the phase characteristic data D3 output by the phase detector 201. As shown in Fig. 3, the adjustment circuit 202 adjusts the offset of the phase characteristic data D3 using the average value data D11 received from the monitor circuit 203. Furthermore, the adjustment circuit 202 adjusts the gain of the phase characteristic data D3 using the gain adjustment data D12 received from the monitor circuit 203. For example, at the start of the training period, the offset (average value data D11) is set to "0" and the gain (gain adjustment data D12) is set to "1".

[0035] Next, the monitor circuit 203 receives the phase characteristic data D4 whose offset and gain have been adjusted. As shown in FIG. 4, the monitor circuit 203 generates average data D11 and gain adjustment data D12 based on the phase characteristic data D4. The generated average data D11 and gain adjustment data D12 are provided to the adjustment circuit 202, and the offset and gain of the phase characteristic data D4 are adjusted. In this way, during the training period, the adjustment circuit 202 and the monitor circuit 203 adjust the offset and gain of the phase characteristic data D3 by acquiring the phase difference vs. output characteristic (in this example, the S curve of the MM characteristic value) of the phase characteristic data D3. This makes it possible to adjust the phase characteristic data D3 during the training period according to the characteristics of the channel. When the training period ends, the offset (average data D11) and gain (gain adjustment data D12) set in the adjustment circuit 202 are locked.

[0036] FIG. 7 is a diagram showing the MM characteristic values ​​output by phase detector 201. In FIG. 7, the horizontal axis indicates time, and the vertical axis indicates the MM characteristic value. The upper diagram in FIG. 7 is a diagram plotting the average value of 40 samples of the MM characteristic value. The lower diagram in FIG. 7 is a diagram plotting the average value of 640 samples of the MM characteristic value. In the example in FIG. 7, the MM characteristic value is also offset to the positive side due to the characteristics of the channel. Monitor circuit 203 may obtain only one S curve shown in FIG. 6 and obtain the offset (average value data D11) and gain (gain adjustment data D12), or may obtain multiple S curves as shown in FIG. 7 and calculate their average value.

[0037] (4) Post-training movements The operation after training by the clock data recovery circuit 23 will be described. The phase detector 201 receives the data signal D2 output by the analog-to-digital converter 21. The phase detector 201 outputs phase characteristic data D3 (MM characteristic value) based on the data signal D2. The adjustment circuit 202 receives the phase characteristic data D3 output by the phase detector 201. The adjustment circuit 202 adjusts the offset of the phase characteristic data D3 by the average value data D11 locked during the training period. Furthermore, the adjustment circuit 202 adjusts the gain of the phase characteristic data D3 by the gain adjustment data D12 locked during the training period. After the training period ends, the monitor circuit 203 is not used.

[0038] Next, the loop filter 204 receives the phase characteristic data D4 whose offset and gain have been adjusted. The loop filter 204 averages and integrates the phase characteristic data D4, and outputs the adjusted data D5. After the training period ends, the selector 206 is provided with a control signal C1 of "0". The selector 206 provides the adjusted data D5 output from the loop filter 204 to the integrating circuit 207 as the adjusted data D7. The integrating circuit 207 integrates the adjusted data D7, and provides the phase data D8 to the phase interpolating circuit 208. In response to this, the phase interpolating circuit 208 adjusts the phase of the reference clock signal BCL based on the phase data D8, and outputs the receiving clock signal MCL. The analog-to-digital converter 21 samples the data signal D1 based on the receiving clock signal MCL, and outputs the data signal D2.

[0039] In this way, the clock data recovery circuit 23 of this embodiment acquires the phase difference vs. output characteristic (in the above example, the S-curve of the MM characteristic value) during the training period, and adjusts the offset and gain of the phase characteristic data D3 (MM characteristic value) according to the channel characteristics. This allows the loop filter 204, which operates after the training period ends, to converge the adjustment data D5 or phase data D8, and makes it possible for the analog-to-digital converter 21 to acquire the correct data signal D2.

[0040] Phase detector 201 is a device that detects the phase difference between a signal data sequence and a clock signal on the transmitting side, and operates nonlinearly with poor linearity. In addition, the S curve of the MM characteristic value has a problem that the loop characteristics change for each channel, so the phase lock range, phase noise, and lock time change depending on the channel. In this embodiment, the phase difference vs. output characteristic (in the above example, the S curve of the MM characteristic value) is acquired during the training period, so that the phase is locked correctly.

[0041] For example, when the frequency error between the oscillators of the transmitter 1 and the receiver 2 is expected to be about ±100 ppm, it is desirable to set an offset of about 200 ppm by the offset data D6 set in the offset output circuit 205. In other words, it is desirable to set an offset larger than the frequency error between the transmitter and the receiver. This makes it possible to change the phase of the reception clock signal MCL output from the phase interpolation circuit 208 during the training period as if an offset of about +100 ppm exists, even if the actual frequency error is -100 ppm.

[0042] (5) Other embodiments In the above embodiment, the MM characteristic value has been described as an example of the phase characteristic data D3. The phase characteristic data D3 is not limited to the MM characteristic value, and may be any characteristic value calculated according to the phase difference between the receiving clock signal MCL and the transmitting clock signal. Therefore, the S curve of the MM characteristic value that the monitor circuit 203 monitors is only an example, and the phase difference vs. output characteristic that indicates the relationship between the phase difference and the phase characteristic data D3 may be used.

[0043] As another embodiment, the offset data D6 output by the offset output circuit 205 may be variable. For example, the value of the offset data D6 may be freely set by the host CPU of the receiver 2 (slave), or the offset data D6 may be provided by negotiation from the transmitter 1 (master). The transmitter 1 may transmit the offset data D6 to the receiver 2 by low-speed communication before starting high-speed communication.

[0044] As another embodiment, offset data D6 may be calculated from an S curve of the MM characteristic value. For example, offset data D6 may be calculated by calculating the period of the S curve in monitor circuit 203. In this case, offset data D6 calculated in monitor circuit 203 may be added to the output of loop filter 204. In a normal state after the training period, adding offset data D6 to the output of loop filter 204 in advance makes it easier to lock the phase. This makes it possible to reduce the output gain of loop filter 204 and reduce jitter as much as possible.

[0045] Also, if the communication state becomes unstable, etc., a training period may be set again. In this case, the average value data D11 and the gain adjustment data D12 used in the previous training period may be used as the initial settings.

[0046] (6) Aspects of the present invention <1> As described above, the clock data recovery circuit according to the present embodiment includes a phase interpolation circuit that adjusts the phase of a reference clock signal generated by a reference clock generation circuit and generates a reception clock signal, a phase detector that operates in synchronization with the reception clock signal generated by the phase interpolation circuit, inputs a reception digital data signal output from an analog-to-digital converter that converts a reception analog data signal into a reception digital data signal, and outputs phase characteristic data from the reception digital data signal, an adjustment circuit that adjusts the phase characteristic data, a monitor circuit that monitors the phase characteristic data output from the adjustment circuit and calculates an adjustment value to be set in the adjustment circuit based on the phase characteristic data, a loop filter that outputs adjustment data for generating phase data to be set in the phase interpolation circuit based on the phase characteristic data output from the adjustment circuit, and an offset output circuit that outputs offset data for generating phase data to be set in the phase interpolation circuit. During a training period before starting communication, the phase of the reference clock signal to be adjusted in the phase interpolation circuit is changed based on the offset data output from the offset output circuit, and the adjustment value is calculated by the monitor circuit, thereby setting the adjustment value in the adjustment circuit.

[0047] <2> The monitor circuit may calculate the adjustment value based on a phase difference versus output characteristic that indicates the relationship between the phase adjusted in the phase interpolator during the training period and the phase characteristic data.

[0048] <3> The adjustment values ​​may include an offset adjustment value and a gain adjustment value.

[0049] <4> The monitor circuit may calculate the gain adjustment value based on the variance of the phase characteristic data.

[0050] <5> The monitor circuit may acquire the gain adjustment value by referring to a table in which the variance of the phase characteristic data corresponds to the gain adjustment value.

[0051] <6> The monitor circuit may calculate the offset adjustment value based on an average value of the phase characteristic data.

[0052] <7> The phase detector may be a Mueller Muller phase detector, and the phase difference vs. output characteristic may be an S-curve of a Mueller Muller output.

[0053] <8> The receiver according to the present embodiment is <1> ~ <7> The clock data recovery circuit includes any one of the above, a reference clock generation circuit, and an analog-to-digital converter. [Explanation of symbols]

[0054] 2...Receiver, 21...Analog-to-digital converter, 22...Reference clock generating circuit, 23...Clock data recovery circuit, 201...Phase detector, 202...Adjustment circuit, 203...Monitor circuit, 204...Loop filter, 205...Offset output circuit, 206...Selector, 207...Integration circuit, 208...Phase interpolation circuit

Claims

1. a phase interpolation circuit that adjusts the phase of a reference clock signal generated by the reference clock generation circuit to generate a reception clock signal; a phase detector which operates in synchronization with the reception clock signal generated in the phase interpolation circuit, inputs the reception digital data signal output from an analog-to-digital converter which converts a reception analog data signal into a reception digital data signal, and outputs phase characteristic data from the reception digital data signal; an adjustment circuit for adjusting the phase characteristic data; a monitor circuit that monitors the adjusted phase characteristic data output from the adjustment circuit and calculates an adjustment value to be set in the adjustment circuit based on the adjusted phase characteristic data; a loop filter that outputs adjustment data for generating phase data to be set in the phase interpolation circuit based on the adjusted phase characteristic data output from the adjustment circuit; an offset output circuit that outputs offset data for generating the phase data to be set in the phase interpolation circuit; Equipped with A clock data recovery circuit that, during a training period before starting communication, changes the phase of the reference clock signal adjusted in the phase interpolation circuit based on the offset data output from the offset output circuit, while calculating the adjustment value using the monitor circuit, thereby setting the adjustment value in the adjustment circuit.

2. 2. The clock data recovery circuit according to claim 1, wherein the monitor circuit calculates the adjustment value based on a phase difference vs. output characteristic indicating a relationship between the phase adjusted in the phase interpolator during the training period and the phase characteristic data.

3. 3. The clock data recovery circuit according to claim 1, wherein the adjustment value includes an offset adjustment value and a gain adjustment value.

4. 4. The clock data recovery circuit according to claim 3, wherein said monitor circuit calculates said gain adjustment value based on a variance of said adjusted phase characteristic data.

5. 5. The clock data recovery circuit according to claim 4, wherein the monitor circuit acquires the gain adjustment value by referring to a table in which the variance of the adjusted phase characteristic data corresponds to the gain adjustment value.

6. 6. The clock data recovery circuit according to claim 3, wherein the monitor circuit calculates the offset adjustment value based on an average value of the adjusted phase characteristic data.

7. 3. The clock data recovery circuit according to claim 2, wherein said phase detector is a Mueller-Muller phase detector, and said phase difference vs. output characteristic is an S-curve of a Mueller-Muller output.

8. A clock data recovery circuit according to any one of claims 1 to 7; the reference clock generating circuit; and a receiver comprising the analog-to-digital converter.

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