Semiconductor device manufacturing method and semiconductor wafer

Abstract

To appropriately perform alignment when a facet surface is formed on an epitaxial layer.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: preparing an SiC substrate that has a recessed alignment mark on its upper surface, and in which a vertical line erected on the upper surface is inclined to a [11-20] direction side relative to a [0001] direction; growing an epitaxial layer on the upper surface of the SiC substrate so as to cover the alignment mark; and forming a structure on the upper surface of the SiC substrate. The structure is formed at a position at an interval P to the [11-20] direction side from the alignment mark on the upper surface of the SiC substrate. The interval P satisfies a relation of D / tanθ<P<10D / tanθ, with respect to a depth D of the alignment mark, and an inclination angle θ to the [0001] direction of the vertical line.SELECTED DRAWING: Figure 16

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device and a semiconductor wafer.

[0002] Patent Document 1 discloses a SiC substrate with a concave alignment mark formed on the top surface. In this SiC substrate, the top surface is inclined with respect to the (0001) plane so that the [11-20] direction is the off-direction. That is, in this SiC substrate, a perpendicular line erected on the top surface of the SiC substrate is inclined toward the [11-20] direction with respect to the

[0001] direction. When an epitaxial layer is grown on the surface of this SiC substrate so as to cover the alignment mark, a facet inclined with respect to the top surface of the SiC substrate is formed at a position adjacent to the [11-20] direction side of the alignment mark. In the technology of Patent Document 1, the formation of a facet is suppressed by forming the alignment mark into a predetermined shape. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Publication 2019-056726 Summary of the Invention [Problem to be solved by the invention]

[0004] Even if the technique of Patent Document 1 is used, it may not be possible to prevent the formation of facet planes. Also, due to various restrictions, it may not be possible to form an alignment mark as in Patent Document 1, and thus it may not be possible to prevent the formation of facet planes. When an epitaxial layer is formed so as to cover the alignment mark, thereafter, alignment is performed using the concave portion on the surface of the epitaxial layer (that is, the concave portion formed following the alignment mark). At this time, if the facet plane formed in the epitaxial layer interferes with other structures, the concave portion on the surface of the epitaxial layer cannot be correctly recognized by the alignment apparatus, and alignment cannot be appropriately performed. In this specification, a technique capable of appropriately performing alignment even when a facet plane is formed in the epitaxial layer is proposed.

Means for Solving the Problem

[0005] The method for manufacturing a semiconductor device disclosed in this specification includes a step of preparing a SiC substrate having a concave alignment mark on the upper surface and the perpendicular line erected on the upper surface being inclined toward the [11-20] direction side with respect to the

[0001] direction, a step of growing an epitaxial layer on the upper surface of the SiC substrate so as to cover the alignment mark, and a step of forming a structure on the upper surface of the SiC substrate. The structure is formed at a position spaced apart by a distance P from the alignment mark toward the [11-20] direction along the upper surface of the SiC substrate. The distance P satisfies the relationship of D / tanθ < P < 10D / tanθ with respect to the depth D of the alignment mark and the inclination angle θ of the perpendicular line with respect to the

[0001] direction.

[0006] Note that the step of preparing a SiC substrate having an alignment mark may be a step of bringing a SiC substrate having an alignment mark into a manufacturing facility, or may be a step of forming an alignment mark on a SiC substrate.

[0007] The step of forming the structure on the upper surface of the SiC substrate may be carried out before the formation of the epitaxial layer or after the formation of the epitaxial layer. That is, the "upper surface of the SiC substrate" in the step of forming the structure on the upper surface of the SiC substrate may be the upper surface of the SiC substrate before the formation of the epitaxial layer or the upper surface of the SiC substrate after the formation of the epitaxial layer (i.e., the upper surface of the epitaxial layer).

[0008] From the inventors' experiments, it was found that the width of the facet plane formed adjacent to the alignment mark when growing the epitaxial layer so as to cover the alignment mark can be predicted from the inclination angle θ (so-called off-angle) with respect to the

[0001] direction of the upper surface of the SiC substrate and the depth D of the alignment mark. Generally, the width of the facet plane is narrower than the calculated width W calculated by the formula W = D / tanθ. Therefore, by setting the interval P so as to satisfy the relationship D / tanθ < P, it is possible to suppress the interference between the facet plane and the structure. Also, if the interval P is made unnecessarily wide, the area occupied by the interval P becomes wide, leading to a decrease in the number of semiconductor devices that can be manufactured from the SiC substrate. As described above, by setting the interval P so as to satisfy the relationship D / tanθ < P < 10D / tanθ (i.e., W < P < 10W), it is possible to suppress the interference between the facet plane and the structure without unnecessarily widening the interval P. Since the interference between the facet plane and the structure can be suppressed, alignment can be appropriately performed using the concave portion on the surface of the epitaxial layer (i.e., the concave portion formed following the alignment mark).

Brief Description of the Drawings

[0009] [Figure 1] Plan view of the SiC substrate. [Diagram 2] Cross-sectional view of the SiC substrate. [Diagram 3] Plan view of the alignment mark on the upper surface of the SiC substrate (i.e., the base substrate). [Figure 4] Explanatory diagram of the alignment mark forming step. [Diagram 5]FIG. 4 is an explanatory diagram of an alignment mark forming process. [Figure 6] FIG. 4 is an explanatory diagram of an alignment mark forming process. [Figure 7] FIG. 4 is an explanatory diagram of an alignment mark forming process. [Figure 8] FIG. 4 is an explanatory diagram of an alignment mark forming process. [Figure 9] FIG. 4 is an explanatory diagram of an alignment mark forming process. [Figure 10] FIG. 4 is an explanatory diagram of an alignment mark forming process. [Figure 11] FIG. [Figure 12] FIG. 2 is a plan view of the alignment marks on the top surface of the SiC layer. [Figure 13] FIG. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] FIG. [Figure 17] FIG. 11 is an enlarged cross-sectional view of an alignment mark according to a second embodiment. [Figure 18] FIG. 4 is an explanatory diagram of an epitaxial growth process in Example 2. [Figure 19] FIG. 11 is an explanatory diagram of a structure forming process according to the second embodiment. [Figure 20] FIG. 13 is an explanatory diagram of a structure forming step according to a modified example of the second embodiment. [Figure 21] 11 is a plan view showing a modified example of an alignment mark on the upper surface of a SiC substrate (i.e., a base substrate). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In one example of the manufacturing method disclosed herein, the step of forming the structure may include forming the structure having a concave shape on the upper surface of the SiC substrate before forming the epitaxial layer. Also, in another example of the manufacturing method disclosed herein, the step of forming the structure may include forming the structure having a convex shape or a concave shape on the upper surface of the epitaxial layer.

[0011] As such, the structures may be formed before the epitaxial layer is formed or after the epitaxial layer is formed.

[0012] In one example manufacturing method disclosed in the present specification, when the top surface of the SiC substrate is viewed from above, an edge of the alignment mark on the [11-20] direction side may be perpendicular to the [11-20] direction.

[0013] This configuration tends to make the calculated width W match the maximum actual facet width with high accuracy.

[0014] In one example of the manufacturing method disclosed herein, the alignment mark may be a first alignment mark. In the step of growing the epitaxial layer, a second alignment mark having a concave shape corresponding to a shape of the first alignment mark may be formed on the upper surface of the epitaxial layer. The manufacturing method may further include a step of performing alignment using the second alignment mark.

[0015] Further, this specification discloses a new semiconductor wafer. This semiconductor wafer has a base substrate, an epitaxial layer, and a structure. The base substrate has a concave alignment mark on its upper surface, and a perpendicular line erected on the upper surface is inclined toward the [11-20] direction side with respect to the <0001> direction, and is composed of SiC. The epitaxial layer is provided on the upper surface of the base substrate and covers the alignment mark. The structure is provided on the upper surface of the base substrate or the upper surface of the epitaxial layer. The structure is arranged at a position spaced apart from the alignment mark by a distance P toward the [11-20] direction along the upper surface of the base substrate. With respect to the depth D of the alignment mark and the inclination angle θ of the perpendicular line with respect to the <0001> direction, the distance P satisfies the relationship of D / tanθ < P < 10D / tanθ.

[0016] According to this semiconductor wafer, alignment can be appropriately performed using the recess on the surface of the epitaxial layer.

[0017] In an example of the semiconductor wafer disclosed in this specification, the structure may be a recess provided on the upper surface of the base substrate. Further, in another example of the semiconductor wafer disclosed in this specification, the structure may be a protrusion or a recess provided on the upper surface of the epitaxial layer.

[0018] As described above, the structure may be provided on the upper surface of the base substrate or on the upper surface of the epitaxial layer.

[0019] In an example of the semiconductor wafer disclosed in this specification, when the upper surface of the base substrate is viewed from above, the edge on the [11-20] direction side of the alignment mark may be perpendicular to the [11-20] direction.

[0020] According to this configuration, the calculation width W is likely to match with high accuracy the maximum value of the width of the actual facet surface.

[0021] In the semiconductor wafer of the example disclosed herein, the alignment mark may be a first alignment mark, and a second alignment mark having a concave shape corresponding to a shape of the first alignment mark may be provided on the upper surface of the epitaxial layer. EXAMPLES

[0022] In the manufacturing method of the first embodiment, a semiconductor device is manufactured from a SiC substrate 12 shown in FIGS. 1 and 2. The SiC substrate 12 is made of 4H-SiC. Hereinafter, the thickness direction of the SiC substrate 12 is referred to as the z direction, one direction perpendicular to the z direction is referred to as the x direction, and a direction perpendicular to the z direction and the x direction is referred to as the y direction. The x direction and the y direction are parallel to the upper surface 12a of the SiC substrate 12. As shown in FIG. 2, the [1-100] direction of the SiC substrate 12 coincides with the y direction. The (0001) plane of the SiC substrate 12 is inclined by an off angle θ with respect to the upper surface 12a of the SiC substrate 12, with the [1-100] direction as an axis. That is, the (0001) plane is inclined with respect to the upper surface 12a in a cross section including the [11-20] direction and the

[0001] direction. The perpendicular line 12s in FIG. 2 indicates a perpendicular line erected on the upper surface 12a. The (0001) plane is inclined at the off angle θ with respect to the upper surface 12a, so that the perpendicular line 12s is inclined at the off angle θ toward the [11-20] direction with respect to the

[0001] direction. The off angle θ may be 10 degrees or less, or may be 5 degrees or less. For example, the off angle θ may be about 4 degrees. As shown in FIG. 1, in a plan view of the upper surface 12a of the SiC substrate 12, the x direction extends along the [11-20] direction.

[0023] In the manufacturing method of the first embodiment, first, an alignment mark forming step is performed. In the alignment mark forming step, a plurality of alignment marks 20 shown in FIG. 3 are formed on the upper surface 12a of the SiC substrate 12. Each alignment mark 20 is a concave shape provided on the upper surface 12a of the SiC substrate 12. Each alignment mark 20 has a rectangular shape on the upper surface 12a with a long side extending along the y direction and a short side extending along the x direction. Therefore, when the upper surface 12a of the SiC substrate 12 is viewed from above, the side surface 24 (i.e., the edge) of each alignment mark 20 on the [11-20] direction side extends perpendicularly to the [11-20] direction. Each alignment mark 20 is arranged at an interval P in the x direction. Although not shown in FIG. 1, the upper surface 12a of the SiC substrate 12 has an element region in which a semiconductor element structure is formed and an external region outside the element region. The outer region is a region that is removed when the SiC substrate 12 is divided into a plurality of semiconductor devices by dicing, etc. Each alignment mark 20 is formed in the outer region of the upper surface 12a of the SiC substrate 12.

[0024] In the alignment mark forming step, the alignment mark 20 can be formed by various methods. FIG. 4 shows a first forming method of the alignment mark 20. In the first forming method, first, as shown in FIG. 4, a resist mask 30 having openings 30a is formed on the upper surface 12a of the SiC substrate 12. Next, the upper surface 12a of the SiC substrate 12 is etched in the openings 30a by anisotropic etching. As a result, a concave alignment mark 20 is formed in each opening 30a. After the alignment mark 20 is formed, the resist mask 30 is removed.

[0025] 5 to 7 show a second forming method of the alignment mark 20. Note that, in FIGS. 5 to 7, cross sections of the element region 13 and the external region 14 are shown. In the second forming method, first, as shown in FIG. 5, a hard mask 32 (for example, a mask made of silicon oxide) is formed on the upper surface 12a of the SiC substrate 12. The hard mask 32 is a mask for controlling the range of ion implantation into the SiC substrate 12. Next, a resist mask 34 having an opening 34a is formed on the hard mask 32. Next, as shown in FIG. 6, the hard mask 32 is etched in the opening 34a by anisotropic etching. Thus, the opening 32a is formed in the hard mask 32. Since the opening 32a is formed so as to reach the SiC substrate 12, the upper surface 12a of the SiC substrate 12 is over-etched when the opening 32a is formed. Therefore, a concave shape is formed on the upper surface 12a of the SiC substrate 12. The concave shape formed in the external region 14 becomes the alignment mark 20. After the opening 32a is formed in the hard mask 32, the resist mask 34 is removed. Next, n-type or p-type impurities are ion-implanted into the upper surface 12a of the SiC substrate 12 through the hard mask 32. Therefore, as shown in FIG. 7, a diffusion layer 40 is formed in the SiC substrate 12 below the opening 32a. In the element region 13, the diffusion layer 40 is formed at a required position. In the external region 14, the diffusion layer 40 is formed below the alignment mark 20. There is no particular problem even if the diffusion layer 40 is formed below the alignment mark 20. As described above, in the second formation method, the alignment mark 20 is formed by utilizing the phenomenon that the upper surface 12a of the SiC substrate 12 is over-etched when the opening 32a is formed in the hard mask 32 for ion implantation.

[0026] 8 to 10 show a third method for forming the alignment mark 20. Note that, in FIGS. 8 to 10, cross sections of the element region 13 and the external region 14 are shown. In the third method, first, as shown in FIG. 8, a resist mask 36 having an opening 36a is formed on the upper surface 12a of the SiC substrate 12. Next, n-type or p-type impurities are ion-implanted into the upper surface 12a of the SiC substrate 12 through the resist mask 36. Therefore, as shown in FIG. 9, a diffusion layer 40 is formed in the SiC substrate 12 below the opening 36a. In the element region 13, the diffusion layer 40 is formed at a required position. In the external region 14, the diffusion layer 40 is formed at a position where the alignment mark 20 is to be formed. Next, the SiC substrate 12 is etched by anisotropic etching in the opening 36a. As a result, a concave shape is formed on the upper surface 12a of the SiC substrate 12 as shown in FIG. 10. The concave shape formed in the external region 14 is the alignment mark 20. After the alignment marks 20 are formed, the resist mask 36 is removed.

[0027] Fig. 11 shows a cross-sectional view taken along line XI-XI in Fig. 3. That is, Fig. 11 shows a cross-sectional view of alignment marks 20a and 20b among alignment marks 20 along the x direction. Note that, although alignment marks 20a and 20b are shown in Fig. 11, the other alignment marks 20 are also formed in the same shape as Fig. 11. As shown in Fig. 11, the depth D of each alignment mark 20 is smaller than the width Wa of each alignment mark 20 in the x direction. Also, a space P is provided between each alignment mark 20 in the x direction.

[0028] In the manufacturing method of the first embodiment, an epitaxial growth process is performed after the alignment mark formation process. In the epitaxial growth process, the SiC layer 50 shown in FIG. 13 and the like is epitaxially grown on the upper surface 12a of the SiC substrate 12. The SiC layer 50 is formed so as to cover each alignment mark 20. When each alignment mark 20 is covered with the SiC layer 50, a concave shape following the shape of the alignment mark 20 is formed on the surface of the SiC layer 50. Hereinafter, the concave shape following the shape of the alignment mark 20 formed on the surface of the SiC layer 50 is referred to as an alignment mark 60. As shown in FIG. 12, a facet surface 60F is formed on a part of each alignment mark 60. The formation of the facet surface 60F will be described below.

[0029] 13 to 16 show how the SiC layer 50 is epitaxially grown on the surface of the SiC substrate 12 in the epitaxial growth step. In the following, the SiC substrate 12 before the epitaxial growth step is referred to as the base substrate 12b, and the entirety of the base substrate 12b and the SiC layer 50 is referred to as the SiC substrate 12. As shown in FIG. 13, when the SiC layer 50 is grown on the base substrate 12b, an alignment mark 60 having a concave shape following the shape of the alignment mark 20 is formed on the upper surface of the SiC layer 50. In the following, the alignment mark 60 following the shape of the alignment mark 20a may be referred to as the alignment mark 60a, and the alignment mark 60 following the shape of the alignment mark 20b may be referred to as the alignment mark 60b. As shown in FIG. 13, the SiC layer 50 grows with a substantially uniform thickness on the upper surface 12a of the base substrate 12b, the side surface 22 on the [-1-120] direction side of the alignment mark 20, and the range spanning the bottom surface 23 of the alignment mark 20. Hereinafter, the thickness of the SiC layer 50 on the upper surface 12a of the base substrate 12b (more specifically, the thickness of the part with a uniform thickness) is referred to as the thickness T. The SiC layer 50 hardly grows on the side surface 24 on the [11-20] direction side of the alignment mark 20. Therefore, the SiC layer 50 does not grow uniformly on the upper surface 12a within the range adjacent to the alignment mark 20 on the [11-20] direction side. In this range, the SiC layer 50 grows so that the thickness of the SiC layer 50 increases with increasing distance from the alignment mark 20, and the surface 60F of the SiC layer 50 becomes parallel to the (0001) plane. The surface 60F parallel to the (0001) plane is a facet 60F.

[0030] When the thickness T of the SiC layer 50 is further increased from the state of FIG. 13, the state shown in FIG. 14 is obtained. In FIG. 14, the imaginary line 50x represents the surface of the SiC layer 50 in the state of FIG. 13, and the thickness increase amount ΔT1 represents the thickness increased from the state of FIG. 13. As shown in FIG. 14, even if the thickness T increases, the SiC layer 50 does not grow on the original facet surface 60F. Also, when the thickness T increases, the SiC layer 50 grows so that the surface of the SiC layer 50 is parallel to the (0001) plane at a position adjacent to the original facet surface 60F on the [11-20] direction side. That is, the facet surface 60F expands in the [11-20] direction side. The width Wf in FIGS. 13 and 14 indicates the width of the facet surface 60F in the x direction. As is clear from FIGS. 13 and 14, when the thickness T increases, the width Wf of the facet surface 60F becomes wider. Thus, when the film thickness T is smaller than the depth D of the alignment mark 20, the width Wf of the facet 60F increases with an increase in the film thickness T. In this case, the width Wf of the facet 60F relatively accurately satisfies the relationship Wf=T / tan θ.

[0031] 14, the thickness T reaches the depth D of the alignment mark 20 as shown in Fig. 15. Then, the alignment mark 20 is buried in the SiC layer 50. In this state (i.e., the state where T=D), the width Wf of the facet 60F relatively accurately satisfies the relationship Wf=D / tan θ.

[0032] When the film thickness T further increases from the state of FIG. 15, the SiC layer 50 grows as shown in FIG. 16. In FIG. 16, the virtual line 50y represents the surface of the SiC layer 50 in the state of FIG. 15 (i.e., the state where T = D), and the film thickness increase amount ΔT2 indicates the film thickness increased from the state of FIG. 15. As shown by the film thickness increase amount ΔT2 in FIG. 16, after the alignment mark 20 is embedded, the SiC layer 50 grows substantially uniformly on all surfaces. That is, on the facet surface 60F, the SiC layer 50 grows with a uniform film thickness similar to that on other surfaces. When the SiC layer 50 grows in this way, even if the film thickness T of the SiC layer 50 increases, the width Wf of the facet surface 60F hardly changes. Therefore, when the film thickness T is greater than the depth D, even if the film thickness T increases, the width Wf of the facet surface 60F hardly changes. For this reason, when the film thickness T is greater than the depth D, the width Wf of the facet surface 60F approximately accurately satisfies the relationship of Wf = D / tanθ.

[0033] As described above, when the film thickness T is smaller than the depth D (i.e., in the cases of FIGS. 13 and 14), the width Wf of the facet surface 60F approximately accurately satisfies the relationship of Wf = T / tanθ. In this case, since T < D, the width Wf approximately accurately satisfies the relationship of Wf < D / tanθ. Also, when the film thickness T is greater than or equal to the depth D (i.e., in the cases of FIGS. 15 and 16), the width Wf approximately accurately satisfies the relationship of Wf = D / tanθ. Therefore, usually, regardless of the film thickness T, the width Wf does not become larger than the calculated width W calculated by the formula of W = D / tanθ. Therefore, by making the interval P in the x-direction between the alignment mark 20a and the alignment mark 20b larger than the calculated width W calculated by the above formula, it is possible to suppress the interference of the facet surface 60F of the alignment mark 60a with the alignment mark 60b.

[0034] Note that the actual width Wf of the facet surface 60F may be larger than the calculated width W due to the influence of manufacturing conditions and the like. Therefore, it is preferable to provide a margin with respect to the calculated width W and provide an interval P. However, if the interval P is made larger than necessary with respect to the calculated width W, the area occupied by the plurality of alignment marks 20 will increase, leading to a decrease in the number of semiconductor devices manufactured from the SiC substrate 12. Also, when the area occupied by the plurality of alignment marks 20 increases, the imaging magnification when imaging the plurality of alignment marks with an alignment camera becomes smaller, and the alignment accuracy decreases. Through various experiments, it has been found that the actual width Wf of the facet surface 60F does not reach 10 times the calculated width W. Therefore, if the interval P is set to satisfy the relationship of W < P < 10W (that is, the relationship of D / tanθ < P < 10D / tanθ), it is possible to suppress the interference of the facet surface 60F of the alignment mark 60 with the adjacent alignment mark 60 and prevent the expansion of the area occupied by the plurality of alignment marks 20. In the manufacturing method of Example 1, since the interval P satisfies the relationship of W < P < 10W, it is possible to suppress the interference of the facet surface 60F of the alignment mark 60 with the adjacent alignment mark 60 and prevent the expansion of the area occupied by the plurality of alignment marks 20.

[0035] In the manufacturing method of the first embodiment, an alignment step using a plurality of alignment marks 60 is performed after the epitaxial growth step. For example, alignment may be performed using a plurality of alignment marks 60, and etching, ion implantation, etc. may be performed on the SiC layer 50, a semiconductor layer other than the SiC layer 50, or other layers (for example, an electrode layer, an insulating layer, etc.). For example, when ion implantation is performed on the grown SiC layer 50, alignment may be performed using the alignment marks 60 to accurately form an opening in an ion implantation mask, and ion implantation may be performed on the SiC layer 50 through the ion implantation mask. Since the facet surface 60F of the alignment mark 60 does not interfere with other alignment marks 60, alignment using the alignment marks 60 can be performed appropriately. In addition, since the interval P between the alignment marks 60 is relatively narrow, the magnification can be increased when the alignment marks 60 are photographed by an alignment camera. Therefore, alignment can be performed with high accuracy.

[0036] Thereafter, the SiC substrate 12 is diced into a plurality of pieces to manufacture the semiconductor device.

[0037] The semiconductor wafer shown in FIG. 16 (i.e., the SiC substrate 12) has the following configuration. The semiconductor wafer (i.e., the SiC substrate 12) has a base substrate 12b and an epitaxial layer (i.e., the SiC layer 50). The base substrate 12b has a concave alignment mark 20a on its upper surface 12a. As shown in FIG. 2, the vertical line drawn on the upper surface 12a is inclined toward the [11-20] direction side with respect to the

[0001] direction. As shown in FIG. 16, the epitaxial layer (i.e., the SiC layer 50) is provided on the upper surface 12a of the base substrate 12b and covers the alignment mark 20a. A concave alignment mark 20b is provided as a structure on the upper surface 12a of the base substrate 12b. The structure (i.e., the alignment mark 20b) is arranged at a position spaced apart by a distance P from the alignment mark 20a toward the [11-20] direction along the upper surface 12a of the base substrate 12b. With respect to the depth D of the alignment mark 20a and the inclination angle θ (i.e., the off-angle θ) of the vertical line drawn on the upper surface 12a with respect to the

[0001] direction, the distance P satisfies the relationship D / tanθ < P < 10D / tanθ. Therefore, in this semiconductor wafer, the facet surface 60F of the alignment mark 60a does not interfere with the alignment mark 60b, and alignment can be appropriately performed using the alignment mark 60a. That is, by using this semiconductor wafer, a semiconductor device can be appropriately manufactured.

Example

[0038] In the manufacturing method of Example 2, as in Examples 1 and 2, a semiconductor device is manufactured from the SiC substrate 12 shown in FIGS. 1 and 2. In this manufacturing method, in the same manner as in Example 1, a concave alignment mark 20 is formed on the upper surface 12a of the SiC substrate 12. Here, as shown in FIG. 17, an alignment mark 20 with a depth D smaller than the width Wa is formed. Next, as shown in FIG. 18, an SiC layer 50 is epitaxially grown on the SiC substrate 12 (i.e., the base substrate 12b) so as to cover the alignment mark 20. Therefore, an alignment mark 60 is formed on the surface of the SiC layer 50 following the alignment mark 20. Also, a facet surface 60F is formed on the [11-20] direction side of the alignment mark 60.

[0039] Next, as shown in FIG. 19, a convex structure 80 is formed on the upper surface of the SiC substrate 12 (i.e., the upper surface of the SiC layer 50). Note that the structure 80 may be a conductor, an insulator, or a semiconductor. Also, the structure 80 may be a part of the semiconductor device or a part of the mask. Here, a convex structure 80 is formed on the [11-20] direction side of the alignment mark 20. Also, here, a gap P is provided along the x direction between the alignment mark 20 and the structure 80. Here, the gap P is set so as to satisfy the relationship of W<P<10W (i.e., the relationship of D / tanθ<P<10D / tanθ). Therefore, interference between the structure 80 and the facet surface 60F can be prevented without making the gap between the structure 80 and the alignment mark 20 wider than necessary.

[0040] Thereafter, an alignment process using the alignment mark 60 is performed. Since the facet surface 60F of the alignment mark 60 does not interfere with the structure 80, alignment using the alignment mark 60 can be appropriately performed.

[0041] Thereafter, the semiconductor device is manufactured by dicing the SiC substrate 12 into a plurality of pieces.

[0042] Note that the semiconductor wafer (i.e., SiC substrate 12) shown in FIG. 19 has the following configuration. The semiconductor wafer (i.e., SiC substrate 12) has a base substrate 12b and an epitaxial layer (i.e., SiC layer 50). The base substrate 12b has a concave alignment mark 20 on its upper surface 12a. As shown in FIG. 2, the perpendicular line erected on the upper surface 12a is inclined toward the [11-20] direction with respect to the

[0001] direction. As shown in FIG. 19, the epitaxial layer (i.e., SiC layer 50) is provided on the upper surface 12a of the base substrate 12b and covers the alignment mark 20. A structure 80 is provided on the upper surface of the epitaxial layer (i.e., SiC layer 50). The structure 80 is arranged at a position spaced by a distance P from the alignment mark 20 in the [11-20] direction on the upper surface 12a of the base substrate 12b. With respect to the depth D of the alignment mark 20 and the inclination angle θ (i.e., off-angle θ) of the perpendicular line erected on the upper surface 12a with respect to the

[0001] direction, the distance P satisfies the relationship of D / tanθ < P < 10D / tanθ. Therefore, in this semiconductor wafer, the facet surface 60F does not interfere with the structure 80, and alignment can be appropriately performed using the alignment mark 60.

[0043] In the above-described Example 2, the structure 80 was a convex portion provided on the upper surface of the SiC layer 50. However, as shown in FIG. 20, the structure 80 may be a concave portion provided on the upper surface of the SiC layer 50. Even with this configuration, interference between the structure 80 and the facet surface 60F can be suppressed.

[0044] In the above-described Examples 1 and 2, each alignment mark 20 had a rectangular shape on the upper surface 12a of the SiC substrate 12. However, each alignment mark 20 may have another shape. In this case, the side surface of each alignment mark 20 on the [11-20] direction side on the upper surface 12a does not have to be perpendicular to the [11-20] direction. For example, as shown in FIG. 21, the side surface 24 (i.e., edge portion) of each alignment mark 20 on the [11-20] direction side may extend along a direction intersecting obliquely with respect to the [11-20] direction.

[0045] In addition, in the above-described Examples 1 and 2, the SiC layer 50 was grown until the film thickness T of the SiC layer 50 became thicker than the depth D of the alignment mark 20. However, the SiC layer 50 may be grown so that the film thickness T of the SiC layer 50 becomes thinner than the depth D of the alignment mark 20. Even in this case, by setting the interval P so as to satisfy the relationship of D / tanθ < P < 10D / tanθ, it is possible to suppress the interference of the facet plane 60F with other structures without making the interval P wider than necessary.

[0046] In addition, in the above-described Examples 1 and 2, the alignment mark 20 was formed. However, it may be brought into the manufacturing facility by purchasing, etc., an SiC substrate 12 on which the alignment mark 20 is formed so as to satisfy the relationship of D / tanθ < P < 10D / tanθ. Even if the same epitaxial growth process and alignment process as in Examples 1 and 2 are performed on the SiC substrate 12 on which the alignment mark 20 is formed in advance, the same effects as in Examples 1 and 2 can be obtained.

[0047] The SiC layer 50 of Examples 1 and 2 is an example of an epitaxial layer. The alignment marks 20a and 20 of Examples 1 and 2 are examples of a first alignment mark. The alignment mark 20b of Example 1 is an example of a concave structure formed on the upper surface of the SiC substrate before forming the epitaxial layer. The structure 80 of Example 2 is an example of a convex or concave structure formed on the upper surface of the epitaxial layer. The alignment marks 60a and 60 of Examples 1 and 2 are examples of a second alignment mark.

[0048] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0049] 12: SiC substrate, 12s: perpendicular line, 20: alignment mark, 50: SiC layer, 60: alignment mark, 60F: facet surface

Claims

1. A method for manufacturing a semiconductor device, comprising: preparing a SiC substrate having a concave alignment mark on an upper surface thereof, the perpendicular line of which is inclined toward the [11-20] direction with respect to the [0001] direction; growing an epitaxial layer on the top surface of the SiC substrate so as to cover the alignment mark; forming a structure on the top surface of the SiC substrate; having the structure is formed along the top surface of the SiC substrate at a position spaced apart from the alignment mark in a [11-20] direction; the interval P satisfies a relationship of D / tan θ<P<10D / tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the perpendicular line with respect to the [0001] direction; Manufacturing method.

2. The method according to claim 1 , wherein in the step of forming the structure, the structure having a concave shape is formed on the upper surface of the SiC substrate before forming the epitaxial layer.

3. The method according to claim 1 , wherein in the step of forming the structure, the structure is formed in a convex or concave shape on the upper surface of the epitaxial layer.

4. The manufacturing method according to any one of claims 1 to 3, wherein when the top surface of the SiC substrate is viewed from above, an edge of the alignment mark on a [11-20] direction side is perpendicular to the [11-20] direction.

5. the alignment mark is a first alignment mark, In the step of growing the epitaxial layer, a second alignment mark having a concave shape corresponding to a shape of the first alignment mark is formed on the upper surface of the epitaxial layer; The method further includes a step of performing alignment using the second alignment mark. The method according to any one of claims 1 to 4.

6. A semiconductor wafer, a base substrate made of SiC, the base substrate having a concave alignment mark on an upper surface thereof, a perpendicular line erected on the upper surface being inclined toward the [11-20] direction with respect to the [0001] direction; an epitaxial layer provided on the top surface of the base substrate and covering the alignment mark; a structure provided on an upper surface of the base substrate or an upper surface of the epitaxial layer; having the structure is disposed along the top surface of the base substrate at a position spaced apart from the alignment mark in a [11-20] direction, the interval P satisfies a relationship of D / tan θ<P<10D / tan θ, where D is a depth of the alignment mark and θ is an inclination angle of the perpendicular line with respect to the [0001] direction; Semiconductor wafer.

7. The semiconductor wafer according to claim 6 , wherein the structure is a recess provided on the top surface of the base substrate.

8. The semiconductor wafer according to claim 6 , wherein the structure is a protrusion or a recess provided on the upper surface of the epitaxial layer.

9. 9. The semiconductor wafer according to claim 6, wherein, when the upper surface of the base substrate is viewed from above, an edge of the alignment mark on a side facing the [11-20] direction is perpendicular to the [11-20] direction.

10. the alignment mark is a first alignment mark, a second alignment mark having a concave shape corresponding to a shape of the first alignment mark is provided on the upper surface of the epitaxial layer; The semiconductor wafer according to any one of claims 6 to 9.

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