Scaling DRAMs with a self-aligned bitline process.

Abstract

A memory device and a method for forming the memory device are described. A method for forming an electronic device is described, in which a spacer is formed around each bit line contact pillar, the spacer contacting the spacer of an adjacent bit line contact pillar. A doped layer is also epitaxially grown on the memory stack, and bit lines are formed on the memory stack. The bit lines are self-aligned with the active areas.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the present disclosure provide electronic devices including self-aligned bitline contacts and methods of forming the same. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased while the feature size (i.e., the smallest component (or line) that can be made using a manufacturing process) has decreased.

[0003] The density of integrated circuits on semiconductor substrates has increased dramatically, and the minimum feature sizes, such as field effect transistor (FET) channel length and word line width on dynamic random access memory (DRAM), have decreased dramatically. As the critical dimensions decrease, etching to form bit lines becomes more difficult, resulting in misalignment and polysilicon band problems, such as skirt defects. Furthermore, increased contact resistance leads to reduced drive current.

[0004] Therefore, there is a need in the art for a method of forming bitline contacts that are self-aligned and free of skirt defects. Summary of the Invention

[0005] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method includes forming a plurality of bitline contact pillars extending across a memory stack, the memory stack including a dielectric material and an active region, forming a spacer around each of the bitline contact pillars, the spacer contacting a spacer of an adjacent bitline contact pillar, epitaxially growing a doped layer over the active region, and forming a bitline on the memory stack, the bitline aligned with the active region.

[0006] Further embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method includes forming spacers around a plurality of bitline contact pillars, the spacers contacting spacers of adjacent bitline contact pillars, the plurality of bitline contact pillars extending across a memory stack including a dielectric material and an active region, and selectively epitaxially growing a doped layer on the memory stack, the doped layer dopant being 1×10 20 ~5×10 21 and selectively epitaxially growing a doped layer having a dopant having a concentration in the range of; depositing one or more of a mask layer, a bitline metal layer, and a barrier metal layer on the memory stack and etching to form bitlines on the memory stack that are aligned with the active areas and are substantially free of skirt defects.

[0007] So that the above-mentioned features of the present disclosure can be understood in detail, a more detailed description of the present disclosure briefly summarized above may be had with reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure may admit of other equally effective embodiments, and therefore, the accompanying drawings show only typical embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure. The embodiments described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference symbols indicate similar elements. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a DRAM device according to the prior art; [Diagram 2] 1 is a top view of a DRAM device according to the prior art; [Diagram 3] 1 is a cross-sectional view of a DRAM device according to one or more embodiments. [Figure 4] 1 is a top view of a DRAM device according to one or more embodiments. [Diagram 5] 1 is a top view of a DRAM device according to one or more embodiments. [Figure 6A] 1 is a top view of a DRAM device according to one or more embodiments. [Figure 6B] 2 is a view along line 201 of the DRAM device of FIG. 6A according to one or more embodiments. [Figure 6C] 2 is a view along line 201 of the DRAM device of FIG. 6A according to one or more embodiments. [Figure 7A] 1 is a top view of a DRAM device according to one or more embodiments. [Figure 7B] 7B is a view along line 201 of the DRAM device of FIG. 7A according to one or more embodiments. [Figure 7C] 7B is a view along line 201 of the DRAM device of FIG. 7A according to one or more alternative embodiments. [Figure 8A]1 is a top view of a DRAM device according to one or more embodiments. [Figure 8B] 8B is a view along line 201 of the DRAM device of FIG. 8A according to one or more embodiments. [Figure 8C] 8B is a view along line 201 of the DRAM device of FIG. 8A according to one or more alternative embodiments. [Figure 9] FIG. 1 is a process flow diagram of a method for forming a device according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Before describing certain example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0010] As used herein and in the appended claims, the term "substrate" refers to a surface or a portion of a surface on which a process acts. Also, as will be understood by those skilled in the art, unless otherwise clearly indicated in the context, a reference to a substrate may refer to only a portion of the substrate. Furthermore, a reference to depositing on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0011] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed in a manufacturing process. For example, substrate surfaces on which processing can be performed include silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may undergo pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to direct film processing on the surface of the substrate itself, in this disclosure, any of the disclosed film processing steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as indicated by the context. Thus, for example, if a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0012] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores data bits by storing a packet of charge (i.e., a binary one) or no charge (i.e., a binary zero) on a capacitor. Charge is gated onto the capacitor through an access transistor, and sensed by noting the voltage perturbation caused by turning on the same transistor to dump the charge packet onto the interconnect line at the transistor output. Thus, a single DRAM cell is made of one transistor and one capacitor.

[0013] A DRAM device having a self-aligned bit line contact without skirt defects and a method for forming the self-aligned bit line contact are provided. One or more embodiments of the present disclosure advantageously address the problem of misalignment and skirt defects of polysilicon bands despite the need to shrink critical dimensions. In some embodiments, the resistance of the bit line contact is reduced by providing self-alignment without skirt defects of polysilicon bands.

[0014] Some embodiments of the present disclosure advantageously provide a method using epitaxial growth of a doped layer to form a self-aligned bit line after forming a spacer around the bit line contact pillar. One or more embodiments of the present disclosure generally provide a structure including one or more low resistance features formed from a thin film refractory metal (e.g., tungsten) that can be implemented in a bit line structure and / or gate stack. Some embodiments include a method for forming a self-aligned bit line. As an example, a bit line structure formed according to an embodiment of the present disclosure can be a memory type semiconductor device such as a DRAM type integrated circuit.

[0015] FIG. 1 shows a cross-sectional view of a prior art memory device 100. FIG. 2 shows a top view of a prior art memory device 200. As will be appreciated by those skilled in the art, the film stacks shown in the figures are an exemplary portion (bitline portion) of a memory device. With reference to FIGS. 1 and 2, a prior art DRAM device 100 includes a memory stack 101 including a dielectric material 102 and an active area 120. A plurality of bitline contact pillars 115 extend across the memory stack 101. The bitline contact pillars 115 include a silicon nitride layer 118 and a polysilicon layer 110. During processing to form the bitlines 124, skirt defects 114 are formed, and the bitlines 124 do not align with the active area 120. There is a misalignment 116 between the bottoms of the bitlines 124 and the active area 120. As shown in FIG. 2, there is an open area 112 between adjacent bitline contact pillars 115. Without intending to be bound by theory, it is believed that the skirt defect 114 results in increased resistance and reduced drive current.

[0016] Thus, in one or more embodiments, a device 150 is provided that is substantially free of skirt defects. As used herein, the term "substantially free" means that there are less than about 5% skirt defects on the bottom of the bitline contacts, including less than about 4%, less than about 3%, less than about 2%, less than about 1%, and less than about 0.5%. In some embodiments, there are no skirt defects.

[0017] In one or more embodiments, the bitlines 155 are self-aligned with the active areas 170, so that there is substantially no misalignment between the bottoms of the bitlines 155 and the active areas.

[0018] Referring to FIG. 3, the DRAM device 150 of one or more embodiments includes a memory stack 151 including a dielectric material 152 and an active region 170. The dielectric material 152 may include any suitable dielectric material known to one of ordinary skill in the art. As used herein, the term "dielectric material" refers to a material that is an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material 152 includes a low-k dielectric. In one or more embodiments, the dielectric material 152 includes one or more of an oxide, a carbon-doped oxide, silicon dioxide (SiO2), a porous silicon dioxide (SiO2), a silicon dioxide (SiO2), a silicon nitride (SiN), a silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH). In one or more embodiments, the dielectric material includes, but is not limited to, furnace, CVD, PVD, ALD, and spin-on-coat (SoC) deposited films. In one or more embodiments, the dielectric material may undergo in situ or ex situ pre-treatment and post-treatment processes to dope, pour, inject, heat, freeze, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the surface or bulk of the dielectric. In addition to direct film processing on the surface of the dielectric material itself, in one or more embodiments, any of the disclosed film processing steps may be performed on an underlayer formed on the dielectric material, as disclosed in more detail below, and the term "dielectric surface" is intended to include such underlayers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a dielectric surface, the exposed surface of the newly deposited film / layer becomes the dielectric surface. In one or more specific embodiments, the low-k dielectric may be one or more silicon oxides (SiO x ), silicon nitride (SiN), and silicon carbonitride (SiCN).

[0019] As used herein, the term "active region" refers to a layer of material in which a channel, a bit line, a word line, or a capacitor can be made. In one or more embodiments, the active region 170 includes one or more of silicon or doped silicon. For example, in one or more embodiments, the channel material is selected from one or more of Si, molybdenum sulfide (MoS2), or IGZO (In-Ga-Zn-based oxide), and replaces the cavity after the active region material is structured.

[0020] In one or more embodiments, a plurality of bitlines 155 extend across the memory stack 151. As used herein, the term "bitline" refers to a layer of material that is an electrical conductor. In one or more embodiments, the bitlines include, but are not limited to, grown silicon. In one or more embodiments, the bitlines may undergo in situ or ex situ pre- and post-treatment processes to melt, freeze, heat, microwave heat, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure, and / or bake the bulk or surface of the bitlines. In one or more embodiments, forming the bitlines 155 includes depositing one or more of a mask layer 164, a bitline metal layer 158, and a barrier metal layer 156 on the memory stack 151 and etching to form the bitlines 155.

[0021] In one or more embodiments, the mask layer may comprise any suitable material known to one of ordinary skill in the art. In some embodiments, the mask layer may comprise any suitable material such as silicon nitride (SiN), silicon oxide (SiO x ), and carbon (C).

[0022] In one or more embodiments, the bitline metal layer 158 may include any suitable metal known to one of ordinary skill in the art. In some embodiments, the bitline metal layer 158 may include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), or platinum (Pt). In particular embodiments, the bitline metal layer includes one or more of tungsten (W), molybdenum (Mo), and ruthenium (Ru).

[0023] The thickness of bitline metal layer 158 can vary. In some embodiments, bitline metal layer 158 has a thickness in the range of about 100 Å to about 300 Å, or in the range of about 120 Å to about 250 Å, or in the range of about 140 Å to about 200 Å, or in the range of about 160 Å to about 180 Å.

[0024] The bitline metal layer 158 may be deposited by any suitable technique known to those of skill in the art. In some embodiments, the bitline metal layer 158 is deposited by one or more of chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0025] In one or more embodiments, the barrier metal layer 156 may include any suitable metal known to those of skill in the art. In some embodiments, the barrier metal layer 156 (also referred to as a conductive layer) overlies the polycrystalline silicon layer 160. The barrier metal layer 156 can be any suitable conductive material. In some embodiments, the barrier metal layer 156 includes one or more of titanium (Ti), tantalum (Ta), titanium silicide (TiSi), or tantalum silicide (TaSi). In some embodiments, the barrier metal layer 156 includes titanium. In some embodiments, the barrier metal layer 156 consists essentially of titanium. In some embodiments, the barrier metal layer 156 includes or consists essentially of tantalum. In some embodiments, the barrier metal layer 156 includes or consists essentially of titanium silicide. In some embodiments, the barrier metal layer 156 includes or consists essentially of tantalum silicide. As used in this manner, the term "consisting essentially of" means that the subject film contains, on an atomic basis, about 95%, 98%, 99%, or 99.9% or more of the stated element or composition. For example, a barrier metal layer 156 consisting essentially of titanium is deposited with a film that is about 95%, 98%, 99%, or 99.5% or more titanium. In one or more embodiments, the barrier metal layer 156 includes one or more of titanium (Ti), tantalum (Ta), and tungsten (W).

[0026] A mask layer 164 is formed on the bitline metal layer 158. The mask layer 164 may be deposited by any suitable technique known to those of skill in the art. In some embodiments, the mask layer 164 is deposited by one or more of chemical vapor deposition or atomic layer deposition.

[0027] In some embodiments, mask layer 164 includes one or more of silicon nitride, silicon carbonitride, or silicon carbide. In some embodiments, mask layer 164 consists essentially of silicon nitride. In some embodiments, mask layer 164 consists essentially of silicon carbonitride. In some embodiments, mask layer 164 consists essentially of silicon carbide.

[0028] The thickness of the mask layer 164 can vary. In some embodiments, the mask layer 164 has a thickness in the range of about 30 Å to about 50 Å.

[0029] The deposition temperature of mask layer 164 can be controlled, for example, to maintain the thermal budget of the device being formed. In some embodiments, mask layer 164 is formed at a temperature of about 500° C. or less, or about 450° C. or less, or about 400° C. or less, or about 350° C. or less, or about 300° C. or less. In some embodiments, mask layer 164 is formed at a temperature in the range of about 350° C. to about 550° C., or in the range of about 400° C. to about 500° C.

[0030] 3, the bitline 155 includes a silicon nitride layer 158 and a polysilicon layer 160. During the process for forming the bitline 155, no skirt defects are formed and the bitline 155 is self-aligned with the active area 170. There is no misalignment between the bottom of the bitline 155 and the active area 170.

[0031] 4 and 9, formation of memory device 150 includes forming bitline contact pillars 155 on a memory stack during operation 310. Bitline contact pillars 155 include one or more of a polycrystalline silicon (poly-Si) layer 160 and a silicon nitride layer 158. Gaps 157 exist between adjacent bitline contact pillars 155 revealing voids 162.

[0032] 5 and 9, during operation 312, spacers 180 are formed around each of the bitline contact pillars 155. In one or more embodiments, the spacers 180 are in contact with the spacers 180 of adjacent bitline contact pillars 155. Thus, in one or more embodiments, the spacers 180 eliminate the gaps 157 between adjacent bitline contact pillars 155.

[0033] Spacers 180 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, spacers 180 include one or more of silicon nitride (SiN) and silicon carbonitride (SiCN). In a particular embodiment, spacers 180 include silicon nitride (SiN).

[0034] 6A, 6B, 6C, and 9, during operation 330, doped layer 210 is epitaxially grown on the memory stack. Doped layer 210 is grown around bitline contact pillar 155. In some embodiments, doped layer 210 is partially grown so as not to be flush with the top surface of bitline contact pillar 155 and the top surface of spacer 180, as shown in FIG. 6B. With reference to FIG. 6B, in some embodiments, doped layer 210 is below the top surface of bitline contact pillar 155 leaving opening 211 on the top surface of bitline contact pillar 155. In other embodiments, doped layer 210 is completely grown so as to be flush with the top surface of bitline contact pillar 155 and the top surface of spacer 180, as shown in FIG. 6B.

[0035] In one or more embodiments, the doped layer 210 may include any suitable material known to one of ordinary skill in the art. In one or more embodiments, the doped layer includes selective silicon doped with a dopant. The dopant may include any suitable dopant known to one of ordinary skill in the art. In one or more embodiments, the dopant is selected from the group consisting of phosphorus (P), arsenic (As), and combinations thereof.

[0036] In some embodiments, the doped layer is 1×10 20 ~5×10 21 The substrate is doped with a dopant having a concentration in the range of 0.1 to 100 μm.

[0037] 7A, 7B, 7C, and 9, during operation 340, bitlines are formed by depositing one or more of a mask layer, a bitline metal layer 158, and a barrier metal layer 156 on the memory stack. As shown in FIG. 7B, in an embodiment in which the doped layer is deposited below the top surface of the bitline contact pillar 155, the bitline metal layer 158 may be deposited such that it fills the opening 211. With reference to FIG. 7C, in an embodiment in which the doped layer is coplanar with the top surface of the bitline contact pillar 155, the bitline metal layer 158 is deposited on the top surface of the doped layer 210 and the top surface of the bitline contact pillar 155.

[0038] 8A, 8B, 8C, and 9, during operation 350, the memory stack is etched to form bitlines 214. As shown in FIG. 8B, in embodiments where the doped layer is deposited below the top surface of the bitline contact pillars 155, the bitlines 214 are formed such that the bitlines fill the openings 211. With reference to FIG. 8C, in embodiments where the doped layer is coplanar with the top surface of the bitline contact pillars 155, the bitlines 214 are formed on the top surface of the doped layer 210, with the bottom surface of the bitlines 214 being substantially coplanar with the top surface of the spacers 180.

[0039] Further embodiments of the present disclosure are directed to methods of forming a memory device. As will be appreciated by those skilled in the art, the methods described may form a portion of a memory device (e.g., a bit line) that may be part of a complete memory device. Figure 9 illustrates a process flow of an exemplary method 300 for forming a memory device.

[0040] In the context of describing the materials and methods discussed herein (particularly in the context of the claims below), the use of the terms "a," "an," and "the" and similar referents should be construed to encompass both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each separate value within the range, and each separate value is incorporated herein as if it were individually set forth herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is intended only to better elucidate the materials and methods, and does not impose limitations on the scope of the invention unless otherwise claimed. No language in this specification should be construed as indicating any unclaimed element as essential to the practice of the disclosed materials and methods.

[0041] Throughout this specification, reference to "one embodiment," "a particular embodiment," "one or more embodiments," or "one embodiment" means that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in one embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0042] Although the present disclosure has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is intended to cover modifications and variations that are within the scope of the appended claims, and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a plurality of bitline contact pillars extending across a memory stack, the memory stack including a dielectric material and an active region; forming a spacer around each of the bitline contact pillars, the spacer in contact with the spacer of an adjacent bitline contact pillar; epitaxially growing a doped layer on the active region; forming bit lines on the memory stacks, the bit lines aligned with the active areas; epitaxially growing the doped layer on the active region includes growing the doped layer partially around the bitline contact pillar below a top surface of the bitline contact pillar and a top surface of the spacer; The method, wherein forming the bitlines includes filling openings on the top surfaces of the bitline contact pillars with one or more of a mask layer, a bitline metal layer, and a barrier metal layer.

2. A method for forming a semiconductor device, comprising: forming a plurality of bitline contact pillars extending across a memory stack, the memory stack including a dielectric material and an active region; forming a spacer around each of the bitline contact pillars, the spacer in contact with the spacer of an adjacent bitline contact pillar; epitaxially growing a doped layer on the active region; forming bit lines on the memory stacks, the bit lines aligned with the active areas; epitaxially growing the doped layer on the active region includes growing the doped layer completely around the bitline contact pillar and flush with a top surface of the bitline contact pillar and a top surface of the spacer; The method, wherein forming the bitlines includes depositing one or more of a mask layer, a bitline metal layer, and a barrier metal layer on the top surface of the doped layer and on the top surface of the bitline contact pillar.

3. The dielectric material is silicon oxide (SiO ｘ 3. The method of claim 1 or 2, wherein the low-k dielectric is selected from the group consisting of silicon nitride (SiN), silicon carbonitride (SiCN), and combinations thereof.

4. The method of claim 1 or 2, wherein the plurality of bitline contact pillars comprises one or more of a polysilicon layer and a silicon nitride layer.

5. The method of claim 1 or 2, wherein forming the bitlines further comprises etching to form the bitlines.

6. The mask layer is made of silicon nitride (SiN), silicon oxide (SiO ｘ 6. The method of claim 5, further comprising one or more of:

7. 6. The method of claim 5, wherein the bitline metal layer comprises one or more of tungsten (W), molybdenum (Mo), and ruthenium (Ru).

8. 6. The method of claim 5, wherein the barrier metal layer comprises one or more of titanium (Ti), tantalum (Ta), and tungsten (W).

9. The method of claim 1 or 2, wherein the spacers comprise one or more of silicon nitride (SiN) and silicon carbonitride (SiCN).

10. 3. The method of claim 1 or 2, wherein the doped layer comprises selective silicon doped with a dopant selected from the group consisting of phosphorus (P), arsenic (As), and combinations thereof.

11. The dopant is 1×10 ２０ ~5×10 ２１ The method of claim 10 having a concentration in the range of

12. The method of claim 1 or 2, wherein the bitlines are substantially free of skirt defects.

13. 1. A method of forming a semiconductor device, comprising: forming spacers around a plurality of bitline contact pillars, the spacers contacting the spacers of adjacent bitline contact pillars, the plurality of bitline contact pillars extending across a memory stack including a dielectric material and an active region; selectively epitaxially growing a doped layer on the memory stack, the doped layer having a thickness of 1×10 ２０ ~5×10 ２１ selectively epitaxially growing a doped layer doped with a dopant having a concentration in the range of depositing one or more of a mask layer, a bitline metal layer, and a barrier metal layer over the memory stack and etching to form bitlines on the memory stack that are aligned with the active areas and are substantially free of skirt defects; Including, Selectively epitaxially growing the doped layer on the memory stack includes growing the doped layer partially around the bitline contact pillar below a top surface of the bitline contact pillar and a top surface of the spacer; The method, wherein depositing one or more of the mask layer, the bitline metal layer, and the barrier metal layer on the memory stack and etching to form bitlines on the memory stack includes filling openings on the top surfaces of the bitline contact pillars with one or more of the mask layer, the bitline metal layer, and the barrier metal layer.

14. A method for forming a semiconductor device, comprising the steps of: forming spacers around a plurality of bitline contact pillars, the spacers contacting the spacers of adjacent bitline contact pillars, the plurality of bitline contact pillars extending across a memory stack including a dielectric material and an active region; selectively epitaxially growing a doped layer on the memory stack, the doped layer being doped with a dopant having a concentration in the range of 1×10 20 to 5×10 21 ; depositing one or more of a mask layer, a bitline metal layer, and a barrier metal layer over the memory stack and etching to form bitlines on the memory stack that are aligned with the active areas and are substantially free of skirt defects; Selectively epitaxially growing the doped layer on the memory stack includes growing the doped layer completely around the bitline contact pillar and flush with a top surface of the bitline contact pillar and a top surface of the spacer; The method, wherein depositing one or more of the mask layer, the bitline metal layer, and the barrier metal layer on the memory stack and etching to form bitlines on the memory stack includes depositing one or more of the mask layer, the bitline metal layer, and the barrier metal layer on the top surface of the doped layer and on the top surface of the bitline contact pillar.

15. The dielectric material is silicon oxide (SiO ｘ 15. The method of claim 13 or 14, comprising a low-k dielectric selected from the group consisting of silicon nitride (SiN), silicon carbonitride (SiCN), and combinations thereof.

16. 15. The method of claim 13 or 14, wherein the bitline metal layer comprises one or more of tungsten (W), molybdenum (Mo), and ruthenium (Ru).

17. 15. The method of claim 13 or 14, wherein the barrier metal layer comprises one or more of titanium (Ti), tantalum (Ta), and tungsten (W).

18. 15. The method of claim 13 or 14, wherein the doped layer comprises selective silicon and the dopant is selected from the group consisting of phosphorus (P), arsenic (As), and combinations thereof.

Images