Semiconductor materials, manufacturing methods and semiconductor devices

Abstract

A semiconductor material, a manufacturing method and a semiconductor device are disclosed, which include a first substrate, a first oxide layer and an upper silicon layer stacked together, the first oxide layer being located on the substrate, and the upper silicon layer being located on a side of the first oxide layer away from the first substrate, where the first oxide layer has an average thickness H1 along a first direction, and the upper silicon layer has an average thickness H2 along the first direction, satisfying 0.01≦H2 / H1≦100, and 0.01 μm≦H1≦5 μm, 0.01 μm≦H2≦0.5 μm. The thickness of the upper silicon layer of the semiconductor material is less than 500 nm, and through a selective polishing process, the deviation of the thickness variation of the upper silicon layer is less than ±10 nm, which is beneficial to improving the thickness uniformity of the upper silicon layer on the surface of the semiconductor material.

Description

[Technical field]

[0001] This application claims priority based on a Chinese patent application filed with the China Patent Office on December 27, 2022, bearing application number 202211652486.8 and entitled "Semiconductor Material, Manufacturing Method and Semiconductor Device", the entire contents of which are incorporated herein by reference.

[0002] The present application is in the field of semiconductor materials, and more particularly, to semiconductor materials, manufacturing methods and semiconductor devices. [Background technology]

[0003] Silicon-on-insulator substrates as engineering substrate wafers are semiconductor materials obtained by introducing a uniformly distributed oxide layer on the basis of a conventional wafer, and this semiconductor material has a sandwich structure including a stacked top silicon layer, a buried oxide layer, and a supporting substrate. The thickness of the top silicon layer of the semiconductor material used in partially depleted devices directly affects the electrical properties of the device, such as withstand voltage and on-resistance. Therefore, how to fabricate a top silicon layer with a thinner thickness and uniform thickness change in semiconductor materials is an urgent problem that needs to be solved. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a semiconductor material, a manufacturing method and a semiconductor device that aims to solve the problem of device performance degradation caused by thick top silicon layers and non-uniform thickness variations in semiconductor materials. [Means for solving the problem]

[0005] According to the first aspect, the semiconductor material of the present application includes a stacked first substrate, a first oxide layer, and an upper silicon layer. The first oxide layer is located on the substrate, and the upper silicon layer is located on the side of the first oxide layer away from the first substrate. Here, the first oxide layer has an average thickness H1 along a first direction, and the upper silicon layer has an average thickness H2 along the first direction. 0.01 ≦ H2 / H1 ≦ 100, and 0.01 μm ≦ H1 ≦ 5 μm, 0.01 μm ≦ H2 ≦ 0.5 μm are satisfied.

[0006] In some embodiments, the upper silicon layer includes a first surface and a second surface that are spaced apart from each other along the first direction. The first oxide layer is provided on the second surface, and between the first surface and the second surface, there is a minimum thickness H min and a maximum thickness H max existing, 0.1% ≦ (H max - H min ) / (H max + H min ) ≦ 5%, and H max > H2, H min < H2 are satisfied. In some embodiments, the upper silicon layer 0.05 μm ≦ H max ≦ 0.5 μm, and / or 0.03 μm ≦ H min ≦ 0.3 μm are satisfied.

[0007] According to the second aspect, the present application further provides a method for manufacturing a semiconductor material including the following steps. A first substrate and a second substrate are respectively provided, and a first oxide layer is formed on the first substrate and / or the second substrate. Oxygen ion implantation is performed on the second substrate so that the second substrate includes a first separation layer, a second oxide layer, and a second separation layer stacked along a first direction. The second substrate is bonded to the first substrate so that the first oxide layer is located between the first substrate and the second substrate. The second isolation layer, the second oxide layer, and a portion of the first isolation layer are thinned to form an upper silicon layer on the first oxide layer to produce a semiconductor material.

[0008] In some embodiments, when the first oxide layer is located on the second substrate, the step of implanting oxygen ions into the second substrate when forming the first oxide layer on the second substrate includes implanting oxygen ions from a side of the second substrate on which the first oxide layer is located, and the implanted oxygen ions pass through the first oxide layer into the second substrate.

[0009] In some embodiments, thinning the second isolation layer, the second oxide layer, and a portion of the first isolation layer includes: subjecting the second separation layer to a first chemical mechanical polishing to expose the second oxide layer; subjecting the second oxide layer to a second chemical mechanical polishing to expose the first isolation layer; and performing a third chemical mechanical polishing on a portion of the first isolation layer to form the top silicon layer.

[0010] In some embodiments, the first chemical mechanical polishing step uses an alkaline slurry having a pH value of 11 to 13; and / or The second chemical mechanical polishing uses an acidic slurry having a pH value of 3 to 5, and / or In the third chemical mechanical polishing, an alkaline slurry having a pH value of 10 to 12 is used.

[0011] In some embodiments, the first chemical mechanical polishing has a polishing temperature of 20 to 40° C. and a polishing removal rate of 0.5 μm / min to 1 μm / min; and / or The polishing temperature of the second chemical mechanical polishing is 20 to 40° C., and the polishing removal rate is 0.1 μm / min to 0.6 μm / min, and / or The polishing temperature in the third chemical mechanical polishing is 20 to 40° C., and the polishing removal rate is 60 nm / min to 120 nm / min.

[0012] In some embodiments, the method further includes mechanically grinding the second separation layer prior to the step of performing a first chemical mechanical polishing on the second separation layer to expose the second oxide layer, and a remaining thickness of the second separation layer after the mechanical grinding is in the range of 4 to 10 μm.

[0013] In some embodiments, the method further includes annealing the second substrate and the first substrate before mechanically grinding the second separation layer, the annealing temperature being 1320-1380°C and the annealing time being 6-8h.

[0014] In some embodiments, the oxygen ion implantation has an oxygen ion implantation energy of 100 kev to 500 kev and an implantation dose of 7E16 cm -2 ~2E19cm -2 The oxygen ion implantation angle is 6-8°, the ion implantation temperature is ≧300°C, and the oxygen ion beam current is ≧10mA.

[0015] In some embodiments, the first oxide layer has an average thickness H1 along a first direction, and the top silicon layer has an average thickness H2 along the first direction; The relationship 0.01≦H2 / H1≦100, 0.01 μm≦H1≦5 μm, and 0.01 μm≦H2≦0.5 μm are satisfied.

[0016] In some embodiments, the second oxide layer has an average thickness H3 along a first direction, a distance between the second oxide layer and the first oxide layer in the first direction is H, and a thinning dimension of the first separation layer in the first direction is H0; H2+H0≦H, and 100 nm≦H3≦400 nm and 50 nm≦H0≦300 nm are satisfied.

[0017] In some embodiments, the material of the first and second isolation layers is silicon and the material of the second oxide layer is silicon dioxide.

[0018] According to a third aspect, the present application further provides a semiconductor device, the semiconductor device comprising the semiconductor material described above, or the semiconductor device comprising a semiconductor material obtained by the manufacturing method described above. Effect of the Invention

[0019] Compared with the prior art, the semiconductor material of the present application includes a first substrate, a first oxide layer, and an upper silicon layer, which are stacked, the first oxide layer is located on the substrate, and the upper silicon layer is located on the side of the first oxide layer away from the first substrate, where the first oxide layer has an average thickness H1 along a first direction, and the upper silicon layer has an average thickness H2 along the first direction, and satisfies 0.01≦H2 / H1≦100, and 0.01 μm≦H1≦5 μm, 0.01 μm≦H2≦0.5 μm. The thickness of the upper silicon layer of the semiconductor material of the present application is less than 500 nm, and through the selective polishing process, the deviation of the thickness variation of the upper silicon layer is less than ±10 nm, which is beneficial to improving the thickness uniformity of the upper silicon layer on the surface of the semiconductor material.

[0020] The method for manufacturing a semiconductor material of the present application includes the following steps: providing a first substrate and a second substrate, respectively; forming a first oxide layer on the first substrate and / or the second substrate; performing oxygen ion implantation on the second substrate; making the second substrate include a first isolation layer, a second oxide layer, and a second isolation layer stacked along a first direction; bonding the second substrate to the first substrate such that the first oxide layer is located between the first substrate and the second substrate; thinning a portion of the second isolation layer, the second oxide layer, and the first isolation layer to form an upper silicon layer on the first oxide layer, thereby manufacturing a semiconductor material. In the manufacturing method of the present application, by carrying out at least three polishing and thinning processes on the second isolation layer, the second oxide layer and the first isolation layer, an automatic stopping process of polishing due to the difference in the materials of each layer is realized, and the process of polishing errors can be greatly shortened; and the second oxide layer formed by oxygen ion implantation completely eliminates the errors caused by the first and second polishing, which not only improves the manufacturing efficiency of the process, but also makes it possible to manufacture the upper silicon layer by only considering the polishing of the first isolation layer, which greatly improves the thickness uniformity of the upper silicon layer, and ensures the manufacture of a semiconductor material with an upper silicon layer thickness of less than 500 nm. [Brief description of the drawings]

[0021] [Figure 1] 1 is a schematic structural diagram of a semiconductor material provided in an embodiment of the present application. [Diagram 2] FIG. 2 is a structural schematic diagram of a first substrate provided in an embodiment of the present application. [Diagram 3] FIG. 2 is a structural schematic diagram of a second substrate provided in an embodiment of the present application. [Figure 4] FIG. 2 is a structural schematic diagram of a second substrate after oxygen ion implantation provided in an embodiment of the present application. [Diagram 5] FIG. 2 is a structural schematic diagram of bonding a first substrate and a second substrate provided in an embodiment of the present application; [Figure 6] FIG. 2 is a structural schematic diagram of a first substrate after mechanical grinding provided in an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram of a structure after a first chemical mechanical polishing provided in an embodiment of the present application. [Figure 8] FIG. 2 is a schematic diagram of a structure after a second chemical mechanical polishing provided in an embodiment of the present application. [Figure 9] FIG. 2 is a partially enlarged view of part A in FIG. [Figure 10] FIG. 5 is a partial enlarged view of part B in FIG. [Figure 11] FIG. 9 is a partial enlarged view of part C in FIG. 8. [Figure 12] FIG. 2 is a structural schematic diagram of another first substrate provided in an embodiment of the present application. [Figure 13] FIG. 2 is a structural schematic diagram of another second substrate provided in an embodiment of the present application. [Figure 14] FIG. 2 is another structural schematic diagram of a second substrate after oxygen ion implantation provided in an embodiment of the present application; [Explanation of symbols]

[0022] 101 - first substrate, 102 - first oxide layer, 103 - top silicon layer, 104 - second substrate, 1031 - first surface, 1032 - second surface, 1041 - first separation layer, 1042 - second oxide layer, 1043 - second separation layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The present application provides a semiconductor material, a manufacturing method and a semiconductor device, and in order to make the objectives, technical solutions and effects of the present application clearer, the present application will be described in more detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application, and are not used to limit the present application.

[0024] Silicon on insulator substrate as engineering substrate wafer is based on traditional polished wafer, and by unique technical means, a uniformly distributed oxide layer called buried oxide layer is introduced, which becomes a semiconductor material with a sandwich structure of silicon layer / buried oxide layer / support substrate of the upper device. Silicon-on-insulator substrate has advantages that bulk silicon does not have, such as realizing complete physical isolation of components in integrated circuits, completely eliminating the parasitic latch-up effect of bulk silicon CMOS circuits, and has obvious advantages in power consumption, operating speed, radiation resistance and device integration, so it has attracted a lot of attention. In recent years, with the continuous progress of process technology, the production of silicon-on-insulator substrates has been rapidly developed. Silicon-on-insulator substrate materials can be divided into two categories according to the thickness of the silicon layer of the upper device: thin silicon-on-insulator (top silicon is usually less than 1 μm) and thick silicon-on-insulator (top silicon is usually larger than 1 μm), and are widely used in products such as RF front-end devices, power devices, image processors, and microelectromechanical device systems.

[0025] At present, the manufacturing technology of silicon-on-insulator substrates can be divided into oxygen injection isolation technology, direct bond thinning technology, and intelligent stripping technology by hydrogen ion implantation according to the product application requirements and material index parameter requirements such as the thickness of the top silicon device layer and the thickness of the buried oxide layer. Although the thickness of the top silicon and the thickness of the buried oxide layer of the wafer produced by oxygen injection isolation technology are very uniform, due to the limitations of the oxygen ion implantation process, the thickness of the silicon layer of the device cannot exceed 300nm, and the thickness of the buried oxide layer cannot exceed 240nm. In addition, discontinuous silicon island defects are often found in the buried oxide layer, which makes the breakdown voltage of the buried oxide layer much lower than that of traditional thermal oxidation, limiting the product application and technological development of oxygen injection isolation technology. Intelligent stripping technology has the characteristics of mature process, good uniformity of the device layer, and low process cost, and has become the mainstream manufacturing technology of insulator silicon substrate materials, but due to strict technical patent protection, only individual manufacturers are allowed to use this technology in production. Although the direct bonding thinning technology has the characteristics of a simple process and low cost, it is difficult to precisely control the thickness uniformity of the silicon layer of the device through the thinning process.

[0026] The applicant found that in the existing polishing process, due to the polishing sequence, thickness differences occur between the center and edge of the polished surface, and as the polishing depth continues to increase and the thickness of the upper silicon layer 103 decreases, the difference in thickness non-uniformity becomes more and more obvious, so that if the polishing process is directly used to manufacture the upper silicon layer 103, a thickness uniformity problem will inevitably occur. Therefore, how to reduce the thickness non-uniformity of the upper silicon layer 103 while making the upper silicon layer 103 thinner has become an urgent problem to be solved.

[0027] Referring to FIG. 1, the semiconductor material provided in the present application includes a stacked first substrate 101, a first oxide layer 102, and an upper silicon layer 103. The first oxide layer 102 is located on the substrate, and the upper silicon layer 103 is located on the side away from the first substrate 101 of the first oxide layer 102. Here, the first oxide layer 102 has an average thickness H1 along a first direction, and the upper silicon layer 103 has an average thickness H2 along the first direction, satisfying 0.01 ≦ H2 / H1 ≦ 100, and 0.01 μm ≦ H1 ≦ 5 μm, 0.01 μm ≦ H2 ≦ 0.5 μm.

[0028] In some embodiments, the thickness of the upper silicon layer 103 of the semiconductor material of the present application is less than 500 nm. Through the selective polishing process, the deviation of the thickness variation of the upper silicon layer 103 is less than ±10 nm, which is beneficial to improving the uniformity of the thickness of the upper silicon layer 103 on the surface of the semiconductor material. Here, the first direction specifically refers to the direction indicated by the arrow in FIG. 1. It can be understood that the first direction respectively refers to the thickness direction of the first oxide layer 102 and the upper silicon layer 103, and the average thickness can be understood as the calculated value of (maximum thickness + minimum thickness) / 2.

[0029] In some embodiments, further referring to FIG. 9, the upper silicon layer 103 includes a first surface 1031 and a second surface 1032 that are arranged apart from each other along the first direction. The first oxide layer 102 is provided on the second surface 1032. The second surface 1032 is connected to the first oxide layer 102. Between the first surface 1031 and the second surface 1032, there is a minimum thickness H min and a maximum thickness H max existing, satisfying 0.1% ≦ (H max - H min ) / (H max + H min ) ≦ 5%, and H max > H2, H min < H2. Here, (H max - H min ) / (H max + H min) is used to represent the uniformity of the upper silicon layer 103. The first direction specifically refers to the direction indicated by the arrow in FIG. 1 , and it can be understood that the first direction refers to the thickness direction of the upper silicon layer 103, respectively.

[0030] In some embodiments, the top silicon layer 103 further comprises a thickness of 0.05 μm≦H max ≦0.5μm, 0.03μm≦H min Meets ≦0.3μm. max may be any of 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, or in a range between any two values; min It can be understood that the value of H may be any of 0.03 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, or a range between any two values. max and H min When each of the above ranges meets the requirements, the uniformity precision of the thickness of the upper silicon layer 103 can be ensured, and the quality of the semiconductor material can be improved.

[0031] In some embodiments, the present application further discloses a method for producing a semiconductor material, the method including: A first substrate 101 and a second substrate 104 are provided, respectively; forming a first oxide layer 102 on the first substrate 101 and / or the second substrate 104; Implanting oxygen ions into the second substrate 104 so that the second substrate 104 includes a first separation layer 1041, a second oxide layer 1042, and a second separation layer 1043 stacked along a first direction; bonding the second substrate 104 to the first substrate 101 such that the first oxide layer 102 is located between the first substrate 101 and the second substrate 104; The second isolation layer 1043, the second oxide layer 1042 and a portion of the first isolation layer 1041 are thinned to form an upper silicon layer 103 on the first oxide layer 102 to produce a semiconductor material.

[0032] In some embodiments, when forming the first oxide layer 102 on the second substrate 104, the step of performing oxygen ion implantation on the second substrate 104 includes performing oxygen ion implantation from the side of the second substrate 104 on which the first oxide layer 102 is provided, and the implanted oxygen ions enter the second substrate 104 through the first oxide layer 102. When oxygen ion implantation is performed on the second substrate 104 after the first oxide layer 102 is formed on the second substrate 104, the formed first oxide layer 102 can mitigate the effect of the oxygen ions on the silicon crystal lattice after implantation into the substrate, and reduce damage to the second substrate 104 caused by the oxygen ion implantation.

[0033] In some embodiments, the step of thinning the second isolation layer 1043, the second oxide layer 1042, and a portion of the first isolation layer 1041 further comprises: subjecting the second separation layer 1043 to a first chemical mechanical polishing to expose the second oxide layer 1042; performing a second chemical mechanical polishing on the second oxide layer 1042 to expose the first isolation layer 1041; A third chemical mechanical polishing is performed on a portion of the first isolation layer 1041 to form a top silicon layer 103 .

[0034] In some embodiments, the manufacturing method of the present application performs at least three polishing and thinning processes on the second isolation layer 1043, the second oxide layer 1042, and the first isolation layer 1041, thereby realizing an automatic stopping process of polishing due to the difference in materials of each layer, and greatly shortening the process of polishing errors; the second oxide layer 1042 formed by oxygen ion implantation completely eliminates the errors caused by the first and second polishings, not only improving the manufacturing efficiency of the process, but also only needing to consider the polishing of the first isolation layer 1041 in the manufacture of the upper silicon layer 103, thereby greatly improving the thickness uniformity of the upper silicon layer 103, and ensuring the manufacture of a semiconductor material with a thickness of the upper silicon layer 103 less than 500 nm.

[0035] In some embodiments, the first oxide layer 102 can be formed only on the first substrate 101, and oxygen ion implantation can be performed directly on the second substrate 104 to bond the first substrate 101 and the second substrate 104 together.

[0036] In some embodiments, the first oxide layer 102 may be formed simultaneously on the first substrate 101 and the second substrate 104, and when the second substrate 104 is bonded to the first substrate 101, the first oxide layer 102 on the first substrate 101 may bond with the first oxide layer 102 on the second substrate 102 to form a completed oxide structure layer.

[0037] It can be understood that the first oxide layer 102 can be a buried oxide layer of an SOI structure as a semiconductor material, and according to the requirements of different thicknesses of the buried oxide layer, the above-mentioned different formation methods of the first oxide layer 102 can be selected, and generally, in order to facilitate the injection of oxygen ions, the thickness of the first oxide layer 102 formed on the second substrate 104 is relatively thin, and when a thinner buried oxide layer is required, the first oxide layer 102 can only be formed on the second substrate 104 during the manufacturing process, but when a thicker buried oxide layer is required, the first oxide layer 102 can be formed on the first substrate 101 to make the thickness of the buried oxide layer thicker.

[0038] In some embodiments, to perform segment control of chemical mechanical polishing, the first chemical mechanical polishing uses an alkaline slurry with a pH value of 11 to 13, the second chemical mechanical polishing uses an acidic slurry with a pH value of 3 to 5, and the third chemical mechanical polishing uses an alkaline slurry with a pH value of 10 to 12. Chemical mechanical polishing (CMP) is a means of achieving global planarization, and is a technology that combines chemical and mechanical effects. The surface to be polished chemically reacts with the polishing slurry used, etc. to form a soft layer that can be relatively easily removed, and then the soft layer is removed by the abrasive in the polishing slurry and the mechanical action of the polishing pad, and the surface of the other layer is exposed again before the chemical reaction occurs, and the chemical action and the mechanical action are alternately repeated to complete the polishing and thinning of the work surface.

[0039] In some embodiments, in order to further control the processing accuracy of the chemical mechanical polishing, the polishing temperature of the first chemical mechanical polishing is 20 to 40°C, and the polishing removal rate is 0.5 μm / min to 1 μm / min, the polishing temperature of the second chemical mechanical polishing is 20 to 40°C, and the polishing removal rate is 0.1 μm / min to 0.6 μm / min, and the polishing temperature of the third chemical mechanical polishing is 20 to 40°C, and the polishing removal rate is 60 nm / min to 120 nm / min.

[0040] In some embodiments, the method further includes mechanically grinding the second separation layer 1043 before the step of performing a first chemical mechanical polishing on the second separation layer 1043 to expose the second oxide layer 1042, and the remaining thickness of the second separation layer 1043 after mechanical grinding is 4-10 μm. The process of directly using mechanical grinding is simpler and faster than chemical mechanical polishing, so that mechanical grinding can be performed first to improve manufacturing efficiency, and performing mechanical grinding first and then mechanical polishing will not affect the uniformity of the material surface.

[0041] In some embodiments, the method further includes performing an annealing treatment on the second substrate 104 and the first substrate 101 before mechanically grinding the second separation layer 1043, the annealing temperature being 1320-1380° C. and the annealing time being 6-8 h.

[0042] In some embodiments, oxygen ion implantation is performed from one side of the first oxide layer 102, and the process parameters of the ion implantation need to be set accurately to avoid the impact of the ion implantation on the quality of the second substrate 104. In the actual process, the implantation angle, implantation energy and implantation dose of the oxygen ions are controlled to ensure the quality of the product, and the oxygen ion implantation is performed by an ion implantation device, where the oxygen ion implantation energy is 100kev-500kev and the implantation dose is 7E16cm. -2 ~2E19cm -2 , the oxygen ion implantation angle is 6-8°, the ion implantation temperature is ≧300°C, and the oxygen ion beam current is ≧10mA. When the above process parameters are met, defects occurring in the second substrate 104 and the first oxide layer 102 can be reduced or even avoided while ensuring the quality of the second oxide layer 1042. Preferably, the oxygen ion implantation energy is 150-250keV, the implantation dose is 8E16cm. -2 ~1E19cm -2 The oxygen ion implantation angle is 6-8°, the ion implantation temperature is ≧500°C, and the oxygen ion beam current is ≧15mA. Through the appropriate process condition window, the effect of ion implantation can be minimized.

[0043] In some embodiments, a uniformly distributed ion implantation layer is generated by oxygen ion implantation, and the second oxide layer 1042 is formed during the annealing process. The second oxide layer 1042 is used as a barrier layer for chemical mechanical polishing, which can provide good control over the thickness and uniformity of the top silicon layer 103 before the final chemical mechanical polishing. Since the uniformity of the top silicon layer 103 is controlled by the oxygen ion implantation process, the uniformity of the top silicon layer 103 is very good, and the thickness of the second oxide layer 1042 can be freely adjusted according to different oxygen ion implantation processes.

[0044] 10 and 11, in some embodiments, the second oxide layer 1042 has an average thickness H3 along the first direction, the distance between the second oxide layer 1042 and the first oxide layer 102 in the first direction is H, the thinning dimension of the first separation layer 1041 in the first direction is H0, and further satisfies H2+H0≦H, and 100nm≦H3≦400nm, 50nm≦H0≦300nm. Here, the first direction specifically refers to the direction indicated by the arrow in FIG. 1, and it can be understood that the first direction refers to the thickness direction of the second oxide layer 1042, the first oxide layer 102, and the first separation layer 1041 respectively, and considering that there may be some errors in the actual polishing process, H2+H0≦H.

[0045] In some embodiments, the material of the first isolation layer 1041 and the second isolation layer 1043 is silicon, and the material of the second oxide layer 1042 is silicon dioxide.

[0046] In some embodiments, the present application further provides a semiconductor device, the semiconductor device comprising the semiconductor material described above, the semiconductor device comprising a silicon-on-insulator power device.

[0047] Example 1 2 to 9 show the manufacturing process of semiconductor materials. 2 and 3, a first substrate 101 and a second substrate 104 are provided, respectively, and a surface of the second substrate 104 is oxidized to form a first oxide layer 102. Here, the second substrate 104 uses a normal Czochralski single crystal MCZ or zone melt single crystal FZ substrate wafer, which is a perfect single crystal substrate wafer without natural grain defects, and the number of grains with a diameter of 0.12 μm does not exceed 10. The first oxide layer 102 is a thermal oxide layer formed by dry oxygen oxidation or wet oxygen oxidation, the thickness of the oxide layer is 10-200 nm, and the breakdown voltage performance is ≧9MV / cm. The first substrate 101 uses a normal Czochralski single crystal MCZ or zone melt single crystal FZ substrate wafer, which is a perfect single crystal substrate wafer without natural grain defects.

[0048] 4, oxygen ion implantation is performed on the second substrate 104 along one side of the first oxide layer 102, so that the second substrate 104 includes a first separation layer 1041, a second oxide layer 1042, and a second separation layer 1043 stacked along a first direction. Here, the material of the first oxide layer 102 and the second oxide layer 1042 is silicon oxide, the material of the first separation layer 1041 and the second separation layer 1043 is silicon, and in order to form a relatively continuous second oxide layer 1042, the oxygen ion implantation energy is 200keV, the oxygen ion beam current is 40-50mA, and the implantation amount is 4E17cm. -2 The oxygen ion implantation angle is 7°, and the ion implantation temperature is 500°C.

[0049] Referring to FIG. 5, the second substrate 104 is bonded to the first substrate 101 so that the first oxide layer 102 is connected to the first substrate 101, and then annealing is performed to improve the bonding strength and at the same time activate the oxygen ions in the first oxide layer 102 of the second substrate 104 to repair the damaged layer. The annealing temperature after bonding is 1340-1360°C, preferably 1350°C, and the annealing time is 7h.

[0050] Referring to FIG. 6, the second separation layer 1043 is thinned by mechanical grinding to reach a target thickness. In the mechanical grinding, first, primary grinding is performed with a coarse grinding wheel having a mesh number of 800 or less, and then secondary grinding is performed with a fine grinding wheel having a mesh number of 4000 or more. After mechanical grinding, the remaining thickness of the second separation layer 1043 is 4 to 10 μm.

[0051] 7, the second separation layer 1043 is subjected to a first chemical mechanical polishing to expose the second oxide layer 1042, and then an alkaline polishing slurry is used to polish down to the surface of the second oxide layer 1042, and then the polishing is automatically stopped, where an alkaline slurry with a pH value of 11-12 is used, the particle size of the slurry is less than 60 nm, the polishing temperature is 30° C., and the polishing removal rate is 0.7-0.8 μm / min. When polishing down to the second oxide layer 1042, the alkaline slurry only polishes away silicon, but does not polish away silicon oxide, so the polishing automatically stops at the surface of the second oxide layer 1042.

[0052] Referring to FIG. 8, the second oxide layer 1042 is subjected to a second chemical mechanical polishing to expose the first separation layer 1041, in which an acidic slurry with a pH value of 3-4 is used, the particle size of the slurry is less than 50 nm, the polishing temperature is 30° C., and the polishing removal rate is 0.3-0.4 μm / min. When the polishing reaches the interface between the second oxide layer 1042 and the first separation region, the acidic slurry only polishes away silicon oxide, but not silicon, so it automatically stops at the first separation layer 1041.

[0053] 1 and 11, a third chemical mechanical polishing is performed on a part of the first separation layer 1041 to form the upper silicon layer 103. The third chemical mechanical polishing improves the surface roughness and the state of the surface particles, and a semiconductor material with excellent uniformity is obtained. Specifically, in the third chemical mechanical polishing, an alkaline slurry with a pH value of 11 to 12 is used, the particle diameter of the slurry is less than 40 nm, the polishing temperature is 30° C., the polishing removal amount is 50 nm to 300 nm, the polishing removal amount can be understood as the removal height of the first separation region in the first direction, that is, the thinning dimension H0 of the first separation layer 1041 in the first direction, the polishing removal rate is 80 to 100 nm / min, and based on the above process, a semiconductor material is obtained in which the thickness of the upper silicon layer 103 is less than 200 nm, the in-chip film thickness variation deviation is less than ±10 nm, and the thickness non-uniformity (RTG) is less than 5%.

[0054] Example 2 The specific process is the same as that of Example 1, except that the structures of the first substrate 101 and the second substrate 104 provided are different. Referring to Figures 12, 13 and 14, the surface of the first substrate 101 is oxidized to form a first oxide layer 102, no oxide layer is provided on the second substrate 104, and oxygen ions are directly implanted into the second substrate 104, and the structure after bonding is the same as that of Figure 5.

[0055] Example 3 The specific process is the same as that of Example 1, except that the first oxide layer 102 is formed on both the first substrate 101 and the second substrate 104, and the structures thereof are shown in Figures 3 and 12, respectively. The structure after the first substrate 101 and the second substrate 104 are bonded is the same as that shown in Figure 5.

[0056] Comparative Example In comparison with the manufacturing method of this embodiment, in the comparative example, the step of forming an oxide layer by oxygen ion implantation is not used, and a first substrate 101 and a second substrate 104 including an oxide layer are directly bonded, annealed, and thinned to obtain a semiconductor material having a structure similar to that of FIG. 1.

[0057] Referring to Table 1, the test comparison data between the semiconductor material manufactured by the above manufacturing method and the semiconductor material of the comparative example are shown. The formula for calculating the non-uniformity is Non-uniformity=(H max -H min ) / (H max +H min ) [Table 1]

[0058] As can be seen from Table 1, the manufacturing method of the present application can perform a specific chemical mechanical polishing process on the different layer structures generated by oxygen ion implantation, that is, the layer transfer is achieved by selective polishing, and the final multi-layer semiconductor material is obtained, which can greatly reduce the thickness and non-uniformity of the surface of the upper silicon layer 103. Therefore, the selective polishing can greatly reduce the non-uniformity error caused by the long direct polishing process in the comparative example, and can avoid the non-uniformity problem of the upper silicon layer 103 caused by direct polishing, which greatly improves the thickness uniformity of the upper silicon layer 103, and ensures the production of a semiconductor material with a thickness of the upper silicon layer 103 less than 500 nm. In addition, by disposing the first oxide layer 102 on the second substrate 104, the damage to the second substrate 104 caused by oxygen ion implantation can be further reduced, and the overall quality of the material can be improved.

[0059] The above is a detailed introduction of the semiconductor material, manufacturing method and semiconductor device provided in the embodiments of the present application, in which specific examples are used to explain the principles and embodiments of the present application. The description of the above embodiments is only used to understand the technical solutions and core ideas of the present application, and it should be understood that those skilled in the art can modify the technical solutions recorded in the above embodiments or make equivalent substitutions for some technical features, and these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. 1. A method for manufacturing a semiconductor material, comprising the steps of: A first substrate (101) and a second substrate (104) are provided, respectively, and a first oxide layer (102) is formed on the first substrate (101) and / or the second substrate (104); Implanting oxygen ions into the second substrate (104) so ​​that the second substrate (104) includes a first separation layer (1041), a second oxide layer (1042), and a second separation layer (1043) stacked along a first direction; bonding the second substrate (104) to the first substrate (101) such that the first oxide layer (102) is located between the first substrate (101) and the second substrate (104); a top silicon layer (103) is formed on the first oxide layer (102) by thinning the second isolation layer (1043), the second oxide layer (1042) and a portion of the first isolation layer (1041) to produce a semiconductor material; said second separation layer (1043) is mechanically ground, and the remaining thickness of said second separation layer (1043) after said mechanical grinding is between 4 and 10 μm; Thinning the second separation layer (1043), the second oxide layer (1042), and a portion of the first separation layer (1041) comprises: subjecting the second separation layer (1043) to a first chemical mechanical polishing to expose the second oxide layer (1042); subjecting the second oxide layer (1042) to a second chemical mechanical polishing to expose the first separation layer (1041); performing a third chemical mechanical polishing on a portion of the first separation layer (1041) to form the top silicon layer (103); Here, the polishing removal rate of the first chemical mechanical polishing is 0.5 μm / min to 1 μm / min, the polishing removal rate of the second chemical mechanical polishing is 0.1 μm / min to 0.6 μm / min, and the polishing removal rate of the third chemical mechanical polishing is 60 nm / min to 120 nm / min. A method for producing a semiconductor material comprising the steps of:

2. When forming a first oxide layer (102) on the second substrate (104), the step of implanting oxygen ions into the second substrate (104) includes implanting oxygen ions from a side of the second substrate (104) on which the first oxide layer (102) is provided.

2. A method for producing a semiconductor material according to claim 1.

3. The first chemical mechanical polishing uses an alkaline slurry having a pH value of 11 to 13, the second chemical mechanical polishing uses an acidic slurry having a pH value of 3 to 5, and the third chemical mechanical polishing uses an alkaline slurry having a pH value of 10 to 12.

2. A method for producing a semiconductor material according to claim 1.

4. The polishing temperature of the first chemical mechanical polishing is 20 to 40° C., the polishing temperature of the second chemical mechanical polishing is 20 to 40° C., and the polishing temperature of the third chemical mechanical polishing is 20 to 40° C. The method for producing a semiconductor material according to any one of claims 1 to 3.

5. The method further includes annealing the second substrate (104) and the first substrate (101) before mechanically grinding the second separation layer (1043), the annealing temperature is 1320-1380° C., and the annealing time is 6-8 h.

2. A method for producing a semiconductor material according to claim 1.

6. In the oxygen ion implantation, the oxygen ion implantation energy is 100 keV to 500 keV, and the implantation amount is 7E16 cm －２ ~2E19cm －２ The oxygen ion implantation angle is 6-8°, the ion implantation temperature is ≧300° C., and the oxygen ion beam current is ≧10 mA. The method for producing a semiconductor material according to any one of claims 1 to 3 and 5.

7. The first oxide layer (102) has an average thickness H along a first direction. １ and the upper silicon layer (103) has an average thickness H along a first direction. ２ having 0.01≦H ２ / H １ ≦100 and 0.01 μm≦H １ ≦5μm, 0.01μm≦H ２ Meets ≦0.5 μm 2. A method for producing a semiconductor material according to claim 1.

8. The second oxide layer (1042) has an average thickness H along a first direction. ３ a distance between the second oxide layer (1042) and the first oxide layer (102) in a first direction is H, and a thinning dimension of the first separation layer (1041) in the first direction is H ０ and H ２ +H ０ ≦H and 100 nm≦H ３ ≦400 nm, 50 nm≦H ０ Meets the requirement of ≦300 nm A method for producing a semiconductor material according to claim 7.

9. The material of the first isolation layer (1041) and the second isolation layer (1043) is silicon, and the material of the second oxide layer (1042) is silicon dioxide. The method for producing a semiconductor material according to any one of claims 1 to 3, 5, 7 to 8.

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