Manufacturing method of element chip and substrate processing method

Abstract

To highly accurately dice a semiconductor substrate on which a metal film is formed.SOLUTION: A manufacturing method of an element chip includes: a step of preparing a semiconductor substrate which includes a first layer provided with a first principal surface comprising an element region, a divided region, and a mark, and a second principal surface, and including a semiconductor layer; a step of covering a first region of the second principal surface corresponding to the mark with a resist film; a step of forming a metal film on the second principal surface; a step of exposing the semiconductor layer corresponding to the first region by removing the resist film; a step of imaging the semiconductor substrate from a surface side of the metal film with a predetermined camera, detecting a position of the mark through the semiconductor layer corresponding to the first region, and calculating a second region corresponding to the divided region on the surface of the metal film based on the position; a step of exposing the semiconductor layer in the second region by removing the metal film by irradiating the second region with a first laser beam from the surface side of the metal film; and a dicing step.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a component chip and a method for processing a substrate. [Background technology]

[0002] Element chips are usually manufactured by dicing a substrate including a semiconductor layer and the like. The substrate includes a plurality of element regions and division regions that define the element regions. The substrate is diced by removing the semiconductor layer corresponding to the division regions, thereby forming a plurality of element chips. Patent Document 1 teaches that a groove-like gap is formed in the division region called a street by using a laser beam, and the semiconductor layer exposed from the gap is irradiated with plasma to etch the semiconductor layer, thereby dicing the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2013-535114 Summary of the Invention [Problem to be solved by the invention]

[0004] With the technological development of electric vehicles (EVs), the demand for element chips called power devices is increasing. Power devices such as power MOSFETs are mainly used for power conversion, and are required to have high voltage resistance and high heat resistance. Therefore, devices that require heat dissipation, such as power devices, may have a structure that allows current to flow in the thickness direction and a metal film on the back side. Such element chips are obtained, for example, by dicing a substrate that includes a metal film and a semiconductor layer. However, it is difficult to etch the metal film by plasma irradiation, especially when the metal film contains a high-melting point metal that has poor reactivity. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a method for manufacturing an element chip, the method including a preparation step of preparing a semiconductor substrate including a first layer having a first main surface including a plurality of element regions, division regions defining the element regions, and alignment marks, and a second main surface opposite to the first main surface, the first layer including a semiconductor layer, a coating step of coating a first region corresponding to the alignment marks on the second main surface with a resist film, a metal film forming step of forming a metal film on the second main surface, a first exposure step of removing the resist film to expose the semiconductor layer corresponding to the first region, and a camera for detecting an electromagnetic wave passing through the semiconductor layer and the semiconductor substrate from the surface side of the metal film. the first region on the surface of the metal film corresponding to the divided region based on the detected position of the alignment mark; a second exposure step of irradiating the second region from the surface side of the metal film with a first laser light to remove the metal film corresponding to the second region and expose the semiconductor layer corresponding to the second region; and a dicing step of removing the exposed semiconductor layer corresponding to the second region after the second exposure step to divide the semiconductor substrate into a plurality of element chips.

[0006] Another aspect of the present disclosure relates to a substrate processing method, the substrate processing method including a preparation step of preparing a semiconductor substrate including a first layer having a first main surface including a plurality of element regions, division regions defining the element regions, and alignment marks, and a second main surface opposite to the first main surface, the first layer including a semiconductor layer, a coating step of coating a first region of the second main surface corresponding to the alignment marks with a resist film, a metal film formation step of forming a metal film on the second main surface, a first exposure step of removing the resist film to expose the semiconductor layer corresponding to the first region, and a step of exposing the semiconductor substrate from a surface side of the metal film by an electromagnetic wave that transmits through the semiconductor layer. the position of the alignment mark through the semiconductor layer corresponding to the first region is detected based on the detected position of the alignment mark; a second exposure step of irradiating the second region from the surface side of the metal film with a first laser light to remove the metal film corresponding to the second region and expose the semiconductor layer corresponding to the second region; and an etching step of etching the exposed semiconductor layer corresponding to the second region with plasma after the second exposure step. Effect of the Invention

[0007] According to the present disclosure, a semiconductor substrate on which a metal film is formed can be diced or etched with high precision. [Brief description of the drawings]

[0008] [Figure 1] 1 is a flowchart illustrating a method for manufacturing a component chip according to an embodiment of the present disclosure. [Figure 2A] FIG. 1 is a top view diagrammatically illustrating a semiconductor substrate according to an embodiment of the present disclosure. [Figure 2B] 2B is a cross-sectional view of the semiconductor substrate taken along line XX shown in FIG. 2A. [Diagram 3] FIG. 2 is a top view diagrammatically illustrating a transport carrier and a semiconductor substrate held by the transport carrier. [Figure 4]2B is a cross-sectional view of the semiconductor substrate after a bonding step according to an embodiment of the present disclosure taken along line XX in FIG. 2A. [Diagram 5] 2B is a cross-sectional view of the semiconductor substrate after a coating step according to an embodiment of the present disclosure taken along line XX in FIG. 2A. [Figure 6] 2B is a cross-sectional view of the semiconductor substrate after the metal film forming step according to the embodiment of the present disclosure taken along line XX in FIG. 2A. [Figure 7A] 2B is a cross-sectional view of the semiconductor substrate after a first exposure step according to an embodiment of the present disclosure taken along line XX in FIG. 2A. [Figure 7B] FIG. 2 is a top view illustrating a semiconductor substrate after a first exposure step according to an embodiment of the present disclosure. [Figure 8] 2B is a cross-sectional view of the semiconductor substrate after a protective film forming step according to an embodiment of the present disclosure, taken along line XX in FIG. 2A. [Figure 9] 11 is a flowchart illustrating an operation in a calculation step of the laser light irradiation device according to the embodiment of the present disclosure. [Figure 10] 2B is a cross-sectional view of the semiconductor substrate during a calculation process according to an embodiment of the present disclosure taken along line XX in FIG. 2A. [Figure 11A] 2B is a cross-sectional view of the semiconductor substrate after a second exposure step according to an embodiment of the present disclosure taken along line XX in FIG. 2A. [Figure 11B] FIG. 4 is a top view illustrating a semiconductor substrate after a second exposure step according to an embodiment of the present disclosure. [Figure 12] 2B is a cross-sectional view of the semiconductor substrate (element chip) after a dicing process according to an embodiment of the present disclosure taken along line XX in FIG. 2A. [Figure 13] 1 is a cross-sectional view illustrating a schematic structure of a plasma processing apparatus. [Figure 14] FIG. 1 is a block diagram of a plasma processing apparatus used in one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following describes an embodiment of the element chip manufacturing method and substrate processing method according to the present disclosure. However, the present disclosure is not limited to the following examples. In the following description, specific values ​​and materials may be exemplified, but other values ​​and materials may be applied as long as the effects of the present disclosure are obtained.

[0010] (Method of manufacturing element chip) The manufacturing method of the component chip according to the present disclosure includes a preparation step, a coating step, a metal film forming step, a first exposing step, a calculating step, a second exposing step, and a dicing step.

[0011] In the preparation step, a semiconductor substrate including a first layer including a semiconductor layer is prepared. The first layer has a first main surface including a plurality of element regions, division regions defining the element regions, and alignment marks, and a second main surface opposite to the first main surface. Here, the alignment marks refer to marks indicating the division regions or marks provided for positioning.

[0012] In the coating step, the first region is coated with a resist film. Here, the first region is a region corresponding to the alignment mark on the second main surface of the first layer (for example, a region behind the alignment mark). The resist film may be made of any resist material. The area of ​​the front surface of the resist film may be larger than the area of ​​the back surface, and in this case, the width may be narrowed from the front surface side to the back surface side. The cross-sectional area of ​​the resist film in a cross section perpendicular to the thickness direction may be maximum at the front surface. The width of the resist film may be substantially constant from the front surface to the back surface.

[0013] In the metal film forming step, a metal film is formed on the second main surface of the first layer. In the metal film forming step, the metal film is not formed on the region (first region) of the second main surface that is covered with the resist film. The metal film may be formed by, for example, a vapor deposition method or a sputtering method. The metal film may also be formed on the resist film. The material of the metal film is, for example, silver, copper, aluminum, an aluminum alloy, tungsten, nickel, gold, platinum, titanium, etc.

[0014] In the first exposure step, the resist film is removed to expose the semiconductor layer corresponding to the first region. The resist film may be removed, for example, by contacting the semiconductor substrate with a solution that dissolves the resist film. If a metal film is also formed on the resist film, the metal film on the resist film may also be removed when the resist film is removed.

[0015] In the calculation step, the position of the alignment mark is detected, and a second region corresponding to the division region on the surface of the metal film is calculated based on the detected position of the alignment mark. The position of the alignment mark is detected by capturing an image of the semiconductor substrate with a camera that senses electromagnetic waves transmitted through the semiconductor layer. This allows the alignment mark to be detected from the surface side of the metal film. The electromagnetic waves transmitted through the semiconductor layer may be electromagnetic waves having a wavelength of 1100 nm or more and 6 μm or less when the semiconductor layer is made of silicon, for example.

[0016] In the second exposure step, the first laser light is irradiated from the front side of the metal film to the second region to remove the metal film corresponding to the second region and expose the semiconductor layer corresponding to the second region. The first laser light may be a laser light absorbed by the metal film. The first laser light may be a laser light transmitted through the semiconductor layer.

[0017] In the dicing step, after the second exposing step, the semiconductor layer corresponding to the exposed second region is removed to divide the semiconductor substrate into a plurality of element chips. The semiconductor layer may be removed by, for example, irradiating it with plasma.

[0018] As described above, in the metal film forming process, the metal film is not formed in the region (first region) of the second main surface covered with the resist film. Therefore, in order to enable the position of the alignment mark to be detected by the camera, it is necessary to remove the resist film from the second main surface in the first region, but it is not necessary to remove the metal film from the second main surface. Removal of the resist film from the second main surface causes less damage to the second main surface than removal of the metal film from the second main surface. Therefore, the smoothness of the first region of the second main surface is less likely to be damaged, and the electromagnetic waves passing through the semiconductor layer corresponding to the first region are less likely to be scattered. Therefore, the alignment mark can be clearly imaged by a camera that senses the electromagnetic waves, and the position of the alignment mark can be accurately detected. If the position of the alignment mark can be accurately detected, the calculation of the second region, the exposure of the semiconductor layer corresponding to the second region, and the dicing of the semiconductor substrate can be performed with high accuracy.

[0019] The manufacturing method of the element chip may further include a protective film forming step of forming a protective film covering the surface of the metal film prior to the second exposure step. In this case, the protective film corresponding to the second region may be removed together with the metal film corresponding to the second region in the second exposure step, and the semiconductor layer corresponding to the second region may be removed by irradiating the second region with plasma in the dicing step. In this configuration, the protective film can protect the metal film from plasma and debris in the dicing step involving plasma irradiation.

[0020] The manufacturing method of the element chip may further include a bonding step of bonding the first main surface of the semiconductor substrate to a holding sheet before the dicing step. Furthermore, the dicing step may be performed in a state where the semiconductor substrate is held by the holding sheet. This configuration improves the handleability of the semiconductor substrate. Also, it becomes possible to hold a plurality of element chips formed in the dicing step by the holding sheet. The bonding step may be performed before the dicing step, but is preferably performed before the calculation step, for example. The bonding step may be performed before the first exposure step or after the first exposure step. If it is performed after the first exposure step, even if a solution that dissolves the resist film is used in the first exposure step, the solution can be prevented from adhering to the holding sheet.

[0021] The method for manufacturing the element chip may further include a polishing step of polishing the second main surface of the semiconductor substrate prior to the covering step, which improves the smoothness of the second main surface including the first region, and can further suppress scattering of electromagnetic waves passing through the semiconductor layer corresponding to the first region.

[0022] (Substrate processing method) The substrate processing method according to the present disclosure includes a preparing step, a coating step, a metal film forming step, a first exposing step, a calculating step, a second exposing step, and an etching step.

[0023] The preparation step, the coating step, the metal film forming step, the first exposure step, the calculation step, and the second exposure step may be the same as those in the above-mentioned method for manufacturing the component chip.

[0024] In the etching step, after the second exposure step, the semiconductor layer corresponding to the exposed second region is etched with plasma. This etching forms grooves in the semiconductor layer in the division region. As in the above-mentioned method for manufacturing the element chip, the plasma etching of the semiconductor layer can be performed with high accuracy.

[0025] As described above, according to the present disclosure, a semiconductor substrate on which a metal film is formed can be diced or etched with high precision.

[0026] In the following, an example of the manufacturing method of the element chip and the substrate processing method according to the present disclosure will be specifically described with reference to the drawings. The above-mentioned steps can be applied to the steps of the manufacturing method of the element chip and the substrate processing method according to the example described below. The steps of the manufacturing method of the element chip and the substrate processing method according to the example described below can be modified based on the above description. In addition, the matters described below may be applied to the above embodiment. Among the steps of the manufacturing method of the element chip and the substrate processing method according to the example described below, steps that are not essential to the manufacturing method of the element chip and the substrate processing method according to the present disclosure may be omitted. Note that the figures shown below are schematic and do not accurately reflect the shape and number of the actual members.

[0027] FIG. 1 is a flowchart showing a method for manufacturing a component chip according to this embodiment.

[0028] (1) Preparation process (S1) First, a semiconductor substrate to be diced is prepared.

[0029] (Semiconductor Substrate) The semiconductor substrate includes a first layer having a first main surface including a plurality of element regions, division regions that define the element regions, and alignment marks, and a second main surface opposite to the first main surface. The first layer includes a semiconductor layer.

[0030] The first layer may further include a wiring layer and an insulating film on the first main surface side. In this case, the semiconductor substrate corresponding to the element region includes, for example, a wiring layer and a semiconductor layer. The semiconductor substrate corresponding to the division region includes, for example, an insulating film and a semiconductor layer. The insulating film may include a metal material such as TEG (Test Element Group). A plurality of element chips are obtained by etching the semiconductor substrate corresponding to the division region in the thickness direction.

[0031] The size of the semiconductor substrate is not particularly limited, and may be, for example, a maximum diameter of 50 mm or more and 300 mm or less. The shape of the semiconductor substrate is also not particularly limited, and may be, for example, a circle, a square, or a hexagon. The semiconductor substrate may also be provided with a cutout such as an orientation flat or a notch.

[0032] The semiconductor layer includes, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc. The thickness of the semiconductor layer in the element chip is not particularly limited, and may be, for example, 20 μm or more and 1000 μm or less, or 100 μm or more and 300 μm or less.

[0033] The wiring layer constitutes, for example, a semiconductor circuit, an electronic component element, a MEMS, etc., and may include an insulating film, a metal material, a resin layer (for example, polyimide), a resist layer, an electrode pad, a bump, etc. The insulating film may be included as a laminate with a metal material for wiring (a multilayer wiring layer or a rewiring layer).

[0034] The shape of the division regions is not limited to a straight line, and may be a zigzag or wavy line as long as it is set according to the desired shape of the element chip. Examples of the shape of the element chip include a rectangle and a hexagon.

[0035] The width of the divided regions is not particularly limited, and may be set appropriately depending on the size of the semiconductor substrate and the element chip. The width of the divided regions is, for example, 10 μm or more and 300 μm or less. The widths of the divided regions may be the same or different. A plurality of divided regions are usually arranged on the semiconductor substrate. The pitch between adjacent divided regions is also not particularly limited, and may be set appropriately depending on the size of the semiconductor substrate and the element chip.

[0036] The alignment mark is disposed on the surface of the first main surface for positioning the semiconductor substrate. The alignment mark is not particularly limited, and may be a mark indicating the boundary between the division region and the element region (for example, a metal pattern called a seal or seal ring, a pattern made of an insulating material called a scribe line, etc.), or may be a mark specially provided for positioning. The alignment mark is usually distinguishable from the semiconductor layer and the wiring layer by image recognition. The shape of the alignment mark is not particularly limited. The shape of the alignment mark may be a combination of a plurality of straight lines (for example, parallel lines, a grid, etc.), or may be a cross, a circle, a rectangle, etc. Alignment marks other than the boundary line are disposed, for example, in the division region, which is the outer edge portion of the semiconductor substrate. The alignment mark may be disposed in the element region as necessary.

[0037] Fig. 2A is a top view diagrammatically illustrating a semiconductor substrate as viewed from a first main surface side, and Fig. 2B is a cross-sectional view of the semiconductor substrate taken along line XX in Fig. 2A.

[0038] The semiconductor substrate 10 includes a first layer having a first main surface 10X including a plurality of element regions 101, division regions 102 defining the element regions 101, and alignment marks 15, and a second main surface 10Y opposite the first main surface 10X. The first layer includes a semiconductor layer 11. Four cross-shaped alignment marks 15 are arranged on the outer edge of the first main surface 10X. The semiconductor substrate 10 includes one notch 10a.

[0039] (2) Pasting process (S2) After the preparation step and before the dicing step (in this example, before the polishing step), the first main surface of the semiconductor substrate may be attached to a holding sheet, which improves the handleability of the semiconductor substrate.

[0040] (Retaining sheet) In order to improve handling, the holding sheet may be fixed to a frame. The semiconductor substrate may be subjected to each process while being held by, for example, a transport carrier including a frame and a holding sheet fixed to the frame.

[0041] The frame is a frame body having an opening with an area equal to or larger than the entire semiconductor substrate, and has a predetermined width and a substantially constant thin thickness. The frame has a degree of rigidity that allows the frame to be transported while holding the holding sheet and the semiconductor substrate. The shape of the opening of the frame is not particularly limited, and may be, for example, a circle, a rectangle, a hexagon, or other polygon. Examples of the material of the frame include metals such as aluminum and stainless steel, and resins.

[0042] The material of the holding sheet is not particularly limited. In particular, it is preferable that the holding sheet includes an adhesive layer and a flexible non-adhesive layer, in that the semiconductor substrate can be easily attached thereto.

[0043] The material of the non-adhesive layer is not particularly limited, and examples thereof include thermoplastic resins such as polyolefins such as polyethylene and polypropylene, and polyesters such as polyvinyl chloride and polyethylene terephthalate. The resin film may contain various additives such as rubber components (e.g., ethylene-propylene rubber (EPM), ethylene-propylene-diene rubber (EPDM)) for adding elasticity, plasticizers, softeners, antioxidants, and conductive materials. The thermoplastic resin may also have a functional group that exhibits a photopolymerization reaction, such as an acrylic group. The thickness of the non-adhesive layer is not particularly limited, and is, for example, 50 μm or more and 300 μm or less, and preferably 50 μm or more and 150 μm or less.

[0044] The outer periphery of the surface having the adhesive layer (adhesive surface) is attached to one surface of the frame, covering the opening of the frame. One main surface (first main surface) of the semiconductor substrate is attached to a portion of the adhesive surface exposed from the opening of the frame, thereby holding the semiconductor substrate on the holding sheet. The semiconductor substrate may be held on the holding sheet via a die attach film (DAF).

[0045] The adhesive layer is preferably made of an adhesive component whose adhesive strength decreases when irradiated with ultraviolet (UV) rays. This allows the device chip to be easily peeled off from the adhesive layer by irradiating it with UV rays when picking up the device chip after dicing, making it easier to pick up. For example, the adhesive layer can be obtained by applying a UV-curable acrylic adhesive to one side of the non-adhesive layer to a thickness of 5 μm or more and 100 μm or less (preferably 5 μm or more and 15 μm or less).

[0046] FIG. 3 is a top view showing a schematic diagram of a transport carrier and a semiconductor substrate held thereon. FIG. 4 is a cross-sectional view of the semiconductor substrate after the bonding step according to the present embodiment, taken along the line XX in FIG. 2A. The transport carrier 20 includes a frame 21 and a holding sheet 22 fixed to the frame 21. The frame 21 may be provided with a notch 21a or a corner cut 21b for positioning. The outer periphery of the adhesive surface 22X of the holding sheet 22 is attached to one surface of the frame 21, and one main surface of the semiconductor substrate 10 is attached to a portion of the adhesive surface 22X exposed from the opening of the frame 21. During plasma processing, the holding sheet 22 is placed on a stage installed in a plasma processing device so that the stage and the non-adhesive surface 22Y opposite to the adhesive surface 22X come into contact with each other.

[0047] (3) Polishing process (S3) Prior to the covering step, the second main surface of the semiconductor substrate may be polished to improve the smoothness of the second main surface, and the polishing step may thin the semiconductor substrate to a desired thickness.

[0048] (4) Covering process (S4) A first area on the second main surface corresponding to the alignment mark is covered with a resist film.

[0049] The resist film includes a resist material. The resist material may be contained in a liquid resist solution or may be a dry film resist. The resist material may be, for example, a photoresist. The photoresist includes, for example, a resist resin, a photosensitizer, and an additive. The resist resin is not particularly limited, but for example, a novolac resin (such as a phenol novolac resin) is used. As the photosensitizer, for example, an acid generator that generates an organic acid with high acidity by light irradiation can be used. The resist film may be a positive type or a negative type, but a negative type resist is preferable because it is easy to adjust the cross-sectional shape of the patterned resist film by the amount of exposure. The resist resin may be a water-soluble resin. The thickness of the resist film is not particularly limited, but it is preferable that the thickness is thicker than the thickness of the metal film formed in the metal film forming process (S5) described later in order to facilitate removal (lift-off) of the metal film in the first exposure process (S6) described later.

[0050] The method for forming the resist film is not particularly limited, but may be formed by applying a resist solution, or may be formed by pasting a dry film resist using a laminating machine. The resist solution contains, for example, a resist material and a solvent. The solvent is not particularly limited, but may be, for example, methyl ethyl ketone, propylene glycol monomethyl ether acetate, or the like. The resist film is formed by applying the resist solution to the second main surface to form a coating film, and drying the coating film. The temperature at which the coating film is heated for drying may be 50°C or higher, 60°C or higher, or 90°C or higher.

[0051] The method for forming a coating film on the second main surface (applying the resist solution to the second main surface) may be any method that allows the resist solution to be applied uniformly onto the second main surface, and may be, for example, spin coating, spray coating, slit coating, or other methods. Spin coating is performed using a spin coating application device. Spray coating is performed using a spray application device. Slit coating is performed using a slit coater.

[0052] Next, the resist film is patterned to selectively cover the first region with the resist film. The patterning includes an exposure step of irradiating the resist film with light in a pattern corresponding to the arrangement of the first region, and a development step of removing the resist film covering the areas other than the first region with a developer. The patterning may further include a washing step of washing the remaining developer with pure water or the like. The exposure step is a step of changing the solubility of the resist film in the developer by irradiating the resist film with UV light, for example. The development step may be performed using a developer and a development method (dip development or spray development) that are suitable for the characteristics of the resist film. It is preferable to make the cross-sectional shape of the patterned resist film in an inverse tapered shape by adjusting the exposure conditions and development conditions. By making the cross-sectional shape of the resist film in an inverse tapered shape, a metal film is less likely to be formed on the side of the patterned resist film in the metal film formation step described later, so that the semiconductor layer corresponding to the first region can be easily exposed in the first exposure step described later.

[0053] (1st area) The first region is determined, for example, from the position of a cutout such as an orientation flat or a notch provided in a semiconductor substrate, or the position of a cutout such as a corner cut or a notch provided in a frame, with reference to design information such as a design drawing. The design information indicates the positional relationship between each cutout and an alignment mark. A part of the second main surface corresponding to the alignment mark determined from the position of the cutout is the first region. In other words, at least a part of the alignment mark and at least a part of the first region face each other, and at least a part of the alignment mark overlaps with the first region when viewed from the normal direction of the second main surface.

[0054] The position of the alignment mark determined by referring to the design information as described above may deviate from the actual position of the alignment mark due to dimensional variations of the substrate, variations in the alignment mark formation positions, etc. However, a positional deviation of, for example, about several hundred μm is allowed. Here, a relatively wide area on the second main surface corresponding to the alignment mark may be determined as the first area.

[0055] When the alignment mark is a boundary line, the first region includes at least parts of two boundary lines (for example, an intersection of lattice-like boundary lines, or parts of two adjacent parallel lines). Such a first region is, for example, an arc or a ring along the outer edge of the semiconductor substrate. When the alignment mark is not a boundary line, the entire alignment mark overlaps with the first region when viewed from the normal direction of the second main surface. When the smallest circle that surrounds the alignment mark other than a boundary line is drawn, the circular or rectangular portion that has a diameter (or long side length) of about 5 to 10 times the diameter of the circle and overlaps with the circle can be determined as the first region.

[0056] It is preferable to determine the first region so that the metal film formed in the metal film forming step does not enter the field of view of the camera used in the calculation step. This is to avoid mistaking the metal film for an alignment mark. For example, if the diameter of the smallest circle is 100 μm and the field of view of the camera is 300 μm square, the diameter (or the long side length) of the first region may be about 500 μm.

[0057] 5 is a cross-sectional view of the semiconductor substrate after the covering step according to the present embodiment, taken along line XX in FIG. 2A. A resist film 50 is formed in a first region R1 on the second main surface 10Y of the semiconductor substrate 10. The resist film 50 narrows from the front side (farther from the second main surface 10Y) toward the back side (closer to the second main surface 10Y). Due to this inverse tapered shape, in the subsequent metal film forming step, the metal film 30 formed on the second main surface 10Y and the metal film 30 formed on the resist film 50 are easily separated from each other.

[0058] (5) Metal film formation process (S5) After the covering step, a metal film is formed on the second main surface of the semiconductor substrate.

[0059] The metal film is formed, for example, to pass a current in the thickness direction or to improve heat dissipation. The metal film is disposed adjacent to the semiconductor layer, but an adhesive layer or the like may be interposed between the two. The material of the metal film is, for example, silver, copper, aluminum, aluminum alloy, tungsten, nickel, gold, platinum, titanium, or the like. The metal film is formed, for example, by a vapor deposition method, a sputtering method, a plating method, or the like. The metal film may be a single layer, or may be two or more layers. The metal film may be, for example, a semiconductor layer having titanium, nickel, and gold laminated in order (Au / Ni / Ti), a semiconductor layer having titanium, nickel, and silver laminated in order (Ag / Ni / Ti), or a semiconductor layer having titanium, nickel, and aluminum alloy laminated in order (Al alloy / Ni / Ti).

[0060] The thickness (total thickness) of the metal film is not particularly limited and is appropriately set depending on the application of the element chip. The thickness of the metal film is, for example, 50 nm or more and 100 μm or less. When the metal film is a laminate of Au / Ni / Ti, for example, the thickness of Au is 50 nm or more and 200 nm or less, the thickness of Ni is 200 nm or more and 400 nm or less, and the thickness of Ti is 100 nm or more and 300 nm or less. When the metal film is a laminate of Ag / Ni / Ti, for example, the thickness of Ag is 200 nm or more and 30 μm or less, the thickness of Ni is 200 nm or more and 400 nm or less, and the thickness of Ti is 100 nm or more and 300 nm or less. When the metal film is a laminate of Al alloy / Ni / Ti, for example, the thickness of the Al alloy is 200 nm or more and 30 μm or less, the thickness of the Ni is 200 nm or more and 400 nm or less, and the thickness of the Ti is 100 nm or more and 300 nm or less.

[0061] 6 is a cross-sectional view of the semiconductor substrate after the metal film forming process according to this embodiment, taken along line XX in FIG. 2A. A metal film 30 is formed in a region of the second main surface 10Y of the semiconductor substrate 10 except for the first region R1. In addition, a metal film 30 is also formed on a resist film 50. The metal film 30 on the second main surface 10Y and the metal film 30 on the resist film 50 are separated from each other. However, the two metal films 30 may be connected to each other.

[0062] (6) First exposure step (S6) After the metal film forming step, the resist film and the metal film thereon are removed (lifted off) to expose the semiconductor layer corresponding to the first region.

[0063] In the first exposure step, the resist film and the metal film thereon may be removed by contacting the semiconductor substrate with a solution (developer) that dissolves the resist film. The type of solution that dissolves the resist film is not particularly limited.

[0064] 7A is a cross-sectional view of the semiconductor substrate after the first exposure step according to the present embodiment taken along the line XX in FIG. 2A. FIG. 7B is a top view diagrammatically illustrating the semiconductor substrate after the first exposure step according to the present embodiment. The resist film 50 and the metal film 30 are removed from the four first regions R1 so that the four alignment marks 15 arranged on the first main surface 10X of the semiconductor substrate 10 are entirely exposed. The first region R1 is a circle surrounding the alignment mark 15. In FIG. 7B, the metal film 30 is shown hatched for the sake of convenience.

[0065] (7) Protective film formation process (S7) Prior to the second exposure step (in this example, prior to the calculation step), a protective film is formed to cover the surface of the metal film. The protective film protects the metal film corresponding to the element region from the plasma used in the dicing step and debris generated in the dicing step in the dicing step. The protective film corresponding to the second region is removed together with the metal film in the second exposure step.

[0066] (protective film) The protective film includes, for example, a thermosetting resin such as polyimide, a resist material such as a photoresist, or a water-soluble resin such as an acrylic resin. The protective film is formed, for example, by applying a raw material liquid of the protective film to the surface of the metal film using a method such as spin coating or spray coating. Among them, a water-soluble resin is preferable because it can be removed by washing with water. Examples of the water-soluble resin that can be used include polyvinyl alcohol, polyacrylamide, polyvinylpyrrolidone, 2-acrylamido-2-methylpropanesulfonic acid, sodium polyacrylate, sodium polystyrenesulfonate, lithium polystyrenesulfonate, and diallyldimethylammonium chloride.

[0067] The thickness of the protective film is not particularly limited, but is preferably such that it is not completely removed in the plasma dicing process. For example, the thickness of the protective film is calculated by calculating the amount (thickness) of the protective film etched in the plasma dicing process, and set to be equal to or greater than this amount of etching.

[0068] The protective film transmits electromagnetic waves that pass through the semiconductor layer, so even if the protective film is formed on the first region where the semiconductor layer is exposed, the protective film does not prevent the camera used in the calculation process from capturing an image of the alignment mark.

[0069] 8 is a cross-sectional view of the semiconductor substrate after the protective film forming step according to this embodiment, taken along the line XX in FIG. 2A. The protective film 40 is formed so as to cover the metal film 30 of the semiconductor substrate 10.

[0070] (8) Calculation process (S8) The semiconductor substrate is imaged from the surface side of the metal film by a camera that senses electromagnetic waves that pass through the semiconductor layer, and the position and shape of the alignment mark are detected through the semiconductor layer corresponding to the first region. Based on data related to the detected alignment mark, a second region corresponding to the divided region on the surface of the metal film is calculated.

[0071] (camera) The camera can sense the electromagnetic waves that pass through the semiconductor layer. This allows the alignment mark to be imaged from the front side of the metal film through the semiconductor layer corresponding to the first region. The electromagnetic waves that pass through the semiconductor layer may be generated, for example, by a near-infrared halogen lamp that is disposed on the front side of the metal film and has a peak wavelength of 1000 nm or more.

[0072] The camera may be, for example, an infrared camera capable of sensing electromagnetic waves in the near-infrared region (wavelength band of 750 nm or more and 1200 nm or less), but an infrared camera having sensitivity in a longer wavelength region is preferable. The infrared camera constitutes the imaging section of the laser light irradiation device described below. The imaging section may include a camera other than an infrared camera (e.g., a camera that senses visible light). The imaging section may include multiple infrared cameras. The field of view of the infrared camera is not particularly limited, but may be 300 μm square or more from the viewpoint of improving accuracy.

[0073] (Laser light irradiation device) The laser light irradiation device includes, for example, an arm for loading and unloading the semiconductor substrate, a stage for placing the semiconductor substrate, an irradiation head for irradiating the laser beam, a drive unit for driving the stage, an input unit for inputting data relating to the division region, the first region and / or the alignment mark, an imaging unit for imaging the semiconductor substrate placed on the stage, an image processing unit for detecting the shape of the imaged semiconductor substrate, etc., a calculation unit for determining the position of the semiconductor substrate, the first region and / or the second region based on the shape of the semiconductor substrate detected by the image processing unit and the input data, and a control unit for controlling these.

[0074] The input unit includes, for example, a touch panel. The above-mentioned various data are input to the input unit, for example, by an operator. The control unit, image processing unit, and calculation unit include, for example, a computer. The imaging unit includes, for example, a camera. The drive unit includes, for example, a ball screw and a linear guide mechanism. As the ball screw rotates, the stage moves translationally and / or vertically below the irradiation head and the camera.

[0075] (Second area) The second region is calculated from the position of the detected alignment mark and data from the input unit. The second region is a part of the surface of the metal film corresponding to the divided region. In other words, at least a part of the divided region and at least a part of the second region face each other, and when viewed from the normal direction of the surface of the metal film, at least a part of the divided region overlaps with the second region. Preferably, the entire divided region overlaps with the second region.

[0076] FIG. 9 is a flowchart showing the operation in the calculation step of the laser light irradiation device according to this embodiment.

[0077] When the protective film forming process is completed, the operation of the laser light irradiation device in the calculation process is started (T10). The driving unit drives the stage to move the first region below the infrared camera. The imaging unit captures an image of the alignment mark from the surface side of the metal film through the semiconductor layer corresponding to the first region with the infrared camera (T11). The image processing unit processes the captured image to detect the position and shape of the alignment mark (T12). The calculation unit calculates the position of the divided region on the surface of the metal film from the detected alignment mark and the input data related to the divided region (T13). This determines the second region corresponding to the divided region on the surface of the metal film. Thereafter, the operation of the laser light irradiation device in the calculation process is completed (T14).

[0078] 10 is a cross-sectional view of the semiconductor substrate during the calculation process according to this embodiment, taken along line XX in FIG. 2A. An infrared camera 300 captures an image of the alignment mark 15 through the semiconductor layer 11 corresponding to the first region R1. The captured image is processed to detect the shape of the alignment mark 15, etc. The position of the divided region is calculated from the detected shape of the alignment mark 15, etc.

[0079] (9) Second exposure process (S9) The second region is irradiated with a first laser beam from the front surface side of the metal film to remove the protective film and the metal film corresponding to the second region, thereby exposing the semiconductor layer corresponding to the second region.

[0080] The driving unit drives the stage to move the edge of the semiconductor substrate below the irradiation head. When the semiconductor substrate is placed in a predetermined position, the irradiation unit starts irradiating the second region with the first laser light. While the first laser light is being irradiated, the driving unit further moves the stage in a planar direction based on the size and shape of the second region. This removes the protective film and metal film corresponding to the second region.

[0081] (First laser beam) It is preferable that the first laser light is absorbed by the metal film and transmitted through the semiconductor layer, in which case the metal film is removed by irradiation with the first laser light, but surface roughness and internal crystal disorder of the semiconductor layer below the metal film are suppressed.

[0082] From the viewpoint of suppressing damage to the semiconductor layer, the first laser light preferably has a wavelength that is not easily absorbed by the semiconductor constituting the semiconductor layer. For example, when the semiconductor layer is silicon, the first laser light preferably has a wavelength of 1100 nm or more and 6 μm or less, and an example thereof is a carbon monoxide laser. The wavelength of the first laser light is not limited to this wavelength range, and may be a shorter wavelength range that has the advantage of high light collection. Specifically, the first laser light may have a wavelength of 850 nm or more and 1100 nm or less, or may have a wavelength of 190 nm or more and 450 nm or less. More specifically, the wavelength of the first laser light may be 980 nm, 1064 nm, or 1030 nm in the near infrared region, or 355 nm, 305 nm, 308 nm, or 266 nm in the ultraviolet region.

[0083] The frequency of the first laser light is not particularly limited, but is, for example, 1 kHz or more and 200 kHz or less. The laser oscillation mechanism of the first laser light is not particularly limited, and examples thereof include a semiconductor laser using a semiconductor as a medium for laser oscillation, a gas laser using a gas such as carbon dioxide (CO2) as a medium, a solid-state laser using YAG or the like, and a fiber laser. The laser oscillator is also not particularly limited, but a pulsed laser oscillator that oscillates a pulsed laser light is preferable because it has a small thermal effect on the semiconductor substrate.

[0084] The pulse width of the laser light is not particularly limited, but from the viewpoint of reducing the thermal effect and suppressing damage to the semiconductor layer, it is preferably 500 nanoseconds or less, and more preferably 200 nanoseconds or less. -15 seconds) or hundreds of femtoseconds (100×10 -15 seconds) to 100 picoseconds (100×10 -12 It is preferable to use an ultrashort pulse laser beam having a pulse width of about 100 s.

[0085] After the second exposure step, the exposed semiconductor layer may be irradiated with a second laser beam to improve the smoothness of the semiconductor layer. For example, the second laser beam may be a long-pulse laser beam having a pulse width of several hundreds of nanoseconds to several milliseconds, or may be a laser beam whose intensity distribution in a plane perpendicular to the optical axis is shaped into a flat-top distribution (top-hat distribution).

[0086] Fig. 11A is a cross-sectional view of the semiconductor substrate after the second exposure step according to the present embodiment, taken along line XX in Fig. 2A. Fig. 11B is a top view showing the semiconductor substrate after the second exposure step according to the present embodiment. The protective film 40 and the metal film 30 corresponding to the second region R2 are removed, and the semiconductor layer 11 corresponding to the second region R2 is exposed. In Fig. 11B, the protective film 40 is shown hatched for the sake of convenience.

[0087] (10) Dicing process (S10) The semiconductor layer corresponding to the exposed second region is removed to divide the semiconductor substrate into a plurality of element chips. The dicing step can be performed by irradiating the second region with plasma (first plasma) from the front side of the metal film.

[0088] Fig. 12 is a cross-sectional view of the semiconductor substrate after the dicing process according to this embodiment, taken along line XX in Fig. 2A. The semiconductor layer 11 corresponding to the second region R2 is removed, and a plurality of element chips 200 are formed.

[0089] Before the dicing step, a step of cleaning the surface of the metal film with a second plasma may be performed. The second plasma is usually generated under different conditions from the first plasma generated during dicing. Such a cleaning step is performed, for example, for the purpose of reducing residues resulting from the second exposure step. This makes it possible to perform plasma dicing of higher quality.

[0090] Next, an embodiment of the plasma processing apparatus used in the dicing process will be specifically described. Fig. 13 is a cross-sectional view showing a schematic structure of the plasma processing apparatus. In Fig. 13, the semiconductor substrate is held by a transport carrier. The structure of the plasma processing apparatus is not limited to this.

[0091] (Plasma processing equipment) The plasma processing apparatus 100 includes a stage 111. The transport carrier 20 is placed on the stage 111 so that the surface of the holding sheet 22 that holds the semiconductor substrate 10 faces upward. The stage 111 is large enough to accommodate the entire transport carrier 20. A cover 124 having a window 124W for exposing at least a part of the semiconductor substrate 10 is disposed above the stage 111. A pressing member 107 for pressing the frame 21 when the frame 21 is placed on the stage 111 is disposed on the cover 124. The pressing member 107 is preferably a member that can come into point contact with the frame 21 (for example, a coil spring or a resin having elasticity). This makes it possible to correct the distortion of the frame 21 while suppressing the heat of the frame 21 and the cover 124 from affecting each other.

[0092] The stage 111 and the cover 124 are disposed in the vacuum chamber 103. The vacuum chamber 103 is generally cylindrical with an open top, and the top opening is closed by a dielectric member 108, which is a lid. Examples of materials constituting the vacuum chamber 103 include aluminum, stainless steel (SUS), and aluminum with anodized surface. Examples of materials constituting the dielectric member 108 include dielectric materials such as yttrium oxide (Y2O3), aluminum nitride (AlN), alumina (Al2O3), and quartz (SiO2). A first electrode 109 is disposed above the dielectric member 108 as an upper electrode. The first electrode 109 is electrically connected to a first high-frequency power supply 110A. The stage 111 is disposed on the bottom side of the vacuum chamber 103.

[0093] A gas inlet 103a is connected to the vacuum chamber 103. A process gas source 112 and an ashing gas source 113, which are supply sources of a plasma generating gas (process gas), are connected to the gas inlet 103a by piping. The vacuum chamber 103 is also provided with an exhaust port 103b. A decompression mechanism 114 including a vacuum pump for exhausting gas in the vacuum chamber 103 and reducing the pressure is connected to the exhaust port 103b. With the process gas being supplied into the vacuum chamber 103, high frequency power is supplied from a first high frequency power supply 110A to a first electrode 109, whereby plasma is generated in the vacuum chamber 103.

[0094] The stage 111 includes an electrode layer 115 and a metal layer 116, each of which is substantially circular, a base 117 that supports the electrode layer 115 and the metal layer 116, and an outer periphery 118 that surrounds the electrode layer 115, the metal layer 116, and the base 117. The outer periphery 118 is made of a metal that is conductive and resistant to etching, and protects the electrode layer 115, the metal layer 116, and the base 117 from plasma. An annular outer periphery ring 129 is disposed on the upper surface of the outer periphery 118. The outer periphery ring 129 serves to protect the upper surface of the outer periphery 118 from plasma. The electrode layer 115 and the outer periphery ring 129 are made of, for example, the above-mentioned dielectric materials.

[0095] An electrode for electrostatic chuck (hereinafter referred to as ESC electrode 119) and a second electrode 120 electrically connected to second high frequency power supply 110B are arranged inside electrode layer 115. A DC power supply 126 is electrically connected to ESC electrode 119. ESC electrode 119 and DC power supply 126 configure an electrostatic chuck mechanism. Holding sheet 22 is pressed against and fixed to stage 111 by the electrostatic chuck mechanism. Hereinafter, a case where an electrostatic chuck mechanism is provided as a fixing mechanism for fixing holding sheet 22 to stage 111 will be described as an example, but is not limited to this. Holding sheet 22 may be fixed to stage 111 by a clamp (not shown).

[0096] The metal layer 116 is made of, for example, aluminum having an alumite coating formed on its surface. A coolant flow path 127 is formed in the metal layer 116. The coolant flow path 127 cools the stage 111. By cooling the stage 111, the holding sheet 22 placed on the stage 111 is cooled, and the cover 124, a part of which is in contact with the stage 111, is also cooled. This prevents the semiconductor substrate 10 and the holding sheet 22 from being damaged by being heated during plasma processing. The coolant in the coolant flow path 127 is circulated by a coolant circulation device 125.

[0097] A plurality of supports 122 penetrating the stage 111 are disposed near the outer periphery of the stage 111. The supports 122 support the frame 21 of the transport carrier 20. The supports 122 are driven to move up and down by a first lifting mechanism 123A. When the transport carrier 20 is transported into the vacuum chamber 103, it is handed over to the supports 122 that have risen to a predetermined position. When the upper end surface of the supports 122 is lowered to the same level as the stage 111 or lower, the transport carrier 20 is placed at a predetermined position on the stage 111.

[0098] A plurality of lifting rods 121 are connected to the ends of the cover 124, enabling the cover 124 to be raised and lowered. The lifting rods 121 are driven to rise and lower by a second lifting mechanism 123B. The operation of lifting and lowering the cover 124 by the second lifting mechanism 123B can be performed independently of the first lifting mechanism 123A.

[0099] The control device 128 controls the operations of the elements constituting the plasma processing device 100, including the first high frequency power supply 110A, the second high frequency power supply 110B, the process gas source 112, the ashing gas source 113, the pressure reducing mechanism 114, the coolant circulating device 125, the first lifting mechanism 123A, the second lifting mechanism 123B, and the electrostatic adsorption mechanism. Fig. 14 is a block diagram of the plasma processing device used in this embodiment.

[0100] The etching of the semiconductor substrate 10 is performed by carrying the transport carrier 20 holding the semiconductor substrate 10 into the vacuum chamber 103, with the semiconductor substrate 10 placed on the stage 111. When carrying the semiconductor substrate 10, the cover 124 is raised to a predetermined position in the vacuum chamber 103 by driving the lift rod 121. A gate valve (not shown) opens and the transport carrier 20 is carried in. The multiple support parts 122 are waiting in the raised state. When the transport carrier 20 reaches a predetermined position above the stage 111, the transport carrier 20 is handed over to the support parts 122. The transport carrier 20 is handed over to the upper end surface of the support part 122 so that the adhesive surface 22X of the holding sheet 22 faces upward.

[0101] When the transport carrier 20 is transferred to the support 122, the vacuum chamber 103 is placed in a sealed state. Next, the support 122 starts to descend. The upper end surface of the support 122 descends to the same level as the stage 111 or lower, so that the transport carrier 20 is placed on the stage 111. Next, the lift rod 121 is driven. The lift rod 121 lowers the cover 124 to a predetermined position. At this time, the distance between the cover 124 and the stage 111 is adjusted so that the pressing member 107 arranged on the cover 124 can make point contact with the frame 21. As a result, the frame 21 is pressed by the pressing member 107, and the frame 21 is covered by the cover 124, and the semiconductor substrate 10 is exposed from the window 124W.

[0102] The cover 124 is, for example, a doughnut shape having a substantially circular outer contour, with a constant width and a thin thickness. The diameter of the window 124W is smaller than the inner diameter of the frame 21, and the outer diameter of the window 124W is larger than the outer diameter of the frame 21. Therefore, when the transport carrier 20 is mounted at a predetermined position on the stage 111 and the cover 124 is lowered, the cover 124 can cover the frame 21. At least a part of the semiconductor substrate 10 is exposed from the window 124W.

[0103] The cover 124 is made of, for example, a dielectric material such as ceramics (e.g., alumina, aluminum nitride, etc.) or quartz, or a metal such as aluminum or aluminum whose surface has been anodized. The pressing member 107 can be made of a resin material in addition to the above-mentioned dielectric materials and metals.

[0104] After the transport carrier 20 is handed over to the support portion 122, a voltage is applied from the DC power supply 126 to the ESC electrodes 119. As a result, the holding sheet 22 is electrostatically attracted to the stage 111 at the same time as the holding sheet 22 comes into contact with the stage 111. Note that application of the voltage to the ESC electrodes 119 may be started after the holding sheet 22 is placed on (in contact with) the stage 111.

[0105] When the etching is completed, the gas in the vacuum chamber 103 is discharged, and the gate valve is opened. The transport carrier 20 holding the multiple element chips 200 is carried out from the plasma processing apparatus 100 by the transport mechanism that enters through the gate valve. When the transport carrier 20 is carried out, the gate valve is quickly closed. The process of carrying out the transport carrier 20 may be performed in a reverse procedure to the procedure of mounting the transport carrier 20 on the stage 111 as described above. That is, after the cover 124 is raised to a predetermined position, the applied voltage to the ESC electrodes 119 is made zero, the adsorption of the transport carrier 20 to the stage 111 is released, and the support portion 122 is raised. After the support portion 122 is raised to a predetermined position, the transport carrier 20 is carried out.

[0106] The conditions for generating the plasma (first plasma) for etching the semiconductor layer are set according to the material of the semiconductor layer and the like.

[0107] The semiconductor layer is plasma etched, for example, by the Bosch process. In the Bosch process, the semiconductor layer is etched vertically in the depth direction (thickness direction). When the semiconductor layer contains Si, the Bosch process digs the semiconductor layer in the depth direction by sequentially repeating a deposition step, a deposition film etching step, and a Si etching step.

[0108] The deposition step is performed under the following conditions: while supplying C4F8 as a process gas at 150 sccm or more and 250 sccm or less, the pressure in the vacuum chamber is adjusted to 15 Pa or more and 25 Pa or less, the power input from the first high frequency power supply to the first electrode is set to 1500 W or more and 2500 W or less, and the power input from the second high frequency power supply to the second electrode is set to 0 W or more and 50 W or less, and the processing time is from 2 seconds to 15 seconds or less.

[0109] The deposition film etching step is performed under the following conditions: for example, SF6 is supplied as a process gas at 200 sccm or more and 400 sccm or less, the pressure in the vacuum chamber is adjusted to 5 Pa or more and 15 Pa or less, the power input from the first high frequency power supply to the first electrode is set to 1500 W or more and 2500 W or less, and the power input from the second high frequency power supply to the second electrode is set to 300 W or more and 1000 W or less, and the processing time is 2 seconds or more and 10 seconds or less.

[0110] The Si etching step is performed under the following conditions: for example, SF6 is supplied as a process gas at 200 sccm or more and 400 sccm or less, the pressure in the vacuum chamber is adjusted to 5 Pa or more and 15 Pa or less, the power input from the first high frequency power supply to the first electrode is set to 1500 W or more and 2500 W or less, and the power input from the second high frequency power supply to the second electrode is set to 50 W or more and 500 W or less, and the processing time is 10 seconds or more and 20 seconds or less.

[0111] By repeating the deposition step, the deposited film etching step, and the Si etching step under the above conditions, the semiconductor layer containing Si can be etched vertically in the depth direction at a rate of 10 μm / min or more and 20 μm / min or less.

[0112] So far, the manufacturing method of the element chip including the dicing step has been described, but the present embodiment also includes a substrate processing method including an etching step instead of the dicing step. In the etching step of the substrate processing method, after the second exposure step, the semiconductor layer corresponding to the exposed second region is etched with plasma. In this etching step, the semiconductor substrate is not divided, and grooves corresponding to the division regions may be formed in the semiconductor substrate. [Industrial Applicability]

[0113] The present disclosure can be used in a manufacturing method of an element chip and a substrate processing method. [Explanation of symbols]

[0114] 10: Semiconductor substrate 10a:Notch 10X: First main surface 10Y: 2nd principal surface 101: Element area 102: Split area 11: Semiconductor layer 15: Alignment mark R1: 1st area R2: 2nd area 20: Transport carrier 21: Frame 21a:Notch 21b: Corner cut 22: Retaining sheet 22X: Adhesive surface 22Y: Non-adhesive surface 30: Metal film 40:Protective film 50: Resist film 100: Plasma processing device 103: Vacuum chamber 103a: Gas inlet 103b: Exhaust port 108: Dielectric member 109: First electrode 110A: First high frequency power source 110B: second high frequency power source 111: Stage 112: Process gas source 113: Ashing gas source 114: Pressure reduction mechanism 115: Electrode layer 116: Metal layer 117: Foundation 118: Outer periphery 119:ESC electrode 120: second electrode 121: Lifting rod 122: Support part 123A: First lift mechanism 123B: Second lift mechanism 124: Cover 124W: Window section 125: Refrigerant circulation device 126:DC power supply 127: Coolant flow path 128: Control device 129: Outer ring 200: Element chip 300: Infrared camera

Claims

1. a preparation step of preparing a semiconductor substrate, the semiconductor substrate including a first layer having a first main surface including a plurality of element regions, division regions defining the element regions, and an alignment mark, and a second main surface opposite to the first main surface, the first layer including a semiconductor layer; a coating step of coating a first area of ​​the second main surface corresponding to the alignment mark with a resist film; a metal film forming step of forming a metal film on the second main surface; a first exposure step of removing the resist film to expose the semiconductor layer corresponding to the first region; a calculation step of capturing an image of the semiconductor substrate from the front side of the metal film by a camera that senses electromagnetic waves transmitted through the semiconductor layer, detecting a position of the alignment mark through the semiconductor layer corresponding to the first region, and calculating a second region on the surface of the metal film corresponding to the divided region based on the detected position of the alignment mark; a second exposure step of irradiating the second region with a first laser light from a surface side of the metal film to remove the metal film corresponding to the second region and expose the semiconductor layer corresponding to the second region; a dicing step of removing the semiconductor layer corresponding to the exposed second region after the second exposure step, and dividing the semiconductor substrate into a plurality of element chips; A method for manufacturing an element chip comprising the steps of:

2. The method further includes a protective film forming step of forming a protective film that covers a surface of the metal film before the second exposure step, In the second exposure step, the protective film corresponding to the second region is removed together with the metal film corresponding to the second region; 2. The method for producing element chips according to claim 1, wherein in the dicing step, the semiconductor layer corresponding to the second region is removed by irradiating the second region with plasma.

3. The method further includes a step of attaching the first main surface of the semiconductor substrate to a holding sheet prior to the dicing step, 3. The method for producing element chips according to claim 1, wherein the dicing step is performed in a state where the semiconductor substrate is held by the holding sheet.

4. 4. The method for producing an element chip according to claim 1, further comprising a polishing step of polishing said second main surface of said semiconductor substrate prior to said covering step.

5. a preparation step of preparing a semiconductor substrate, the semiconductor substrate including a first layer having a first main surface including a plurality of element regions, division regions defining the element regions, and an alignment mark, and a second main surface opposite to the first main surface, the first layer including a semiconductor layer; a coating step of coating a first area of ​​the second main surface corresponding to the alignment mark with a resist film; a metal film forming step of forming a metal film on the second main surface; a first exposure step of removing the resist film to expose the semiconductor layer corresponding to the first region; a calculation step of capturing an image of the semiconductor substrate from the front side of the metal film by a camera that senses electromagnetic waves transmitted through the semiconductor layer, detecting a position of the alignment mark through the semiconductor layer corresponding to the first region, and calculating a second region on the surface of the metal film corresponding to the divided region based on the detected position of the alignment mark; a second exposure step of irradiating the second region with a first laser light from a surface side of the metal film to remove the metal film corresponding to the second region and expose the semiconductor layer corresponding to the second region; an etching step of etching the semiconductor layer corresponding to the exposed second region with plasma after the second exposure step; A substrate processing method comprising:

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