Semiconductor Devices

Abstract

To provide a technique that suppresses injection of a hole when a diode is in forward bias.SOLUTION: A semiconductor device includes a first main electrode, a second main electrode, and a semiconductor layer having the first main electrode formed on a lower surface thereof and the second main electrode formed on an upper surface thereof. The semiconductor layer includes a p-type semiconductor region that is disposed at a position exposed to the upper surface and electrically connected to the second main electrode, and an n-type semiconductor region that is in contact with the p-type semiconductor region and is separated from the second main electrode by the p-type semiconductor region. The n-type semiconductor region includes a trap region provided at a position in contact with the p-type semiconductor region, and a positive hole trap is formed on the trap region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] When a forward bias is applied to a diode (including diodes built into MOSFETs), electrons are injected from the n-type cathode region into the high-resistance region, and holes are injected from the p-type anode region into the high-resistance region. When the voltage applied to the diode changes from forward bias to reverse bias, the electrons and holes that were injected into the high-resistance region during forward bias each move in the opposite direction to when the diode was in forward bias. This reverse flow of electrons and holes is called the recovery current, and is the main cause of recovery loss.

[0003] In addition, when a diode is formed using silicon carbide, it is known that when holes injected into the high-resistance region reach the n-type cathode region and electrons and holes recombine in the n-type cathode region, the recombination energy causes defects at the interface between the n-type cathode region and the high-resistance region to grow.

[0004] In order to suppress such an increase in recovery loss or the growth of stacking faults, it is important to keep the hole concentration in the high resistance region low when the diode is forward biased. 1 / 2 The present invention discloses a technique for preventing holes injected into a high-resistance region from reaching an n-type cathode region by forming a center and reducing the carrier lifetime in the high-resistance region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-80035 A Summary of the Invention [Problem to be solved by the invention]

[0006] The technology of Patent Document 1 can suppress the hole concentration in the high resistance region by promoting recombination of electrons and holes injected into the high resistance region. However, the technology of Patent Document 1 cannot suppress the injection of holes from the p-type anode region when the diode is forward biased. This specification provides a technology for suppressing the injection of holes when the diode is forward biased. [Means for solving the problem]

[0007] One embodiment of the semiconductor device disclosed in this specification may include a first main electrode, a second main electrode, and a semiconductor layer. The semiconductor layer has the first main electrode coated on a lower surface thereof and the second main electrode coated on an upper surface thereof. The semiconductor layer may have a p-type semiconductor region and an n-type semiconductor region. The p-type semiconductor region is disposed at a position exposed on the upper surface thereof and is electrically connected to the second main electrode. The n-type semiconductor region is in contact with the p-type semiconductor region and is separated from the second main electrode by the p-type semiconductor region. The n-type semiconductor region further has a trap region provided at a position in contact with the p-type semiconductor region. A hole trap is formed in the trap region.

[0008] In the semiconductor device, the trap region in which a hole trap is formed is provided in a position adjacent to the p-type semiconductor region, and therefore, when the semiconductor device is forward biased, the trap region forms an energy barrier against holes, thereby suppressing the injection of holes from the p-type semiconductor region to the n-type semiconductor region. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a schematic cross-sectional view of a main portion of an embodiment of a diode. [Diagram 2] FIG. 4 is a diagram showing the concentration distribution of aluminum and n-type impurities in the depth direction of a semiconductor layer. [Diagram 3] 1A and 1B are diagrams illustrating the action and effect of a trap region when a forward bias is applied, in which (A) shows the density of holes captured in a hole trap, and (B) shows the potential of the trap region. [Figure 4] FIG. 4 is a diagram showing the concentration distribution of aluminum and n-type impurities in the depth direction of a semiconductor layer. [Diagram 5] FIG. 1 is a schematic cross-sectional view of a main portion of an embodiment of a MOSFET. [Figure 6] FIG. 2 is a schematic cross-sectional view of a main portion of another embodiment of a MOSFET. [Figure 7] 7 is a schematic cross-sectional view of a main part of the MOSFET shown in FIG. 6 during a manufacturing process. [Figure 8] 7 is a schematic cross-sectional view of a main part of the MOSFET shown in FIG. 6 during a manufacturing process. [Figure 9] 7 is a schematic cross-sectional view of a main part of the MOSFET shown in FIG. 6 during a manufacturing process. [Figure 10] 7 is a schematic cross-sectional view of a main part of the MOSFET shown in FIG. 6 during a manufacturing process. [Figure 11] FIG. 2 is a schematic cross-sectional view of a main portion of another embodiment of a MOSFET. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] (Diode embodiment) 1, the diode 1 includes a semiconductor layer 10, a cathode electrode 22 covering the lower surface of the semiconductor layer 10, and an anode electrode 24 covering the upper surface of the semiconductor layer 10. The material of the cathode electrode 22 and the anode electrode 24 may be, for example, Al, Ni, Ti, Mo, or Co. The cathode electrode 22 is an example of a first main electrode, and the anode electrode 24 is an example of a second main electrode.

[0011] The semiconductor layer 10 is made of silicon carbide (SiC) and has n + a cathode region 12 of the n-type; -The semiconductor device has a p-type high resistance region 14 and a p-type anode region 16.

[0012] The cathode region 12 is disposed at a position exposed on the lower surface of the semiconductor layer 10, and is in ohmic contact with the cathode electrode 22. The cathode region 12 is, for example, a silicon carbide substrate having a (0001) plane orientation, and also serves as a base substrate for epitaxially growing the high-resistance region 14, as described later.

[0013] The high resistance region 14 is disposed between the cathode region 12 and the anode region 16, and is in contact with both the cathode region 12 and the anode region 16. The high resistance region 14 is separated from the cathode electrode 22 by the cathode region 12, and from the anode electrode 24 by the anode region 16. The high resistance region 14 is made of silicon carbide formed by crystal growth from the surface of the cathode region 12 using an epitaxial growth technique, and has a lower concentration of n-type impurities than the cathode region 12. The high resistance region 14 is an example of an n-type semiconductor region.

[0014] The high resistance region 14 has a non-trapping region 14a and a trapping region 14b. The non-trapping region 14a is disposed closer to the cathode region 12 than the trapping region 14b and is in contact with the cathode region 12. The trapping region 14b is disposed closer to the anode region 16 than the non-trapping region 14a and is in contact with the anode region 16.

[0015] The non-trap region 14a is a region where hole traps are not substantially formed. On the other hand, the trap region 14b is a region where hole traps are formed. Here, the hole trap is a trap formed at a deep energy level in the band gap by defects, impurities, etc., and is a trap that can particularly capture holes. Information on the energy level, density, depth, etc. of the hole trap can be obtained by the DLTS (Deep Level Transient Spectroscopy) method. The method of forming the hole trap is not particularly limited. For example, in the diode 1 of this embodiment, the hole trap is formed by introducing aluminum into the range corresponding to the trap region 14b of the high resistance region 14 using ion implantation technology.

[0016] The anode region 16 is disposed at a position exposed on the upper surface of the semiconductor layer 10, and is in ohmic contact with the anode electrode 24. The method for forming the anode region 16 is not particularly limited. For example, in the diode 1 of this embodiment, the anode region 16 may be formed by using an ion implantation technique to introduce p-type impurities having a higher concentration than the n-type impurities of the high resistance region 14 in multiple stages with different range distances into the upper layer portion of the high resistance region 14 formed by crystal growth. For example, aluminum is used as the p-type impurity. The anode region 16 is an example of a p-type semiconductor region.

[0017] 2 shows the aluminum concentration distribution in the depth direction of the semiconductor layer 10. The area indicated by the reference symbol "16" is the anode region 16, the area indicated by the reference symbol "14b" is the trapping region 14b, and the area indicated by the reference symbol "14a" is the non-trapping region 14a. The dashed line indicates the concentration of n-type impurities contained in the semiconductor layer 10.

[0018] The anode region 16 contains more aluminum than n-type impurities. Therefore, the anode region 16 is p-type. Note that, although FIG. 2 shows the concentration of aluminum contained in the anode region 16 as being constant in the depth direction, as described above, since aluminum is introduced by multi-stage ion implantation, in reality, multiple peaks exist at intervals in the depth direction.

[0019] The trapping region 14b contains less aluminum than the n-type impurities. Therefore, the trapping region 14b is n-type. As shown in FIG. 2, the aluminum concentration distribution has a step in the range corresponding to the trapping region 14b. Here, the step in the concentration distribution refers to a range in which the decrease in concentration in the depth direction is suppressed compared to the ranges above and below, and more specifically, refers to a range including a portion in which no decrease in concentration occurs in the depth direction. As described above, the trapping region 14b is formed by ion implantation of aluminum, so that the peak of the aluminum concentration in the depth direction is located in the trapping region 14b. Therefore, the trapping region 14b includes a portion in which the aluminum concentration increases.

[0020] It is known that hole traps are formed in regions where aluminum is introduced. The density of hole traps is roughly proportional to the aluminum concentration. Therefore, the density distribution of hole traps in the depth direction of the semiconductor layer 10 shows a distribution similar to the aluminum concentration distribution shown in FIG. 2. Therefore, it can be said that the trap region 14b is an n-type region that includes a peak in the density distribution of hole traps in the depth direction. In addition, the trap region 14b is an n-type region where the density of hole traps is 10 14 cm -3 More preferably, the hole trap density is in the range of 10 16 cm -3 It can also be said that the above areas are covered.

[0021] Next, the operation of the diode 1 will be described. When a forward bias is applied between the cathode electrode 22 and the anode electrode 24 so that the anode electrode 24 has a higher potential than the cathode electrode 22, electrons are injected from the cathode region 12 into the high resistance region 14, and holes are injected from the anode region 16 into the high resistance region 14, resulting in electrical continuity between the cathode electrode 22 and the anode electrode 24. Next, when a reverse bias is applied between the cathode electrode 22 and the anode electrode 24 so that the anode electrode 24 has a lower potential than the cathode electrode 22, the electrons and holes injected into the high resistance region 14 during the forward bias move in the opposite direction to that during the forward bias. Such a reverse flow of electrons and holes is called a recovery current.

[0022] Here, the function of the trap region 14b when forward biased will be described with reference to Fig. 3. Here, the "p" region in the figure corresponds to the anode region 16, the "hole trap" region corresponds to the trap region 14b, and the "n - " corresponds to the non-trapping region 14a. When a forward bias is applied, holes are captured in the hole traps in the trapping region 14b, and the density of captured holes in the trapping region 14b increases (see FIG. 3A). When holes are captured in the hole traps, the potential of the hole traps increases, and a potential barrier against holes is formed in the trapping region 14b (see FIG. 3B). This suppresses the injection of holes from the anode region 16 to the high resistance region 14. Since the injection of holes from the anode region 16 to the high resistance region 14 is itself suppressed, the hole concentration in the high resistance region 14 under forward bias can be kept low. As a result, the recovery current is suppressed when a reverse bias is applied, and the recovery loss is reduced.

[0023] Also, in the diode 1 of this embodiment, assuming that the energy level of hole trapping in the trap region 14b is Et, the energy level of the valence band in the trap region 14b is Ev, and the band gap of the trap region 14b is Eg, the relationship Et - Ev < Eg / 2 holds, that is, the relationship that Et - Ev is smaller than the mid-band gap holds. The energy level Et of the hole trap formed by ion implantation of aluminum can have such a relationship. A hole trap with an energy level satisfying such a relationship does not capture holes under zero bias. Therefore, in the diode 1, problems such as a reduction in breakdown voltage due to charged hole traps do not occur.

[0024] Also, in the diode 1 of this embodiment, the high-resistance region 14 has a non-trap region 14a. By providing the non-trap region 14a, an increase in the forward voltage can be suppressed compared to the case where hole traps are formed throughout the high-resistance region 14. Therefore, the diode 1 of this embodiment can suppress recovery loss while suppressing an increase in the forward voltage.

[0025] As shown in FIG. 4, by making the concentration of n-type impurities in the trap region 14b higher than the concentration of n-type impurities in the non-trap region 14a, the concentration of aluminum contained in the trap region 14b can also be increased. In this example, the concentration of aluminum in the trap region 14b is higher than the concentration of n-type impurities in the non-trap region 14a. Thus, when the concentration of aluminum in the trap region 14b is high, the density of hole traps also becomes high, and the injection of holes during forward bias can be effectively suppressed. In order to selectively increase the concentration of n-type impurities in the trap region 14b, for example, when epitaxially growing the high-resistance region 14, it may be formed such that the concentration of n-type impurities in the range corresponding to the trap region 14b becomes high, or n-type impurities may be ion-implanted into the range corresponding to the trap region 14b after epitaxial growth.

[0026] (Embodiment of MOSFET) A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 2 with a built-in diode will be described below with reference to Fig. 5. The MOSFET 2 is used in, for example, an inverter device that supplies AC power to an AC motor, and the built-in diode operates as a freewheel diode.

[0027] 5, the MOSFET 2 includes a semiconductor layer 110, a drain electrode 122 covering the lower surface of the semiconductor layer 110, a source electrode 124 covering the upper surface of the semiconductor layer 110, and a trench gate portion 130 provided in the upper layer portion of the semiconductor layer 110. The material of the drain electrode 122 and the source electrode 124 may be, for example, Al, Ni, Ti, Mo, or Co. The drain electrode 122 is an example of a first main electrode, and the source electrode 124 is an example of a second main electrode.

[0028] The semiconductor layer 110 is made of silicon carbide (SiC) and has n + A drain region 112 of the n - A p-type high resistance region 114, a p-type body region 116, and an n + and a source region 118 of the same type.

[0029] The drain region 112 is disposed at a position exposed on the lower surface of the semiconductor layer 110, and is in ohmic contact with the drain electrode 122. The drain region 112 is a silicon carbide substrate having a (0001) plane orientation, and also serves as a base substrate for epitaxially growing the high-resistance region 114.

[0030] The high resistance region 114 is disposed between the drain region 112 and the body region 116, and is in contact with both the drain region 112 and the body region 116. The high resistance region 114 is separated from the drain electrode 122 by the drain region 112, and is separated from the source electrode 124 by the body region 116. The high resistance region 114 is made of silicon carbide formed by crystal growth from the surface of the drain region 112 using an epitaxial growth technique, and has a lower concentration of n-type impurities than the drain region 112. The high resistance region 114 is an example of an n-type semiconductor region.

[0031] The high resistance region 114 has a non-trap region 114a and a trap region 114b. Most of the non-trap region 114a is disposed closer to the drain region 112 than the trap region 114b, and is in contact with the drain region 112. The trap region 114b is disposed between the non-trap region 114a and the body region 116, and is in contact with the body region 116. The non-trap region 114a is a region in which no hole traps are formed. On the other hand, the trap region 114b is a region in which hole traps are formed. The aluminum concentration distribution and the hole trap density distribution of the trap region 114b are similar to those of the trap region 14b of the diode 1 described above.

[0032] The body region 116 is disposed at a position exposed on the upper surface of the semiconductor layer 110 and is in ohmic contact with the source electrode 124. The body region 116 has a main body region 116a and an electric field relaxation region 116b. The main body region 116a is disposed at a position exposed on the upper surface of the semiconductor layer 110 and is in contact with the side surface of the trench gate portion 130. The electric field relaxation region 116b is in contact with the bottom surface of the main body region 116a and is disposed away from the side surface of the trench gate portion 130. Furthermore, the electric field relaxation region 116b is formed so as to protrude downward from the bottom surface of the main body region 116a beyond the bottom surface of the trench gate portion 130. When such an electric field relaxation region 116b is formed, the electric field at the bottom surface of the trench gate portion 130 can be relaxed when the MOSFET 2 is turned off.

[0033] The method for forming the body region 116 is not particularly limited. For example, in the MOSFET 2 of this embodiment, the body region 116 may be formed by using an ion implantation technique to introduce p-type impurities having a higher concentration than the n-type impurities of the high-resistance region 114 in multiple stages with different range distances into the upper layer of the high-resistance region 114 formed by epitaxial growth. For example, aluminum is used as the p-type impurity. The body region 116 is an example of a p-type semiconductor region.

[0034] The source region 118 is disposed at a position exposed on the upper surface of the semiconductor layer 110, is provided on the body region 116, and is separated from the high-resistance region 114 by the body region 116. The method for forming the source region 118 is not particularly limited. In the MOSFET 2 of this embodiment, the source region 118 is formed by introducing an n-type impurity into the upper layer portion of the semiconductor layer 110 using an ion implantation technique.

[0035] The trench gate portion 130 faces the main body region 116a at a portion separating the non-trap region 114a of the high resistance region 114 from the source region 118. The trench gate portion 130 includes a trench gate electrode 132 and a gate insulating film 134 provided in a trench that penetrates from the upper surface of the semiconductor layer 110 through the source region 118 and the main body region 116a to the non-trap region 114a of the high resistance region 114. The trench gate electrode 132 is formed by filling the trench coated with the gate insulating film 134 using a CVD technique. The gate insulating film 134 is formed by coating the inner wall of the trench using a CVD technique.

[0036] In the MOSFET 2, a diode is built in, with the drain region 112 as the anode region and the body region 116 as the cathode region. This built-in diode operates as a freewheel diode. The action and effect when the built-in diode operates are the same as those of the diode 1 described above. That is, by providing the trap region 114b, the injection of holes from the body region 116 to the high resistance region 114 when forward biased can be suppressed, and the hole concentration of the high resistance region 114 can be suppressed. As a result, the recovery current when a reverse bias is applied is suppressed, and the recovery loss is reduced. Note that in the MOSFET 2, the trap region 114b is selectively formed so as to contact the bottom surface of the electric field relaxation region 116b of the body region 116. The hole injection from the body region 116 is mainly from the electric field relaxation region 116b. Therefore, even if the trap region 114b is selectively provided for the electric field relaxation region 116b, the injection of holes from the body region 116 to the high resistance region 114 can be effectively suppressed.

[0037] Furthermore, in the MOSFET 2, the trap region 114b is disposed away from the side surface of the trench gate portion 130. Therefore, the trap region 114b is disposed away from the channel formed on the side surface of the trench gate portion 130 when the MOSFET 2 is turned on. As a result, an increase in the channel resistance of the MOSFET 2 is suppressed. In this manner, the MOSFET 2 can suppress an increase in the recovery current while suppressing an increase in the channel resistance.

[0038] (Another embodiment of the MOSFET) A MOSFET 3 incorporating a diode will be described with reference to Fig. 6. Components common to the MOSFET 2 shown in Fig. 5 are given the same reference numerals.

[0039] MOSFET3 is characterized in that the trapping region 114b extends along the in-plane direction of the semiconductor layer 110 so as to divide the non-trapping region 114a. Specifically, the trapping region 114b extends in the in-plane direction of the semiconductor layer 110 from at least the bottom surface of the electric field reduction region 116b to a position below the trench gate portion 130. In addition, the trapping region 114b is disposed at a position deeper than the bottom surface of the trench gate portion 130 and is separated from the bottom surface of the trench gate portion 130.

[0040] In addition, the MOSFET 3 is characterized in that the n-type impurity concentration of the trapping region 114b is higher than the n-type impurity concentration of the non-trapping region 114a, and the carrier concentration of the trapping region 114b is higher than the carrier concentration of the non-trapping region 14a. The relationship of the n-type impurity concentrations between the non-trapping region 114a and the trapping region 114b can be the same as the relationship of the n-type impurity concentrations between the non-trapping region 14a and the trapping region 14b illustrated in Fig. 4. The trapping region 114b with a high concentration of n-type impurities can function as a current spreading region.

[0041] Since the trap region 114b extends widely along the in-plane direction of the semiconductor layer 110, it is possible to effectively suppress the injection of holes from the body region 116. In addition, since the trap region 114b extends widely along the in-plane direction of the semiconductor layer 110, when the MOSFET 3 is turned on, electrons injected from the source region 118 through the channel into the high-resistance region 114 can flow while spreading in the in-plane direction due to the trap region 114b. Therefore, a wide current path is ensured in the MOSFET 3, and a low on-resistance can be obtained.

[0042] In addition, even if the trap region 114b extends widely in the in-plane direction, in an example in which the trap region 114b is formed at a position shallower than the electric field relaxation region 116b (i.e., the electric field relaxation region 116b is exposed to the non-trap region 114a) and is in contact with the side and bottom surfaces of the trench gate portion 130, the on-resistance is low but the hole injection may increase. In addition, even if the trap region 114b extends widely in the in-plane direction, in an example in which the trap region 114b is formed at a position deeper than the electric field relaxation region 116b, the hole injection is suppressed but the on-resistance may increase. For this reason, in an example in which the trap region 114b extends widely in the in-plane direction, it is desirable to form the trap region 114b in the positional relationship shown in FIG. 6 in order to achieve both the suppression of hole injection and low on-resistance.

[0043] (MOSFET manufacturing method) A method for manufacturing the MOSFET 3 shown in FIG. 6 will be described with reference to FIGS.

[0044] First, as shown in FIG. 7, a high resistance region 114 of n-type SiC is grown by crystal growth from the upper surface of a drain region 112, which is an n-type SiC substrate, using a crystal growth technique.

[0045] Next, as shown in FIG. 8, aluminum ions and nitrogen ions are introduced to a predetermined depth in the high resistance region 114 using an ion implantation technique to form a trap region 114b extending so as to separate the non-trap region 114a.

[0046] Next, as shown in FIG. 9, aluminum ions are introduced into a portion of the non-trapping region 114a above the trapping region 114b using an ion implantation technique to form an electric field reduction region 116b in contact with the trapping region 114b.

[0047] Next, as shown in FIG. 10, the main body region 116a of p-type SiC is crystal-grown from the upper surfaces of the non-trapping regions 114a and the electric field relaxation regions 116b, thereby completing the body region 116.

[0048] Next, a source region 118 is formed using an ion implantation technique. Next, a trench gate portion 130 is formed using a known manufacturing technique. Thereafter, a drain electrode 122 is formed on the lower surface of the semiconductor layer, and a source electrode 124 is formed on the upper surface of the semiconductor layer, thereby completing the MOSFET 3 shown in FIG.

[0049] (Another embodiment of the MOSFET) A MOSFET 4 incorporating a diode will be described with reference to Fig. 11. Components common to the MOSFET 3 shown in Fig. 6 are given the same reference numerals.

[0050] MOSFET 4 is characterized in that a lower electric field relief region 116c is further provided below electric field relief region 116b. In order to distinguish electric field relief region 116b from lower electric field relief region 116c, electric field relief region 116b will hereinafter be referred to as upper electric field relief region 116b.

[0051] The upper electric field relief region 116b is in contact with the bottom surface of the main body region 116a and is disposed away from the side surface of the trench gate portion 130. The upper electric field relief region 116b also extends parallel to the longitudinal direction (y-axis direction) of the trench gate portion 130.

[0052] The lower electric field relaxation region 116c is in contact with the lower surface of the upper electric field relaxation region 116b, and is provided at a position deeper than the bottom surface of the trench gate portion 130 and shallower than the trap region 114b. The lower electric field relaxation region 116c extends parallel to a direction (x-axis direction) perpendicular to the longitudinal direction (y-axis direction) of the trench gate portion 130, and is disposed at intervals in the longitudinal direction (y-axis direction) of the trench gate portion 130. The trap region 114b is disposed between adjacent lower electric field relaxation regions 116c. The lower electric field relaxation region 116c may extend at an angle to the longitudinal direction (y-axis direction) of the trench gate portion 130, not limited to the case where it is perpendicular to the longitudinal direction (y-axis direction) of the trench gate portion 130. In this way, the upper electric field relaxation region 116b and the lower electric field relaxation region 116c are disposed at different depths in the semiconductor layer 110 and extend in different directions.

[0053] If such upper electric field relief region 116b and lower electric field relief region 116c are provided, the electric field at the bottom surface of the trench gate portion 130 can be further relaxed when the MOSFET 4 is turned off. Furthermore, since both the upper electric field relief region 116b and the lower electric field relief region 116c are disposed at positions shallower than the trap region 114b, hole injection from the body region 116 including these electric field relief regions 116b and 116c is suppressed.

[0054] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0055] One embodiment of the semiconductor device disclosed in this specification can include a first main electrode, a second main electrode, and a semiconductor layer. The semiconductor layer has the first main electrode coated on its lower surface and the second main electrode coated on its upper surface. The semiconductor layer can have a p-type semiconductor region and an n-type semiconductor region. The p-type semiconductor region is disposed at a position exposed on the upper surface and is electrically connected to the second main electrode. The n-type semiconductor region is in contact with the p-type semiconductor region and is separated from the second main electrode by the p-type semiconductor region. The n-type semiconductor region further has a trap region provided at a position in contact with the p semiconductor region. A hole trap is formed in the trap region. The semiconductor device of this embodiment may be a diode or a diode incorporated in a MOSFET.

[0056] In the semiconductor device of the above embodiment, the density distribution of the hole traps in the depth direction of the semiconductor layer may have a peak in the range corresponding to the trap region. In the semiconductor device of this embodiment, it is shown that hole traps are intentionally formed in the range corresponding to the trap region by using, for example, ion implantation technology or the like.

[0057] In the semiconductor device of the above embodiment, when the energy level of the hole trap in the trap region is Et, the energy level of the valence band in the trap region is Ev, and the bandgap of the trap region is Eg, the relationship Et - Ev < Eg / 2 may hold. In the semiconductor device of this embodiment, the breakdown voltage reduction is suppressed.

[0058] In the above embodiment, the semiconductor layer may be silicon carbide. In the semiconductor device of this embodiment, since the hole concentration in the n-type semiconductor region when a forward bias is applied is suppressed, the growth of stacking defects, which is a problem inherent to silicon carbide, is also suppressed.

[0059] In the semiconductor device according to the above embodiment, the trap region may contain aluminum. It is known that hole traps are formed in silicon carbide by introducing aluminum. For this reason, it has been shown that hole traps are formed in the trap region containing aluminum.

[0060] In the semiconductor device of the above embodiment, the concentration distribution of the n-type impurity in the n-type semiconductor region may be higher in the range corresponding to the trap region than in other ranges. By increasing the concentration of the n-type impurity in the trap region, the trap region can have a high aluminum concentration while maintaining the n-type. Therefore, the trap region can also have a high density of hole traps.

[0061] The semiconductor device according to the embodiment may further include a trench gate provided in a trench extending from the upper surface of the semiconductor layer through the p-type semiconductor region to the n-type semiconductor region. The trap region may be disposed at a position away from a side surface of the trench gate. In the semiconductor device according to the embodiment, an increase in recovery current can be suppressed while an increase in channel resistance is suppressed.

[0062] In one example of the semiconductor device of the above embodiment, the p-type semiconductor region may have an electric field relaxation region that protrudes downward from the bottom surface of the trench gate portion at a position away from the side surface of the trench gate portion. The trap region may be disposed so as to contact the bottom surface of the electric field relaxation region. In the semiconductor device of this embodiment, it is possible to suppress an increase in recovery current while suppressing an increase in channel resistance.

[0063] Another example of the semiconductor device of the above embodiment may further include a trench gate portion provided in a trench that extends from the upper surface of the semiconductor layer through the p-type semiconductor region to the n-type semiconductor region. The p-type semiconductor region may have an electric field relaxation region that protrudes downward from a bottom surface of the trench gate portion at a position away from the side surface of the trench gate portion. The trap region may be disposed so as to contact the bottom surface of the electric field relaxation region. In the semiconductor device of this embodiment, hole injection from the electric field relaxation region of at least the p-type semiconductor region can be suppressed.

[0064] In another example of the semiconductor device of the above embodiment, the trap region may extend in an in-plane direction of the semiconductor layer from at least the bottom surface of the electric field relaxation region to a position below the trench gate portion and be disposed at a position away from the bottom surface of the trench gate portion. In the semiconductor device of this embodiment, hole injection from the p-type semiconductor region can be suppressed.

[0065] In another example of the semiconductor device of the above embodiment, the concentration distribution of the n-type impurity in the n-type semiconductor region may be higher in the area corresponding to the trap region than in other areas. In the semiconductor device of this embodiment, the trap region can function as a current spreading region. Therefore, the semiconductor device of this embodiment can have low on-resistance characteristics.

[0066] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful. [Explanation of symbols]

[0067] 1: Diode 10: Semiconductor layer 12: Cathode region 14: High resistance region 14a: Non-trap area 14b: Trap area 16: Anode region 22: Cathode electrode 24: Anode electrode 110: Semiconductor layer 112: Drain region 114: High resistance region 114a: Non-trap area 114b: Trap area 116: Body region 116a: Main body area 116b: Electric field relaxation region 118: Source area 122: Drain electrode 124: Source electrode 130: Trench gate section 132: Trench gate electrode 134: Gate insulating film

Claims

1. A semiconductor device comprising: A first main electrode; A second main electrode; a semiconductor layer having a lower surface coated with the first main electrode and an upper surface coated with the second main electrode; The semiconductor layer is a p-type semiconductor region that is disposed at a position exposed on the upper surface and is electrically connected to the second main electrode; an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region, the n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, a hole trap is formed in the trap region, The energy level of the hole trap in the trap region is Et, The energy level of the valence band of the trapping region is defined as Ev, If the band gap of the trap region is Eg, then The relationship Et-Ev<Eg / 2 is established. a trench gate portion provided in a trench extending from the upper surface of the semiconductor layer through the p-type semiconductor region to the n-type semiconductor region, the trap region is disposed at a position away from a side surface of the trench gate portion, the p-type semiconductor region has an electric field relaxation region that protrudes downward below a bottom surface of the trench gate portion at a position away from the side surface of the trench gate portion, The trap region is disposed so as to be in contact with a bottom surface of the electric field reduction region.

2. 2. The semiconductor device according to claim 1, wherein a density distribution of said hole traps in a depth direction of said semiconductor layer has a peak in a range corresponding to said trap region.

3. The semiconductor device according to claim 1 , wherein the semiconductor layer is made of silicon carbide.

4. The semiconductor device according to claim 3 , wherein the trapping region includes aluminum.

5. 5. The semiconductor device according to claim 4, wherein the n-type impurity concentration distribution in said n-type semiconductor region is higher in a range corresponding to said trap region than in other ranges.

6. A semiconductor device comprising: A first main electrode; A second main electrode; a semiconductor layer having a lower surface coated with the first main electrode and an upper surface coated with the second main electrode; The semiconductor layer is a p-type semiconductor region that is disposed at a position exposed on the upper surface and is electrically connected to the second main electrode; an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region, the n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, a hole trap is formed in the trap region, The energy level of the hole trap in the trap region is Et, The energy level of the valence band of the trapping region is defined as Ev, If the band gap of the trap region is Eg, then The relationship Et-Ev<Eg / 2 is established. a trench gate portion provided in a trench extending from the upper surface of the semiconductor layer through the p-type semiconductor region to the n-type semiconductor region, the p-type semiconductor region has an electric field relaxation region that protrudes downward from a bottom surface of the trench gate portion at a position away from a side surface of the trench gate portion, The trap region is disposed so as to be in contact with a bottom surface of the electric field reduction region.

7. 7. The semiconductor device according to claim 6, wherein the trap region extends in an in-plane direction of the semiconductor layer from at least the bottom surface of the electric field reduction region to a position below the trench gate portion and is positioned away from the bottom surface of the trench gate portion.

8. 8. The semiconductor device according to claim 7, wherein the n-type impurity concentration distribution in said n-type semiconductor region is higher in a range corresponding to said trap region than in other ranges.

9. A semiconductor device comprising: A first main electrode; A second main electrode; a semiconductor layer having a lower surface coated with the first main electrode and an upper surface coated with the second main electrode; The semiconductor layer is a p-type semiconductor region that is disposed at a position exposed on the upper surface and is electrically connected to the second main electrode; an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region, the n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, a hole trap is formed in the trap region, the semiconductor layer is silicon carbide; the trapping region comprises aluminum; a trench gate portion provided in a trench extending from the upper surface of the semiconductor layer through the p-type semiconductor region to the n-type semiconductor region, the p-type semiconductor region has an electric field relaxation region that protrudes downward from a bottom surface of the trench gate portion at a position away from a side surface of the trench gate portion, The trap region is disposed so as to be in contact with a bottom surface of the electric field reduction region.

10. A semiconductor device comprising: A first main electrode; A second main electrode; a semiconductor layer having a lower surface coated with the first main electrode and an upper surface coated with the second main electrode; The semiconductor layer is a p-type semiconductor region that is disposed at a position exposed on the upper surface and is electrically connected to the second main electrode; an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region, the n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, a hole trap is formed in the trap region, a trench gate portion provided in a trench extending from the upper surface of the semiconductor layer through the p-type semiconductor region to the n-type semiconductor region, the p-type semiconductor region has an electric field relaxation region that protrudes downward from a bottom surface of the trench gate portion at a position away from a side surface of the trench gate portion, The trap region is disposed so as to be in contact with a bottom surface of the electric field reduction region.

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