GGNMOS transistor structures, ESD protection devices and circuits

Abstract

The present invention provides a GGNMOS transistor structure, an ESD protection device, and an ESD protection circuit, in which the GGNMOS transistor structure improves the ESD current discharge capability per unit size of the ESD protection device through the action of a PNPN parasitic thyristor formed by an N-well, a P-type highly doped region, and an N-type highly doped region, and the GGNMOS transistor structure can limit the instantaneous peak current of ESD through the action of an equivalent resistance formed by the N-well, so that each GGNMOS transistor of the ESD protection device is uniformly conductive, thereby improving the reliability of the ESD protection circuit.

Description

[Technical field]

[0001] The present invention relates to the technical field of ESD protection design for integrated circuits, and in particular to GGNMOS transistor structures, ESD protection devices and circuits.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to a Chinese patent application with application number 202110810592.3, entitled "GGNMOS transistor structure, ESD protection device and circuit," filed with the China Patent Office on July 16, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Electrostatic discharge (ESD) is the main cause of electrical over stress (EOS) destruction of electronic components and integrated circuits (ICs). Although the physical size of devices has become smaller as the line width of integrated circuit process nodes has progressed to the deep submicron stage, the instantaneous voltage caused by ESD is still very high (usually exceeding several thousand volts), causing catastrophic and permanent damage and directly leading to circuit burnout. Therefore, ESD protection design has become one of the important issues in integrated circuit reliability research.

[0004] Currently, the most commonly used ESD protection device is GGNMOS (Gate-Ground N-Metal-Oxide-Semiconductor, i.e., gate-grounded NMOS). GGNMOS devices mainly use the conduction of a parasitic NPN transistor to drain the ESD current. Here, the parasitic NPN transistor is composed of a drain, a P-well, and a source, and the conduction of the parasitic NPN transistor depends on the avalanche breakdown voltage of a reverse PN junction of a collector, and the PN junction is composed of a drain and a P-well. When selecting a GGNMOS transistor as an ESD protection device, a large size design is required to make the drained ESD current large enough. In practical applications, due to the constraints of integrated circuit size and the uniformity of ESD current drainage, GGNMOS transistors are usually designed as multi-finger structures, which are equivalent to multiple NMOS structures connected in parallel.

[0005] FIG. 1 is a schematic diagram showing an exemplary GGNMOS transistor structure in the prior art, which includes a P-substrate 100, a P-well 110, a P-type highly doped region 120, a first N-type highly doped region 131, a gate structure 140, a second N-type highly doped region 132, and an insulating structure 150, where the insulating structure 150 is disposed between the P-type highly doped region 120 and the first N-type highly doped region 131, and the gate structure 140 is disposed between the first N-type highly doped region 132 and the first N-type highly doped region 133. The highly doped P-type region 120 and the first highly doped N-type region 131 are both connected to a negative electrode, the second highly doped N-type region 132 is connected to a positive electrode, the first highly doped N-type region 131 is used as a source region, and the second highly doped N-type region 132 is used as a drain region, and the first highly doped N-type region 131, the second highly doped N-type region 132 and the P-type substrate 100 thereunder form a parasitic NPN transistor.

[0006] FIG. 2 is an exemplary ESD protection circuit in the prior art, in which the drain of an NMOS transistor is connected to the positive terminal, the source and gate are connected together and connected to the negative terminal, the positive terminal is connected to an input / output terminal, and the negative terminal is grounded.

[0007] 3 is an IV curve of an exemplary GGNMOS transistor in the prior art in ESD, in which the parasitic NPN transistor of the GGNMOS transistor conducts and discharges when the voltage rises to Vt1, at which point it rapidly transitions to a snap-back state, the voltage drops to Vh, and as the discharge continues, the voltage across the device rises accordingly, reaching the breakdown voltage Vt2 at point A and burning out. Also, the ESD current drain of the GGNMOS transistors of each finger is not uniform, which reduces the ESD protection capability of the entire circuit.

[0008] In order to optimize the ESD current conduction non-uniformity of the GGNMOS transistor, FIG. 4 is a schematic diagram showing another exemplary GGNMOS transistor structure in the prior art, in which an improved single-finger GGNMOS transistor structure includes a P-substrate 200 (P-SUBBSTRATE), a P-well 210, an N-well 260, a P-type highly doped region 220, an insulating structure 230, a first N-type highly doped region 241, a gate structure 250, a second N-type highly doped region 242 and a third N-type highly doped region 243, and the insulating structure 230 is a gate structure 250 that is connected to the P-type highly doped region 220 and the N-type highly doped region 243. a gate structure 250 is provided on the upper surface of the P well 210 between the first N type highly doped region 241 and the second N type highly doped region 242, the P type highly doped region 220 and the first N type highly doped region 241 are connected to a negative electrode, the third N type highly doped region 243 is connected to a positive electrode, the first N type highly doped region 241 is used as a source region, the second N type highly doped region 242 and the third N type highly doped region 243 are used as drain regions, and the N well 260 constitutes an equivalent resistor.

[0009] 5 shows another exemplary ESD protection circuit in the prior art, in which a first end of the resistor R-n_well is connected to a positive electrode, a second end of the resistor R-n_well is connected to a drain of an NMOS transistor, a source and a gate of the NMOS transistor are connected to a negative electrode, a positive electrode is connected to an input / output terminal, and a negative electrode is grounded. Such an ESD protection device with a GGNMOS transistor structure improves the uniformity of the ESD current discharge of each finger, but reduces the ESD current discharge capability per unit size of the GGNMOS transistor of each finger.

[0010] Therefore, there is a need to provide a new GGNMOS transistor structure, ESD protection device and ESD protection circuit to improve the uniformity of ESD current drainage and increase the ESD current drainage capability per unit size. Summary of the Invention [Problem to be solved by the invention]

[0011] In view of the above-mentioned deficiencies of the prior art, the present invention aims to provide a GGNMOS transistor structure, an ESD protection device and an ESD protection circuit for improving the ESD current discharge capability per unit size while solving the problem that the ESD current discharge of the multi-finger GGNMOS transistor is not uniform. [Means for solving the problem]

[0012] To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor device comprising: A P-type substrate; a first N well, a P well, and a second N well disposed laterally in that order on the P-type substrate; a first P-type highly doped region disposed over the first N-well; a first N-type highly doped region disposed on the first N-well, the first N-type highly doped region having an insulating structure disposed between the first N-type highly doped region and the first P-type highly doped region; a second highly doped P-type region over the P-well, the second highly doped P-type region having an insulating structure between the second highly doped P-type region and the first highly doped N-type region; a second N-type highly doped region over the P-well, the second N-type highly doped region having an insulating structure between the second N-type highly doped region and a second P-type highly doped region; a third N-type highly doped region disposed above a junction between the P well and the second N well; a fourth N-type highly doped region disposed on the second N-well, the fourth N-type highly doped region having an insulating structure disposed between the fourth N-type highly doped region and the third N-type highly doped region; a gate structure disposed on a top surface of the P-well between the third heavily doped N-type region and the second heavily doped N-type region, the first P-type highly doped region, the first N-type highly doped region and the fourth N-type highly doped region are all connected to a positive electrode, and the second P-type highly doped region, the second N-type highly doped region and the gate structure are all connected to a negative electrode; A GGNMOS transistor structure is provided.

[0013] Specifically, the second N-type highly doped region is used as a source region, and the third N-type highly doped region and the fourth N-type highly doped region are used as drain regions.

[0014] Specifically, the first N-well and the first P-type highly doped region constitute an equivalent PNP transistor, the first N-well, the first P-type highly doped region and the second N-type highly doped region constitute an equivalent NPN transistor, and the second N-well constitutes an equivalent resistor.

[0015] Specifically, the top surface of the first P-type highly doped region, the top surface of the first N-type highly doped region, the top surface of the second P-type highly doped region, the top surface of the second N-type highly doped region, the top surface of the third N-type highly doped region, and the top surface of the fourth N-type highly doped region are flush with each other.

[0016] Specifically, the first highly doped P-type region, the first highly doped N-type region, the second highly doped P-type region, the second highly doped N-type region, the third highly doped N-type region, and the fourth highly doped N-type region have the same junction depth.

[0017] Specifically, the positive electrode is connected to an input / output terminal, and the negative electrode is grounded.

[0018] The present invention further provides an ESD protection device, comprising at least two of the above-mentioned GGNMOS transistor structures, each of which is connected in parallel.

[0019] Specifically, the number of the GGNMOS transistor structures is an even number.

[0020] The present invention further provides an ESD protection circuit, including at least two ESD protection modules, each ESD protection module being connected in parallel, and each ESD protection module including a resistor, an NMOS transistor, a PNP transistor, and an NPN transistor; A first end of the resistor is connected to a positive terminal, a second end of the resistor is connected to a drain of the NMOS transistor, and a gate and a source of the NMOS transistor are connected to a negative terminal; an emitter of the PNP transistor is connected to a first end of the resistor, a base of the PNP transistor is connected to a collector of the NPN transistor, a collector of the PNP transistor is connected to a base of the NPN transistor, and an emitter of the NPN transistor is connected to a gate and a source of the NMOS transistor; Provides ESD protection circuitry.

[0021] Furthermore, the positive terminal of the ESD protection circuit is connected to the input / output terminal, and the negative terminal is grounded. Effect of the Invention

[0022] As described above, the GGNMOS transistor structure, ESD protection device and ESD protection circuit of the present invention provide the following beneficial effects:

[0023] The first N-well and the first P-type highly doped region of the GGNMOS transistor structure of the present invention constitute an equivalent PNP transistor, the first N-well, the first P-type highly doped region and the second N-type highly doped region constitute an equivalent NPN transistor, and the equivalent PNP transistor and the equivalent NPN transistor constitute a PNPN parasitic thyristor structure. The GGNMOS transistor structure of the present invention utilizes the characteristics of a thyristor, that is, a small on-resistance value, a low on-voltage, and a strong discharge capability per unit size, to improve the ESD current discharge capability per unit size of an ESD protection device and improve the reliability of an ESD protection circuit.

[0024] The second N-well of the GGNMOS transistor structure of the present invention constitutes an equivalent resistance, which allows each GGNMOS transistor of the ESD protection device to conduct uniformly and drain ESD current uniformly, improving the uniformity of the ESD protection circuit.

[0025] All the P-type highly doped regions and N-type highly doped regions of the GGNMOS transistor structure of the present invention can be done simultaneously in the MOS process, saving ESD ion implantation photomasks and processes, saving costs, reducing process complexity, and reducing the contamination problems caused during processing. [Brief description of the drawings]

[0026] [Figure 1]FIG. 1 is a schematic diagram illustrating an exemplary GGNMOS transistor structure in the prior art. [Diagram 2] FIG. 1 illustrates an exemplary ESD protection circuit in the prior art. [Diagram 3] FIG. 1 shows an IV curve of an exemplary GGNMOS transistor under ESD in the prior art. [Figure 4] FIG. 1 is a schematic diagram illustrating another exemplary GGNMOS transistor structure in the prior art. [Diagram 5] FIG. 1 illustrates another exemplary ESD protection circuit in the prior art. [Figure 6] FIG. 1 is a schematic diagram illustrating a GGNMOS transistor structure provided according to embodiment 1 of the present invention. [Figure 7] FIG. 10 illustrates an ESD protection circuit provided according to embodiment 3 of the present invention. [Figure 8] FIG. 11 is a diagram showing an IV curve of the ESD protection device of the second embodiment of the present invention under ESD. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, the embodiments of the present invention will be described with specific examples, but those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Furthermore, the present invention can be implemented or applied in different specific embodiments, and the details of the specification can be modified or changed in various ways based on different perspectives and applications without departing from the spirit of the present invention.

[0028] It should be noted that the drawings (FIGS. 6 to 8) provided in this embodiment merely show a schematic representation of the basic concept of the present invention, and therefore the drawings only show components related to the present invention and are not drawn according to the number, shape, or size of the components when implemented; the type, number, and proportion of each component when implemented can be freely changed, and the layout of the components may be more complex.

[0029] <Embodiment 1> As shown in FIG. 6 , this embodiment includes a P-type substrate (P-SUBSTRATE) 300, a first N well 311, a P well 320, and a second N well 312 that are provided laterally on the P-type substrate in this order, a first P-type highly doped region 331 provided on the first N well 311, a first N-type highly doped region 341 provided on the first N well 311, the first N-type highly doped region 341 having an insulating structure 350 provided between the first N-type highly doped region 341 and the first P-type highly doped region 331, a second P-type highly doped region 332 provided on the P well 320, the second P-type highly doped region 332 having an insulating structure 350 provided between the second P-type highly doped region 332 and the first N-type highly doped region 341, and a second P-type highly doped region 332 having an insulating structure 350 provided between the second P-type highly doped region 332 and the first N-type highly doped region 341. 3. A GGNMOS transistor structure comprising: a second N-type highly doped region 342 disposed on the P-well 320, with an insulating structure 350 disposed between the second N-type highly doped region 342 and a second P-type highly doped region 332; a third N-type highly doped region 343 disposed on the P-well 320 and the second N-well 312, with a gate structure 360 ​​formed on a channel between the third N-type highly doped region 343 and the second N-type highly doped region 342; and a fourth N-type highly doped region 344 disposed on the second N-well 312, with an insulating structure 350 disposed between the fourth N-type highly doped region 344 and the third N-type highly doped region 343, The first P-type highly doped region 331, the first N-type highly doped region 341 and the fourth N-type highly doped region 344 are all connected to a positive electrode, and the second P-type highly doped region 332, the second N-type highly doped region 342 and the gate structure 360 ​​are all connected to a negative electrode; A GGNMOS transistor structure is provided.

[0030] Specifically, as shown in FIG. 6, the P-type substrate 300 is disposed at the bottom layer, and the material of the P-type substrate 300 includes, but is not limited to, sapphire, silicon carbide, silicon, and graphene. Any material that can be used as a substrate is suitable, and the description thereof will be omitted here.

[0031] Specifically, as shown in FIG. 6, the first N well 311, the P well 320 and the second N well 312 are provided on the P type substrate 300, the P well 320 is between the first N well 311 and the second N well 312, the first N well 311 and the second N well 312 are N type lightly doped, the P well 320 is P type lightly doped, and the doping concentration can be set according to actual needs.

[0032] Specifically, as shown in FIG. 6 , the first P-type highly doped region 331 and the first N-type highly doped region 341 are disposed on the first N-well 311, the first P-type highly doped region 331 and the first N-type highly doped region 341 are separated from each other by an insulating structure 350, the insulating structure 350 having a depth greater than that of the first P-type highly doped region 331 and the first N-type highly doped region 341, the second P-type highly doped region 332 and the second N-type highly doped region 342 are disposed on the P-well 320, the second P-type highly doped region 332 and the second N-type highly doped region 342 .... the second P-type highly doped region 332 and the second N-type highly doped region 342; the third N-type highly doped region 343 is provided over the P-well 320 and the second N-well 312; the fourth N-type highly doped region 344 is provided over the second N-well 312; the third N-type highly doped region 343 and the fourth N-type highly doped region 344 are separated from each other by an insulating structure 350; the insulating structure 350 has a depth greater than a depth of the third N-type highly doped region 343 and the fourth N-type highly doped region 344. The first P-type highly doped region 331 and the second P-type highly doped region 332 are highly P-type doped, and the first N-type highly doped region 341, the second N-type highly doped region 342, the third N-type highly doped region 343 and the fourth N-type highly doped region 344 are highly N-type doped, and the doping concentrations can be set according to actual needs, and the description is omitted here.

[0033] 6, the upper surface of the first P-type highly doped region 331, the upper surface of the first N-type highly doped region 341, the upper surface of the second P-type highly doped region 332, the upper surface of the second N-type highly doped region 342, the upper surface of the third N-type highly doped region 343, and the upper surface of the fourth N-type highly doped region 344 are flush with each other. However, this can be set according to the actual process environment conditions, and the description will be omitted here.

[0034] 6, the first P-type highly doped region 331, the first N-type highly doped region 341, the second P-type highly doped region 332, the second N-type highly doped region 342, the third N-type highly doped region 343, and the fourth N-type highly doped region 344 have the same depth. However, this can be set according to the actual process environment conditions, and the description will be omitted here.

[0035] Specifically, as shown in FIG. 6 , the second N-type highly doped region 342 is used as a source region, the third N-type highly doped region 343 and the fourth N-type highly doped region 344 are used as drain regions, the source region, the drain region and the gate structure 360 ​​constitute a GGNMOS transistor, and the source region, the third N-type highly doped region 343 and the P-well 320 form a parasitic NPN transistor.

[0036] Specifically, as shown in FIG. 6, the first P-type highly doped region 331 and the first N-well 311 form an equivalent PNP transistor, the first N-well 311, the first P-type highly doped region 331 and the second N-type highly doped region 342 form an equivalent NPN transistor, the equivalent PNP transistor and the equivalent NPN transistor form a PNPN parasitic thyristor structure, and the second N-well 312 forms an equivalent resistor.

[0037] <Embodiment 2> This embodiment provides an ESD protection device, which includes at least two GGNMOS transistor structures according to embodiment 1, and the GGNMOS transistor structures are shown in Fig. 6, and each of the GGNMOS transistor structures is connected in parallel. From the viewpoint of semiconductor device structure, the at least two GGNMOS transistor structures according to embodiment 1 are referred to as an ESD protection device.

[0038] Specifically, the structure of each GGNMOS transistor can be described in the first embodiment, and the description will be omitted here. The positive electrodes of each GGNMOS transistor structure are connected to each other, and the negative electrodes are connected to each other, thereby realizing a parallel structure. As an example, the positive electrodes of each GGNMOS transistor structure are connected to the input / output terminal, and the negative electrodes of each GGNMOS transistor structure are grounded. When a positive ESD pulse is applied to the GGNMOS transistor, the ESD current flows from the positive electrode to the drain of the GGNMOS transistor, raising the drain voltage. When the voltage rises to the avalanche breakdown voltage of the parasitic NPN transistor of the GGNMOS transistor, the parasitic NPN transistor becomes conductive and discharges the ESD current. In the prior art, the resistance of the ESD circuit of the middle finger of the multi-finger GGNMOS transistor structure is the highest, which is higher than the resistance of the ESD circuit of the surrounding fingers, so that the parasitic NPN transistor of the middle finger conducts before the surrounding fingers, resulting in uneven ESD current discharge of the fingers, which causes uneven ESD current discharge capability of the multi-finger GGNMOS transistor, and reduces the ESD protection capability of the entire circuit. On the other hand, the ESD protection device of the present embodiment can limit the instantaneous peak current of ESD by the action of the equivalent resistance, and the parasitic NPN transistor of each finger conducts uniformly to discharge the ESD current uniformly, and the action of the PNPN parasitic thyristor structure utilizes the characteristics of the thyristor, which have a small on-resistance value, a low on-voltage, and a strong discharge capability per unit size, to improve the ESD current discharge capability per unit size of the ESD protection device.

[0039] As an example, the number of the GGNMOS transistor structures included in the ESD protection device is an even number.

[0040] It should be noted that in this embodiment, the ESD protection device includes four GGNMOS transistor structures as shown in FIG. 6 connected in parallel, but in actual applications, an appropriate number of GGNMOS transistor structures may be selected and connected in parallel according to the needs of actual ESD protection capability, including but not limited to 2-finger, 3-finger, 5-finger, 6-finger, and 8-finger, and is not limited by this embodiment.

[0041] Specifically, FIG. 8 is an IV curve of ESD when the ESD protection device of this embodiment is used. When there is an ESD pulse, the GGNMOS transistor first reaches a trigger voltage Vt1, the parasitic NPN transistor conducts and discharges the ESD current, and then quickly transitions to a snap-back state, and the voltage drops to Vh1. Due to the effect of the equivalent resistance, the on-resistance value of the ESD circuit is large, and the ESD pulse further rises and continues to discharge, so that the voltage applied to the GGNMOS transistor rises rapidly, and the GGNMOS transistors of each finger are uniformly conducted. After reaching the voltage Vt2, a large amount of current flows into the P well 320, so the potential of the P well 320 rises rapidly. Due to the effect of the PN-PN parasitic thyristor described in embodiment 1, most of the ESD current is quickly discharged from the PNPN parasitic thyristor.

[0042] <Embodiment 3> As shown in FIG. 7, this embodiment is an ESD protection circuit including at least two ESD protection modules, each ESD protection module being connected in parallel, and each ESD protection module includes a resistor R-n_well, an NMOS transistor, a PNP transistor, and an NPN transistor; A first end of the resistor R-n_well is connected to a positive electrode, a second end of the resistor R-n_well is connected to a drain of the NMOS transistor, and a gate and a source of the NMOS transistor are connected to a negative electrode; The emitter of the PNP transistor is connected to the first end of the resistor R-n_well, the base of the PNP transistor is connected to the collector of the NPN transistor, the collector of the PNP transistor is connected to the base of the NPN transistor, and the emitter of the NPN transistor is connected to the gate and source of the NMOS transistor; Provides ESD protection circuitry.

[0043] Specifically, as an example, the NMOS transistor has a parasitic NPN transistor, the details of which can be referred to in embodiment 2, and the description is omitted here. In practical application, any triode structure is suitable for the present invention, and is not limited by this embodiment. From the viewpoint of electric circuits, at least two GGNMOS transistor structures of embodiment 1 are called ESD protection modules.

[0044] Specifically, as an example, the resistor R-n_well is used to improve the uniformity of the conduction of the parasitic NPN transistor. In practical application, any resistor structure is suitable for the present invention and is not limited by this embodiment.

[0045] Specifically, as an example, the positive electrode of the ESD protection circuit in this embodiment is connected to the input / output terminal, and the negative electrode is grounded.

[0046] Specifically, as an example, the PNP transistor and the NPN transistor form a PNPN parasitic thyristor structure. In practical application, any thyristor structure is suitable for the present invention and is not limited by this embodiment.

[0047] Specifically, when a positive ESD pulse is applied to the ESD protection circuit of this embodiment, the ESD current is uniformly discharged by the action of the resistor R-n_well and the PNPN parasitic thyristor structure, thereby improving the ESD current discharge capability per unit size.

[0048] In summary, the present invention provides a GGNMOS transistor structure, an ESD protection device and an ESD protection circuit, the GGNMOS transistor structure comprising a P-type substrate, a first N-well, a P-well and a second N-well disposed laterally on the P-type substrate in that order, a first P-type highly doped region disposed on the first N-well, a first N-type highly doped region disposed on the first N-well, the first N-type highly doped region being disposed with an insulating structure between the first N-type highly doped region and the first P-type highly doped region, and a second P-type highly doped region disposed on the P-well, the second P-type highly doped region being disposed with an insulating structure between the second P-type highly doped region and the first N-type highly doped region. a second highly doped N-type region provided on the P-well, the second highly doped N-type region having an insulating structure between the second highly doped N-type region and the second highly doped P-type region, a third highly doped N-type region provided on a junction between the P-well and the second N-well, a fourth highly doped N-type region provided on the second N-well, the fourth highly doped N-type region having an insulating structure between the fourth highly doped N-type region and the third highly doped N-type region, and a gate structure provided on an upper surface of the P-well between the third highly doped N-type region and the second highly doped N-type region, wherein the first highly doped P-type region, the first highly doped N-type region, and the fourth highly doped N-type region are all connected to a positive electrode, and the second highly doped P-type region, the second highly doped N-type region, and the gate structure are all connected to a negative electrode. The GGNMOS transistor structure of the present invention utilizes the characteristics of the thyristor, such as a small on-resistance value, a low on-voltage, and a strong discharge capability per unit size, to improve the ESD current discharge capability per unit size of the ESD protection device and improve the reliability of the ESD protection circuit. The second N-well of the GGNMOS transistor structure of the present invention forms an equivalent resistance, which allows each GGNMOS transistor of the ESD protection device to be uniformly conductive and uniformly discharge the ESD current, thereby improving the uniformity of the ESD protection circuit.All the P-type highly doped regions and N-type highly doped regions of the GGNMOS transistor structure of the present invention can be simultaneously performed in the MOS process, saving the ESD ion implantation photomask and process, saving the cost, reducing the process complexity, and reducing the contamination problem caused during the process treatment. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

[0049] The above-described embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Those skilled in the art may modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those having ordinary knowledge in the technical field to which the present invention pertains without departing from the spirit and technical ideas disclosed in the present invention are still intended to be included in the scope of the claims of the present invention. [Explanation of symbols]

[0050] 300 P-SUBBSTRATE 311 1st N-well 312 Second N-well 320 P-well 331 First P-type highly doped region 332 Second P-type highly doped region 341 First N-type highly doped region 342 Second N-type highly doped region 343 Third N-type highly doped region 344 4th N-type highly doped region 350 Insulation structure 360 Gate Structure

Claims

1. A P-type substrate; a first N well, a P well, and a second N well disposed laterally in that order on the P-type substrate; a first P-type highly doped region disposed over the first N-well; a first N-type highly doped region disposed on the first N-well, the first N-type highly doped region having an insulating structure disposed between the first N-type highly doped region and the first P-type highly doped region; a second highly doped P-type region over the P-well, the second highly doped P-type region having an insulating structure between the second highly doped P-type region and the first highly doped N-type region; a second N-type highly doped region disposed over the P-well, the second N-type highly doped region having an insulating structure disposed between the second N-type highly doped region and a second P-type highly doped region; a third N-type highly doped region disposed above a junction between the P well and the second N well; a fourth N-type highly doped region provided on the second N-well, the fourth N-type highly doped region having an insulating structure provided between the fourth N-type highly doped region and the third N-type highly doped region; a gate structure disposed on a top surface of the P-well between the third heavily doped N-type region and the second heavily doped N-type region, the first P-type highly doped region, the first N-type highly doped region and the fourth N-type highly doped region are all connected to a positive electrode, and the second P-type highly doped region, the second N-type highly doped region and the gate structure are all connected to a negative electrode; 1. A GGNMOS transistor structure comprising:

2. the second N-type highly doped region is used as a source region, and the third N-type highly doped region and the fourth N-type highly doped region are used as drain regions; 2. The GGNMOS transistor structure of claim 1.

3. The P well, the first N well and the first P type highly doped region constitute an equivalent PNP transistor, the first N well, the P well and the second N type highly doped region constitute an equivalent NPN transistor, and the second N well constitutes an equivalent resistor.

2. The GGNMOS transistor structure of claim 1.

4. The equivalent PNP transistor and the equivalent NPN transistor form a PNPN parasitic thyristor structure.

4. The GGNMOS transistor structure of claim 3.

5. an upper surface of the first highly doped P-type region, an upper surface of the first highly doped N-type region, an upper surface of the second highly doped P-type region, an upper surface of the second highly doped N-type region, an upper surface of the third highly doped N-type region, and an upper surface of the fourth highly doped N-type region are flush with each other; 2. The GGNMOS transistor structure of claim 1.

6. the first highly doped P-type region, the first highly doped N-type region, the second highly doped P-type region, the second highly doped N-type region, the third highly doped N-type region, and the fourth highly doped N-type region have the same junction depth.

2. The GGNMOS transistor structure of claim 1.

7. the first N-well and the second N-well are N-type lightly doped, and the P-well is P-type lightly doped; 2. The GGNMOS transistor structure of claim 1.

8. the isolation structure has a depth greater than a depth of the first P-type highly doped region, a depth of the first N-type highly doped region, a depth of the second P-type highly doped region, a depth of the second N-type highly doped region, a depth of the third N-type highly doped region, and a depth of the fourth N-type highly doped region.

2. The GGNMOS transistor structure of claim 1.

9. The positive terminal is connected to an input / output terminal, and the negative terminal is grounded.

2. The GGNMOS transistor structure of claim 1.

10. 7. An ESD protection device comprising at least two GGNMOS transistor structures according to any one of claims 1 to 6, each of said GGNMOS transistor structures being connected in parallel.

1. An ESD protection device comprising:

11. the number of said GGNMOS transistor structures is an even number; 11. The ESD protection device of claim 10.

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