Silicon Carbide Substrate

Abstract

To provide a silicon carbide substrate that has an SJ structure, is easy to manufacture, and has improved characteristics.SOLUTION: A drift layer 2 consists of first to third partially parallel pn layers 51-53 stacked in sequence. The first and third partially parallel pn layers 51 and 53 are trench embedded parallel pn layers. The second partially parallel pn layer 52 is a multi-epitaxial parallel pn layer, and its thickness t2 is thin, about 0.65 μm±0.05 μm. The n-type regions 62,67 and p-type regions 63,68 of the first and third partially parallel pn layers 51,53 are connected to each other by the n-type region 64 and p-type region of the second partially parallel pn layer 52, respectively. The stripe shapes of the n-type regions 62,67 and p-type regions 63,68 of the first and third partially parallel pn layers 51,53 and the stripe shapes of the n-type regions 64 and p-type regions of the second partially parallel pn layer 52 intersect at an angle of 45 degrees or more.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a silicon carbide substrate. [Background technology]

[0002] Conventionally, there has been known a super junction semiconductor device having a super junction (SJ) structure in which a drift layer is a parallel pn layer in which n-type regions and p-type regions with high impurity concentrations are alternately arranged adjacent to each other in a direction parallel to the main surface of a semiconductor substrate. A multi-stage epitaxial (multi-epitaxial) method or a trench-filled epitaxial method is used to form a drift layer with an SJ structure.

[0003] In forming the SJ structure, the multi-stage epitaxial method involves gradually thickening the n-type epitaxial layer by multiple stages of epitaxial growth until it reaches a specified thickness, and repeating ion implantation to selectively form a p-type region after each stage of epitaxial growth. In the trench-filling epitaxial method, a trench is formed in an n-type epitaxial layer that has been grown to a specified thickness by one stage of epitaxial growth, and the inside of the trench is filled with a p-type epitaxial layer.

[0004] In a high-voltage super-junction semiconductor device using silicon carbide (SiC) as a semiconductor material, it is necessary to thicken the drift layer. For this reason, it is easier to fabricate (manufacture) the epitaxial layer that becomes the drift layer by growing it to a predetermined thickness in one stage of epitaxial growth, and then filling the trench by epitaxial growth after forming the trench, using a trench-filling epitaxial method, rather than a multistage epitaxial method in which the epitaxial layer that becomes the drift layer is thickened stepwise by multiple stages of epitaxial growth to a predetermined thickness.

[0005] When using the trench-filled epitaxial method, a trench is formed in the n-type epitaxial layer that becomes the drift layer, and a p-type epitaxial layer is filled in the trench to create an SJ structure. The thicker the drift layer is, the deeper the trench must be formed, so it is difficult to form the trench by etching (hereafter referred to as trench etching) and to completely fill the inside of the trench with the epitaxial layer.

[0006] The reason why trench etching becomes more difficult as the drift layer becomes thicker is because trench etching is anisotropic dry etching. As the trench becomes deeper, it becomes more difficult to form a good trench shape with sidewalls that are approximately perpendicular to the main surface of the semiconductor substrate by dry etching, and the width of the trench tends to be wide near the top of the opening and narrow near the bottom (lower part of the opening). In addition, the roughness of the trench sidewalls (height difference between the concave and convex) tends to increase.

[0007] In addition, the oxide film (SiO2 film) used as a mask for trench etching must be thick enough not to disappear during dry etching. This makes it difficult to form the oxide film used as a mask for trench etching, and to perform dry etching to selectively remove the oxide film and open the portion corresponding to the trench formation region. Another problem is that the oxide film increases the stress generated in the semiconductor substrate.

[0008] The deeper the trench, the higher the aspect ratio (= trench depth / trench width) of the trench, which means the epitaxial growth time is longer. In addition, the epitaxial layers epitaxially grown on both sides of the trench join together near the top of the trench opening, blocking the top of the trench opening and making it impossible to fill the epitaxial layers, which makes it easy for voids to form inside the trench.

[0009] For these reasons, in a high-voltage super-junction semiconductor device using silicon carbide as a semiconductor material, it is difficult to make substantially the entire drift layer in the depth direction an SJ structure (hereinafter referred to as a full SJ structure), and it has been practical to make the drift layer an SJ structure only in the portion on the front surface side of the semiconductor substrate (hereinafter referred to as a partial SJ structure). The structure of a conventional super-junction semiconductor device with a partial SJ structure will be described. Figure 22 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0010] A conventional silicon carbide semiconductor device 110 shown in Fig. 22 is a superjunction MOSFET (Metal Oxide Semiconductor Field Effect Transistor) of a planar gate structure having a drift layer 102 of a partial SJ structure on a semiconductor substrate 120 made of silicon carbide. + The epitaxial layers 122 to 124 are laminated in order on a mold starting substrate 121. + The starting substrate 121 is n + The gate electrode 102 is a type drain region 101 .

[0011] The epitaxial layers 122 and 123 constitute the drift layer 102 having a partial SJ structure. - The n-type epitaxial layer 122 is a portion on the drain side of the drift layer 102 and occupies more than half of the thickness of the drift layer 102. - The epitaxial layer 122 is a normal n-type epitaxial layer that does not have an SJ structure. - When the SJ structure is formed by the trench-filling epitaxial method, the trench depth of the SJ structure is limited to 20 μm to 25 μm, depending on the width of the trench and the filling by the epitaxial growth.

[0012] As described above, since there is a limit to the depth of the trench in the SJ structure by the trench filling epitaxial method, if the drift layer 102 is 65 μm thick, and the trench in the SJ structure is 20 μm to 25 μm deep, -The thickness of the drift region 102a is about 45 μm to 40 μm. The epitaxial layer 123 is a parallel pn layer 105 in which n-type regions 103 and p-type regions 104 are alternately and repeatedly arranged adjacent to each other in a direction parallel to the main surface of the semiconductor substrate 120, and is the source side portion of the drift layer 102.

[0013] A p-type base region 106 is selectively provided adjacent to the p-type region 104 in the depth direction inside the n-type epitaxial layer 124. The portion of the n-type epitaxial layer 124 other than the p-type base region 106 is a JFET (Junction FET) region 109. Reference numerals 107, 108, and 111 to 115 respectively denote n + Type source region, p + These are a type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode.

[0014] A conventional method for forming an SJ structure has been proposed in which a gas containing a p-type dopant and an n-type dopant incorporated at a different atomic position from the p-type dopant is introduced to epitaxially grow a p-type epitaxial layer, thereby embedding a p-type epitaxial layer with a uniform carrier concentration distribution without leaving any voids inside a trench with a high aspect ratio (3 or more and 15 or less) formed in the n-type epitaxial layer (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0015] [Patent Document 1] JP 2018-142682 A Summary of the Invention [Problem to be solved by the invention]

[0016] In a super-junction semiconductor device, the higher the breakdown voltage, the greater the on-resistance reduction effect of the SJ structure, but to achieve a high breakdown voltage, the drift layer must be made thicker. However, when the drift layer becomes thicker, it is difficult to make the drift layer a full SJ structure, as described above. In addition, when the drift layer is made into a partial SJ structure, the on-resistance reduction effect of the SJ structure is lower than that of a full SJ structure. For example, in a super-junction semiconductor device with a breakdown voltage of 6.5 kV, the drift layer has a thickness of about 65 μm, so that the following problems arise when making the drift layer into a full SJ structure.

[0017] When using a multistage epitaxial method to form a drift layer of the above thickness into a full SJ structure, several tens of stages of epitaxial growth are required to reach a specified thickness for the epitaxial layer that will become the drift layer. Even if the total number of stages of epitaxial growth is reduced by increasing the thickness of each stage of epitaxial growth, and ion implantation, which is repeated for each stage of epitaxial growth, is performed using an ion implantation device capable of achieving high acceleration energy of several MeV, it is not realistic to form a full SJ structure using the multistage epitaxial method.

[0018] On the other hand, when using the trench-filling epitaxial method to form a drift layer of the above thickness into a full SJ structure, it is extremely difficult to form a drift layer into a full SJ structure because it requires the formation of a trench with a depth of about 60 μm and a high aspect ratio, and epitaxial growth that is extremely difficult to completely fill the inside of the trench with an epitaxial layer. For this reason, the trench width must be made wider in order to perform trench etching and epitaxial growth without any problems.

[0019] If the trench width is widened, the speed at which the epitaxial layer fills the trench decreases, and it takes a long time to form the SJ structure. Furthermore, if the trench width is too wide, the epitaxial layer is only formed along the inner wall of the trench, and the inside of the trench cannot be completely filled with the epitaxial layer, which increases the challenges of the epitaxial layer filling technology. Also, if the trench width is widened, the repetition pitch of the n-type and p-type regions of the parallel pn layer becomes wider, which reduces the effect of the SJ structure in reducing the on-resistance.

[0020] Thus, whether the multi-stage epitaxial method or the trench-filling epitaxial method is used, it becomes difficult to form the SJ structure, and the characteristics of the super-junction semiconductor device deteriorate.

[0021] In order to solve the problems associated with the conventional techniques described above, an object of the present invention is to provide a silicon carbide substrate that has an SJ structure, is easy to manufacture, and has improved characteristics. [Means for solving the problem]

[0022] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide substrate according to the present invention includes a first conductivity type region and a second conductivity type region arranged parallel to a main surface. Extending in a stripe shape and in a direction perpendicular to the stripe extending direction A silicon carbide substrate having alternating parallel pn layers, the substrate having the following characteristics: . before The first partial parallel pn layer is laminated on a starting substrate made of silicon carbide. Forming a part of the parallel pn layer . The second partial parallel pn layer is stacked on the first partial parallel pn layer and forms a part of the parallel pn layer. The third partial parallel pn layer is laminated on the second partial parallel pn layer. The first partial parallel p-n layer includes a first epitaxial layer of a first conductivity type made of silicon carbide stacked on the starting substrate, first trenches extending from a surface of the first epitaxial layer to a predetermined depth, the first conductivity type regions being portions of the first epitaxial layer between adjacent first trenches, and the second conductivity type region being a second epitaxial layer of a second conductivity type embedded in the first trench.

[0023] before Second partially parallel pn layer a third epitaxial layer of a first conductivity type made of silicon carbide laminated on the first epitaxial layer, The second conductivity type region of The third epitaxial layer Crystal defects are introduced throughout the entire structure. The direction in which the first conductivity type region and the second conductivity type region of the third partial parallel p-n layer extend in stripes parallel to the main surface intersects the direction in which the first conductivity type region and the second conductivity type region of the second partial parallel p-n layer extend in stripes parallel to the main surface. The third partial parallel pn layer is Stacked on the third epitaxial layer First conductivity type made of silicon carbide The fourth an epitaxial layer; Fourth From the surface of the epitaxial layer to the second partial parallel pn layer and terminate inside the second partial parallel pn layer. Second A trench and the Fourth The adjacent epitaxial layers Second the first conductive region being a portion between the trenches; Second Second conductivity type buried in trench The fifth and the second conductivity type region being an epitaxial layer.

[0024] The first conductivity type region and the second conductivity type region of the second partial parallel pn layer have the same impurity concentrations as the first conductivity type region and the second conductivity type region of the first partial parallel pn layer, respectively. The first conductivity type region and the second conductivity type region of the third partial parallel pn layer have the same impurity concentrations as the first conductivity type region and the second conductivity type region of the first partial parallel pn layer, respectively.

[0025] In the silicon carbide substrate according to the present invention, the second partial parallel pn layer is ,before The semiconductor device is characterized in having the second conductivity type region, which is a diffusion region containing a second conductivity type impurity introduced into the third epitaxial layer, and the first conductivity type region, which is a portion of the third epitaxial layer excluding the diffusion region. In addition, in the silicon carbide substrate according to the present invention, in the above-mentioned invention, the second conductivity type region of the third partial parallel pn layer terminates inside the second partial parallel pn layer.

[0026] In the silicon carbide substrate according to the present invention, in the above-mentioned invention, the second partial parallel pn layer is made of silicon carbide having a lower impurity concentration than the first conductivity type region. The above The semiconductor device is characterized by having a third epitaxial layer, the second conductivity type region being a diffusion region containing a second conductivity type impurity introduced into the third epitaxial layer, and the first conductivity type region being a diffusion region containing a first conductivity type impurity introduced into the third epitaxial layer.

[0027] Further, the silicon carbide substrate according to the present invention is ,before the first conductivity type region and the second conductivity type region of the second partial parallel pn layer Parallel to the main surface The direction in which the first conductive type region and the second conductive type region of the first partial parallel pn layer extend in a stripe shape is Parallel to the main surface It is characterized in that it forms an angle of 45 degrees or more with the direction in which it extends in a stripe shape.

[0028] In addition, in the silicon carbide substrate according to the present invention, the first conductivity type region and the second conductivity type region of the second partial parallel pn layer are Parallel to the main surface The direction in which the first conductive type region and the second conductive type region of the first partial parallel pn layer extend in a stripe shape is Parallel to the main surface It is characterized in that the direction is perpendicular to the direction in which the electrodes extend in a stripe shape.

[0029] In addition, in the silicon carbide substrate according to the present invention, the second partial parallel pn layer has a periodic concentration distribution in the depth direction.

[0030] In addition, in the silicon carbide substrate according to the present invention, the second partial parallel pn layer is thinner than the first partial parallel pn layer.

[0031] In addition, in the silicon carbide substrate according to the present invention, the third partial parallel pn layer is thicker than the second partial parallel pn layer. In addition, the silicon carbide substrate of the present invention is characterized in that, in the above-mentioned invention, the first conductivity type region and the second conductivity type region of the first partial parallel pn layer are connected to the first conductivity type region and the second conductivity type region of the third partial parallel pn layer, respectively, via the second partial parallel pn layer.

[0032] According to the above-mentioned invention, the drift layer has a structure in which partial parallel pn layers (trench-buried parallel pn layers) formed by a trench-buried epitaxial method and partial parallel pn layers (multistage epitaxial parallel pn layers) formed by a multistage epitaxial method are alternately stacked in three or more layers, so that the majority of the total thickness of the thick drift layer for achieving a high breakdown voltage can be made into an SJ structure (full SJ structure).

[0033] Furthermore, according to the above-described invention, trench-buried parallel pn layers (first and third partial parallel pn layers) having a thickness thinner than the total thickness of the drift layer are formed. Therefore, when forming the trench-buried parallel pn layers, the depth of the SJ trenches (first and second trenches) can be made shallower than the total thickness of the drift layer, which makes it easy to both etch the SJ trench and to bury the epitaxial layer inside the SJ trench.

[0034] According to the above-mentioned invention, the total thickness of the drift layer can be easily increased by using the trench-buried parallel pn layer among the three or more partial parallel pn layers constituting the drift layer. Also, the more the number of trench-buried parallel pn layers is increased, the thinner the trench-buried parallel pn layers can be, and the narrower the width of the SJ trench can be. Therefore, the width of the n-type region and the p-type region of the trench-buried parallel pn layer can be narrowed, thereby increasing the effect of reducing the on-resistance. Effect of the Invention

[0035] ADVANTAGEOUS EFFECTS OF THE PRESENT DISCLOSURE According to the silicon carbide substrate of the present invention, it is possible to easily manufacture a silicon carbide substrate having an SJ structure and a silicon carbide semiconductor device having an SJ structure, and it is possible to improve the characteristics of the silicon carbide substrate and the silicon carbide semiconductor device. [Brief description of the drawings]

[0036] [Figure 1] 1 is a plan view showing a layout of a silicon carbide semiconductor device in accordance with a first embodiment, as viewed from the front surface side of a semiconductor substrate. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 3 is a plan view showing an example of a layout of the drift layer of the SJ structure in FIG. 2 as viewed from the front surface side of the semiconductor substrate. [Figure 4] 3 is a plan view showing an example of a layout of the drift layer of the SJ structure in FIG. 2 as viewed from the front surface side of the semiconductor substrate. [Diagram 5] 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to a first embodiment. [Figure 6] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 7] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 8] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 9]1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 10] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 11] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 12] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 13] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 14] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 15] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 16] 1 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 17] FIG. 11 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 18] FIG. 11 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to a second embodiment. [Figure 19] FIG. 11 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a third embodiment. [Figure 20] FIG. 11 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a fourth embodiment. [Figure 21] FIG. 2 is a characteristic diagram showing the doping concentration of an ion implantation region of a multistage epitaxial parallel pn layer. [Figure 22] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] A preferred embodiment of the silicon carbide substrate according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to similar configurations, and duplicated explanations are omitted. In addition, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index represents a negative index.

[0038] (Embodiment 1) The structure of the silicon carbide semiconductor device according to the first embodiment will be described by taking a super junction MOSFET with a trench gate structure as an example. Fig. 1 is a plan view showing a layout of the silicon carbide semiconductor device according to the first embodiment as viewed from the front surface side of a semiconductor substrate. Fig. 2 is a cross-sectional view showing a cross-sectional structure taken along line A-A' in Fig. 1. Fig. 2 shows a section from the outermost unit cell (on the chip end side) of a plurality of unit cells (constitutive units of an element) arranged in an active region 10 to the chip end (end of a semiconductor substrate (silicon carbide substrate) 40).

[0039] Figures 3 and 4 are plan views showing an example of a layout of the drift layer 2 of the super junction (SJ) structure of Figure 2 as viewed from the front surface side of the semiconductor substrate. Figures 3 and 4 (a) to (c) show layouts of the SJ structure along the cutting lines B-B', C-C', and D-D' in Figure 2, respectively. In Figure 3, the number of p-type regions (second conductivity type regions) 63, 65, and 68 of the first to third partial parallel pn layers 51 to 53 is simplified and shown to be fewer than in Figure 2, and n-type regions (first conductivity type regions) 62, 64, and 67 are shown by dotted hatching, and p-type region 65 is shown by oblique hatching (similar to Figure 4).

[0040] 1 according to the first embodiment is a super junction MOSFET including an active region 10, an intermediate region 20, and an edge termination region 30 in a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and having an SJ structure (full SJ structure) in substantially the entire drift layer 2 in the depth direction Z from the active region 10 to the edge termination region 30. The drift layer 2 having the full SJ structure means that an SJ structure is formed on the source side of the drift layer 2 with a thickness t5 that is, for example, 80% or more of a total thickness t4 of the drift layer 2.

[0041] A semiconductor element having a predetermined element structure is disposed in the active region 10. The active region 10 is a region through which a main current flows when the semiconductor element is in an on-state. The intermediate region 20 is a region between the active region 10 and the edge termination region 30, and is adjacent to the active region 10 and surrounds the periphery of the active region 10. The edge termination region 30 is a region between the intermediate region 20 and the end of the semiconductor substrate 40, and surrounds the periphery of the active region 10 via the intermediate region 20, and maintains a breakdown voltage by mitigating the electric field on the front surface side of the semiconductor substrate 40. The breakdown voltage is the limit voltage at which the semiconductor device does not malfunction or break down.

[0042] In the edge termination region 30, a breakdown voltage structure such as a junction termination extension (JTE) structure 34, a field limiting ring (FLR), or a field plate (FP) is disposed on the front surface side of the semiconductor substrate 40. In addition, as one of the JTE structures, a breakdown voltage structure of a spatial modulation structure in which multiple p-type high concentration impurity regions and p-type low concentration impurity regions are alternately combined with each other while changing the width of each region may be used. Figure 2 illustrates the case where the JTE structure 34 is disposed on the front surface side of the semiconductor substrate 40 in the edge termination region 30.

[0043] A vertical MOSFET having a typical trench gate structure is disposed as a semiconductor element having a predetermined element structure in the active region 10. The trench gate structure is formed by a p-type base region 4, a n-type base region 5, and a n-type MOSFET 6 provided on the front surface side of a semiconductor substrate 40. +Type source region 5, p ++ The semiconductor substrate 40 is made of silicon carbide. + On the front surface of a starting substrate 41, epitaxial layers 42 to 44 which become the drift layer 2, the n-type current diffusion region 3 and the p-type base region 4 are deposited in this order.

[0044] The principal surface of the semiconductor substrate 40 on the side of the p-type epitaxial layer 44 is the front surface, and + The main surface (n + The back surface of the semiconductor substrate 40 is the back surface of the starting substrate 41. The crystal plane orientation of the front surface of the semiconductor substrate 40 is, for example, the (0001) plane, which is a so-called Si plane. + The starting substrate 41 is n + The gate trench 7 penetrates the p-type epitaxial layer 44 from the front surface of the semiconductor substrate 40 in the depth direction Z to form an n-type - The gate electrodes 42 reach into the type epitaxial layer 43 and extend in a stripe shape in a second direction Y, which will be described later.

[0045] Between the gate trenches 7 adjacent to each other, the p-type base regions 4 and n-type base regions 5 are formed so as to extend linearly in the second direction Y, for example. + Type source region 5 and p ++ The p-type contact region 6 is selectively provided on each of the active regions 10. The p-type base region 4 extends outward from the active region 10 to a step 31, which will be described later. + Type source region 5 and p ++ The contact region 6 is provided between the front surface of the semiconductor substrate 40 and the p-type base region 4 in contact with the p-type base region 4, and is exposed at the front surface of the semiconductor substrate 40.

[0046] n + The source region 5 faces the gate electrode 9 via the gate insulating film 8 on the side wall of the gate trench 7. ++ The contact region 6 is an n + The p-type epitaxial layer 44 is disposed at a position farther from the gate trench 7 than the p-type source region 5. +Type source region 5 and p ++ The portion excluding the contact region 6 is the p-type base region 4. An epitaxial layer 42, which is a drift layer 2 of a full SJ structure, is provided between the p-type base region 4 and the rear surface of the semiconductor substrate 40. The configuration of the drift layer 2 of the full SJ structure will be described later.

[0047] An n-type current diffusion region 3 is provided between the p-type base region 4 and the drift layer 2, in contact with the p-type base region 4 and the drift layer 2. The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 is disposed between adjacent gate trenches 7 and adjacent to the gate trench 7. The n-type current diffusion region 3 reaches a position deeper than the gate trench 7 from the front surface of the semiconductor substrate 40.

[0048] Inside the n-type current diffusion region 3, p + The mold regions 11 to 13 are selectively provided. + The mold region 11 faces the bottom surface of the gate trench 7 in the depth direction Z. + The p-type region 11 is disposed at a position deeper than the interface between the p-type base region 4 and the n-type current diffusion region 3 from the front surface of the semiconductor substrate 40 and separated from the p-type base region 4. + The type region 11 is p + The outermost p + Type region 11 (hereinafter, the outermost p + The mold region 11a extends beyond a step 31 (described later) to the outside.

[0049] p + The p-type region 12 is disposed between the adjacent gate trenches 7. + The gate trench 7 is provided apart from the mold region 11. + The p-type region 12 is in contact with the p-type base region 4. + The mold region 13 is the outermost p + The outermost p +The p-type region 11a and the p-type base region 4 are in contact with each other. + The mold region 13 extends from the outermost gate trench 7a to the step 31. + The mold regions 11 and 12 have the function of reducing the electric field concentration on the gate insulating film 8 at the bottom surface of the gate trench 7 .

[0050] An interlayer insulating film 14 is provided on the entire front surface of the semiconductor substrate 40 so as to cover the gate electrode 9. The source electrode 15 is connected to the n-type semiconductor substrate 40 via a contact hole opened in the interlayer insulating film 14. + Type source region 5 and p ++ The p-type contact region 6 is in ohmic contact with and electrically connected to these regions. A source electrode 15 extends outward from the active region 10 and is electrically connected to the p-type base region 4 at an intermediate region 20.

[0051] The source electrode 15 extends from the active region 10 to the intermediate region 20, and terminates inside (towards the center of the chip) the gate metal wiring 22 of the intermediate region 20, which will be described later. A barrier metal (not shown) may be provided between the source electrode 15 and the interlayer insulating film 14. The barrier metal has the function of preventing atomic diffusion and mutual reaction between regions facing each other across the barrier metal. A passivation film (not shown) covers the entire front surface of the semiconductor substrate 40. The portion of the source electrode 15 exposed from the opening of the passivation film becomes a source pad.

[0052] The intermediate region 20 is located outside the center of the outermost gate trench 7a in a first direction X parallel to the front surface of the semiconductor substrate 40, and extends in a second direction Y parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X. + This region extends from the outer side of the end of the type source region 5 to the step 31. In the portion of the intermediate region 20 outer than the source electrode 15, an insulating layer formed by laminating a field oxide film 36 and an interlayer insulating film 14 in this order extends from the edge termination region 30 side onto a first surface 40a (described later) of the front surface of the semiconductor substrate 40.

[0053] A gate runner 21 and a gate metal wiring 22 are disposed in the intermediate region 20. The gate runner 21 is provided on a first surface 40a of the front surface of the semiconductor substrate 40 via a field oxide film 36, and is connected to the gate electrode 9 and a gate pad (not shown) at portions not shown, electrically connecting the gate electrode 9 and the gate pad. The gate runner 21 is covered with an interlayer insulating film 14. The gate metal wiring 22 is electrically connected to the gate runner 21 via a contact hole opened in the interlayer insulating film 14.

[0054] In edge termination region 30, for example, p-type epitaxial layer 44 is removed from the entire area of ​​edge termination region 30, thereby forming a step 31 that makes the front surface of semiconductor substrate 40 lower (recessed toward the drain side) in edge termination region 30 than a portion 40a on the active region 10 side (hereinafter referred to as a first surface). By forming step 31, n-type epitaxial layer 44 is formed in a portion 40b (hereinafter referred to as a second surface) outside step 31 on the front surface of semiconductor substrate 40. - The type epitaxial layer 43 is exposed.

[0055] The outermost p + The p-type region 11a is exposed. A portion 40c (a mesa edge of the step 31: hereinafter referred to as the third surface) between the first surface 40a and the second surface 40b of the front surface of the semiconductor substrate 40 contains the p-type base region 4 and the p + The mold region 13 is exposed. Exposing to the second and third faces 40b, 40c of the front surface of the semiconductor substrate 40 means that the mold region 13 is disposed in the surface region of the second and third faces 40b, 40c of the front surface of the semiconductor substrate 40 and contacts the field oxide film 36 on the second and third faces 40b, 40c.

[0056] In addition, the surface area of ​​the second surface 40b of the semiconductor substrate 40 includes the outermost p + The JTE structure 34 is provided outside the mold region 11a. +The impurity concentration of the p-type regions (two in this example; hereinafter, referred to as first and second JTE regions 32 and 33 from the active region 10 side) is lower than that of the p-type region 11a, and the impurity concentration is lower as it is disposed on the outside. The first and second JTE regions 32 and 33 are, for example, - The doped epitaxial layer 43 is penetrated to reach the epitaxial layer 42 .

[0057] The first JTE region 32 is the outermost p + The second JTE region 33 is adjacent to the outside of the first JTE region 32. A predetermined breakdown voltage is ensured in the edge termination region 30 by a pn junction between the first and second JTE regions 32, 33 and an n-type region of the partial parallel pn layer closest to the source side (n-type region 67 of third partial parallel pn layer 53), which will be described later. In addition, a surface region of the second face 40b of the front surface of the semiconductor substrate 40 has an n-type region 67, away from the JTE structure 34, exposed at the edge of the semiconductor substrate 40. + A mold stop area 35 is optionally provided.

[0058] Although not shown, a region (hereinafter referred to as spatial modulation region) may be provided between adjacent first and second JTE regions 32, 33 of JTE structure 34, in which a p-type region having the same impurity concentration as the first JTE region 32 on the inside and a p-type region having the same impurity concentration as the second JTE region 33 on the outside are alternately and repeatedly arranged adjacent to each other in a concentric circle shape surrounding active region 10. For example, when the breakdown voltage is 1.7 kV or more, it is preferable to provide a spatial modulation region in JTE structure 34.

[0059] The JTE structure 34 and the n + In the portion other than the mold stopper region 35, n - The n-type epitaxial layer 43 is exposed. The second and third faces 40b, 40c of the front surface of the semiconductor substrate 40 are covered with an insulating layer in which a field oxide film 36 and an interlayer insulating film 14 are laminated in this order. The field oxide film 36 extends onto a first face 40a of the front surface of the semiconductor substrate 40 in the intermediate region 20. +A drain electrode 16 is provided on the entire back surface of the starting mold substrate 41.

[0060] Next, the configuration of the drift layer 2 (epitaxial layer 42) of the full SJ structure will be described. The drift layer 2 of the full SJ structure has n + Three or more parallel pn layers (hereinafter referred to as partial parallel pn layers) are continuously laminated on the front surface of mold starting substrate 41 so as to have a total thickness t4 of drift layer 2. The partial parallel pn layers are continuously arranged from active region 10 to the chip end in the same pattern for each partial parallel pn layer.

[0061] Each partial parallel pn layer constituting the drift layer 2 has a full SJ structure formed by a trench-filling epitaxial method or a full SJ structure formed by using a multi-stage epitaxial method. The full SJ structure is a structure in which an SJ structure in which n-type regions and p-type regions are alternately and repeatedly arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 40 extends in the depth direction Z over substantially the entire total thickness t4 of the drift layer 2.

[0062] A partial parallel pn layer formed by the trench-filled epitaxial method (hereinafter referred to as a trench-filled parallel pn layer) is formed by forming a trench (hereinafter referred to as an SJ trench) that penetrates a thick n-type epitaxial layer formed by one stage (single time) of epitaxial growth in the depth direction Z, and then filling the inside of the SJ trench with a p-type epitaxial layer.

[0063] A partial parallel pn layer formed using a multistage epitaxial method (hereinafter referred to as a multistage epi-parallel pn layer) is formed by performing ion implantation on a thin n-type epitaxial layer formed by one stage of epitaxial growth to selectively form a p-type region that penetrates the n-type epitaxial layer in the depth direction Z. Crystal defects are introduced into the multistage epi-parallel pn layer by ion implantation.

[0064] These trench-buried parallel pn layers and multistage epitaxial parallel pn layers are alternately stacked in three or more layers (three layers in FIG. 2: first to third partial parallel pn layers 51 to 53 described later) to form a drift layer 2 with a full SJ structure. Multistage epitaxial parallel pn layers (partial parallel pn layers) are arranged between trench-buried parallel pn layers (partial parallel pn layers) adjacent to each other in the depth direction Z, adjacent to these trench-buried parallel pn layers. Both the partial parallel pn layers closest to the source and the partial parallel pn layers closest to the drain are trench-buried parallel pn layers.

[0065] By including the multi-stage epitaxial parallel pn layer in part of the drift layer 2, the minority carrier (hole) lifetime of the drift layer 2 is shorter than when the drift layer 2 is composed only of a trench-buried parallel pn layer without crystal defects or when silicon (Si) without crystal defects is used as the semiconductor material. ++ The p-type contact region 6, the p-type base region 4 and the p + The n-type region 11, the n-type current diffusion region 3, the n-type region of the partial parallel pn layer, the n-type drift region 2a and the n + A parasitic diode (body diode) formed by a pn junction with the type drain region 1 provides soft recovery, making it possible to reduce noise during reverse recovery of the parasitic diode.

[0066] The n-type and p-type regions of the partial parallel pn layer are arranged in stripes extending in a direction parallel to the front surface of the semiconductor substrate 40. The stripe shapes of the n-type and p-type regions of the trench-buried parallel pn layer and the stripe shapes of the n-type and p-type regions of the multistage epi-parallel pn layer extend in different directions, are not parallel when viewed from the front surface side of the semiconductor substrate 40, and intersect at an angle of, for example, 45 degrees or more, and are preferably perpendicular to each other. This makes it possible to connect the n-type regions and p-type regions of the trench-buried parallel pn layers adjacent to each other in the depth direction Z via the n-type regions and p-type regions of the multistage epi-parallel pn layers, respectively, even if the positions of the n-type regions and p-type regions are misaligned.

[0067] In both the trench-buried parallel pn layer and the multistage epitaxial parallel pn layer, the n-type and p-type regions adjacent to each other in the direction parallel to the front surface of the semiconductor substrate 40 have the same width and are generally charge-balanced. The n-type and p-type regions of the multistage epitaxial parallel pn layer have approximately the same impurity concentration as the n-type and p-type regions of the trench-buried parallel pn layer, respectively. Approximately the same impurity concentration means that the impurity concentrations are the same within a range that includes an error allowed by process variations. The interface between the trench-buried parallel pn layer and the multistage epitaxial parallel pn layer is a flat surface that is approximately parallel to the front surface of the semiconductor substrate 40.

[0068] The thickness of the trench-buried parallel pn layer is sufficiently thicker than the thickness of the multi-stage epitaxial parallel pn layer, and the trench-buried parallel pn layer accounts for the majority of the drift layer 2. The drift layer 2 of the full SJ structure only needs to have three or more odd-numbered partial parallel pn layers that satisfy the above conditions, and the greater the number of stages of partial parallel pn layers, the greater the number of stages of trench-buried parallel pn layers that make up the drift layer 2. The greater the number of stages of trench-buried parallel pn layers, the thinner the thickness that each trench-buried parallel pn layer can be relative to the total thickness t4 of the drift layer 2.

[0069] The thinner the trench-buried parallel pn layer is, the shallower the SJ trench can be. This makes it easier to perform trench etching to form the SJ trench in the trench-buried parallel pn layer and to fill the SJ trench with an epitaxial layer. Therefore, even if the width of the SJ trench is narrowed, the depth of the SJ trench can be made shallow, and the above-mentioned process problems associated with using silicon carbide as the semiconductor material can be avoided, allowing a full SJ structure to be formed.

[0070] Hereinafter, when the drift layer 2 of the full SJ structure is composed of three partial parallel pn layers, the drift layer 2 of the full SJ structure has first and third trench-buried parallel pn layers (first and third partial parallel pn layers 51, 53) and a second multi-stage epitaxial parallel pn layer (second partial parallel pn layer 52) arranged between these trench-buried parallel pn layers.

[0071] The first partial parallel pn layer 51 is a trench-buried parallel pn layer. The first partial parallel pn layer 51 is formed by alternately and repeatedly arranging n-type regions 62 and p-type regions 63 adjacent to each other in the first direction X. The n-type regions 62 and p-type regions 63 extend linearly in the <11-20> direction of silicon carbide, which is parallel to the second direction Y ( FIG. 3( a )). Therefore, the pn junction surface between the p-type region 63 and the n-type region 62 is a substantially flat surface parallel to the {1-100} plane along which an epitaxial layer with good crystallinity initially grows, and is substantially perpendicular to the front surface of the semiconductor substrate 40.

[0072] The first partial parallel pn layer 51 has an SJ trench (first trench) 61 penetrating the n-type epitaxial layer that constitutes the first partial parallel pn layer 51. The aspect ratio of the SJ trench 61 (=depth of the SJ trench 61 / width of the SJ trench 61) is, for example, 5 or more and 15 or less. The n-type region 62 is a portion of the n-type epitaxial layer that constitutes the first partial parallel pn layer 51 that remains after the SJ trench 61 is formed. The p-type region 63 is a p-type epitaxial layer buried inside the SJ trench 61.

[0073] In the first partial parallel pn layer 51, an n-type region 62 is disposed along the chip edge at the outermost side of the semiconductor substrate 40. The annular portion of the n-type region 62 along the chip edge as viewed from the front surface side of the semiconductor substrate 40 surrounds the periphery of the central portion of the semiconductor substrate 40 and connects all linear portions of the n-type region 62. The n-type region 62 and the p-type region 63 have the same width and are generally charge balanced. The narrower the width and repetition pitch of the n-type region 62 and the p-type region 63, the higher the on-resistance reduction effect. The drain side portion of the first partial parallel pn layer 51 may be a normal n-type drift region 2a that does not have an SJ structure.

[0074] The second partial parallel pn layer 52 is a multistage epitaxial parallel pn layer, and is adjacent to the source side of the first partial parallel pn layer 51. The second partial parallel pn layer 52 is formed by alternately and repeatedly arranging n-type regions 64 and p-type regions 65 adjacent to each other in the second direction Y. The n-type regions 64 and p-type regions 65 extend linearly in the first direction X. When viewed from the front surface of the semiconductor substrate 40, the stripe shape of the n-type regions 64 and p-type regions 65 is perpendicular to the stripe shape of the n-type regions 62 and p-type regions 63 of the first partial parallel pn layer 51 (FIG. 3(b)).

[0075] The n-type region 64 is a portion of the n-type epitaxial layer that constitutes the second partial parallel pn layer 52 that remains after the formation of the p-type region 65. The p-type region 65 is an ion-implanted region (diffusion region) selectively formed in the n-type epitaxial layer that constitutes the second partial parallel pn layer 52, and penetrates the n-type epitaxial layer in the depth direction Z to reach the first partial parallel pn layer 51. The n-type region 64 and the p-type region 65 have the same impurity concentrations as the n-type region 62 and the p-type region 63 of the first partial parallel pn layer 51, respectively, and are in contact with the n-type region 62 and the p-type region 63, respectively.

[0076] As described above, when viewed from the front surface side of the semiconductor substrate 40, the stripe shape of the n-type regions 62 and p-type regions 63 of the first partial parallel pn layer 51 is not parallel to the stripe shape of the n-type regions 64 and p-type regions 65 of the second partial parallel pn layer 52. This makes it possible to reliably bring the n-type region 62 and p-type region 63 of the first partial parallel pn layer 51 into contact with the n-type region 64 and p-type region 65 of the second partial parallel pn layer 52, respectively, at the interface between the first partial parallel pn layer 51 and the second partial parallel pn layer 52.

[0077] The thickness of the second partial parallel pn layer 52 is thinner than the trench-buried parallel pn layer, and is, for example, about 0.65 μm±0.05 μm. By making the second partial parallel pn layer 52 have the above thickness, when the third partial parallel pn layer 53 is formed on the second partial parallel pn layer 52, it is possible to prevent the SJ trench 66 of the third partial parallel pn layer 53 from penetrating the second partial parallel pn layer 52 in the depth direction Z and reaching the first partial parallel pn layer 51. If the SJ trench 66 of the third partial parallel pn layer 53 reaches the first partial parallel pn layer 51, a charge imbalance occurs between the n-type region 64 and the p-type region 65 of the second partial parallel pn layer 52, which is not preferable.

[0078] Furthermore, by making the second partial parallel pn layer 52 have the above thickness, it is possible to allow impurities ion-implanted using a general ion implantation device to reach from the ion-implanted surface (one surface) of the epitaxial layer constituting the second partial parallel pn layer 52 to the other surface. In addition, a diffusion region (here, p-type region 65) formed by ion implantation can be formed to a depth penetrating the epitaxial layer in the depth direction Z, and with a uniform doping concentration in the depth direction Z. A uniform impurity concentration means that the impurity concentration is approximately the same within a range including an allowable error due to process variations.

[0079] In the second partial parallel pn layer 52, an n-type region 64 is disposed along the chip end at the outermost side of the semiconductor substrate 40. The annular portion of the n-type region 64 along the chip end as viewed from the front surface side of the semiconductor substrate 40 surrounds the periphery of the central portion of the semiconductor substrate 40, connects all linear portions of the n-type region 64, and contacts the annular portion of the n-type region 62 of the first partial parallel pn layer 51 along the chip end as viewed from the front surface side of the semiconductor substrate 40 in the depth direction Z. The n-type region 64 and the p-type region 65 have the same width and are generally charge-balanced. The narrower the width and the repetition pitch of the n-type region 64 and the p-type region 65, the higher the on-resistance reduction effect.

[0080] The third partial parallel pn layer 53 is a trench-buried parallel pn layer, and is adjacent to the source side of the second partial parallel pn layer 52. The third partial parallel pn layer 53 has the same layout as the n-type regions 62 and p-type regions 63 of the first partial parallel pn layer 51, and is formed by alternately and repeatedly arranging n-type regions 67 and p-type regions 68 adjacent to each other in the first direction X. For this reason, the stripe shape of the n-type regions 67 and p-type regions 68 is perpendicular to the stripe shape of the n-type regions 64 and p-type regions 65 of the second partial parallel pn layer 52 (FIG. 3(c)).

[0081] The third partial parallel pn layer 53 has an SJ trench 66 penetrating the n-type epitaxial layer constituting the third partial parallel pn layer 53. The bottom surface of the SJ trench 66 reaches the drain side beyond the interface between the third partial parallel pn layer 53 and the second partial parallel pn layer 52, and terminates inside the second partial parallel pn layer 52. The SJ trench 66 preferably faces the SJ trench 61 of the first partial parallel pn layer 51. The aspect ratio of the SJ trench 66 (=depth of the SJ trench 66 / width of the SJ trench 66) is, for example, 5 or more and 15 or less.

[0082] The n-type region 67 is a portion of the n-type epitaxial layer constituting the third partial parallel pn layer 53 that remains after the formation of the SJ trench 66. The n-type region 67 is in contact with the n-type region 64 of the second partial parallel pn layer 52, and is connected to the n-type region 62 of the first partial parallel pn layer 51 via the n-type region 64. The p-type region 68 is a p-type epitaxial layer buried inside the SJ trench 66. The p-type region 68 is in contact with the p-type region 65 of the second partial parallel pn layer 52, and is connected to the p-type region 63 of the first partial parallel pn layer 51 via the p-type region 65.

[0083] As described above, when viewed from the front surface side of the semiconductor substrate 40, the stripe shape of the n-type regions 64 and p-type regions 65 of the second partial parallel pn layer 52 is not parallel to the stripe shape of the n-type regions 67 and p-type regions 68 of the third partial parallel pn layer 53. This makes it possible to reliably bring the n-type region 64 and p-type region 65 of the second partial parallel pn layer 52 into contact with the n-type region 67 and p-type region 68 of the third partial parallel pn layer 53, respectively, at the interface between the second partial parallel pn layer 52 and the third partial parallel pn layer 53.

[0084] Furthermore, as described above, the bottom surface of the SJ trench 66 terminates inside the second partial parallel pn layer 52, thereby ensuring contact between the p-type region 68 and the p-type region 65 of the second partial parallel pn layer 52. The n-type region 67 and the p-type region 68 have the same impurity concentrations as the n-type region 62 and the p-type region 63 of the first partial parallel pn layer 51, respectively. The n-type region 67 and the p-type region 68 have the same width and are generally charge-balanced. The narrower the width and repetition pitch of the n-type region 67 and the p-type region 68, the greater the on-resistance reduction effect.

[0085] In this manner, the n-type region 62 of the first partial parallel pn layer 51 and the n-type region 67 of the third partial parallel pn layer 53 are connected in the depth direction Z via the n-type region 64 of the second partial parallel pn layer 52. The p-type region 63 of the first partial parallel pn layer 51 and the p-type region 68 of the third partial parallel pn layer 53 are connected in the depth direction Z via the p-type region 65 of the second partial parallel pn layer 52. The first to third partial parallel pn layers 51 to 53 are stacked in order to form the drift layer 2 with a full SJ structure.

[0086] As described above, the trench-buried parallel pn layer and the multistage epitaxial parallel pn layer may be arranged such that the stripe shapes of the n-type regions and p-type regions are not parallel to each other, and the layout of the n-type regions and p-type regions of the first to third partial parallel pn layers as viewed from the front surface side of the semiconductor substrate 40 can be modified in various ways. To form the trench-buried parallel pn layer, the degree of epitaxial growth of the p-type epitaxial layer into the SJ trench varies depending on the properties of the crystal plane orientation of the sidewall of the SJ trench.

[0087] 4, the n-type regions 62', 67' and the p-type regions 63', 68' of the first and third partial parallel pn layers 51', 53' are formed in a stripe shape extending in the <1-100> direction of silicon carbide parallel to the second direction Y'. The n-type region 64' and the p-type region 65' of the second partial parallel pn layer 52' ​​are formed in a stripe shape extending parallel to the first direction X'. The layout of the n-type region 67' and the p-type region 68' of the third partial parallel pn layer 53' is the same as that of the n-type region 62' and the p-type region 63' of the first partial parallel pn layer 51', respectively.

[0088] In the first and third partial parallel pn layers 51', 53', the pn junction surfaces between the p-type regions 63', 68' and the n-type regions 62', 67' have a predetermined inclination with respect to the side walls of the SJ trenches 61', 66' based on the properties of the {11-20} planes that become the side walls of the SJ trenches 61', 66' when the p-type epitaxial layers that become the p-type regions 63', 68' are embedded in the SJ trenches 61', 66'. When the first to third partial parallel pn layers 51'-53' shown in Figure 4 are used as the drift layer 2, the cross-sectional view is obtained by changing the first and second directions X, Y in Figure 2 to the first and second directions X', Y'.

[0089] Next, a method for manufacturing the silicon carbide semiconductor device 50 according to the first embodiment will be described. Fig. 5 is a flowchart outlining the outline of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figs. 6 to 16 are cross-sectional views showing states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment. Figs. 6 to 8 and 11 to 16 are cross-sectional views perpendicular to the second direction Y of the active region 10 (see Fig. 2), and Figs. 9 and 10 are cross-sectional views perpendicular to the first direction X of the active region 10.

[0090] First, a substrate with both sides chemically mechanically polished (CMP) was + The starting substrate (semiconductor wafer) 41 is cleaned, for example, by organic cleaning and RCA cleaning. +The starting mold substrate 41 may have a crystal structure of, for example, a four-layer hexagonal crystal structure of silicon carbide (4H-SiC), and the front surface may be a (0001) surface, i.e., a so-called Si surface. + The starting substrate 41 is n + This becomes the first type drain region.

[0091] Next, as shown in FIG. 6, a chemical vapor deposition (CVD) apparatus was used to deposit n + An n-type epitaxial layer (first epitaxial layer) 201 is epitaxially grown (formed) as a part of the epitaxial layer 42 (drift layer 2) on the front surface of the starting substrate 41 (step S1). The thickness t1 and impurity concentration of the n-type epitaxial layer 201 are, for example, about 40 μm and 1×10 16 / cm 3 That's about it.

[0092] Next, the epitaxial substrate (n + An epitaxial substrate in which an n-type epitaxial layer 201 is laminated on a starting substrate 41 is cleaned by, for example, organic cleaning and RCA cleaning. Next, an oxide (SiO2) film 211 is formed on the surface of the n-type epitaxial layer 201 to a thickness of, for example, about 6 μm using, for example, a plasma chemical vapor deposition (PCVD) device.

[0093] Next, a resist film 212 having openings corresponding to the formation regions of the SJ trenches 61 is formed on the surface of the oxide film 211 by photolithography. The opening pattern of the resist film 212 is striped extending in the second direction Y. The opening width w11 of the striped opening pattern of the resist film 212 and the remaining width w12 between adjacent openings are both, for example, about 2.5 μm.

[0094] Next, the oxide film 211 is dry-etched using the resist film 212 as a mask, thereby leaving the oxide film 211 with the same stripe-shaped opening pattern as the resist film 212. As a result, a portion of the oxide film 211 corresponding to a formation region of the SJ trench 61 of the first partial parallel pn layer 51 is opened. Then, the resist film 212 is removed.

[0095] 7, the n-type epitaxial layer 201 is dry-etched using the remaining portion of the oxide film 211 as a mask to form an SJ trench 61 (step S2). The depth d1 of the SJ trench 61 is, for example, about 30 μm. The portions of the n-type epitaxial layer 201 remaining between the adjacent SJ trenches 61 become the n-type regions 62 of the first partial parallel pn layer 51. Then, the remaining portions of the oxide film 211 are removed using, for example, hydrofluoric acid (HF).

[0096] The n-type epitaxial layer 201 is located closer to the bottom of the SJ trench 61 than the n-type epitaxial layer 201. + The portion on the side of the starting substrate 41 is a normal n-type drift region 2a that does not have an SJ structure. + Another n-type epitaxial layer that becomes an n-type buffer region (not shown) may be formed on the front surface of the starting substrate 41. In this case, in the process of step S2, an SJ trench 61 may be formed that penetrates the n-type epitaxial layer 201 in the depth direction Z and reaches the n-type buffer region.

[0097] 8, the epitaxial substrate is cleaned, for example, by organic cleaning and RCA cleaning. Next, the inside of the SJ trench 61 is filled with a p-type epitaxial layer (second epitaxial layer) 202 epitaxially grown (formed) using a CVD apparatus (step S3). In the process of step S3, an excess p-type epitaxial layer 202 is epitaxially grown also on the surface of the n-type epitaxial layer 201 so as to protrude above the SJ trench 61.

[0098] The p-type epitaxial layer 202 may be epitaxially grown by a hydride vapor phase epitaxy (HVPE) method using a mixed gas obtained by adding hydrogen chloride (HCl) gas, which is a hydrogen compound, to a source gas containing, for example, aluminum (Al) as a dopant. The impurity concentration of the p-type epitaxial layer 202 is, for example, 1×10 16 / cm 3 That's about it.

[0099] Next, excess p-type epitaxial layer 202 present above the surface of n-type epitaxial layer 201 is removed by grinding and polishing, leaving p-type epitaxial layer 202 only inside SJ trench 61 (step S4). The portion of p-type epitaxial layer 202 remaining inside SJ trench 61 becomes p-type region 63 of first partial parallel pn layer 51.

[0100] Next, the surfaces of n-type epitaxial layer 201 and p-type epitaxial layer 202 are planarized by CMP (step S5). As a result, a first partial parallel pn layer 51 (see FIG. 3(a)) in which n-type epitaxial layer 201 and p-type epitaxial layer 202 are n-type region 62 and p-type region 63, respectively, is formed as the first partial parallel pn layer constituting drift layer 2.

[0101] 9, a CVD apparatus is used to epitaxially grow (form) an n-type epitaxial layer (third epitaxial layer) 203 as a part of the epitaxial layer 42 (drift layer 2) on the first partial parallel pn layer 51 (step S6). The thickness t2 of the n-type epitaxial layer 203 is, for example, about 0.65 μm. The impurity concentration of the n-type epitaxial layer 203 is approximately the same as the impurity concentration of the n-type epitaxial layer 201.

[0102] Next, the epitaxial substrate (n +The epitaxial substrate in which the first partial parallel pn layer 51 and the n-type epitaxial layer 203 are laminated in this order on the starting substrate 41 is cleaned by, for example, organic cleaning, RCA cleaning, etc. Next, an oxide film 213 is formed on the surface of the n-type epitaxial layer 203 to a thickness of, for example, about 2 μm using, for example, a PCVD device.

[0103] Next, a resist film 214 having openings corresponding to regions for forming the p-type regions 65 of the second partial parallel p-n layer 52 is formed by photolithography on the surface of the oxide film 213. The opening pattern of the resist film 214 is striped extending in the first direction X perpendicular to the opening pattern of the resist film 212 used for forming the first partial parallel p-n layer 51, and the opening width w13 and the remaining width w14 between adjacent openings are both about 2.5 μm, for example.

[0104] 10, the oxide film 213 is dry-etched using the resist film 214 as a mask, thereby leaving the oxide film 213 with the same stripe-shaped opening pattern as the resist film 214. This opens the portions of the oxide film 213 corresponding to the formation regions of the p-type regions 65 of the second partial parallel pn layer 52. Then, the resist film 214 is removed. As described above, only FIGS. 9 and 10 show the cross-sectional shapes in the cross section perpendicular to the first direction X.

[0105] Next, using the remaining portion of the oxide film 213 as a mask, a typical ion implantation device is used to perform ion implantation 215 of p-type impurities such as aluminum to form a p-type region 65 penetrating the n-type epitaxial layer 203 in the depth direction Z inside the n-type epitaxial layer 203 (step S7). The ion implantation 215 may be a multi-stage ion implantation with different acceleration energies to form, for example, a box profile.

[0106] The impurity concentration of p-type region 65 is approximately the same as the impurity concentration of p-type epitaxial layer 202. The portions of n-type epitaxial layer 203 between adjacent p-type regions 65 become n-type regions 64 of second partial parallel p-n layer 52. As a result, second partial parallel p-n layer 52 consisting of n-type region 64 and p-type region 65 is formed as the second partial parallel p-n layer that constitutes drift layer 2 (see FIG. 3(b)).

[0107] Here, an example is described in which one multistage epitaxial parallel pn layer (second partial parallel pn layer 52) is arranged, but two or more multistage epitaxial parallel pn layers may be arranged in succession. In this case, each time the process from step S6 to step S7 is repeated, one multistage epitaxial partial parallel pn layer can be laminated. In Fig. 5, this one repetition is indicated by an arrow E2 pointing from step S7 to step S6.

[0108] Then, the remaining portion of the oxide film 213 is removed, for example, with hydrofluoric acid. When two or more multistage epitaxial parallel pn layers are arranged in succession, the p-type regions 65 of the multiple multistage epitaxial parallel pn layers each have a cross section with one peak and two bottoms in terms of the impurity concentration distribution in the depth direction Z. A periodic concentration distribution is formed in which multiple p-type regions 65 having a cross section with one peak and two bottoms in the depth direction Z are connected in the depth direction Z.

[0109] Alternatively, the second partial parallel pn layer 52 may be formed as follows. In the process of step S6, a low impurity concentration n - Then, in the process of step S7, in addition to the ion implantation 215 for forming the p-type region 65 of the second partial parallel p-n layer 52, ion implantation for forming the n-type region (diffusion region) 64 of the second partial parallel p-n layer 52 may be performed.

[0110] Incidentally, since the p-type region 65 (or the p-type region 65 and the n-type region 64) are formed by ion implantation, crystal defects occur in the second partial parallel p-n layer 52. In the case of silicon, these crystal defects are repaired by annealing, but in the case of silicon carbide, they are not repaired even if annealing is performed in a subsequent process, and the crystal defects remain in the second partial parallel p-n layer 52. These crystal defects shorten the carrier lifetime in the second partial parallel p-n layer 52.

[0111] In this way, by forming a region with a short carrier lifetime in the drift layer 2, it is possible to reduce the high injection carriers when the parasitic diode (body diode) is turned on. This has the effect of suppressing hard recovery caused by the extraction of hole carriers in the reverse recovery state of the parasitic diode. It is preferable to achieve charge balance by making the amount of impurities, which is the product of the impurity concentration and area, approximately equal in each partial parallel pn layer.

[0112] Next, the epitaxial substrate (n + The epitaxial substrate in which the first and second partial parallel p-n layers 51, 52 are laminated in order on the type starting substrate 41 is cleaned by, for example, organic cleaning, RCA cleaning, etc. Next, as shown in Fig. 11, an n-type epitaxial layer 204 is epitaxially grown (formed) on the second partial parallel p-n layer 52 as a part of the epitaxial layer 42 (drift layer 2) using a CVD apparatus (step S8).

[0113] In the process of step S8, thickness t3 of n-type epitaxial layer 204 is, for example, about 25 μm. The impurity concentration of n-type epitaxial layer 204 is approximately the same as the impurity concentration of n-type epitaxial layer 201. Through the steps up to this point, the thickness of epitaxial layer 42 becomes total thickness t4 (=about 65 μm) of drift layer 2. Here, total thickness t4 of drift layer 2 is an example in the case where silicon carbide semiconductor device 50 has a withstand voltage of 6.5 kV class.

[0114] Next, the epitaxial substrate (n +The epitaxial substrate in which the first and second partial parallel pn layers 51, 52 and the n-type epitaxial layer 204 are laminated in this order on the starting substrate 41 is cleaned by, for example, organic cleaning, RCA cleaning, etc. Next, an oxide film 216 is formed on the surface of the n-type epitaxial layer 204 to a thickness of, for example, about 6 μm using, for example, a PCVD device.

[0115] Next, a resist film 217 having openings corresponding to the formation regions of the SJ trenches 66 is formed by photolithography on the surface of the oxide film 216. The opening pattern of the resist film 217 is striped extending in the second direction Y, the same as the opening pattern of the resist film 212 used in forming the first partial parallel pn layer 51, and the opening width w15 and the remaining width w16 between adjacent openings are both, for example, about 2.5 μm.

[0116] Next, the oxide film 216 is dry-etched using the resist film 217 as a mask, thereby leaving the oxide film 216 with the same stripe-shaped opening pattern as the resist film 217. As a result, a portion of the oxide film 216 corresponding to a formation region of the SJ trench 66 of the third partial parallel pn layer 53 is opened. Then, the resist film 217 is removed.

[0117] 12, the n-type epitaxial layer 204 is dry-etched using the remaining portion of the oxide film 216 as a mask to form an SJ trench 66 (step S9). Here, the SJ trench 66 is formed to have the same width as the SJ trench 61 of the first partial parallel pn layer 51, so that the SJ trench 66 and the SJ trench 61 are opposed to each other in the depth direction Z with as little misalignment as possible, thereby enhancing the effect of reducing the on-resistance by the SJ structure.

[0118] The depth d3 of the SJ trench 66 is a depth that penetrates the n-type epitaxial layer 204 in the depth direction Z to reach the second partial parallel p-n layer 52 but does not penetrate the second partial parallel p-n layer 52. The portions of the n-type epitaxial layer 204 remaining between adjacent SJ trenches 66 become the n-type regions 67 of the third partial parallel p-n layer 53. Then, the remaining portions of the oxide film 216 are removed using, for example, hydrofluoric acid.

[0119] 13, the epitaxial substrate is cleaned, for example, by organic cleaning and RCA cleaning. Next, the inside of the SJ trench 66 is filled with a p-type epitaxial layer 205 epitaxially grown (formed) using a CVD apparatus (step S10). In the process of step S10, an excess p-type epitaxial layer 205 is epitaxially grown also on the surface of the n-type epitaxial layer 204 so as to protrude above the SJ trench 66.

[0120] The p-type epitaxial layer 205 may be epitaxially grown by the HVPE method using a mixed gas obtained by adding hydrogen chloride gas, which is a hydrogen compound, to a source gas containing, for example, aluminum as a dopant, in the same manner as the epitaxial growth of the p-type epitaxial layer 202. The impurity concentration of the p-type epitaxial layer 205 is approximately the same as that of the p-type epitaxial layer 202.

[0121] Next, excess p-type epitaxial layer 205 present above the surface of n-type epitaxial layer 204 is removed by grinding and polishing, leaving p-type epitaxial layer 205 only inside SJ trench 66 (step S11). The portion of p-type epitaxial layer 205 remaining inside SJ trench 66 becomes p-type region 68 of third partial parallel pn layer 53.

[0122] Next, the surfaces of n-type epitaxial layer 204 and p-type epitaxial layer 205 are planarized by CMP (step S12). As a result, a third partial parallel pn layer 53 in which n-type epitaxial layer 204 and p-type epitaxial layer 205 are made into n-type region 67 and p-type region 68, respectively, is formed as a third partial parallel pn layer constituting drift layer 2 (see FIG. 3(c)).

[0123] The first to third partial parallel pn layers 51 to 53 formed in the steps up to this point form an SJ structure with a thickness t5 of about 55 μm, and a drift layer 2 (epitaxial layer 42) with a total thickness t4 of about 65 μm is formed, having a full SJ structure with n-type and p-type regions each having a width of 2.5 μm (repeat pitch is 5.0 μm).

[0124] Here, a drift layer 2 with a full SJ structure composed of three partial parallel pn layers is described as an example, but when increasing the number of stacked partial parallel pn layers that compose the drift layer 2, the partial parallel pn layers can be increased by two layers (multi-stage epitaxial parallel pn layers and trench-buried parallel pn layers) each time the processes from step S6 to step S12 described above are repeated once. In Fig. 5, this one repetition is indicated by an arrow E1 pointing from step S12 to step S6.

[0125] For example, when drift layer 2 having a full SJ structure is composed of five partial parallel pn layers, the first, third and fifth trench-buried parallel pn layers are set to a thickness of 18 μm, and the second and fourth multistage epitaxial parallel pn layers are set to a thickness of 0.65 μm. This makes it possible to form an SJ structure with the same thickness t5 as when drift layer 2 is composed of the first to third partial parallel pn layers 51 to 53, even when drift layer 2 is composed of five partial parallel pn layers.

[0126] Next, an element structure is formed on the drift layer 2 of the full SJ structure (step S13). Specifically, first, as shown in FIG. 14, a CVD apparatus is used to deposit n - The n-type epitaxial layer 43 is epitaxially grown (formed) to a thickness of, for example, about 0.5 μm. Next, the n-type epitaxial layer 43 is formed by photolithography and ion implantation of p-type impurities. - The surface region of the p-type epitaxial layer 43 is + Type region 11 and p + The mold regions 12a and 12b are alternately and repeatedly formed at intervals in the first direction X.

[0127] p + Type region 11 is p +The p + Type region 11 is p + type area 12(p + Alternatively, the p-type region 12a) may be deeper than the p-type region 12b and terminated inside the third partial parallel pn layer 53 in the lower layer. + The width of the p-type region 11 is made wider than the width of the p-type region 68 of the third partial parallel pn layer 53 and narrower than the repetition pitch of the n-type regions 67 and the p-type regions 68. Next, the n - An n-type region 3 a is formed in a surface region of the n-type epitaxial layer 43 .

[0128] Next, as shown in FIG. - The thickness of the p-type epitaxial layer 43 is then increased. Next, the n-type epitaxial layer 43 is formed by photolithography and ion implantation of p-type impurities. - The thickened portion 43a of the epitaxial layer 43 is p + The p-type regions 12b are selectively formed, and adjacent p + Type regions 12a and p + The mold region 12b is connected to p + A mold region 12 is formed.

[0129] Next, photolithography and ion implantation of n-type impurities are used to create n - An n-type region 3b is formed in a thickened portion 43a of the epitaxial layer 43, and the n-type region 3a and the n-type region 3b adjacent to each other in the depth direction are connected to form an n-type current diffusion region 3.

[0130] Next, as shown in FIG. 16, a CVD apparatus is used to - On the n-type epitaxial layer 43, a p-type epitaxial layer 44 that will become the p-type base region 4 is epitaxially grown. + On the front surface of the starting substrate 41, an epitaxial layer 42, n - A n-type epitaxial layer 43 and a p-type epitaxial layer 44 are laminated in this order, and a semiconductor substrate (semiconductor wafer) 40 is fabricated.

[0131] Next, a set of steps of photolithography and ion implantation is repeated under different conditions to form n + Type source region 5 and p ++ The n-type contact region 6 is selectively formed on the p-type epitaxial layer 44. + Type source region 5 and p ++ The portion excluding the contact region 6 becomes the p-type base region 4 .

[0132] Next, by photolithography and etching, + A gate trench 7 is formed so as to penetrate the p-type source region 5 and the p-type base region 4 and reach the n-type current diffusion region 3. The bottom surface of the gate trench 7 is, for example, p + It may be terminated inside the mold region 11. Next, a heat treatment is performed on the diffusion region formed by ion implantation to activate the impurities.

[0133] Next, a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7. Next, the polysilicon (poly-Si) layer deposited on the front surface of the semiconductor substrate 40 so as to fill the inside of the gate trench 7 is etched back, leaving only the portion that will become the gate electrode 9 inside the gate trench 7. Next, an interlayer insulating film 14 is formed over the entire front surface of the semiconductor substrate 40.

[0134] Next, surface electrodes (source electrode 15 and drain electrode 16) are formed on both sides of semiconductor substrate 40 by a general method (step S14). Each part of intermediate region 20 and edge termination region 30 (see FIG. 2), which are not shown in FIGS. 6 to 16, is formed at a predetermined timing. Thereafter, the semiconductor wafer is diced (cut) into individual chips, thereby completing silicon carbide semiconductor device 50 shown in FIGS. 2 and 3.

[0135] As described above, according to the first embodiment, the drift layer has a structure in which trench-buried parallel pn layers (partial parallel pn layers) and multi-stage epitaxial parallel pn layers (partial parallel pn layers) are alternately stacked in three or more layers. This allows the majority of the total thickness of the thick drift layer to achieve high breakdown voltage to be an SJ structure (full SJ structure). Therefore, more than half of the drift layer is a normal n structure that is not an SJ structure. - Compared to the conventional structure (see FIG. 22) that has a partial SJ structure that becomes a type drift region, the on-resistance can be reduced.

[0136] Moreover, according to the first embodiment, among the three or more partial parallel pn layers constituting the drift layer, the total thickness of the drift layer can be easily increased by the trench-buried parallel pn layers. Also, the more the number of trench-buried parallel pn layers is increased, the thinner the trench-buried parallel pn layers can be, and the narrower the width of the SJ trench can be. Therefore, the widths of the n-type region and p-type region of the trench-buried parallel pn layers can be narrowed, thereby enhancing the effect of reducing the on-resistance.

[0137] Moreover, according to the first embodiment, in forming the trench-buried parallel pn layer, the depth of the SJ trench can be made shallower than the total thickness of the drift layer, so that trench etching of the SJ trench and embedding of the epitaxial layer inside the SJ trench are both easy. Therefore, the manufacturing is easy and the characteristics can be improved. Moreover, according to the first embodiment, it is useful when the drift layer is 10 μm or thicker and the breakdown voltage is 1 kV or more, and is particularly suitable for the drift layer is 30 μm or thicker and the breakdown voltage is 3 kV or more.

[0138] Furthermore, according to the first embodiment, the stripe shapes of the n-type and p-type regions of the trench-buried parallel pn layer and the stripe shapes of the n-type and p-type regions of the multistage epitaxial parallel pn layer extend in different directions when viewed from the front surface side of the semiconductor substrate, thereby making it possible to reliably connect the n-type regions and the p-type regions of the trench-buried parallel pn layer adjacent to each other in the depth direction via the n-type regions and p-type regions of the multistage epitaxial parallel pn layer, respectively.

[0139] In this way, since the n-type regions and p-type regions of the partial parallel p-n layers adjacent in the depth direction can be easily connected to each other, it is possible to omit the formation of alignment marks for aligning the n-type regions and p-type regions of the partial parallel p-n layers in the depth direction and to align them. Therefore, it is possible to avoid unique problems with alignment that arise due to the characteristics of silicon carbide (such as the alignment mark being buried during epitaxial growth depending on the surface orientation).

[0140] (Embodiment 2) Next, the structure of a silicon carbide semiconductor device according to the second embodiment will be described. Fig. 17 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the second embodiment. A silicon carbide semiconductor device 70 according to the second embodiment differs from the silicon carbide semiconductor device 50 (Fig. 2) according to the first embodiment in that a planar gate structure is used instead of the trench gate structure. The silicon carbide semiconductor device 70 according to the second embodiment includes each part of a general planar gate structure on a drift layer 2 (epitaxial layer 42) of a full SJ structure similar to that of the first embodiment.

[0141] Specifically, in the second embodiment, semiconductor substrate 40′ is a n-type semiconductor substrate made of silicon carbide. + An epitaxial layer 42, which is the drift layer 2 of the full SJ structure similar to that of the first embodiment, and an n-type epitaxial layer 43', which is to become an n-type JFET region 74, are deposited in this order on the front surface of a starting substrate 41. The main surface of the semiconductor substrate 40' on the side of the n-type epitaxial layer 43' is the front surface, and the n + The main surface (n+ The back surface of the mold starting substrate 41 is referred to as the back surface.

[0142] A p-type base region 71 is selectively provided in the n-type epitaxial layer 43', penetrating the n-type epitaxial layer 43' in the depth direction. The p-type base region 71 is adjacent to the p-type region 68 of the third partial parallel pn layer 53 in the depth direction Z. An n-type base region 71 is provided between the front surface of the semiconductor substrate 40' and the p-type base region 71, in contact with the p-type base region 71 and exposed to the front surface of the semiconductor substrate 40'. + type source region 72 and p + Mold contact regions 73 are selectively provided.

[0143] The p-type base region 71 of the n-type epitaxial layer 43′ + type source region 72 and p + The portion excluding the contact region 73 is an n-type JFET region 74. The n-type JFET region 74 is exposed on the front surface of the semiconductor substrate 40'. + The n-type source region 72 is spaced apart from the n-type JFET region 74. + Between the p-type source region 72 and the n-type JFET region 74 lies a p-type base region 71. + The contact region 73 is an n + The n-type source region 72 is disposed farther from the n-type JFET region 74 than the n-type source region 72 .

[0144] The p-type base region 71, n + A gate electrode 76 is provided on the surface of the portion sandwiched between the n-type source region 72 and the n-type JFET region 74, with a gate insulating film 75 interposed therebetween. An interlayer insulating film 77 is provided on the entire front surface of the semiconductor substrate 40 so as to cover the gate electrode 76. A source electrode 78 is connected to the n-type source region 72 via a contact hole opened in the interlayer insulating film 77. + type source region 72 and p + The semiconductor substrate 40′ is electrically connected to the first contact region 73. The configuration from the drift layer 2 to the back surface side of the semiconductor substrate 40′ is the same as in the first embodiment.

[0145] The method for manufacturing silicon carbide semiconductor device 70 according to the second embodiment may be the same as the method for manufacturing silicon carbide semiconductor device 50 according to the first embodiment (see FIG. 5), except that in step S13, instead of the trench gate structure, a planar gate structure is formed by a general method. Fig. 18 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the second embodiment. That is, specifically, first, the processes of steps S1 to S12 are performed in the same manner as in the first embodiment.

[0146] 18, in the process of step S13, an n-type epitaxial layer 43' that will become an n-type JFET region 74 is epitaxially grown (formed) on the third partial parallel pn layer 53. + An epitaxial layer 42 and an n-type epitaxial layer 43' are laminated in this order on the front surface of a starting mold substrate 41 to produce a semiconductor substrate (semiconductor wafer) 40'.

[0147] Next, a set of steps of photolithography and ion implantation is repeated under different conditions to form p-type base regions 71, n + type source region 72 and p + The p-type base region 71 and the n-type contact region 73 are selectively formed in the n-type epitaxial layer 43'. + type source region 72 and p + The portion excluding the contact region 73 becomes an n-type JFET region 74 .

[0148] Next, a gate insulating film 75 is formed on the entire front surface of the semiconductor substrate 40'. Next, a polysilicon layer is formed on the front surface of the semiconductor substrate 40' and patterned to form n-type JFET regions 74 between adjacent n-type JFET regions 74. + A portion that becomes gate electrode 76 is left on the surface between type source regions 72. Next, interlayer insulating film 14 is formed all over the front surface of semiconductor substrate 40. Thereafter, step S14 and subsequent steps are performed in order to complete silicon carbide semiconductor device 70 shown in FIG.

[0149] As described above, according to the second embodiment, even when the first embodiment is applied to a planar gate structure, it is possible to obtain the same effects as those of the first embodiment.

[0150] (Embodiment 3) Next, a structure of a silicon carbide semiconductor device according to the third embodiment will be described. Fig. 19 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the third embodiment. A silicon carbide semiconductor device 80 according to the third embodiment differs from the silicon carbide semiconductor device 50 (Fig. 2) according to the first embodiment in that an SJ trench 81 is formed in a p-type epitaxial layer 221 which becomes a p-type region 83 of a third partial parallel pn layer 84 (trench-buried parallel pn layer), and an n-type epitaxial layer 222 which becomes an n-type region 82 is buried inside the SJ trench 81.

[0151] The method for manufacturing silicon carbide semiconductor device 80 according to the third embodiment can be achieved by performing the processes of steps S8 to S11 of the method for manufacturing silicon carbide semiconductor device 50 according to the first embodiment (see FIG. 5) with the conductivity type (n-type, p-type) reversed. That is, specifically, first, the processes of steps S1 to S7 are performed similarly to the first embodiment. Next, in the process of step S8, p-type epitaxial layer 221 is epitaxially grown (formed) on second partial parallel pn layer 52 as a part of epitaxial layer 85 (drift layer 2).

[0152] Next, in step S9, an SJ trench 81 is formed in the p-type epitaxial layer 221. The portions of the p-type epitaxial layer 221 remaining between adjacent SJ trenches 81 become p-type regions 83 of the third partial parallel pn layer 84. The SJ trenches 81 may be formed in the same manner as in the first embodiment, using an oxide film mask having an opening in a portion facing a region where the n-type region 82 is to be formed. Next, in step S10, the n-type epitaxial layer 222 is embedded inside the SJ trench 81.

[0153] The portion of n-type epitaxial layer 222 epitaxially grown in the process of step S10 that remains inside SJ trench 81 becomes n-type region 82 of third partial parallel p-n layer 84. Next, in the process of step S11, the excess portion of n-type epitaxial layer 222 that has grown epitaxially outside SJ trench 81 is removed, leaving n-type epitaxial layer 222 only inside SJ trench 81. Thereafter, the processes from step S12 onwards are performed in order to complete silicon carbide semiconductor device 80 shown in FIG.

[0154] The first partial parallel pn layer 51 (trench-buried parallel pn layer) closest to the drain side is formed in the same manner as in the first embodiment, and cannot be formed with its conductivity type reversed like the third partial parallel pn layer 84 described above. + The entire portion between the starting substrate 41 and the first partial parallel pn layer 51 where the SJ structure is not formed (the portion corresponding to the n-type drift region 2a in FIG. 2) becomes a p-type region, and the p-type region and the n + This is because a pn junction with the starting mold substrate 41 is formed.

[0155] Furthermore, the exposure of the opening pattern onto the etching mask for forming the SJ trench 81 may be performed by using a reticle (not shown) that was used to expose the opening pattern onto the resist film 212 (see FIG. 6) that was used as a mask for forming an opening pattern in the oxide film 211 (see FIGS. 6 and 7) that is the etching mask for forming the SJ trench 61 of the first partial parallel p-n layer 51. In this case, the p-type region 83 of the third partial parallel p-n layer 84 is disposed at a position facing the n-type region 62 of the first partial parallel p-n layer 51 in the depth direction Z.

[0156] The SJ trench 81 may be formed so that the p-type region 83 of the third partial parallel p-n layer 84 faces the n-type region 62 of the first partial parallel p-n layer 51 in the depth direction Z. In this case, the SJ trench 81 may be formed by using an etching mask (oxide film) having openings in an opening pattern shifted in the first direction X by the width (one column) of the n-type region 62, in order to form an opening pattern in a resist film used as a mask in an etching mask (oxide film) for forming the SJ trench 81.

[0157] The second embodiment may be applied to silicon carbide semiconductor device 80 according to the third embodiment, and a planar gate structure may be used instead of the trench gate structure.

[0158] As described above, according to the third embodiment, even when the conductivity type of the trench-buried parallel pn layer (excluding the first partial parallel pn layer) that constitutes the drift layer is inverted, it is possible to obtain the same effects as those of the first and second embodiments.

[0159] (Embodiment 4) Next, the structure of a silicon carbide semiconductor device according to the fourth embodiment will be described. Fig. 20 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to the fourth embodiment. A silicon carbide semiconductor device 80' according to the fourth embodiment differs from the silicon carbide semiconductor device 80 (Fig. 19) according to the third embodiment in that the width w1 of the SJ trench 81' in the third partial parallel pn layer 84' (trench-buried parallel pn layer) is made wider, and the width w2 of the n-type region 82' in the third partial parallel pn layer 84' is made wider than the width w3 of the p-type region 83'.

[0160] As long as the n-type region and the p-type region are roughly charge-balanced for each partial parallel pn layer constituting the drift layer 2, the widths of the n-type region and the p-type region may be different. For example, for the third partial parallel pn layer 84', the width w2 of the n-type region 82' and the width w3 of the p-type region 83' may be approximately 3.0 μm and 1.5 μm, respectively. In this case, the thickness t3' of the third partial parallel pn layer 84' can be increased to deepen the depth d3' of the SJ trench 81'. The depth d3' of the SJ trench 81' is, for example, approximately 35 μm.

[0161] Even if the depth d3' of the SJ trench 81' is deepened, by widening the width w1 of the SJ trench 81', it becomes easier to form the SJ trench 81' in a good trench shape with sidewalls that are approximately perpendicular to the main surface of the semiconductor substrate 40 in the p-type epitaxial layer 221' that becomes the p-type region 83' of the third partial parallel p-n layer 84'. Furthermore, by widening the width w1 of the SJ trench 81', it becomes easier to avoid problems that occur when embedding the n-type epitaxial layer 222' that becomes the n-type region 82' of the third partial parallel p-n layer 84' inside the SJ trench 81'.

[0162] A problem that occurs when the n-type epitaxial layer 222' is embedded in the SJ trench 81' is that the n-type epitaxial layers 222' epitaxially grown on both side walls of the SJ trench 81' join together near the upper portion of the opening of the SJ trench 81', blocking the upper portion of the opening of the SJ trench 81' and making it impossible to embed the n-type epitaxial layer 222'. By making it easier to avoid this problem, it becomes easier to completely embed the n-type epitaxial layer 222' inside the SJ trench 81', and the on-resistance reduction effect of the SJ structure is enhanced.

[0163] The n-type region 82' and p-type region 83' of the third partial parallel pn layer 84' are generally charge balanced. For this reason, the p-type impurity concentration of p-type region 83' is higher than the n-type impurity concentration of n-type region 82'. When making the p-type impurity concentration of the p-type region different for each partial parallel pn layer constituting the drift layer 2, it is preferable to make the p-type impurity concentration of the p-type region of the partial parallel pn layer closest to the source the highest, and to make the p-type impurity concentration of the p-type region lower in the partial parallel pn layer disposed in a position closer to the drain side.

[0164] Therefore, it is preferable that the p-type impurity concentrations of the p-type regions 62, 65 of the first and second partial parallel pn layers 51, 52 be equal to or lower than the p-type impurity concentration of the p-type region 83' of the third partial parallel pn layer 84'. By making the p-type impurity concentration of the p-type region 83' of the third partial parallel pn layer 84' closest to the source the highest, and making the p-type impurity concentrations of the p-type regions of the first and second partial parallel pn layers 51, 52 arranged closer to the drain side lower, it is possible to increase the effect of reducing the on-resistance by the SJ structure when the p-type impurity concentrations of the p-type regions differ for each partial parallel pn layer.

[0165] The manufacturing method of the silicon carbide semiconductor device 80' according to the fourth embodiment is the same as the manufacturing method of the silicon carbide semiconductor device 80 according to the third embodiment, except that the thickness t3' of the p-type epitaxial layer 221', which is part of the epitaxial layer 85' (drift layer 2), is increased, the depth d3' of the SJ trench 81' formed in the p-type epitaxial layer 221' is increased, and the width w1 of the SJ trench 81' is increased.

[0166] The second embodiment may be applied to a silicon carbide semiconductor device 80' according to the fourth embodiment, and a planar gate structure may be used instead of the trench gate structure.

[0167] As described above, according to the fourth embodiment, even if the widths of the n-type regions and p-type regions differ for each partial parallel pn layer constituting the drift layer, as long as the n-type regions and p-type regions are roughly charge balanced for each partial parallel pn layer constituting the drift layer, the same effects as those of the first to third embodiments can be obtained.

[0168] (Example) Next, the thickness t2 (see FIGS. 2, 9, and 10) of the second partial parallel pn layer 52 (multistage epitaxial parallel pn layer) was examined. FIG. 21 is a characteristic diagram showing the doping concentration of the ion implantation region of the multistage epitaxial parallel pn layer. The horizontal axis of FIG. 21 shows the depth from the ion implantation surface, and the vertical axis shows the aluminum doping concentration. The thickness t2 (see FIGS. 2, 9, and 10) of the p-type region formed by ion implanting aluminum into an n-type epitaxial layer of silicon carbide in multiple stages at different acceleration energies (hereinafter referred to as multistage ion implantation) was 1×10 16 / cm 3 The box profile of the degree of the change is shown in FIG.

[0169] This multi-stage ion implantation corresponds to ion implantation 215 (see FIG. 10) for forming p-type region 65 of second partial parallel p-n layer 52. The n-type epitaxial layer subjected to multi-stage ion implantation corresponds to n-type epitaxial layer 203 (FIGS. 9 and 10) constituting second partial parallel p-n layer 52. The box profile of the p-type region shown in FIG. 21 corresponds to the doping concentration distribution of p-type region 65 of second partial parallel p-n layer 52.

[0170] Multi-stage ion implantation was performed in eight stages (eight times) with different acceleration energies from a direction perpendicular to the ion implantation surface in a temperature environment of 500°C. A box profile was formed by ion implantation, but compared to a semiconductor region formed by epitaxial growth, the impurity concentration in the depth direction Z of the semiconductor region of the box profile formed by ion implantation is not uniform, and has a periodic concentration distribution.

[0171] Multi-stage ion implantation was performed using a general ion implantation device under the following conditions: The acceleration energy and dose of the first stage ion implantation were 700 keV and 2.20 × 10 11 / cm 2 The acceleration energy and dose of the second ion implantation are 550 keV and 8.00×10 10 / cm 2The acceleration energy and dose of the third ion implantation are 400 keV and 2.00×10 11 / cm 2 The acceleration energy and dose of the fourth ion implantation are 220 keV and 1.50×10 11 / cm 2 It is.

[0172] The acceleration energy and dose of the fifth ion implantation are 100 keV and 1.00×10 11 / cm 2 The acceleration energy and dose of the sixth ion implantation are 50 keV and 3.00×10 10 / cm 2 The acceleration energy and dose of the seventh ion implantation are 30 keV and 2.00×10 10 / cm 2 The acceleration energy and dose of the eighth ion implantation are 20 keV and 1.50×10 11 / cm 2 It is.

[0173] From the results shown in FIG. 21, the concentration of ions was 1×10 16 / cm 3 It has been confirmed that the doping concentration decreases as the depth from the ion implantation surface becomes deeper than 0.65 μm (the portion indicated by the symbol F). For this reason, it is preferable that the thickness t2 of the second partial parallel pn layer 52 is about 0.65 μm or less. Furthermore, the present inventors have confirmed that although a portion with a low impurity concentration occurs in the surface region of the ion implantation surface, it is removed by hydrogen etching when the upper epitaxial layer is formed.

[0174] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0175] INDUSTRIAL APPLICABILITY As described above, the silicon carbide substrate according to the present invention is useful for silicon carbide semiconductor devices having a withstand voltage of 1 kV or higher, and is particularly suitable for silicon carbide semiconductor devices having a withstand voltage of 3.3 kV or higher. [Explanation of symbols]

[0176] 1n + Type drain region 2. Drift layer 2a n-type drift region 3 n-type current diffusion region 3a,3b n-type region 4,71 p-type base region 5,72 n + Type Source Area 6 p ++ Mold Contact Area 7,7a Gate trench 8,75 Gate insulating film 9,76 Gate electrode 10 Active area 11,11a,12,12a,12b,13p + type area 14,77 Interlayer insulating film 15,78 Source electrode 16 Drain electrode 20 Intermediate area 21 Gate Runner 22 Gate metal wiring 30 Edge Termination Area 31 Steps 32 1st JTE Area 33 2nd JTE area 34 JTE structure 35 n + Mold stopper area 36 Field oxide 40,40' Semiconductor substrate 40a: A portion of the front surface of the semiconductor substrate on the active region side (first surface) 40b: A portion (second surface) outside the step on the front surface of the semiconductor substrate 40c: A portion of the front surface of the semiconductor substrate between the first surface and the second surface (a stepped mesa edge: a third surface) 41 n+ Starting substrate 42,42' epitaxial layer 43 n - Type epitaxial layer 43' n-type epitaxial layer 43a: The n-type epitaxial layer has been thickened 44 p-type epitaxial layer 50,70,80,80' Silicon carbide semiconductor device 51,51' 1st partially parallel pn layer 52,52' 2nd partially parallel pn layer 53,53',84,84' 3rd partially parallel pn layer 61,61' SJ trench of the first partial parallel pn layer 62,62' n-type region of the first partial parallel pn layer 63,63' p-type region of the first partial parallel pn layer 64,64' n-type region of the second partial parallel pn layer 65,65' p-type region of the second partial parallel pn layer 66,66',81,81' SJ trench of the third parallel pn layer 67,67',82,82' n-type region of the third partial parallel pn layer 68,68',83,83' p-type region of the third partial parallel pn layer 73 p + Mold Contact Area 74 n-type JFET region 201,203,204,222 n-type epitaxial layer 202,205,221 p-type epitaxial layer 211,213,216 Oxide film 212,214,217 Resist film w1 Width of the SJ trench of the third partial parallel pn layer w2 Width of the n-type region of the third partial parallel pn layer w3 Width of the p-type region of the third partial parallel pn layer w11, w13, w15 Resist film opening width w12, w14, w16 Remaining width between adjacent openings in resist film X: A first direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction Z depth direction

Claims

1. A silicon carbide substrate having first and second conductivity type regions extending in a stripe pattern parallel to a main surface and including parallel pn layers repeatedly arranged alternately in a direction perpendicular to the stripe pattern, A starting substrate made of silicon carbide; a first partial parallel pn layer that is stacked on the starting substrate and forms a part of the parallel pn layer; a second partial parallel pn layer stacked on the first partial parallel pn layer and forming a part of the parallel pn layer; a third partial parallel pn layer stacked on the second partial parallel pn layer and constituting a part of the parallel pn layer; Equipped with The first partial parallel pn layer is a first epitaxial layer of a first conductivity type made of silicon carbide laminated on the starting substrate; a first trench extending from a surface of the first epitaxial layer to a predetermined depth; the first conductivity type region being a portion of the first epitaxial layer between adjacent first trenches; the second conductivity type region being a second epitaxial layer of a second conductivity type embedded in the first trench; the second partial parallel pn layer has a third epitaxial layer of a first conductivity type made of silicon carbide stacked on the first epitaxial layer, and crystal defects are introduced into the second conductivity type region inside the third epitaxial layer or into the entire third epitaxial layer; a direction in which the first conductivity type region and the second conductivity type region of the third partial parallel p-n layer extend in stripes parallel to the main surface intersects a direction in which the first conductivity type region and the second conductivity type region of the second partial parallel p-n layer extend in stripes parallel to the main surface, The third partial parallel pn layer is a fourth epitaxial layer of a first conductivity type made of silicon carbide laminated on the third epitaxial layer; a second trench extending from a surface of the fourth epitaxial layer to the second partial parallel pn layer and terminating within the second partial parallel pn layer; the first conductivity type region being a portion of the fourth epitaxial layer between adjacent second trenches; the second conductivity type region being a fifth epitaxial layer of a second conductivity type embedded in the second trench; the first conductivity type region and the second conductivity type region of the second partial parallel pn layer have the same impurity concentrations as the first conductivity type region and the second conductivity type region of the first partial parallel pn layer, respectively; the first conductivity type region and the second conductivity type region of the third partial parallel p-n layer having the same impurity concentrations as the first conductivity type region and the second conductivity type region of the first partial parallel p-n layer, respectively.

2. The second partial parallel pn layer, the second conductivity type region being a diffusion region containing a second conductivity type impurity introduced into the third epitaxial layer; 2 . The silicon carbide substrate according to claim 1 , further comprising: a first conductivity type region which is a portion of said third epitaxial layer excluding said diffusion region. 3 .

3. A silicon carbide substrate as described in claim 1 or 2, characterized in that the second conductivity type region of the third partial parallel pn layer terminates inside the second partial parallel pn layer.

4. The second partial parallel pn layer is the third epitaxial layer made of silicon carbide having an impurity concentration lower than that of the first conductivity type region of the parallel pn layer; the second conductivity type region being a diffusion region containing a second conductivity type impurity introduced into the third epitaxial layer; 4. The silicon carbide substrate according to claim 1, wherein the first conductivity type region is a diffusion region containing a first conductivity type impurity introduced into the third epitaxial layer.

5. A silicon carbide substrate as described in any one of claims 1 to 4, characterized in that the direction in which the first conductivity type region and the second conductivity type region of the second partial parallel p-n layer extend in stripes parallel to the main surface forms an angle of 45 degrees or more with the direction in which the first conductivity type region and the second conductivity type region of the first partial parallel p-n layer extend in stripes parallel to the main surface.

6. 6. The silicon carbide substrate according to claim 5, wherein a direction in which the first conductivity type region and the second conductivity type region of the second partial parallel p-n layer extend in stripes parallel to the main surface is perpendicular to a direction in which the first conductivity type region and the second conductivity type region of the first partial parallel p-n layer extend in stripes parallel to the main surface.

7. 7. The silicon carbide substrate according to claim 1, wherein the second partial parallel pn layer has a periodic concentration distribution in a depth direction.

8. 8. The silicon carbide substrate according to claim 1, wherein the second partial parallel pn layer is thinner than the first partial parallel pn layer.

9. 9. The silicon carbide substrate according to claim 1, wherein the third partial parallel pn layer is thicker than the second partial parallel pn layer.

10. A silicon carbide substrate described in any one of claims 1 to 9, characterized in that the first conductivity type region and the second conductivity type region of the first partial parallel pn layer are connected to the first conductivity type region and the second conductivity type region of the third partial parallel pn layer, respectively, via the second partial parallel pn layer.

Images