SOI Wafer

Abstract

To provide an SOI wafer whose terrace width can be made smaller than that of a thin-film SOI wafer produced by a smart cut method and which has an active layer with a thickness of less than 1 μm, which can be realized by a bonding method.SOLUTION: An SOI wafer includes: a support substrate made of silicon single crystal; an oxide film located on the support substrate; and an active layer located on the oxide film and made of silicon single crystal. The thickness of the active layer is 0.3 μm or more and less than 1 μm, the width of the region where the oxide film or the support substrate is exposed outward from the outer edge of the active layer when viewed from above is 1.5 mm or less in the radial direction from the end surface of the soi wafer, and the support substrate and the oxide film are arranged in a stepped manner at the peripheral edge of the SOI wafer, and the width W and the thickness T satisfy T≥0.36 W+0.32.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an SOI wafer. [Background technology]

[0002] SOI wafers (Silicon on Insulator) are a well-known type of semiconductor wafer. SOI wafers have a structure in which an insulating film such as silicon oxide (SiO2) and a single-crystal silicon layer used as the device active layer (sometimes called the "active layer" or "SOI layer") are formed in this order on a supporting substrate. SOI wafers are classified according to the thickness of their active layer; those with an active layer thickness of 1 μm or more are called "thick-film SOI," while those with an active layer thickness of less than 1 μm are called "thin-film SOI." Generally, thick-film SOI is used in power devices and BiCMOS, while thin-film SOI is used in CMOS-LSI, etc.

[0003] Here, the SmartCut method (registered trademark) and the bonding method are known as representative methods for manufacturing SOI wafers. In the SmartCut method, a high concentration of hydrogen ions is implanted into a silicon substrate for the active layer to form an embrittlement-treated layer. The silicon substrate is then peeled off at the embrittlement-treated layer to form an active layer, and the peeled active layer is then bonded to a support substrate via an oxide film to produce an SOI wafer (see, for example, Patent Document 1). The SmartCut method cannot implant hydrogen ions deep into the wafer from the surface, making it impossible to obtain a thick active layer. Therefore, it is a technology applicable only to thin-film SOI manufacturing. On the other hand, the bonding method forms an oxide film (also called a "BOX (Buried Oxide) layer") on at least one of the support substrate and the active layer substrate, and then these substrates are stacked together via the oxide film, followed by a bonding heat treatment at a high temperature of approximately 1200°C to produce an SOI wafer (see, for example, Patent Document 2). The bonding method involves bonding two silicon wafers together with an oxide film between them, so the thickness of the active layer can be adjusted as desired, and is therefore generally used in the manufacture of thick-film SOI. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 5-211128 [Patent Document 2] JP 8-250688 Summary of the Invention [Problem to be solved by the invention]

[0005] The non-SOI region at the periphery of an SOI wafer, i.e., the portion where the support substrate or oxide film is exposed beyond the outer edge of the active layer, is called the "terrace portion." The width of the terrace portion is called the "terrace width" (JEITA EM-3604A).

[0006] Figure 1(A) shows an optical microscope image of a thin-film SOI wafer fabricated using a typical Smart Cut process before final polishing. It is a magnified image of the peripheral area, including the boundary between the active layer and the terrace. The terrace width of a thin-film SOI wafer is typically greater than 2 mm and less than 3 mm, even before final polishing. Furthermore, as shown in Figure 1(A), the boundary between the active layer and the oxide film is distorted, resulting in the formation of multiple dot-like protrusions (called SOI islands) on the terrace. These boundaries and SOI islands can cause contamination during device fabrication. Therefore, the terrace is subjected to final polishing. However, as shown in Figure 1(B), the boundary after final polishing is not circular, but rather undulating. Furthermore, the final terrace width increases to 3 mm or more (in Figure 1(B), the terrace width after final polishing is approximately 4–5 mm).

[0007] To increase the effective area for device fabrication, the edge exclusion of semiconductor wafers has been increasing from 3 mm from the wafer edge to 2 mm, with further reductions to 1 mm being required. While a reduction in the edge exclusion is also expected for thin-film SOI, it is necessary to reduce the terrace width. However, as mentioned above, thin-film SOI wafers fabricated using the Smart Cut method have a wide terrace width and low bonding strength at the periphery of the active layer, making it difficult to reduce the terrace width to 2 mm or less. In fact, even if additional terrace polishing is performed on the periphery to remove SOI islands, the terrace width increases from 2 mm to 3–4 mm, and waviness is formed.

[0008] In order to realize a narrower terrace width for thin-film SOI wafers, the inventors attempted to apply the bonding method, which is used for thick-film SOI wafers, instead of the Smart Cut method, which is conventionally used for thin-film SOI fabrication. Specifically, the inventors investigated whether it would be possible to fabricate thin-film SOI wafers with an active layer thickness of less than 1 μm using the bonding method.

[0009] The present inventors attempted to thin the active layer by lamination with a terrace width of 2 mm, which is narrower than the lower limit of the terrace width in the Smart Cut method, but discovered that in this case, part of the active layer was completely removed in the thickness direction, exposing the oxide film.

[0010] Therefore, an object of the present invention is to provide a method for manufacturing an SOI wafer that can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method. [Means for solving the problem]

[0011] The present inventors have conducted extensive research to solve the above problems and have come to the following findings. (A) First, to reduce the thickness of the active layer of an SOI wafer by bonding to less than 1 μm without exposing the oxide film, the active layer substrate must be ground with high precision. Therefore, the application of dry chemical planarization (DCP) processing using local plasma etching is considered suitable, at least in the final stage of thinning. Because DCP processing uses local plasma etching, the surface roughness is inferior to that of a conventionally polished surface. Therefore, after DCP processing, the surface of the active layer substrate is subjected to final polishing.

[0012] (B) However, when the DCP process and finish polishing were performed with a terrace width of 2 mm, it was experimentally confirmed that the oxide film was exposed at the edge of the active layer where the active layer was located before the finish polishing. Even when the terrace width was set to 3 mm, assuming the extension of the edge exclusion region to be false, the oxide film was still exposed. After detailed investigation into the cause of this, the inventors concluded that the pressure from the pad at the edge of the active layer during finish polishing was greater than that at the center of the active layer due to the shape of the SOI wafer before the finish polishing, resulting in excessive removal of the edge of the active layer.

[0013] (C) Therefore, by optimizing the shape of the SOI wafer before final polishing, it is possible to suppress pressure from the pad at the edge of the active layer, and as a result, it is possible to prevent the exposure of the oxide film. The terrace width before final polishing is a particularly important indicator of the shape of the SOI wafer. The present invention is based on the above findings and studies, and has the following gist and configuration.

[0014] The method for producing an SOI wafer of the present invention includes an oxide film forming step of forming an oxide film on a surface of at least one of an active layer substrate made of silicon single crystal and a support substrate made of silicon single crystal; a bonding step of bonding the active layer substrate and the support substrate together via the oxide film; a thinning step of thinning the active layer substrate from a surface opposite to the support substrate after the bonding step, the thinning step includes a first step of flattening the surface of the active layer substrate by dry chemical etching, and a second step of polishing the surface of the active layer substrate to form an active layer having a thickness of less than 1 μm; Prior to the second step, the width of the region where the oxide film or the support substrate is exposed outward from the outer edge of the active layer substrate in a top view is set to 1.5 mm or less in the radial direction from the end face of the SOI wafer.

[0015] Here, it is preferable that the thickness of the active layer is 0.3 μm or more.

[0016] Furthermore, the method for producing an SOI wafer of the present invention further includes, between the bonding step and the thinning step, a chamfering step of chamfering an edge of the active layer substrate so that a peripheral portion on the support substrate side remains, a wet etching step following the chamfering step of wet-etching the remaining portion to expose a part of the oxide film, and a removal step following the wet etching step of removing the peripheral portion of the oxide film, wherein the width is set to 1.5 mm or less in the removal step, and when the width is W (mm) and the thickness is T (μm), it is preferable that W and T satisfy the following formula (1): Note T≧0.36W+0.32 (1)

[0017] On the other hand, the method for producing an SOI wafer of the present invention further includes, between the bonding step and the thinning step, a surface grinding step of grinding the surface of the active layer substrate, and a peripheral portion polishing step of polishing the peripheral portion of the active layer substrate from an oblique direction relative to the main surface of the active layer substrate following the surface grinding step, and it is preferable that in the peripheral portion polishing step, the width is set to 1.5 mm or less, and when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (2): Note T≧0.54W+0.24 (2)

[0018] In addition, it is preferable that the method for producing an SOI wafer of the present invention further includes, between the bonding step and the thinning step, an edge grinding step of grinding edges of the bonded active layer substrate and support substrate to form a continuous rounded or tapered surface via the oxide film.

[0019] The SOI wafer of the present invention comprises a support substrate made of single crystal silicon, an oxide film located on the support substrate, and an active layer made of single crystal silicon located on the oxide film, wherein the thickness of the active layer is less than 1 μm, and the width of a region where the oxide film or the support substrate is exposed outward from the outer edge of the active layer in a top view is 1.5 mm or less in the radial direction from the end face of the SOI wafer.

[0020] Here, the thickness of the active layer is preferably 0.3 μm or more.

[0021] In the SOI wafer of the present invention, it is preferable that the support substrate and the oxide film are arranged in a stepped manner at the peripheral portion of the SOI wafer, and when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (1): Note T≧0.36W+0.32 (1)

[0022] On the other hand, in the SOI wafer of the present invention, it is preferable that the support substrate is exposed at the peripheral portion of the SOI wafer, the ends of the oxide film and the active layer have continuous rounded or tapered surfaces, and when the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (2): Note T≧0.54W+0.24 (2)

[0023] In addition, in the SOI wafer of the present invention, it is preferable that the edges of the active layer and the support substrate have a continuous rounded or tapered surface with the oxide film interposed therebetween. [Effects of the Invention]

[0024] According to the SOI wafer manufacturing method of the present invention, it is possible to provide a SOI wafer manufacturing method that can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method. [Brief explanation of the drawings]

[0025] [Figure 1] 1A and 1B are photographs showing the vicinity of a terrace portion of an SOI wafer produced by the Smart Cut method according to the prior art, where (A) is an optical microscope photograph of the vicinity of the terrace portion before finish polishing, and (B) is a photograph of the vicinity of the terrace portion after finish polishing. [Figure 2] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to an embodiment of the present invention. [Figure 3] 1A to 1C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to a first preferred embodiment of the present invention. [Figure 4] FIG. 3 is a schematic cross-sectional view illustrating a second step of finish polishing in the method for producing an SOI wafer according to the first preferred embodiment of the present invention. [Figure 5] 5A to 5C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to a second preferred embodiment of the present invention. [Figure 6] FIG. 10 is a schematic cross-sectional view illustrating a second step of finish polishing in a method for producing an SOI wafer according to a second preferred embodiment of the present invention. [Figure 7] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing an SOI wafer according to a third preferred embodiment of the present invention. [Figure 8] FIG. 10 is a schematic cross-sectional view illustrating a second step of finish polishing in a method for producing an SOI wafer according to a third preferred embodiment of the present invention. [Figure 9] 1 is a graph showing the relationship between the terrace width and the thickness of the active layer in Experimental Examples 1 to 3. [Figure 10]Photographs (A) and (B) are of the vicinity of the terrace portion after finish polishing in Experimental Example 3, and photographs (C) and (D) are of the vicinity of the terrace portion after finish polishing in Experimental Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of the present invention will be described with reference to the drawings. For the sake of convenience, the thickness and width of each component are exaggerated in Fig. 2 to Fig. 8, rather than representing the actual thickness ratio.

[0027] (SOI wafer manufacturing method) A method for manufacturing an SOI wafer according to one embodiment of the present invention will be described with reference to FIG. 2. The method for manufacturing an SOI wafer 100 according to one embodiment of the present invention includes an oxide film formation step (FIGS. 2(A) and 2(B)) of forming an oxide film 11A on at least one surface of an active layer substrate 10A made of single crystal silicon and a support substrate 20 made of single crystal silicon; a bonding step (FIG. 2(C)) of bonding the active layer substrate 10A and the support substrate 20 together via the oxide film 11A; and a thinning step (FIGS. 2(D) and 2(E)) of thinning the active layer substrate 10A from the surface opposite the support substrate 20 after the bonding step. Note that, for convenience of illustration, the oxide film 11A is formed on the active layer substrate 10A in FIG. 2, but an oxide film may be formed on the support substrate 20, or on both the active layer substrate 10A and the support substrate 20.

[0028] In this embodiment, the thinning process includes a first step of dry chemical etching the surface of the active layer substrate 10C to flatten the surface, and a second step of polishing the surface of the active layer substrate 10C to form an active layer 10 with a thickness of less than 1 μm (FIGS. 2(D) and 2(E)). Prior to this second step, the width W of the region where the oxide film 11 or the support substrate 20 is exposed beyond the outer edge of the active layer substrate in a top view is set to 1.5 mm or less in the radial direction from the edge of the SOI wafer 100. FIG. 2(E) is a schematic cross-sectional view of the SOI wafer 100 obtained by this manufacturing method. Hereinafter, the width of the region where the oxide film 11 or the support substrate 20 is exposed beyond the outer edge of the active layer substrate in a top view is referred to as the "terrace width." In this specification, the "edge of the SOI wafer" refers to the outermost periphery of the SOI wafer in a top view. Each step will be described in detail below.

[0029] First, as shown in FIG. 2(A), an active layer substrate 10A is prepared. A single crystal silicon wafer made of a silicon single crystal is used as the active layer substrate 10A. The single crystal silicon wafer can be obtained by slicing a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) with a wire saw or the like. An arbitrary impurity dopant element may be added to make the wafer n-type or p-type.

[0030] 2(A), a support substrate 20 is prepared separately from the active layer substrate 10A. The support substrate 20 is a wafer used as a support substrate for the SOI wafer 100, and may be a single crystal silicon wafer similar to the active layer substrate 10A. The active layer substrate 10A and the support substrate 20 may be different from each other in terms of oxide concentration, conductivity type, etc., or may be the same.

[0031] Next, as shown in FIG. 2(B), an oxide film 11A is formed on the active layer substrate 10A by, for example, heat treatment in an oxidizing atmosphere. While the oxide film 11A is shown formed on the entire surface of the active layer substrate 10A, it may be formed on only one side of the active layer substrate 10A. As described above, the oxide film may be formed on the support substrate 20, or on both the active layer substrate 10A and the support substrate 20. The oxide film 11A may be made of, for example, silicon oxide (SiO2) and may be formed using a commonly used thermal oxide film forming apparatus. The thickness of the oxide film 11A may be appropriately set within a range that allows its use as an SOI. While not intended to be limiting, the thickness of the oxide film 11A located between the active layer substrate 10A and the support substrate 20 may be, for example, 0.1 to 10 μm, or may be 10 to 30 μm.

[0032] 2(C), the active layer substrate 10A and the support substrate 20 are bonded together via the oxide film 11A so that the oxide film 11A is located between the active layer substrate 10A and the support substrate 20. This bonding can be performed using a general wafer bonding device. After this bonding, it is also preferable to perform a heat treatment to strengthen the bond strength of the bonded joint. The bond strengthening heat treatment can be performed, for example, in an oxidizing gas or inert gas atmosphere at a temperature of 800°C to 1200°C for 10 minutes to 6 hours.

[0033] Next, in order to form the final active layer 10 (see FIG. 2(E)), a thinning process is performed to thin the active layer substrate 10A from the surface opposite the support substrate 20 (FIGS. 2(D) and 2(E)). This thinning process includes a first process of dry chemical etching the active layer substrate 10C to flatten the surface, and a second process of polishing the surface of the active layer substrate 10C to form an active layer 10 with a thickness T of less than 1 μm. Prior to this first process, the active layer substrate 10A may be subjected to a well-known surface grinding method or mirror polishing method.

[0034] Here, the first step involves DCP (Dry Chemical Planarization) processing. In DCP processing, etching gas is converted into plasma using microwaves to generate ions and reactive radicals, and localized plasma etching is performed using the radicals as the main etchant. During plasma etching, the etching gas is injected while measuring the thickness and changing the stage speed, thereby performing high-precision local processing. This type of DCP processing can be performed using a general DCP processing machine. This DCP processing can reduce the tolerance of the active layer thickness.

[0035] The DCP processing in the first step uses local plasma etching, and therefore the surface roughness is inferior to polishing by mechanical polishing, chemical mechanical polishing (CMP), or the like. Therefore, in the second step, the active layer substrate 10C is finish-polished to form the active layer 10. The thickness T of the active layer 10 after finish-polishing is set to less than 1 μm. The thickness of the active layer substrate may be set to less than 1 μm at the stage after DCP processing. The polishing allowance by finish polishing is usually about 0.05 μm to 0.30 μm, and the surface roughness can be improved by finish polishing. Either double-sided polishing or single-sided polishing can be used for finish polishing, but single-sided polishing is more preferable.

[0036] Here, it is essential to set the terrace width W to 1.5 mm or less at least prior to the second step. The terrace width W may be set to the above range prior to the first step. In the DCP processing in the first step, the thickness of the active layer substrate 10C is measured in advance, and DCP processing is performed based on the measurement results, so that the thickness has almost no effect on the terrace width after processing. To set the terrace width T to 1.5 mm or less, known methods such as chamfer etching, terrace polishing, and terrace-free wafer fabrication can be applied.

[0037] According to the study by the present inventors, it has been experimentally confirmed that when the second step is performed, if the terrace width T is 1.5 mm or less, even if the thickness T of the active layer 10 after the second step of finish polishing is less than 1 μm, the oxide film 11 will not be exposed. Note that "no exposure of the oxide film" here does not refer to the oxide film that was exposed before the finish polishing, but rather means that the unexposed portion that was not exposed before the finish polishing is exposed after the finish polishing.

[0038] Contrary to the inventors' expectations, thinning of thin-film SOI wafers by the bonding method was successfully achieved by narrowing the terrace width T to 1.5 mm or less rather than widening it during the second step. The inventors believe this is because, when the active layer is very thin (less than 1 μm), if the terrace width exceeds 1.5 mm immediately before the final polishing, the polishing pad sinks into the SOI wafer's peripheral edge, resulting in greater pressure toward the peripheral edge and resulting in more of the active layer being ground away. On the other hand, the inventors believe that if the terrace width is 1.5 mm or less immediately before the final polishing, the active layer, oxide film, and supporting substrate have a relatively smooth shape when viewed macroscopically at the peripheral edge of the SOI wafer, resulting in less pressure on the edge of the active layer.

[0039] As described above, this embodiment provides a method for manufacturing an SOI wafer that can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method. Preferred embodiments of this embodiment will be described below in order.

[0040] (First Preferred Embodiment) In the first preferred embodiment, in order to set the terrace width T to 1.5 mm or less, a so-called "chamfering etching method" is performed prior to the thinning process. That is, as shown in FIG. 3, it is preferable to first perform a chamfering process between the lamination process and the thinning process, in which the edge of the active layer substrate 10A is chamfered so that the peripheral edge portion of the support substrate side 20 remains. After the active layer substrate 10A is chamfered, it becomes the active layer substrate 10B1 as shown in FIG. 3(B). During this chamfering, the oxide film 11A is removed, separating the active layer substrate 10B1 into an upper oxide film 11C and a lower oxide film 11B.

[0041] Following this chamfering step, a wet etching step is preferably performed, as shown in FIG. 3(C), in which the remaining portion of the active layer substrate 10B1 on the support substrate side is wet-etched to expose a portion of the oxide film 11B. After the etching step, the active layer substrate 10B2 is formed. Following this wet etching step, a removal step is performed to remove the peripheral portion of the oxide film 11B (FIG. 3(D)). A general polishing or grinding method can be used in this removal step, and it is preferable to set the terrace width in this removal step to 1.5 mm or less. Finally, by performing the thinning step described above, a thin-film SOI wafer with an active layer thickness of less than 1 μm can be produced (FIG. 3(E)).

[0042] In this preferred embodiment, it is preferable to carry out the removal step so that W and T satisfy the following formula (1), where W (mm) is the terrace width and T (μm) is the active layer thickness. T≧0.36W+0.32 (1) If the terrace width and the active layer thickness satisfy the formula (1), a thin-film SOI wafer in which the oxide film is not exposed can be more reliably realized.

[0043] In this preferred embodiment, as shown in Figures 4(A) to 4(C), the terrace width during finish polishing is 1.5 mm or less, which prevents the polishing pad P from sinking into the peripheral portion of the SOI wafer 200 during finish polishing. This prevents further exposure of the oxide film 11 even after forming an active layer 10 with a thickness of less than 1 µm. However, depending on the polishing conditions, if the terrace width exceeds 1.5 mm or if T and W do not satisfy the above formula (1), the terrace width of the SOI wafer 200' to be fabricated will be W' (W' > W), as shown in Figure 4(D), and the peripheral portion of the active layer 10 may be excessively removed, resulting in exposure of the oxide film 11.

[0044] (Second Preferred Embodiment) In a second preferred embodiment, in order to set the terrace width to 1.5 mm or less, a so-called "terrace polishing method" is performed prior to the thinning step. That is, as shown in FIG. 5, it is preferable to first perform a surface grinding step of grinding the surface of the active layer substrate 10A between the bonding step and the thinning step. After the surface grinding, the active layer substrate 10B is formed, and an oxide film 11B is formed accordingly (FIG. 5(B)). A known grinding method can be used for the surface grinding.

[0045] Following this surface grinding step, a peripheral polishing step is preferably performed, in which the peripheral portion of the active layer substrate 10B is polished obliquely relative to the main surface of the active layer substrate 10B. After the peripheral polishing step, the active layer 10C is formed, and the edges of the oxide film 11B and the support substrate 20 are also polished (FIG. 5(C)). This peripheral polishing can also be performed using a known polishing method in which only the outer periphery is polished while the support substrate 20 is held by a holding plate or the like having an uneven surface. Furthermore, this peripheral polishing step preferably results in a terrace width of 1.5 mm or less. Finally, the previously described thinning step is performed to produce a thin-film SOI wafer having an active layer thickness of less than 1 μm (FIG. 5(D)).

[0046] In this preferred embodiment, it is preferable to perform the peripheral polishing step so that W and T satisfy the following formula (2), where W (mm) is the terrace width and T (μm) is the active layer thickness. T≧0.54W+0.24 (2) If the terrace width and the active layer thickness satisfy the formula (2), a thin-film SOI wafer in which the oxide film is not exposed can be more reliably realized.

[0047] 6(A) to 6(C), in this preferred embodiment, the terrace width during finish polishing is 1.5 mm or less, which can suppress sinking of the polishing pad P at the peripheral edge of the SOI wafer 300 during finish polishing, and can prevent further exposure of the oxide film 11 even after forming an active layer 10 with a thickness of less than 1 μm. However, depending on the polishing conditions, if the terrace width exceeds 1.5 mm or if T and W do not satisfy the above formula (2), the terrace width of the SOI wafer 300′ to be fabricated will be W′ (W′>W), as shown in FIG. 6(D), and the peripheral edge of the active layer 10 may be excessively removed, resulting in exposure of the oxide film 11.

[0048] Comparing the control of the terrace width by the chamfer etching method described above with the control of the terrace width by the terrace polishing method, the terrace polishing method tends to make the active layer substrate 10C more likely to come into contact with the polishing pad P, and the oxide film 11 is more likely to be exposed when that portion is ground away. Therefore, it is more preferable to use the first embodiment for controlling the terrace width.

[0049] (Third Preferred Embodiment) In a third preferred embodiment, in order to set the terrace width to 1.5 mm or less, a so-called "terrace-free" SOI wafer is formed prior to the thinning process (sometimes referred to as "rounding processing"). That is, as shown in FIG. 7, between the bonding process and the thinning process, an edge grinding process is preferably performed in which the edges of the bonded active layer substrate 10B and support substrate 20 are ground to form a continuous rounded or tapered surface via the oxide film 11B (FIGS. 7(A)-(C)). More specifically, the bonded active layer substrate 10B and support substrate 20 are preferably ground on the periphery using a grinding stone of a predetermined shape (FIG. 7(B)), followed by surface grinding (FIG. 7(C)). After surface grinding, a continuous rounded or tapered surface is formed. Between the above-mentioned periphery grinding and the surface grinding, it is also preferable to form an intermediate SOI wafer of the same type, stack them, and etch them while they are laminated and clamped together to improve the surface roughness caused by the periphery grinding. Finally, by carrying out the thinning process described above, a thin-film SOI wafer with an active layer thickness of less than 1 μm can be fabricated.

[0050] Even in a so-called "terrace-free" SOI wafer, there may be an exposed region of the oxide film 11 of about several nm to several tens of nm, as shown in Fig. 7(C). However, this exposure is not a flat surface exposure, and is not visible to the naked eye. Therefore, if the edge of the SOI wafer is a continuous rounded or tapered surface through the oxide film, it will be treated in this specification as having a terrace width of substantially 0 mm.

[0051] In this preferred embodiment, as shown in Figures 8(A) to 8(C), the terrace width during finish polishing is substantially 0 mm, and the pressure applied by the polishing pad P to the peripheral edge of the SOI wafer 400 during finish polishing is averaged. Therefore, even after forming an active layer 10 with a thickness of less than 1 µm, new exposure of the oxide film 11 can be almost certainly prevented, which is particularly preferable. Furthermore, compared with the first and second preferred embodiments described above, this preferred embodiment is preferable because it can best prevent exposure of the oxide film 11.

[0052] Although there is no particular limitation on the thickness of the active layer of the so-called "thin film SOI" that can be produced by this production method, it is preferable to set the lower limit of the thickness to 0.3 μm in consideration of processing accuracy and productivity.

[0053] Before or after the thinning step, the support substrate 20 may be thinned separately depending on the application, and during this thinning, the insulating film on the surfaces other than the bonding surface may be ground or polished.

[0054] (SOI wafer) Next, the SOI wafer of this embodiment obtained by the above manufacturing method will be described. Identical components are designated by the same reference numerals, and redundant description will be omitted. As shown in FIG. 2(E), the SOI wafer 100 of this embodiment has a support substrate 20 made of single-crystal silicon, an oxide film 11 located on the support substrate 20, and an active layer 10 made of single-crystal silicon and located on the oxide film 11. The thickness T of the active layer 10 is less than 1 μm, and the width of the region where the oxide film 11 or the support substrate 20 is exposed outward from the outer edge of the active layer 10 in a top view (i.e., terrace width) is 1.5 mm or less in the radial direction from the end face of the SOI wafer 100.

[0055] Here, the thickness T of the active layer 10 can be set to 0.3 μm or more.

[0056] As shown in FIG. 4(C), in the SOI wafer 200 according to the preferred embodiment of the present invention, the support substrate 20 and the oxide film 11 are arranged in a stepped manner at the peripheral portion of the SOI wafer 200, and when the terrace width is W (mm) and the thickness of the active layer 10 is T (μm), it is preferable that W and T satisfy the above-mentioned formula (1). T≧0.36W+0.32 (1) This SOI wafer 200 is obtained by the first preferred embodiment (chamfer etching method) described above.

[0057] In addition, as shown in FIG. 6(C), in an SOI wafer 300 according to a preferred embodiment of the present invention, the support substrate 20 is exposed at the peripheral portion of the SOI wafer 300, and the ends of the oxide film 11 and the active layer 10 are continuously rounded or tapered surfaces. When the terrace width is W (mm) and the thickness of the active layer 10 is T (μm), it is preferable that W and T satisfy the above-mentioned formula (2). T≧0.54W+0.24 (2) This SOI wafer 300 is obtained by the second preferred embodiment (terrace polishing method) described above.

[0058] 8(C), in the SOI wafer 400 according to the preferred embodiment of the present invention, the edges of the active layer 10 and the support substrate 20 preferably have a continuous rounded or tapered surface via the oxide film 11. In this case, as described above, the terrace width can be treated as being substantially 0 mm. This SOI wafer 400 is obtained by the third preferred embodiment (terrace-free) described above. [Example]

[0059] As the substrate for the active layer, an n-type silicon wafer (diameter: 200 mm, thickness: 725 μm, oxygen concentration: 3.0 × 10) was obtained from a single crystal silicon ingot obtained by the CZ method. 17 atoms / cm 3 A p-type silicon wafer (diameter: 200 mm, thickness: 725 μm, oxygen concentration: 1.2 × 10) was prepared as a support substrate. 18 atoms / cm 3 , dopant type: boron) was prepared. Next, the silicon wafer for the active layer was introduced into a thermal oxide film preparation device and subjected to an oxide film formation process at 1050°C in a hydrogen and oxygen mixed gas atmosphere to form a silicon oxide film with a thickness of 2.5 μm, and the active layer substrate and the support substrate were bonded together. The bonded wafer was then transported into a vertical heat treatment device in an oxygen gas atmosphere, where the temperature inside the device was raised to 800°C and held there for 2 hours, and then raised to 1000°C and held there for 1 hour, for heat treatment to strengthen the bond. Thereafter, the terrace width was adjusted as in the following Experimental Examples 1 to 3, and then thinning was performed by DCP processing and finish polishing.

[0060] (Experimental Example 1) The active layer substrate was thinned to 3 μm using chamfer etching. The terrace width was set to 0.7 mm. DCP processing was then performed using a DCP processing machine, and finally, a single-sided polishing machine was used to polish the substrate to a removal allowance of 0.20 μm, repeating this process until the oxide film was exposed. After DCP processing, it was confirmed that the oxide film was not exposed until the active layer thickness was 0.50 μm, but that the oxide film was exposed when the active layer thickness was less than 0.50 μm.

[0061] The terrace width after chamfer etching was adjusted to the value shown in Table 1 below, and the conditions other than the terrace width were kept the same as above, and the lower limit of the active layer thickness after finish polishing, at which the oxide film would not be exposed, was measured. The lower limit values ​​of the terrace width and active layer thickness are shown below. The approximation line (corresponding to the above-mentioned equation (1)) obtained from these results using the least squares method is shown in Figure 9.

[0062] [Table 1]

[0063] (Experimental Example 2) The substrate for the active layer was thinned to 3 μm using the terrace polishing method. The terrace width was 1.0 mm. DCP processing was then performed using a DCP processing machine, and finally, a single-sided polishing device was used to polish the substrate to a removal allowance of 0.20 μm, and thinning was repeated until the oxide film was exposed. After DCP processing, it was confirmed that the oxide film was not exposed until the active layer thickness was 0.8 μm, but it was confirmed that the oxide film was exposed when the active layer thickness was less than 0.8 μm.

[0064] The terrace width after terrace polishing was adjusted to the value shown in Table 2 below, and the conditions other than the terrace width were kept the same as above, and the lower limit of the active layer thickness after finish polishing at which the oxide film would not be exposed was measured. The lower limit values ​​of the terrace width and active layer thickness are shown below. The approximation line (corresponding to the above-mentioned equation (2)) obtained from these results using the least squares method is shown in Figure 9.

[0065] [Table 2]

[0066] (Experimental Example 3) Terrace-free SOI wafers were fabricated, and the active layer substrate was thinned to 3 μm. DCP processing was then performed using a DCP processing machine, and finally, the polishing allowance was set to 0.20 μm using a single-sided polishing machine, and thinning was repeated until the oxide film was exposed. It was confirmed that the oxide film was not exposed at least until the active layer thickness reached 0.3 μm. No experiments were performed on active layer thicknesses less than 0.3 μm. The results are shown in Figure 9, along with those of Experimental Examples 1 and 2 above. The terrace width is shown as 0 mm.

[0067] Regarding the exposure of the oxide film, Figures 10(A) and (B) show representative photographs of the active layer thickness of 0.30 μm in Experimental Example 3. (A) is a photograph of the periphery other than the notch, and (B) is a photograph of the notch. No exposed oxide film was observed in either Figure 10(A) or (B). On the other hand, Figures 10(C) and (D) show the results for Experimental Example 2, where the terrace width was 2.0 mm and the active layer thickness was 0.90 μm. (C) is a photograph of the periphery other than the notch, and (D) is a photograph of the notch. Exposed oxide film was observed in both Figures 10(A) and (B).

[0068] From the above results, it was confirmed that by making the terrace width 1.5 mm or less before finish polishing, it is possible to manufacture thin-film SOI wafers with an active layer thickness of less than 1 μm by the bonding method. It was also confirmed that when making the terrace width 1.5 mm or less by the chamfer etching method, it is preferable to satisfy the above-mentioned formula (1), and when making the terrace width 1.5 mm or less by the terrace polishing method, it is preferable to satisfy the above-mentioned formula (2). [Industrial Applicability]

[0069] According to the present invention, it is possible to provide a method for manufacturing an SOI wafer, which can reduce the terrace width compared to thin-film SOI wafers manufactured by the Smart Cut method, and can realize an SOI wafer having an active layer with a thickness of less than 1 μm by a bonding method. [Explanation of symbols]

[0070] 10 Active layer 10A active layer substrate 11 Oxide film 20 Support substrate T active layer thickness W terrace width

Claims

1. An SOI wafer having a support substrate made of single crystal silicon, an oxide film located on the support substrate, and an active layer made of single crystal silicon located on the oxide film, The thickness of the active layer is 0.3 μm or more and less than 1 μm, a width of a region where the oxide film or the support substrate is exposed outward from an outer edge of the active layer in a top view is 1.5 mm or less in a radial direction from an end face of the SOI wafer; the support substrate and the oxide film are arranged in a stepped manner at a peripheral portion of the SOI wafer, When the width is W (mm) and the thickness is T (μm), W and T satisfy the following formula (1). Note T≧0.36W+0.32...(1)

2. The SOI wafer of claim 1 , wherein the width is 0.7 mm or more.

3. 3. The SOI wafer according to claim 1, wherein the oxide film has a thickness of 2.5 μm or more and 30 μm or less.

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