Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device which can prevent decrease in channel mobility, and worsening of reliability of a gate insulative film, and a method for manufacturing such a silicon carbide semiconductor device.SOLUTION: A method for manufacturing a silicon carbide semiconductor device includes, removing, by etching, a precipitation layer produced on a trench inner wall during thermal treatment or by sacrificial oxidation after the thermal treatment, before deposition of a gate insulative film and after the thermal treatment for rounding a trench corner portion. The etching is low-damage etching by use of plasma of etching gas containing neither carbon nor oxygen. The low-damage etching does not cause the oxidation on a trench side wall and does not cause re-deposition of a CF-based polymer thereon. In addition, thanks to the low-damage etching, a height of a protrusion, on a semiconductor face, formed on the trench side wall during trench etching is made 3 nm or smaller, and the trench side wall becomes a flat face. Thus, roughness scattering by the trench side wall can be decreased. The gate insulative film covers the protrusion on the semiconductor face, on the trench side wall.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, in vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) with a trench gate structure using silicon carbide (SiC) as the semiconductor material, it is known that various processes performed during trench formation or after trench formation and before the formation of the gate insulating film can cause damage layers, excess carbon (C) precipitate layers, dopant precipitate layers, etc. on the inner walls of the trench.

[0003] For example, in a semiconductor substrate made of silicon carbide, a trench is formed by anisotropic etching using high-density plasma, but a damaged layer is formed on the inner wall of the trench due to collisions of ions and radicals generated from the plasma. When the inner wall of the trench is sacrificially oxidized to remove the damaged layer on the inner wall of the trench, a silicon oxide (SiO2) film is formed by sacrificially oxidizing the inner wall of the trench, and excess carbon is desorbed from the surface region (silicon carbide portion) of the inner wall of the trench and precipitated on the inner wall of the trench, forming an excess carbon precipitate layer.

[0004] When high-temperature annealing (heat treatment) is performed to round the corners of the trench, the dopant is redeposited on the inner wall surface of the trench, forming a highly-doped dopant precipitate layer. These damaged layers, excess carbon precipitate layers, and dopant precipitate layers on the inner wall of the trench are removed by chemical dry etching (CDE) or plasma etching (PE) using gases containing carbon tetrafluoride (CF4) and oxygen (O2).

[0005] A conventional method for manufacturing a silicon carbide semiconductor device will be described using a MOSFET as an example. Fig. 7 is a flow chart showing an outline of the conventional method for manufacturing a silicon carbide semiconductor device. In forming a MOS gate of a conventional silicon carbide semiconductor device, first, a trench is formed from the front surface of a semiconductor substrate to a predetermined depth by photolithography and etching (hereinafter referred to as trench etching) (step S101). This trench etching is, for example, anisotropic etching using high-density plasma.

[0006] The semiconductor substrate is a n-type semiconductor substrate using silicon carbide as the semiconductor material. + On the front surface of the starting substrate, - The epitaxial layers that become the p-type drift region and the p-type base region are stacked in order. The main surface of the semiconductor substrate that faces the p-type epitaxial layer that becomes the p-type base region is the front surface. + In the process of step S101, the trench is formed by extending from the front surface of the semiconductor substrate to the n-type epitaxial layer formed in the p-type epitaxial layer. + through the p-type source region and the p-type base region. - The mold drift region is reached.

[0007] A damaged layer is formed on the inner wall of the trench due to trench etching. - Near the first boundary between the p-type drift region and the p-type base region, and near the first boundary between the p-type base region and the n + The etching rate of the epitaxial layer near the second boundary with the mold source region is slower than the etching rate of the epitaxial layer between the first and second boundaries. The portion of the epitaxial layer with the slow etching rate remains as a protrusion on the side wall of the trench. As a result, a step is formed on the side wall of the trench 7 due to the protrusion.

[0008] Next, the corners of the trench are rounded by plasma etching or high-temperature (e.g., 1500°C or higher) annealing (step S102). The process of step S102 simultaneously etches the inner wall of the trench and causes surface diffusion of silicon (Si) and carbon (C) on the inner wall of the trench, rounding the corners of the trench. When the process of step S102 is performed by high-temperature annealing, a precipitate layer of dopant with a high impurity concentration is formed on the inner wall of the trench as described above.

[0009] Next, the inner wall of the trench is sacrificially oxidized to form a sacrificial oxide film (step S103), and the sacrificial oxide film is removed to remove the damaged layer and the dopant precipitate layer generated on the inner wall of the trench. As described above, the sacrificial oxidation in step S103 forms an excess carbon precipitate layer on the inner wall of the trench. The process in step S103 can be omitted. Next, the inner wall of the trench is chemically dry etched or plasma etched using a gas containing CF4 and O2 (step S104).

[0010] The process of step S104 removes the excess carbon precipitate layer on the inner wall of the trench. If the process of step S103 is omitted, the process of step S104 removes the damage layer and the dopant precipitate layer on the inner wall of the trench. Next, a gate insulating film is deposited along the inner wall of the trench (step S105), and then a gate electrode is formed inside the trench (step S106). Then, each part other than the MOS gate (not shown) is formed at a predetermined timing by a general method to complete a conventional silicon carbide semiconductor device.

[0011] A method has been proposed as a conventional method for manufacturing a silicon carbide semiconductor device in which, after forming a trench, the inner wall of the trench is left as is without sacrificially oxidizing it, or a damaged layer on the inner wall of the trench is removed by chemical dry etching using a gas containing CF4 and O2, and then a gate insulating film is deposited (see, for example, Patent Document 1 below). In Patent Document 1 below, by not sacrificially oxidizing the inner wall of the trench, it is possible to deposit an n-type base region having a higher impurity concentration than a p-type base region. +This prevents accelerated oxidation of the inner wall of the trench in the portion where the source region is exposed. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] Patent No. 6299102 Summary of the Invention [Problem to be solved by the invention]

[0013] However, etching using gas containing CF4 and O2 causes new problems, such as the inner wall of the trench being thinly oxidized and an excess carbon precipitate layer being reformed on the inner wall of the trench, or a carbon-based polymer containing fluorine being generated and attached to the inner wall of the trench. The excess carbon precipitate layer formed on the inner wall of the trench reduces the channel mobility and increases the on-resistance. The carbon-based polymer containing fluorine formed on the inner wall of the trench reduces the reliability of the gate insulating film.

[0014] An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can prevent a decrease in channel mobility and a decrease in the reliability of a gate insulating film, in order to solve the problems associated with the conventional techniques described above. [Means for solving the problem]

[0015] In order to solve the above-mentioned problems and achieve the objects of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: A first semiconductor region of a first conductivity type is provided within a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region.

[0016] The trench penetrates through the third semiconductor region and the second semiconductor region to reach the first semiconductor region. A gate insulating film is provided along an inner wall of the trench. A gate electrode is provided inside the trench on the gate insulating film. A first electrode is electrically connected to the third semiconductor region and the second semiconductor region. A second electrode is provided on a second main surface of the semiconductor substrate. On the sidewall of the trench, a protrusion of the semiconductor surface at the interface between regions of different conductivity types has a height of 3 nm or less. The gate insulating film is a deposited oxide film, which contacts the semiconductor surface on the inner wall of the trench and covers the protrusion of the semiconductor surface on the sidewall of the trench.

[0017] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features: A first step is performed of forming a first conductivity type silicon carbide layer on a starting substrate of a first conductivity type made of silicon carbide, the first conductivity type being a first semiconductor region having a lower impurity concentration than the starting substrate; A second step is performed of forming a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer, the second conductivity type being a second semiconductor region of a second conductivity type; A third step is performed of selectively forming a first conductivity type third semiconductor region in a surface region of the second conductivity type silicon carbide layer; A fourth step is performed of forming a trench by first etching, penetrating the third semiconductor region and the second conductivity type silicon carbide layer to reach the first conductivity type silicon carbide layer.

[0018] A fifth step is performed in which the corners of the trench are rounded by heat treatment. After the fifth step, a sixth step is performed in which the inner wall of the trench is second-etched in a plasma atmosphere. After the sixth step, a seventh step is performed in which a gate insulating film is deposited along the inner wall of the trench. An eighth step is performed in which a gate electrode is formed on the gate insulating film inside the trench. In the sixth step, the second etching uses an etching gas that does not contain a first element that causes a carbon-containing deposit to adhere to the inner wall of the trench and a second element that oxidizes the inner wall of the trench, and the second etching removes a precipitate layer that has formed on the inner wall of the trench before the sixth step to expose a semiconductor surface on the inner wall of the trench and recedes the semiconductor surface to approach a flat surface, and in the seventh step, a deposition oxide film is deposited as the gate insulating film on the semiconductor surface of the inner wall of the trench. Effect of the Invention

[0019] ADVANTAGEOUS EFFECTS OF THE PRESENT DISCLOSURE ... The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the advantage that it is possible to prevent a decrease in channel mobility and to prevent a decrease in the reliability of the gate insulating film. [Brief description of the drawings]

[0020] [Figure 1] 1 is a cross-sectional view showing an example of a structure of a silicon carbide semiconductor device according to an embodiment; [Diagram 2] 1 is a flowchart outlining a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Diagram 3] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. [Figure 4] 4 is a perspective view showing a schematic diagram of the surface shape of the portion enclosed by frame A in FIG. 3, detected by AFM. [Diagram 5] 5 is an enlarged cross-sectional view showing a portion of the sidewall of the trench in FIG. 4. [Figure 6] 3 is a cross-sectional view showing a schematic surface shape of a sidewall of a trench immediately after the processing in step S4 of FIG. 2. [Figure 7] 1 is a flowchart outlining a conventional method for manufacturing a silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with that. In the following description of the embodiments and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted.

[0022] (Embodiment) The structure of a silicon carbide semiconductor device according to an embodiment will be described using a MOSFET as an example. Fig. 1 is a cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to an embodiment. A silicon carbide semiconductor device 10 according to the embodiment shown in Fig. 1 is a vertical MOSFET having a general trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as a semiconductor material.

[0023] The semiconductor substrate 30 is a n-type semiconductor substrate using silicon carbide as a semiconductor material. + On the front surface of the starting substrate 31, an n-type buffer region 2, - The epitaxial layers 32 to 34 that become the p-type drift region (first semiconductor region) 3 and the p-type base region (second semiconductor region) 4 are stacked in order. The main surface of the semiconductor substrate 30 facing the p-type epitaxial layer 34 is the front surface, and the n-type + The main surface (n + The back side of the starting substrate 31 is referred to as the back side. + The starting substrate 31 is n + The gate electrode is a gate-type drain region 1.

[0024] The n-type epitaxial layer 32 is the n-type buffer region 2. The n-type buffer region 2 may not be provided. - The drift region 3 is an n - In the depth direction Z, the n-type epitaxial layer 33 (first conductivity type silicon carbide layer) is provided with the n-type buffer region 2 (or the n-type + The p-type base region 4 is in contact with the front surface of the semiconductor substrate 30 and the n-type drain region 1. - Between the n-type drift region 3, - It is provided in contact with the mold drift region 3 .

[0025] Between the front surface of the semiconductor substrate 30 and the p-type base region 4, in contact with the p-type base region 4, + type source region (third semiconductor region) 5 and p + The contact regions 6 are selectively provided. + Type source region 5 and p + The n-type contact region 6 is exposed on the front surface of the semiconductor substrate 30. + Type source region 5 and p + The portion excluding the contact region 6 is the p-type base region 4 .

[0026] The p-type base region 4, n + Type source region 5 and n - When the MOSFET is in the on-state, a channel (n-type inversion layer) 4a is formed in the portion sandwiched between the n-type drift region 3 and the n-type + The p-type contact region 6 may not be provided, and the p-type base region 4 may be exposed on the front surface of the semiconductor substrate 30. The trench 7 is formed by extending from the front surface of the semiconductor substrate 30 in the depth direction Z. + The n-type source region 5 and the p-type base region 4 are connected to each other. - The type drift region 3 is reached.

[0027] The trench 7 extends linearly in, for example, a first direction X parallel to the front surface of the semiconductor substrate 30. The corners of the trench 7 are rounded. By rounding the corners of the trench 7, the electric field applied to the gate insulating film 8 at the corners of the trench 7 can be alleviated, and therefore the gate withstand voltage can be ensured. The corners of the trench 7 are the boundaries between the sidewalls and the bottom surface of the trench 7.

[0028] On the side wall of the trench 7, n - A first boundary 41 between the p-type drift region 3 and the p-type base region 4 and a second boundary 42 between the p-type base region 4 and the n + The first and second boundaries 41 and 42 terminate at the second boundary 42 with the type source region 5. The terminations of the first and second boundaries 41 and 42 are exposed at the sidewall of the trench 7. No step is formed on the sidewall of the trench 7 at the terminations of the first and second boundaries 41 and 42, and the sidewall of the trench 7 is substantially flat over the entire surface.

[0029] "No step occurs on the sidewall of trench 7" means that the heights of protrusions 41a, 42a (see FIG. 3 described later) occurring at the end portions of the first and second boundaries 41, 42 on the sidewall of trench 7, respectively, are approximately 3 nm or less. The height of protrusions 41a, 42a on the sidewall of trench 7 refers to distance d (see FIG. 3) from the apex of protrusions 41a, 42a on the sidewall of trench 7 to the portion of the sidewall surface of trench 7 excluding protrusions 41a, 42a.

[0030] The protrusions 41a, 42a on the sidewalls of the trench 7 protrude into the trench 7 in a second direction Y perpendicular to the sidewalls of the trench 7, and extend in a first direction X along the sidewalls of the trench 7. The protrusions 41a, 42a on the sidewalls of the trench 7 have their most protruding points (apexes) on the terminations of the first and second boundaries 41, 42, respectively, and have a substantially triangular cross-sectional shape that becomes lower from the apexes toward both main surfaces of the semiconductor substrate 30.

[0031] A gate insulating film 8 is provided along the inner wall of the trench 7. The gate insulating film 8 is, for example, a deposited oxide film such as a high temperature oxide (HTO) film. Inside the trench 7, a gate electrode 9 is provided on the gate insulating film 8 so as to fill the inside of the trench 7. The trench 7, the gate insulating film 8, and the gate electrode 9 form a MOS gate.

[0032] The interlayer insulating film 11 is provided on the front surface of the semiconductor substrate 30 and covers the gate electrode 9. The source electrode 12 is provided on the interlayer insulating film 11 so as to be embedded in a contact hole in the interlayer insulating film 11. The source electrode 12 is connected to an n-type + Type source region 5 and p + The p-type base region 4 and the n-type contact region 6 are in ohmic contact with each other. + Type source region 5 and p + The contact region 6 is electrically connected to the contact area 6 .

[0033] p + When the type contact region 6 is not provided, the source electrode 12 is + The n-type contact region 6 is in ohmic contact with the p-type base region 4. + A drain electrode 13 is provided on the entire surface of the back surface of the starting substrate 31. + Type drain region 1(n + contacting the starting substrate 31), + The gate electrode 1 is electrically connected to the drain region 1 .

[0034] Next, a method for manufacturing a silicon carbide semiconductor device 10 according to an embodiment will be described with reference to Figs. 1 to 6. Fig. 2 is a flow chart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to an embodiment. Fig. 2 shows only a step of forming a MOS gate. Fig. 3 is a cross-sectional view showing a state during the manufacturing process of the silicon carbide semiconductor device according to the embodiment. Fig. 3 shows a cross-sectional structure of trench 7 immediately after the processing of step S4 in Fig. 2, cut along a cutting line parallel to the second direction Y.

[0035] Fig. 4 is a perspective view showing a schematic result of detecting the surface shape of the portion surrounded by frame A in Fig. 3 (the sidewall of trench 7) by an atomic force microscope (AFM). Fig. 4 shows a schematic surface shape of the sidewall of the trench immediately after processing in step S1 in Fig. 2. Fig. 5 is a plan view showing a part of the sidewall of the trench in Fig. 4. Fig. 6 is a plan view showing a schematic surface shape of the sidewall of the trench immediately after processing in step S4 in Fig. 2.

[0036] 5 and 6 show the sidewall of trench 7 viewed from the second direction Y, and show the same location (near protrusions 41a and 42a) of the sidewall of trench 7. On the graph axes (three axes) of FIG. 4, distances x and y are the distances on parallel lines in the first and second directions X and Y, respectively, and depth z is the distance (depth) on parallel lines in the depth direction Z. On the graph axes (two axes) of FIG. 5 and 6, distances x and y are the distances on parallel lines in the first and second directions X and Y, respectively. In FIG. 4 to 6, the height difference in the second direction Y is shown by hatching.

[0037] First, we developed a n-type semiconductor device using silicon carbide. + n-type drain region 1 + A mold starting substrate 31 is prepared. Next, + On the front surface of the starting substrate 31, an n-type buffer region 2, - The epitaxial layers 32 to 34 which become the n-type drift region 3 and the p-type base region 4 are sequentially epitaxially grown to produce a semiconductor substrate (semiconductor wafer) 30. The thickness of the n-type epitaxial layer 32 may be, for example, about 1 μm.

[0038] Next, n is implanted into the surface region of the p-type epitaxial layer 34 by ion implantation. + Type source region 5 and p + Then, a heat treatment is performed to activate the impurities introduced by ion implantation. This heat treatment is performed to selectively form all of the diffusion regions (n + Type source region 5 and p +This may be carried out once after the formation of the mold contact region 6), or may be carried out each time a diffusion region is formed by ion implantation.

[0039] Next, photolithography and etching (trench etching) are performed to remove n-type GaN from the front surface of the semiconductor substrate 30. + The n-type source region 5 and the p-type base region 4 are connected to each other. - A trench 7 is formed so as to reach the mold drift region 3 (step S1: fourth step). The trench etching is, for example, anisotropic etching using high-density plasma. A damaged layer (not shown) is formed on the inner wall of the trench 7 due to the trench etching.

[0040] In this trench etching, steps are formed on the sidewalls of trench 7 due to protrusions 41a', 42a' (FIGS. 4 and 5). This is presumably because the etching rate in the vicinity of first and second boundaries 41, 42 of epitaxial layers 33, 34 is slower than the etching rate of a portion between first and second boundaries 41, 42 of epitaxial layers 33, 34, and the portions of epitaxial layers 33, 34 with a slower etching rate remain on the sidewalls of trench 7 as protrusions 41a', 42a'.

[0041] Next, the corners of the trench 7 are rounded by plasma etching or high-temperature annealing at, for example, 1500° C. or higher (step S2: fifth process). The process of step S2 simultaneously etches the inner wall of the trench 7 and causes surface diffusion of silicon (Si) and carbon (C) on the inner wall of the trench 7, rounding the corners of the trench 7. When the process of step S2 is performed by high-temperature annealing, a precipitate layer (not shown) of dopant with a high impurity concentration is formed on the inner wall of the trench 7.

[0042] Next, the inner wall of trench 7 is sacrificially oxidized (step S3), and then the sacrificial oxide film is removed to remove the damaged layer and dopant precipitate layer generated on the inner wall of trench 7. By the sacrificial oxidation in step S3, an excess carbon precipitate layer (not shown) is formed on the inner wall of trench 7. The process of step S3 can be omitted. Next, the inner wall of trench 7 is etched using an etching gas that does not contain a first element that causes deposits that cause characteristic degradation to adhere to the inner wall of trench 7, and does not contain a second element that oxidizes the inner wall of trench 7 (step S4: sixth process).

[0043] The first element is, for example, carbon (C) that generates a carbon-based polymer (for example, a CF-based polymer) containing fluorine. The second element is, for example, oxygen (O) that bonds with silicon (Si) in the silicon carbide portion on the inner wall of the trench 7 to generate excess carbon (C). The etching gas used in the process of step S4 may be any gas that contains a halogen element such as fluorine (F) or chlorine (Cl) that causes an etching reaction, and does not contain either of the first or second elements, and may be, for example, nitrogen trifluoride (NF3) gas or chlorine trifluoride (ClF3) gas.

[0044] The process of step S4 is preferably isotropic low-damage dry etching using radicals (hereinafter referred to as low-damage etching), such as chemical dry etching or plasma etching. For example, low-damage etching can be achieved by using plasma etching that uses radicals generated from plasma generated in the chamber. Alternatively, even lower-damage etching can be achieved by using chemical dry etching that uses radicals generated from plasma generated elsewhere and transported into the chamber.

[0045] By carrying out the process of step S4 under the above conditions, the inner wall of trench 7 can be etched without using oxygen, and therefore the SiC surface (etching surface) is not oxidized. The etching surface refers to the front surface of semiconductor substrate 30 and the inner wall surface of trench 7. Furthermore, when fluorine atoms are contained in the etching gas used in the process of step S4, fluorine atoms have small bond energy and are easily decomposed into radicals at low power, enabling low-damage etching.

[0046] In addition, since all reaction products generated in the processing furnace (chamber) of the etching apparatus during the processing of step S4 are gasified and exhausted to the outside from the processing furnace, the SiC surface is less roughened by the reaction products generated during the processing of step S4. Fluorine atoms contained in the etching gas adhere to the SiC surface, but since the fluorine attached to the SiC surface is removed by a cleaning process (not shown) performed between each of the processing steps S1 to S6, the etching gas used in the processing of step S4 may contain fluorine.

[0047] The process of step S4 removes the excess carbon precipitate layer on the inner wall of trench 7. If the process of step S3 is omitted, the process of step S4 removes the damage layer and the precipitate layer of dopant generated on the inner wall of trench 7 in the processes of steps S1 and S2. Since an etching gas not including the first and second elements is used in the process of step S4, problems such as the inner wall of trench 7 being oxidized to re-form the excess carbon precipitate layer or a carbon-based polymer including fluorine being attached to the inner wall of the trench, as in the conventional method (FIG. 7), do not occur.

[0048] Furthermore, the processing of step S4 reduces the height (distance d) of the protrusions 41a', 42a' (see FIGS. 4 and 5) occurring on the sidewall of the trench 7 to 3 nm or less. As a result, the protrusions 41a, 42a do not form steps on the sidewall of the trench 7, and the entire sidewall of the trench 7 becomes substantially flat (see FIG. 6). In FIGS. 1, 3, and 6, the protrusions on the sidewall of the trench 7 after the processing of step S4 are indicated by the symbols 41a, 42a. The amount of etching of the sidewall of the trench 7 by the processing of step S4 (thickness in the second direction Y from the sidewall) is 100 nm or less.

[0049] Next, for example, an HTO film is deposited as a gate insulating film 8 along the front surface of the semiconductor substrate 30 and the inner wall of the trench 7 (step S5: seventh process). Next, for example, polysilicon (poly-Si) is embedded inside the trench 7 to form a gate electrode 9 (step S6: eighth process). The trench 7, gate insulating film 8, and gate electrode 9 formed by the processes of steps S1 to S6 constitute a MOS gate. Then, each part other than the MOS gate (not shown) is formed at a predetermined timing by a general method to complete the silicon carbide semiconductor device 10 of FIG. 1.

[0050] As described above, according to the embodiment, after the heat treatment for rounding the corners of the trench, and before the gate insulating film is deposited along the sidewall of the trench, the dopant precipitate layer generated on the inner wall of the trench by the heat treatment, or, if sacrificial oxidation is performed after the heat treatment, the excess carbon precipitate layer generated on the inner wall of the trench by the sacrificial oxidation, is removed by etching the inner wall of the trench. This etching is dry etching in a plasma atmosphere using an etching gas that does not contain a first element that causes a carbon-containing deposit to adhere to the inner wall of the trench, and a second element that oxidizes the inner wall of the trench. This enables etching with low damage to the inner wall of the trench.

[0051] According to the embodiment, the etching gas used in the etching for removing the dopant precipitate layer or the excess carbon precipitate layer on the inner wall of the trench does not contain a second element that oxidizes the inner wall of the trench, so that the inner wall of the trench is not oxidized during the etching, and the excess carbon precipitate layer is not re-formed on the inner wall of the trench. Therefore, it is possible to suppress a decrease in channel mobility. In addition, the etching gas used in the etching does not contain a first element that causes a carbon-containing deposit to adhere to the inner wall of the trench, so that a fluorine-containing carbon-based polymer does not adhere to the inner wall of the trench during the etching. Therefore, it is possible to suppress a decrease in reliability of the gate insulating film.

[0052] According to the embodiment, n - a first boundary between the p-type drift region and the p-type base region; + The height of the protrusions generated at the second boundary with the type source region can be lowered by etching to remove the dopant precipitate layer or excess carbon precipitate layer on the inner wall of the trench. This makes it possible to eliminate steps on the side walls of the trench due to the protrusions and make the side walls of the trench substantially flat. The steps due to the protrusions are 3 nm or less. Since there are no steps on the side walls of the trench, it is possible to reduce interface roughness scattering at the interface (SiO2 / SiC interface) between the gate insulating film and the silicon carbide part on the inner wall of the trench, thereby suppressing a decrease in channel mobility.

[0053] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention is applicable not only to MOSFETs but also to other MOS type semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) having a p-type collector layer formed on the back surface of a semiconductor substrate, as long as the device has a trench gate structure. [Industrial Applicability]

[0054] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for trench gate type semiconductor devices, and are particularly suitable for trench gate type MOSFETs. [Explanation of symbols]

[0055] 1n + Type drain region 2 n-type buffer region 3n - Mold Drift Region 4 p-type base region 5n + Type Source Area 6 p + Mold Contact Area 7. Trench 8 Gate insulating film 9 Gate electrode 10 Silicon carbide semiconductor device 11 Interlayer insulating film 12 Source electrode 13 Drain electrode 30 Semiconductor Substrate 31 n + Starting substrate 32 n-type epitaxial layer 33n - Type epitaxial layer 34 p-type epitaxial layer 41 n - A first boundary between the p-type drift region and the p-type base region 41a, 42a: Protrusions on the side of the trench after etching in step S4 of FIG. 2 41a', 42a': Protrusions formed on the side of the trench by etching in step S1 of FIG. 2 42 p-type base region and n + Second boundary with type source region X: a first direction in which the trench extends parallel to the front surface of the semiconductor substrate Y: The second direction perpendicular to the sidewall of the trench Z depth direction d Distance from the apex of the protrusion on the sidewall of the trench to the surface (exposed surface) of the epitaxial layer exposed on the sidewall of the trench between the protrusions

Claims

1. a semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided within the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a trench penetrating the third semiconductor region and the second semiconductor region to reach the first semiconductor region; a gate insulating film provided along an inner wall of the trench; a gate electrode provided on the gate insulating film inside the trench; a first electrode electrically connected to the third semiconductor region and the second semiconductor region; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with a height of a protrusion of a semiconductor surface at an interface between regions of different conductivity types on a sidewall of the trench is 3 nm or less; a gate insulating film formed on an inner wall of the trench and in contact with the semiconductor surface, the gate insulating film being a deposited oxide film, the gate insulating film being in contact with the semiconductor surface on an inner wall of the trench and covering a protrusion of the semiconductor surface on a side wall of the trench;

2. A first step of forming a first conductivity type silicon carbide layer on a first conductivity type starting substrate made of silicon carbide, the first conductivity type silicon carbide layer being a first semiconductor region of the first conductivity type having a lower impurity concentration than the starting substrate; a second step of forming a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer, the second conductivity type silicon carbide layer being a second semiconductor region of a second conductivity type; a third step of selectively forming a third semiconductor region of a first conductivity type in a surface region of the second conductivity type silicon carbide layer; a fourth step of forming a trench penetrating the third semiconductor region and the second conductivity type silicon carbide layer to reach the first conductivity type silicon carbide layer by a first etching; A fifth step of rounding corners of the trench by heat treatment; a sixth step of performing a second etching on the inner wall of the trench in a plasma atmosphere after the fifth step; a seventh step of depositing a gate insulating film along an inner wall of the trench after the sixth step; an eighth step of forming a gate electrode on the gate insulating film inside the trench; Including, In the sixth step, In the second etching, an etching gas is used that does not include a first element that causes a carbon-containing deposit to adhere to the inner wall of the trench and a second element that oxidizes the inner wall of the trench; the second etching removes a precipitate layer formed on the inner wall of the trench before the sixth step, exposing a semiconductor surface on the inner wall of the trench and receding the semiconductor surface to approach a flat surface; a seventh step of depositing a deposition oxide film as the gate insulating film on the semiconductor surface of the inner wall of the trench.

3. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the first element is carbon.

4. 4. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the second element is oxygen.

5. 5. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein an etching gas for the second etching is nitrogen trifluoride gas.

6. 5. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein an etching gas for the second etching is chlorine trifluoride gas.

7. 7. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the second etching is chemical dry etching.

8. 8. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein an etching amount of the second etching is 100 nm or less from a sidewall of the trench in a direction perpendicular to the sidewall of the trench.

9. 9. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 2 to 8, wherein in the sixth step, an etching rate is different between a boundary between the first conductivity type silicon carbide layer and the second conductivity type silicon carbide layer, a boundary between the second conductivity type silicon carbide layer and the third semiconductor region, and a surface between each boundary on a side wall of the trench in the first etching of the fourth step, so that heights of protrusions generated at each boundary are reduced to 3 nm or less by the second etching.

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