Component carrier equipped with identification mark

Abstract

A component carrier comprising a stack of at least four electrically insulating layer structures and at least five electrically conductive layer structures stacked in an alternating manner above one another along a stacking direction, where one of the electrically conductive layer structures forms a first outer conductive layer of the stack and where another of the electrically conductive layer structures forms a second outer conductive layer of the stack, the first outer conductive layer and the second outer conductive layer being opposing outer layers of the stack. The component carrier further comprises a first identification mark detectable by a detection device, where the first identification mark is formed in a conductive layer structure arranged closest to the first outer conductive layer, and a second identification mark detectable by a detection device, where the second identification mark is formed in a conductive layer structure arranged closest to the second outer conductive layer. The first identification mark and the second identification mark are formed in a conductive layer structure arranged closest to one another along a stacking direction.

Description

[Technical field]

[0001] The present invention relates to a component carrier equipped with an identification mark. [Background technology]

[0002] In the context of the growing manufacturing capabilities of component carriers with one or more components, and the increasing miniaturization of such components, as well as the increasing number of components connected to component carriers, such as printed circuit boards, more powerful array-like components or packages with multiple components are being adopted, which have multiple contacts or connections with smaller and smaller spaces between those contacts. In particular, component carriers must be mechanically robust, electrically reliable, and capable of operating under harsh conditions. More and more functions are being integrated into component carriers.

[0003] During the manufacturing of complex component carriers such as printed circuit boards (PCBs), it is important to accurately and precisely align and rotate the component carriers. In order to align the component carriers, identification marks can be formed inside the layer structure of the component carrier. The identification marks can be measured by a respective detection device, such as an X-ray detector, where based on the measured picture of the identification marks the respective alignment of the component carriers can be determined.

[0004] However, as each layer comprising the indicia is covered by multiple additional layers during the manufacturing process, the photograph of the indicia (eg, the contrast and outline of the indicia photograph) becomes more obscured.

[0005] Therefore, there may be a need to provide an identification mark that can be properly determined by a detection device to provide proper alignment of the component carrier. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a component carrier is described, comprising a stack of at least four electrically insulating layer structures and at least five conductive layer structures stacked in an alternating manner above one another along a stacking direction, one of the conductive layer structures forming a first outer conductive layer of the stack and another of the conductive layer structures forming a second outer conductive layer of the stack, where the first outer conductive layer and the second outer conductive layer are opposing outer layers of the stack.

[0007] The component carrier further comprises a first identification mark detectable by a detection device, where the first identification mark is formed on the conductive layer structure. In an exemplary embodiment, the first identification mark is formed on the conductive layer structure disposed closest to the first outer conductive layer, and a second identification mark detectable by a detection device, where the second identification mark is formed on the conductive layer structure. In an exemplary embodiment, the second identification mark is formed on the conductive layer structure disposed closest to the second outer conductive layer. The first identification mark and the second identification mark are formed in a stacking direction above each other.

[0008] According to an exemplary embodiment of the present invention, a method for manufacturing the component carrier described above is described. An electrically insulating layer structure and at least five conductive layer structures are stacked in an alternating manner above one another along a stacking direction, one of the conductive layer structures forming a first outer conductive layer of the stack and another of the conductive layer structures forming a second outer conductive layer of the stack, where the first outer conductive layer and the second outer conductive layer are opposite outer layers of the stack. Furthermore, a first identification mark detectable by a detection device is formed on the conductive layer structures. In an exemplary embodiment, the first identification mark is formed on the conductive layer structure that is disposed closest to the first outer conductive layer. A second identification mark detectable by a detection device is formed on the conductive layer structure. In an exemplary embodiment, the second identification mark is formed on the conductive layer structure that is disposed closest to the second outer conductive layer. The first identification mark and the second identification mark are formed in the stacking direction above one another.

[0009] In the context of the present application, the term "component carrier" may particularly denote any support structure on and / or within which one or more components can be accommodated to provide mechanical support and / or electrical connectivity. In other words, the component carrier may be configured as a mechanical and / or electronic carrier of the components. In particular, the component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate, and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different of the above mentioned types of component carriers.

[0010] In the context of the present application, the term "component carrier material" may in particular denote a connected arrangement of one or more electrically insulating layer structures and / or one or more electrically conductive layer structures as used in the technology of component carriers. More particularly, such component carrier materials may be materials used for printed circuit boards (PCBs) or IC substrates. In particular, the conductive material of such a component carrier material may comprise copper. The electrically insulating material of the component carrier material may comprise a resin, in particular an epoxy resin, optionally combined with reinforcing particles such as glass fibers or glass spheres.

[0011] In an embodiment, the component carrier is a stacked component carrier, in which the component carrier is a composite of multiple layers stacked and connected together by applying pressure and / or heat.

[0012] In an embodiment, the at least one electrical insulation layer structure comprises at least one of the group consisting of resins or polymers, such as epoxy resins, cyanate ester resins, benzocyclobutene resins, bismaleimide triazine resins, polyphenylene derivatives (e.g., based on polyphenylene ether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), and / or combinations thereof. Reinforcing structures, such as webs, fibers, spheres, or other types of filler particles, for example made of glass (multilayer glass), can also be used to form composite materials. Semi-cured resins combined with reinforcing agents, such as fibers impregnated with the above-mentioned resins, are called prepregs. These prepregs are often named after their properties, for example FR4 or FR5 to represent their flame retardant properties. Usually, prepregs, especially FR4, are preferred for rigid PCBs, but other materials may also be used, especially epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials. For high frequency applications, high frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate ester resins may be preferred. Besides these polymers, low temperature co-fired ceramics (LTCC) or other low, ultra-low, or extremely low DK materials may be applied within the component carrier as an electrically insulating structure.

[0013] In an embodiment, at least one conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten, and magnesium. Copper is usually preferred, but other materials or coatings thereof are also possible, in particular those coated with superconducting materials or conducting polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0014] The first and second identification marks are formed in a stacking direction above each other. Therefore, a stack can be formed of a plurality of electrically insulating layer structures and a plurality of conductive layer structures, where each identification mark is formed in the conductive layer structure at a spaced apart location of the stack. When the first and second identification marks are formed in a stacking direction above each other, a suitable picture of the alignment of the identification marks obtained by the detection device can be presented. In other words, the first and second identification marks are formed in a manner that the identification mark and the further identification mark completely overlap each other on a projection surface having a projection normal parallel to the stacking direction.

[0015] The identification marks are formed in one of the conductive layer structures. In particular, with this approach, the identification marks are formed in one of the conductive layer structures that are closest to the outer conductive layer, respectively, so that it is easier for a (e.g. x-ray) detection device to detect the circumferential shape and orientation of the identification marks, respectively.

[0016] According to an exemplary embodiment, at least one of the first and second identification marks comprises an inner volume that is free of the material of the conductive layer structure. For example, the inner volume of the identification mark is hollow, e.g., free of copper. In an exemplary embodiment, the inner volume of the identification mark is filled with an electrically insulating material. The electrically insulating material may be similar to an electrically insulating layer structure that is laminated on top of the respective conductive layer structure, such as polypropylene (PP).

[0017] According to an exemplary embodiment, the identification mark comprises a triangular shape. Providing a triangular shape makes it easier to detect the orientation and alignment of the identification mark and the component carrier, respectively.

[0018] According to a further exemplary embodiment, the identification mark comprises an arrow shape. By providing an arrow shape, it becomes easier to detect the orientation and alignment of the identification mark and the component carrier, respectively.

[0019] According to a further exemplary embodiment, the identification mark comprises three identification points forming a triangular shape, where each identification point comprises an inner volume free of conductive material. Orientation of the identification mark is also possible by providing, for example, hollow points or shapes (circles, ellipses or rectangles) that are arranged with respect to each other in such a way that a specific direction can be determined. For example, the three identification points can be formed at the corners of an imaginary triangle.

[0020] According to a further exemplary embodiment, the identification mark is formed at an edge of one of the conductive layer structures.

[0021] According to a further exemplary embodiment, the identification mark is formed at a corner of one of the conductive layer structures.

[0022] According to a further exemplary embodiment, the first and second identification marks have the same circumferential shape, for example, both identification marks, in particular the first and second identification marks, have a triangular shape or are arrow-shaped.

[0023] According to a further exemplary embodiment, the second identification mark is filled with conductive material. For example, the second identification mark only comprises a circumferential extension or path without conductive material. Therefore, the detection device detects only the circumferential path of the identification mark. However, the second identification mark with an inner volume without conductive material and the identification mark described above are formed above each other, so that the overlay and matching, respectively, of both identification marks in the photograph obtained from the detection device can be detected.

[0024] According to a further exemplary embodiment, the second identification mark comprises an interior volume that is free of conductive material.

[0025] According to a further exemplary embodiment, the component carrier further comprises a separating core layer, wherein the separating core layer is removably arranged between at least one electrically insulating layer structure and at least one conductive layer structure on one side and at least one further electrically insulating layer structure and at least one further conductive layer structure on the other side.

[0026] Thus, on both opposing sides of the separated core layer, respective stacks of electrically conductive and electrically insulating layer structures can be formed layer by layer. In the respective electrically conductive layer structures arranged on the opposing sides of the separated core layer, a first identification mark and a second identification mark can be arranged. After the respective stack parts on both sides of the separated core layer are formed, the separated core layer can be removed (e.g. by applying heat or a chemical solution) and each of the two stack parts can be formed in one common manufacturing / lamination step. By forming the first identification mark and the second identification mark, the orientation of each component carrier can be detected before and after removing the separated core layer.

[0027] In an embodiment, the first identifying mark is disposed proximate to the first outer conductive layer and / or the second identifying mark is disposed proximate to the second outer conductive layer.

[0028] In an embodiment, the component carrier further comprises a further first identification mark and / or a further second identification mark formed in each of the other conductive layer structures except for the first and second outer conductive layers.

[0029] In an embodiment, the component carrier further comprises a further identification mark detectable by the detection device, wherein the further identification mark is formed in the respective conductive layer structure disposed closest to the first outer conductive layer or the second outer conductive layer.

[0030] In an embodiment, the stack comprises a mirror surface parallel to the stacking direction, where the further identification mark is arranged on an opposite side with respect to the mirror surface with respect to the first identification mark.

[0031] In an embodiment, the stack comprises a mirror surface parallel to the stacking direction, where the further identification mark is arranged on the same side with respect to the mirror surface with respect to the second identification mark.

[0032] In an embodiment, the further identifying mark comprises an interior volume that is free of conductive material.

[0033] In an embodiment, additional identification marks are formed on each of the other conductive layer structures except for the first and second outer conductive layers.

[0034] In an embodiment, the further identifying mark comprises an interior volume that is free of conductive material.

[0035] In an embodiment, the further identification mark comprises a triangular shape.

[0036] In an embodiment, the further identifying mark comprises the shape of an arrow.

[0037] In an embodiment, the further identification mark comprises three identification points forming a triangular shape, where each identification point comprises an interior volume that is free of conductive material.

[0038] In an embodiment, a further identification mark is formed on the edge of one of the conductive layer structures.

[0039] In an embodiment, the further identification mark is formed at a corner of the conductive layer structure.

[0040] In an embodiment, the further identification mark, the first identification mark, and / or the second identification mark have the same circumferential shape.

[0041] In an embodiment, the further identifying mark is filled with a conductive material.

[0042] In an embodiment, the further identifying mark comprises an interior volume that is free of conductive material.

[0043] In an embodiment, the component carrier is shaped as a plate. This contributes to a compact design, the component carrier nevertheless offering a large base on which to place components. Furthermore, in particular for integrated electronic components, bare dies can advantageously be integrated into thin plates, such as printed circuit boards, thanks to their small thickness.

[0044] In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0045] In the context of this application, the term "printed circuit board" (PCB) may in particular denote a plate-shaped component carrier formed by laminating several conductive layer structures with several electrically insulating layer structures, for example by applying pressure and / or by supplying thermal energy. As a preferred material for PCB technology, the conductive layer structures are made of copper, while the electrically insulating layer structures may have resin and / or glass fibers, the so-called prepreg or FR4 material. The various conductive layer structures may be connected to each other in the desired way by forming holes through the laminate, for example by laser drilling or mechanical drilling, and by filling them partially or completely with a conductive material, in particular copper, to form vias or any other through-hole connections. The filled holes either connect the whole stack (through-hole connections extending through several layers or the whole stack) or they connect at least two conductive layers and are called vias. Similarly, optical interconnections can be formed through the individual layers of the stack to receive electro-optical circuit boards (EOCBs). Apart from one or more components that may be embedded in the printed circuit board, the printed circuit board is usually configured to receive one or more components on one or both opposing faces of the plate-like printed circuit board. They may be connected to the respective main surfaces by soldering. The dielectric part of the PCB may be made of a resin with reinforcing fibers (such as glass fibers).

[0046] In the context of the present application, the term "substrate" may specifically mean a small component carrier. A substrate may be, in relation to a PCB, a relatively small component carrier on which one or more components may be attached and which may act as a connection medium between one or more dies and another PCB. For example, a substrate may have substantially the same size as the components (particularly electronic components) mounted thereon (for example in the case of a chip-scale package (CSP)). More specifically, a substrate may be understood as a carrier for electrical connections or electrical networks and a component carrier comparable to a printed circuit board (PCB), but with a much higher density of horizontally and / or vertically arranged connections. The lateral connections may be, for example, conductive tracks and the vertical connections may be, for example, drilled holes. These lateral and / or vertical connections may be arranged in the substrate and used to provide electrical, thermal and / or mechanical connections of housed or non-housed components (such as bare dies), in particular IC chips, with a printed circuit board or an intermediate printed circuit board. The term "substrate" therefore also includes "IC board". The dielectric portion of the substrate may be composed of a resin with reinforcing particles (such as reinforcing spheres, especially glass spheres).

[0047] The substrate or interposer may have or consist of at least a layer of glass, silicon (Si), and / or a photoimageable or dry-etchable organic material such as an epoxy-based build-up material (such as an epoxy-based build-up film), or a polymeric compound such as polyimide or polybenzoxazole (which may or may not contain photo- and / or thermo-sensitive molecules).

[0048] At least one component may be embedded in the component carrier and / or surface mounted on the component carrier. Such components may be selected from the group consisting of non-conductive inlays, conductive inlays (such as metal inlays, preferably comprising copper or aluminum), heat transfer units (e.g. heat pipes), light guiding elements (e.g. light guides or light guiding connections), electronic components, or combinations thereof. Inlays may be, for example, metal blocks with or without insulating material coatings (IMS inlays) and may be embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their heat conductivity, which should be at least 2 W / mK. Such materials are often based on metals, metal oxides, and / or ceramics, such as, but not limited to, copper, aluminum oxide (Al2O3), or aluminum nitride (AlN). Other geometries with increased surface area are often also used to improve heat exchange capabilities.Further, the components may be active electronic components (implementing at least one pn junction), passive electronic components such as resistors, inductances, or capacitors, electronic chips, storage devices (e.g., DRAM or another data memory), filters, integrated circuits (e.g., field programmable gate arrays (FPGAs), programmable array logic (PALs), generic array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g., field effect transistors (FETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS), junction field effect transistors (JFETs), or insulated gate field effect transistors (IG ... The components may be: InGaAs, IGFETs, all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compounds), optoelectronic interface elements, light emitting diodes, photocouplers, voltage converters (e.g. DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductances, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components may be embedded in the component carrier. For example, magnetic element components may be used. Such magnetic elements may be permanent magnetic elements (ferromagnetic elements, antiferromagnetic elements, multiferroic elements, or ferrimagnetic elements, such as ferrite cores) or paramagnetic elements. However, the component may also be an IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and / or embedded therein.Furthermore, other components may also be used as components, in particular other components that generate and emit electromagnetic radiation and / or that are sensitive to electromagnetic radiation propagating from the environment.

[0049] After processing the internal layer structure of the component carrier, one or both opposing main surfaces of the processed layer structure can be covered symmetrically or asymmetrically (in particular by lamination) with one or more further electrically insulating and / or conductive layer structures, in other words the build-up may be continued until the desired number of layers is obtained.

[0050] After the formation of the stack of electrically insulating and conductive layer structures has been completed, it is possible to proceed with a surface treatment of the resulting layer structure or component carrier.

[0051] In particular, an electrically insulating solder resist can be applied to one or both opposing main surfaces of the layer stack or the component carrier for surface treatment. For example, such a solder resist can be formed on the entire main surface and the layer of solder resist can then be patterned to expose one or more conductive surface portions that are to be used to electrically couple the component carrier to peripheral electronics. Surface portions of the component carrier that remain covered with the solder resist may be effectively protected against oxidation or corrosion, especially surface portions that contain copper.

[0052] With regard to surface treatment, it is also possible to selectively apply a surface finish to exposed conductive surface parts of the component carrier. Such a surface finish can be a conductive cover material on exposed conductive layer structures (e.g. pads, conductive tracks, etc., especially containing or consisting of copper) on the surface of the component carrier. If such exposed conductive layer structures are left unprotected, the exposed conductive component carrier material (especially copper) can oxidize and reduce the reliability of the component carrier. The surface finish can then be formed, for example, as an interface between the surface mounted component and the component carrier. The surface finish has the function of protecting the exposed conductive layer structures (especially copper circuits) and enabling a joining process with one or more components, for example by soldering. Examples of materials suitable for the surface finish are organic solderability preservatives (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), gold (especially hard gold), chemical tin, nickel gold, nickel palladium, etc.

[0053] The above-defined and further aspects of the invention are apparent from and will be elucidated with reference to the example embodiments described hereinafter. [Brief description of the drawings]

[0054] [Figure 1] 1 shows a schematic diagram of a conventional component carrier having a conventional identification marker;

[0055] [Diagram 2] 1 illustrates a schematic diagram of a component carrier with a separate core layer and an identification mark according to an exemplary embodiment;

[0056] [Diagram 3]1 shows a schematic diagram of a component carrier with three identification marks according to an exemplary embodiment;

[0057] [Figure 4] 1 shows a schematic diagram of a component carrier with three identification marks arranged along a stacking direction above each other according to an exemplary embodiment.

[0058] [Diagram 5] 1 illustrates a schematic diagram of an identification mark in the shape of an arrow, according to an exemplary embodiment;

[0059] [Figure 6] 1 illustrates a schematic diagram of an identification mark formed by three dots, according to an exemplary embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0060] The illustrations in the drawings are schematic and in different drawings similar or identical elements are given the same reference signs.

[0061] FIG. 1 shows a schematic diagram of a conventional component carrier 1000 having conventional identification markers 1001, 1002.

[0062] The conventional component carrier 1000 comprises a stack 101 of electrically insulating layer structures 102 and conductive layer structures 103, 106 made of conductive material that are stacked on top of each other in an alternating manner along a stacking direction 104.

[0063] A conventional identification mark 1001 is formed in the conductive layer structure 103 (upper layer L6, inner pattern mirror) in the shape of a triangle. A further conventional identification mark 1002 is formed in the conductive layer structure 106 (lower layer L6) in the shape of a triangle. The identification markers 1001, 1002 are filled with a conductive material. The conventional identification marks 1001, 1002 are not both located above each other along the stacking direction 104, but are offset relative to each other along the stacking direction 104. Furthermore, the conventional identification marks 1001, 1002 are mirror symmetric and have the same pattern in the upper layer L6 and the lower layer L6. A (e.g. x-ray) detection device acquires the respective photographs 110 and detects the shape of the circumference and the orientation of the identification marks 107, respectively.

[0064] The outer covering conductive layer structure 103, 106 (L7) can be a copper foil carrier that can have a thickness between 3 μm and 18 μm. Due to the thick outer covering conductive layer structure 103, 106 (L7), it affects the contrast of the photo 110 of the detection device (e.g., x-ray detection device). Even by adjusting the x-ray source and contrast in each photo 110, the triangular identification markers 1001, 1002 on both sides, which were facing in different directions before core separation, affect the identification of the direction.

[0065] FIG. 2 shows a schematic diagram of a component carrier 100 with a separate core layer 109 and identification marks 107, 108, according to an example embodiment.

[0066] The component carrier 100 comprises a stack 101 of four electrically insulating layer structures 102 and at least one conductive layer structure 103, 106 made of conductive material, stacked in an alternating manner on top of each other along a stacking direction 104. One of the conductive layer structures 103, 106 forms a first outer conductive layer 111 of the stack 101, and another one of the conductive layer structures 103, 106 forms a second outer conductive layer 112 of the stack 101, where the first outer conductive layer 111 and the second outer conductive layer 112 are opposite outer layers of the stack 101. A first identification mark 107 is formed detectable by a detection device. The first identification mark 107 is formed in the conductive layer structure 103 that is arranged closest to the first outer conductive layer 111. Additionally, further first identification marks 107 and / or second identification marks 108 may also be formed in each of the other conductive layer structures 103, 106 except for the outer conductive layers 111, 112.

[0067] Further, a second identification mark 108 is formed detectable by a detection device, where the second identification mark 108 is formed in the conductive layer structure 106 disposed closest to the second outer conductive layer 112. The first identification mark 107 and the second identification mark 108 are formed in the stacking direction 104 above each other.

[0068] The first identification mark 107 and / or the second identification mark 108 comprise an inner volume that is free of conductive material. The identification marks 107, 108 extend along the plane of the respective conductive layer structure 103, 106 and have respective normals parallel to the normal to the plane of the respective conductive layer structure 103, 106.

[0069] In order to illustrate the shapes of the illustrated identification marks 107 and 108, the illustrated identification marks 107 and 108 are shown tilted at 90°. Furthermore, the conductive layers 103 and 106 are represented by layer numbers L4 to L8.

[0070] The identification marks 107, 108 are formed at least in one of the conductive layer structures 103, 106 (layer L6, mirror of the inner pattern) closest to the outer conductive layers 111, 112, respectively. In particular, for example, the identification mark 107 comprises an inner volume that is free of the material of the conductive layer structure. For example, the inner volume of the identification mark 107 is hollow and free of, for example, copper. The electrically insulating material may be similar to the electrically insulating layer structure 102 that is laminated on top of the respective conductive layer structure 103. A (for example x-ray) detection device acquires the respective photographs 110 and detects the circumferential shape and the orientation of the identification marks 107, respectively.

[0071] Covering the conductive layer structure 103, 106 (L7) may be a copper foil that may have a thickness between 3 μm and 18 μm.

[0072] The first identification mark 107 and the second identification mark 108 are formed above each other in a stacking direction 104. Thus, the stack 101 may be formed of a plurality of electrically insulating layer structures 102, 105 and a plurality of conductive layer structures 103, 106, where the respective identification marks 107, 108 are formed in the spaced apart conductive layer structures 103, 106 of the stack 101. When the first identification mark 107 and the second identification mark 108 are formed above each other in a stacking direction 104, a suitable photograph 110 of the alignment of the identification marks 107, 108 obtained by the detection device may be presented.

[0073] The identification marks 107, 108 have the same triangular shape in the illustrated example. In other words, the first identification mark 107 and the second identification mark 108 are formed in a manner that the first identification mark 107 and the second identification mark 108 completely overlap each other on a projection plane having a projection normal parallel to the stacking direction 104.

[0074] The component carrier 100 further comprises a separate core layer 109, where the separate core layer 109 is removably arranged between a central conductive layer structure 103 (L5) on one side and a further conductive layer structure 106 (L5) on the other side. On both opposite sides of the separate core layer 109, respective stack parts of a stack 101 made of conductive layer structures 103, 106 and electrically insulating layer structures 102, 105 can be formed layer by layer. On respective conductive layer structures 103, 106 arranged on opposite sides of the separate core layer 109, a first identification mark 107 and a second identification mark 108 can be formed. After the respective stack parts on both sides of the separate core layer 109 are formed, the separate core layer 109 can be removed so that the two stack parts can be formed in one common manufacturing / lamination step. By forming the identification marks 107, 108, the orientation of the respective component carrier 100 can be detected before and after removing the separate core layer 109.

[0075] 2, the three conductive layer structures 103, 106 (L5, L6, and L7) are copper layers. The identification marks 107, 108 are formed on the conductive layer structure L6 because the patterning process is performed on these layer structures L6 so that the identification marks 107, 108 can be formed in each of such patterning processes. In the conductive layer structures 103, 106 closest to the isolated core layer 109, i.e., L5, and the upper outer conductive layers 111, 112, i.e., L7, the patterning process is not performed before separation from the isolated core layer 109.

[0076] FIG. 3 shows a schematic diagram of a component carrier 100 with three identification marks 107, 301 according to an exemplary embodiment. The stack 101 with conductive layer structures L5, L6, and L7 is a flip stack part of the upper part of the stack 101 of FIG. 2. The first identification mark 107 is the same as the first identification mark 107 of FIG. 2, which may be formed in the conductive layer structure 103 (L6) before being separated from the separated core layer 109, while the third identification mark 301 of FIG. 3 is an additional mark formed in the conductive layer structures L5 and L7 after separation. The third identification mark 301 may have the same shape, for example a triangular shape, and is formed in the stacking direction 104 above each other, similar to the first and second identification marks 107, 108 shown in FIG. 2. The stack 101 has a mirror surface 201 parallel to the stacking direction 104, where the additional identification mark 301 is arranged on the opposite side with respect to the mirror surface 201 with respect to the first identification mark 107.

[0077] The component carrier 100 shown in Fig. 3 can be formed by stacking further electrically insulating layer structures 102, 105 and further outer conductive layers 302 (L4, L8) on top of the outer conductive layer 111 (L5, L7). The identification mark 107 is formed in the conductive layer structure 103 (L6) which is located on the right side by flipping the upper stack part of Fig. 2 and is still now in the center of the stack 101. Therefore, the central identification mark 107 is barely visible in the photograph 110 of the detection device, but the additional further identification mark 301 is formed in the further outer conductive layer 302 (L4, L8) and thus in the conductive layer structures 103, 106 (L5, L7) which are located closest to the surface of the stack 101. Therefore, a geometric representation of the shape of the further identification mark 301 in the photograph 110 of the detection device is possible. The further identification mark 301 may comprise an inner volume which is free of conductive material. Additionally, further identification marks 301 may also be formed on each of the other conductive layer structures 103, 106 except for the outer conductive layers 111, 112.

[0078] Fig. 4 shows a schematic diagram of a component carrier with three identification marks 108, 301 arranged above each other along a stacking direction 104 according to an exemplary embodiment. The component carrier 100 shown in Fig. 4 can be formed by stacking further electrically insulating layer structures 102, 105 and further outer conductive layers 302 (L4, L8) on top of the outer conductive layer 112 (L5, L7).

[0079] The stack 101 with the conductive layer structures L5, L6, and L7 is the stack part of the lower part of the stack 101 in FIG. 2. The second identification mark 108 is the same as the second identification mark 108 in FIG. 2, which may be formed in the conductive layer structure 103 (L6) before being separated from the separated core layer 109, while the third identification mark 301 in FIG. 4 is an additional mark formed in the conductive layer structures L5 and L7 after separation. The third identification mark 301 may have the same shape, for example a triangular shape, and is formed in the stacking direction 104 above each other, similar to the first and second identification marks 107, 108 shown in FIG. 2. The stack 101 has a mirror surface 201 parallel to the stacking direction 104, where the additional identification mark 301 is arranged on the same side with respect to the mirror surface 201 with respect to the second identification mark 108. Additionally, further identification marks 301 may also be formed on each of the other conductive layer structures 103, 106 except for the outer conductive layers 111, 112.

[0080] A second identification mark 108 and a third identification mark 301, having an inner volume free of conductive material, are formed above each other and the overlay and matching of all the identification marks 108, 301, respectively, in the photograph 110 acquired by the detection device can be detected.

[0081] 5 shows a schematic diagram of a first identification mark 107 in the shape of an arrow, according to an exemplary embodiment. The first identification mark 107 has an arrow shape. The second and third identification marks 108, 301 can also have respective shapes.

[0082] 6 shows a schematic diagram of an identification mark 107 formed by three points according to an exemplary embodiment. The three identification points form a triangular shape, where each identification point comprises an inner volume that is free of conductive material. For example, the three identification points may be formed at the corners of an imaginary triangle to form the identification mark 107. The second and third identification marks 108, 301 may also have respective shapes.

[0083] It should be noted that the term "comprising" does not exclude other elements or steps, and that "a" or "an" does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

[0084] It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.

[0085] The implementation of the invention is not limited to the preferred embodiment shown in the drawings and described above, instead many variations are possible using the solutions shown and the principles according to the invention, even in the case of radically different embodiments. [Explanation of symbols]

[0086] 100 Component Carriers 101 Stack 102 Electrical insulation layer structure 103 Conductive layer structure 104 Lamination direction 105 Further Electrical Insulation Layer Structure 106 Further conductive layer structures 107 Identification Mark 108 Second Identification Mark 109 Separate core layer 110 X-ray 111 First outer conductive layer 112 second outer conductive layer 201 Mirror surface 301 Third and Further Identifying Mark 302 Further outer conductive layer

Claims

1. A component carrier, comprising: a stack of at least four electrically insulating layer structures and at least five electrically conductive layer structures stacked in an alternating manner on top of one another along a stacking direction; wherein one of said conductive layer structures forms a first outer conductive layer of said stack and another of said conductive layer structures forms a second outer conductive layer of said stack; wherein the first outer conductive layer and the second outer conductive layer are opposing outer layers of the stack. a first identification mark detectable by a detection device; wherein the first identification mark is formed on the conductive layer structure; a second identifying mark detectable by the detection device; wherein the second identification mark is formed on the conductive layer structure; wherein the first identification mark and the second identification mark are formed above each other in a stacking direction, wherein at least one of the first identification mark and the second identification mark is configured to detect an orientation of the component carrier. A component carrier comprising:

2. the first identification mark comprising an interior volume free of conductive material; The component carrier according to claim 1 .

3. the first identification mark has a triangular shape; The component carrier according to claim 2.

4. the first identification mark having an arrow shape; The component carrier according to claim 2.

5. the first identification mark comprises three identification points forming a triangular shape; wherein each discrimination point comprises an interior volume that is free of said conductive material; The component carrier according to claim 2.

6. the first identification mark is formed on an edge of the one conductive layer structure; A component carrier according to any one of claims 2 to 5.

7. The first identification mark is formed at a corner of the one conductive layer structure. A component carrier according to any one of claims 2 to 5.

8. the first identification mark and the second identification mark have the same circumferential shape; A component carrier according to any one of claims 1 to 7.

9. the second identifying mark is filled with a conductive material and the second identifying mark only comprises a circumferential path that is free of conductive material; The component carrier according to claim 1 .

10. the second identification mark comprising an interior volume free of conductive material; A component carrier according to any one of claims 1 to 8.

11. The component carrier, Separate Core Layer Further equipped with wherein the separating core layer is removably arranged between the at least one electrically insulating layer structure and the at least one conductive layer structure on one side and the at least one further electrically insulating layer structure and the at least one further conductive layer structure on the other side. A component carrier according to any one of claims 1 to 10.

12. the first identifying mark is disposed proximate to the first outer conductive layer; and / or the second identifying mark is disposed proximate to the second outer conductive layer; A component carrier according to any one of claims 1 to 11.

13. The component carrier, a further first identification mark and / or a further second identification mark formed on each of the conductive layer structures other than the first outer conductive layer and the second outer conductive layer; The component carrier according to claim 1 , further comprising:

14. The component carrier, Further identification marks detectable by the detection device Further equipped with wherein the further identification mark is formed on the respective conductive layer structure disposed closest to the first outer conductive layer or the second outer conductive layer. A component carrier according to any one of claims 1 to 13.

15. the stack has mirror surfaces parallel to the stacking direction; wherein the further identification mark is disposed on an opposite side of the mirror surface with respect to the first identification mark. A component carrier as claimed in claim 14.

16. the stack has mirror surfaces parallel to the stacking direction; wherein the further identification mark is disposed on the same side of the mirror surface as the second identification mark. A component carrier as claimed in claim 14.

17. the further identification mark comprising an interior volume free of conductive material; A component carrier according to any one of claims 14 to 16.

18. a further identification mark is formed on each of the other conductive layer structures except for the first outer conductive layer and the second outer conductive layer; A component carrier according to any one of claims 14 to 17.

19. the further identification mark having a triangular shape; A component carrier according to any one of claims 14 to 18.

20. the further identification mark having an arrow shape; A component carrier according to any one of claims 14 to 18.

21. the further identification mark comprises three identification points forming a triangular shape; wherein each discrimination point comprises an inner volume that is free of conductive material; A component carrier according to any one of claims 14 to 18.

22. the further identification mark is formed on an edge of the one conductive layer structure; A component carrier according to any one of claims 14 to 17.

23. the further identification mark is formed at a corner of the conductive layer structure; A component carrier according to any one of claims 14 to 17.

24. the further identification mark, the first identification mark, and / or the second identification mark have the same circumferential shape; A component carrier according to any one of claims 14 to 23.

25. the further identifying mark being filled with a conductive material; A component carrier according to any one of claims 14 to 16.

26. The first identification mark and the second identification mark are formed in a manner that the first identification mark and the second identification mark completely overlap each other on a projection plane having a projection normal line parallel to the stacking direction. A component carrier according to any one of claims 1 to 25.

27. the first and / or second outer conductive layers covering the stack are copper foils, in particular having a thickness between 3 μm and 18 μm; A component carrier according to any one of claims 1 to 26.

28. A method for manufacturing a component carrier, comprising the steps of: forming a stack of at least four electrically insulating layer structures and at least five electrically conductive layer structures stacked in an alternating manner above one another along a stacking direction; wherein one of said conductive layer structures forms a first outer conductive layer of said stack and another of said conductive layer structures forms a second outer conductive layer of said stack; wherein the first outer conductive layer and the second outer conductive layer are opposing outer layers of the stack. Providing a first identification mark detectable by a detection device; forming the first identification mark on a conductive layer structure; Providing a second identification mark detectable by a detection device; and forming the second identification mark on a conductive layer structure; wherein the first identification mark and the second identification mark are formed above each other in a stacking direction, wherein at least one of the first identification mark and the second identification mark is configured to detect an orientation of the component carrier. A method for manufacturing a component carrier comprising:

29. forming a separate core layer; wherein the separating core layer is removably arranged between the at least one electrically insulating layer structure and the at least one electrically conductive layer structure on one side and at least one further electrically insulating layer structure and at least one further electrically conductive layer structure on the other side.

30. The method of claim 28, further comprising:

30. Detecting the orientation of each of the component carriers before and after removing the separated core layer by forming the first identification mark and the second identification mark.

30. The method of claim 29, further comprising:

31. The second identification mark is formed on the conductive layer structure before being separated from the separation core layer.

30. The method of claim 29.

32. forming a further identification mark detectable by a detection device; wherein the further identification mark is formed in the respective conductive layer structure disposed closest to the first outer conductive layer or the second outer conductive layer; wherein the further identification mark is a further mark formed in the conductive layer structure after separation from the separated core layer.

32. The method of claim 31 further comprising:

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