Integrated circuit structure and method for manufacturing an integrated circuit structure (MIM capacitor structure)

Abstract

To provide an integrated circuit structure.SOLUTION: An integrated circuit structure includes a back-end-of-line (BEOL) wiring layer including metal lines and a first region between the metal lines. The integrated circuit structure includes a metal-insulator-metal (MIM) capacitor formed in the first region. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnection electrically connecting between the first electrode and the third electrode, and a second metal interconnection electrically connecting between the second electrode and the fourth electrode.SELECTED DRAWING: Figure 3M

Description

[Technical field]

[0001] The present disclosure relates to the fields of electrical, electronics and computers. In particular, the present disclosure relates to metal-insulator-metal (MIM) capacitors with different plate structures. Typically, MIM capacitors have a sandwich structure and can be called parallel plate capacitors. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. [Background technology]

[0002] Metal-insulator-metal (MIM) capacitors may be used in high performance applications in complementary metal oxide semiconductor (CMOS) technology. For example, MIM capacitors have been used in functional circuits such as mixed signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM), embedded DRAM, and logic circuits. In system-on-chip (SOC) applications, different capacitors for different functional circuits need to be integrated on the same chip to serve different purposes. For example, in mixed signal circuits, capacitors are used as decoupling capacitors and high frequency noise filters. In DRAM and embedded DRAM circuits, capacitors are used as memory storage. However, in RF circuits, capacitors are used in oscillators and phase shift networks for coupling and / or bypass purposes. In microprocessors, capacitors may be used for decoupling. The high frequency and low power of semiconductor chips may require a large number of decoupling capacitors. MIM capacitors have been used for decoupling in these applications. Summary of the Invention [Problem to be solved by the invention]

[0003] An integrated circuit structure is provided. [Means for solving the problem]

[0004] Certain embodiments relate to an integrated circuit structure. The integrated circuit structure includes a back-end-of-line (BEOL) wiring layer including metal lines and a first region between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first region. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode.

[0005] Another embodiment of the present disclosure relates to a method of fabricating an integrated circuit structure, the method including forming a back-end-of-line (BEOL) wiring layer including metal lines and a first region between the metal lines, the method also including forming a metal-insulator-metal (MIM) capacitor in the first region by forming a first electrode, forming a first dielectric layer on the first electrode, forming a second electrode on the first dielectric layer, forming a second dielectric layer on the second electrode, forming a third electrode on the second dielectric layer, forming a third dielectric layer on the third electrode, forming a fourth electrode on the third dielectric layer, forming a first metal interconnect to electrically connect the first electrode and the third electrode, and forming a second metal interconnect to electrically connect the second electrode to the fourth electrode.

[0006] The above summary is not intended to describe each example embodiment or every implementation of the present disclosure.

[0007] The drawings contained in this application are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, explain the principles of the present disclosure. The drawings are merely illustrative of particular embodiments and do not limit the disclosure. [Brief description of the drawings]

[0008] [Figure 1A] 1 is a cross-sectional view of an example semiconductor device illustrating the use of dummy electrodes in open areas between metal lines. [Figure 1B] FIG. 1B is a plan view of the example semiconductor device of FIG. 1A. [Figure 2A] 1A-1C are plan views illustrating example shapes of bottom electrodes of multi-plate MIM capacitor devices in open areas between metal lines, according to embodiments. [Figure 2B] 1 is a plan view illustrating another example shape of a bottom electrode of a multi-plate MIM capacitor device according to an embodiment. [Figure 2C] 1 is a plan view illustrating another example shape of a bottom electrode of a multi-plate MIM capacitor device according to an embodiment. [Figure 3A] 1A-1D are cross-sectional views illustrating a multi-plate MIM capacitor device at an intermediate stage in the manufacturing process, according to an embodiment. [Figure 3B] FIG. 3B is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3A after additional fabrication operations, according to an embodiment. [Figure 3C] FIG. 3C is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3B after additional fabrication operations, according to an embodiment. [Figure 3D] FIG. 3D is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3C after additional fabrication operations, according to an embodiment. [Figure 3E] FIG. 3D is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3D after additional fabrication operations, according to an embodiment. [Figure 3F] FIG. 3E is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3E after additional fabrication operations, according to an embodiment. [Figure 3G] FIG. 3F is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3F after additional fabrication operations, according to an embodiment. [Figure 3H] FIG. 3F is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3G after additional fabrication operations, according to an embodiment. [Figure 3I] FIG. 3C is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3H after additional fabrication operations, according to an embodiment. [Figure 3J] FIG. 3I is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3I after additional fabrication operations, according to an embodiment. [Figure 3K] FIG. 3J is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3J after additional fabrication operations, according to an embodiment. [Figure 3L] FIG. 3K is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3K after additional fabrication operations, according to an embodiment. [Figure 3M] FIG. 3D is a cross-sectional view of the multi-plate MIM capacitor device of FIG. 3L after additional fabrication operations, according to an embodiment. [Figure 4] 1 is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. [Diagram 5] 1 is a cross-sectional view of a multi-plate MIM capacitor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] It should be understood that elements in the figures are illustrated for simplicity and clarity of illustration, and that well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown for simplicity of illustration and clarity of the illustrated embodiment.

[0010] This disclosure describes metal-insulator-metal (MIM) capacitor devices and methods for fabricating MIM capacitor devices. Specifically, this disclosure describes MIM capacitor devices that are disposed in areas between trace metal lines of a semiconductor device and include at least four or five MIM plates (i.e., alternating metal and insulating layers).

[0011] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Other embodiments may be devised without departing from the scope of the present disclosure. It should be noted that the following description and drawings describe various connections and positional relationships between elements (e.g., above, below, adjacent, etc.). These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limiting in this respect. Thus, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect. As an example of an indirect positional relationship, when the present description refers to forming a layer "A" on a layer "B", it includes the situation where there are one or more intervening layers (e.g., layer "C") between layers "A" and "B", as long as the relative properties and functions of layers "A" and "B" are not substantially altered by the intervening layers.

[0012] The following definitions and abbreviations shall be used for the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to include a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that comprises recited elements is not necessarily limited to only those elements, but may include other elements not expressly described or inherent to such composition, mixture, process, method, article, or device.

[0013] In the following description, the terms "top", "bottom", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the structures and methods described as oriented in the drawings. The terms "overlying", "above", "on", "located on" or "located on" mean that a first element, such as a first structure, is above a second element, such as a second structure, where there may be an intervening element, such as an interface structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating or semiconducting layer at the interface between the two elements. It should be noted that the term "selective to", e.g., "a first element selective to a second element", means that the first element can be etched and the second element can act as an etch stop.

[0014] For the sake of brevity, conventional techniques for semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Also, various operations and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and thus, for the sake of brevity, many conventional steps are only briefly mentioned herein without showing details of the well-known processes or are omitted entirely.

[0015] In general, the various processes used to form the microchips that will be packaged into ICs fall into four broad categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0016] Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Another deposition technique is plasma enhanced chemical vapor deposition (PECVD), a process that uses energy in a plasma to create reactions at the wafer surface that would otherwise require the higher temperatures associated with traditional CVD. Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0017] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), chemical mechanical planarization (CMP), etc. One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to dry plasma etching that uses a remote wide beam ion / plasma source to remove substrate material by physically inert gases or chemically reactive gases means or both. Like other dry plasma etching techniques, IBE has advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and reduced substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove material deposited on the wafer. In RIE, the plasma is generated under low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma attack and react with the wafer surface to remove the material.

[0018] Semiconductor doping is the modification of electrical properties, for example by doping the source and drain of a transistor, typically by diffusion or ion implantation or both. These doping processes are followed by a furnace anneal or rapid thermal anneal (RTA). The anneal serves to activate the implanted dopants. Films, both conductors (e.g. polysilicon, aluminum, copper, etc.) and insulators (e.g. various forms of silicon dioxide, silicon nitride, etc.), are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed by the application of a voltage. By forming structures made of these various components, millions of transistors are created, which are wired together to form the complex circuits of modern microelectronic devices.

[0019] Semiconductor lithography is the creation of a three-dimensional relief image or pattern on a semiconductor substrate for later transfer of the pattern to a substrate. In semiconductor lithography, patterns are created with light-sensitive polymers called photoresists. The lithography and etch pattern transfer steps are repeated multiple times to create the complex structures that make up transistors and the many interconnects that connect a circuit's millions of transistors. Each pattern printed on the wafer is aligned with the one before it, and conductors, insulators, and selectively doped regions are gradually built up to form the final device.

[0020] Moving now to a review of the technology more specifically related to aspects of the present disclosure, generally, a MIM capacitor refers to a capacitor having a stacked structure, for example including a bottom electrode, a top electrode and an insulator between them. More specifically, MIM capacitors are commonly used in high performance applications in CMOS technology. Typically, MIM capacitors have a sandwich structure and can be referred to as parallel plate capacitors. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. Both parallel plates are typically formed from TiN, which is patterned and etched using several photolithographic and photomasking steps. The thin insulating dielectric layer typically consists of silicon oxide, silicon nitride, or high dielectric constant materials such as Al2O3, HfO2, ZrO2, or combinations thereof, deposited, for example, by chemical vapor deposition (CVD). In certain embodiments of the present invention, a MIM capacitor having more than the traditional three plates (i.e., a first metal layer, an insulating layer and a second metal layer) is described. For example, certain embodiments of the present invention describe four-plate and five-plate MIM capacitors.

[0021] As described herein, the high frequency and low power of semiconductor chips can require a large number of decoupling capacitors. MIM capacitors have been used for decoupling in these applications. These capacitors can take up valuable chip area and impact the overall size of the chip.

[0022] Certain regions of semiconductor wafers, such as metal fill feature regions between metal wiring, often use dummy metal fill features. These dummy metal fill features do not contribute to device performance at all and are primarily used to meet uniform metal density requirements for effective chemical mechanical planarization (CMP), patterning and etching. In other words, CMP performance may be degraded if there are regions with low amounts of metal features. If the uniform metal density requirements are not met, metal dishing and / or dielectric erosion may occur, which may result in undesirable surface topography after CMP (i.e., not planarized). Certain embodiments of the present invention place MIM capacitors in these metal fill feature regions instead of using dummy metal fill features. Doing so provides the advantage of using decoupling capacitors in areas that would not normally be functional. Additionally, the MIM capacitors include a metal layer that can contribute to meeting the uniform metal density requirements of CMP and other processes.

[0023] Referring now to the drawings, in which like numbers represent the same or similar elements, and first to FIGS. 1A and 1B, an exemplary semiconductor device 100 is shown including a dummy electrode 106 (i.e., a metal filled feature). In this example, a semiconductor wafer or substrate 102 is provided. Several back-end-of-line (BEOL) wiring levels of a semiconductor integrated circuit are shown. At the bottom of FIG. 1A, a lower level wiring 104 and a dummy electrode 106 are formed. A capping layer 108 is formed over the lower level wiring 104 and the dummy electrode 106. The capping layer 108 may be formed of, for example, AlN, SiN, SiCN, combinations thereof, or any other suitable dielectric material. An interlevel dielectric layer 110 is formed over the lower capping layer 108, and several metal interconnects 112 extend upward through the dielectric layer 110 to contact the upper level wiring 114. An upper capping layer 116 is formed over the upper level wiring 114. The upper capping layer 116 may be made of the same or similar material as the lower capping layer 108. The dummy electrode 106 has no function in this semiconductor device, so the dummy electrode 106 does not connect to the lower wiring (not shown) or the upper wiring 114. However, as discussed above, the dummy electrode 106 has the effect of increasing the metal density in the otherwise "free" areas between the active metal lines (e.g., the combination of the upper level wiring 114, the metal interconnect 112, and the lower level wiring 104). This allows for improved performance of the CMP process, but the dummy electrode 106 uses valuable space on the semiconductor wafer.

[0024] 1B, which shows a plan view of the semiconductor device 100 shown in FIG. 1A taken along section line AA. FIG. 1B shows an example of a placement pattern of dummy electrodes 106 and how much space the dummy electrodes 106 may occupy in the open areas between adjacent lower level interconnects 104.

[0025] 2A-2C, several example shapes of the bottom electrode (or first electrode 202) of a MIM capacitor device 200 are shown in accordance with certain embodiments. In each of these figures, the first electrode 202 has a different shape with a different pattern of openings 204 therein. It should be understood that the first electrode 202 may have any suitable shape that meets the uniform metal density requirements of CMP and optimizes the MIM capacitor density across the semiconductor wafer substrate 102.

[0026] 3A-3M, and first to FIG. 3A, an exemplary embodiment illustrates a method for fabricating a four-plate MIM capacitor (MIMcap) device 300. As shown in FIG. 3A, a substrate 302 is provided. In a particular embodiment, the substrate may be an interlevel dielectric layer deposited on a different BEOL layer (not shown). In FIG. 3A, a first (lower) wiring level 304 of an exemplary semiconductor device is shown after completion of several BEOL processing steps (e.g., etching, deposition, metal filling, planarization, etc.). In a particular embodiment, instead of forming a dummy electrode as described above with respect to FIG. 1A and FIG. 1B, a first electrode 306 (or lower electrode) of the MIMcap device 300 is formed. A capping layer or first insulating layer 308 is formed on the first wiring level 304, the first electrode 306, and the surrounding interlevel dielectric layer or substrate 302 as shown in FIG. 3B. This first electrode 306 is the bottom plate of the MIM capacitor. The capping layer (or first insulating layer 308) may be formed of, for example, AlN, SiN, SiCN, combinations thereof, or any other suitable dielectric material.

[0027] 3C, a metal plate 310 is formed on the first insulating layer 308. Although not shown in FIG. 3C, the metal plate 310 may be formed first by a thick metal plate deposition process and then patterned into a desired shape. In certain embodiments, the metal plate 310 is made of at least one of TiN, TaN, Al, or any other suitable electrode material. As shown in FIG. 3C, the position of the metal plate 310 is slightly shifted to the left with respect to the position of the first electrode 306. Specifically, the right side of the metal plate 310 is further left than the right side of the first electrode 306, and the left side of the metal plate 310 is also further left than the left side of the first electrode 306. In certain embodiments, the metal plate 310 may be aligned with the first electrode 306.

[0028] 3D, after patterning the metal plate 310 of FIG. 3C, a first interlayer dielectric layer 312 is formed to cover the surfaces of the first insulating layer 308 and the metal plate 310. The surface of the first interlayer dielectric layer 312 is then planarized, such as by using a CMP process, to expose the top surface of the metal plate 310.

[0029] 3E, a second electrode 314 is formed on the metal plate 310 by a deposition and patterning process. In certain embodiments, the size and location of the second electrode 314 is generally the same as the thick metal plate 310. The combination of the metal plate 310 and the second electrode 314 may actually be considered to be the second electrode of the MIMcap device 300. In certain embodiments, the second electrode 314 is made of TiN, TaN, or any other suitable electrode material. The material of this second electrode 314 may be the same or different from the material of the underlying metal plate 310. It should be understood that if the material of the second electrode 314 is the same as the material of the underlying metal plate 310, then these two layers may be formed in a single step and may be considered as a single layer.

[0030] Referring now to FIG. 3F, a first high-k dielectric layer 316 is conformally formed over the entire surface of the wafer. The conformal first high-k dielectric layer 316 comprises a high-k dielectric material. In general, the term high-k refers to a material that has a high dielectric constant (κ, kappa) compared to silicon dioxide. High-k dielectrics are used in semiconductor fabrication processes, where they are typically used to replace a silicon dioxide gate dielectric or another dielectric layer in a device. Thus, as used herein, the term high-k refers to a material that has a relative dielectric constant κ much higher than silicon dioxide (e.g., hafnium oxide (HfO2) has a dielectric constant κ=25 compared to silicon dioxide's dielectric constant of 4). Examples of suitable high-k dielectric materials include, but are not limited to, HfO2, Al2O3, ZrO2, or lanthanum oxide (La2O3), or combinations thereof. Due to the conformal coating of the first high-k dielectric layer 316, the surface has some topography, with the top level of the high-k dielectric layer 316 being higher in the area of ​​the second electrode 314. However, it should be understood that in other embodiments, the first high-k dielectric layer 316 may be deposited thicker and then planarized by CMP, which would require additional processing steps.

[0031] 3G, a third electrode 318 is formed on the first high-k dielectric layer 316. Although not shown in FIG. 3G, the third electrode 318 may be first formed by a deposition process and then patterned into a desired shape. In a particular embodiment, the third electrode 318 is made of at least one of TiN, TaN, Al, or any other suitable electrode material. As shown in FIG. 3G, the position of the third electrode 318 is slightly shifted to the right with respect to the position of the second electrode 314. Specifically, the right side of the third electrode 318 is further to the right than the right side of the second electrode 314, and the left side of the third electrode 318 is further to the right than the left side of the second electrode 314. In the exemplary embodiment shown in FIG. 3G, the position of the right side of the third electrode 318 generally coincides with the position of the right side of the first electrode 306. This rough alignment allows for subsequent electrical connection between the first electrode 306 and the third electrode 318, as described in more detail below.

[0032] 3H, a second high-k dielectric layer 320 is conformally formed over the entire surface of the wafer. The conformal second high-k dielectric layer 320 comprises a high-k material that may be the same or different than the material of the first high-k dielectric layer 316. Again, due to the conformal coating of the first and second high-k dielectric layers 316 and 320, and the formation of the second and third electrodes 314 and 318, the surface has some topography.

[0033] 3I, a deposition and patterning process forms a fourth electrode 322 on the second high-k dielectric layer 320. The material of this fourth electrode 322 may be the same or different from the material of the underlying electrode layer. In certain embodiments, the size and position of the fourth electrode 322 is generally the same as the thick metal plate 310 and the second electrode 314, although this is not absolutely necessary. This rough alignment of the fourth electrode 322 allows for later electrical connection between the second electrode 314 and the fourth electrode 322, as described in more detail below.

[0034] 3J, a second interlayer dielectric layer 324 is formed over the entire surface of the wafer to cover the fourth electrode 322 and the second high-k dielectric layer 320. Then, a CMP process is performed on the second interlayer dielectric layer 324 to planarize the surface of the layer.

[0035] In this example, the fourth electrode 322 has a stepped surface shape that corresponds to the surface shape of the underlying second high-k dielectric layer 320 (i.e., because the second high-k dielectric layer 320 is conformally formed over all surfaces), and the third electrode 318 has a stepped surface shape that corresponds to the surface shape of the underlying first high-k dielectric layer 316 (i.e., because the first high-k dielectric layer 316 is conformally formed over all surfaces).

[0036] 3K, an etching process (e.g., RIE) is performed on the wafer to create spaces for later formation of metal interconnects and top metal wiring of the BEOL layers, while simultaneously etching adjacent to the MIMcap device 300 to allow for subsequent electrical connection of the various MIMcap electrodes.

[0037] 3L, metal interconnects 328A and 328B and a second wiring level 326 (i.e., upper level wiring) are formed. In areas not corresponding to the MIMcap device 300, the metal interconnect 328A electrically connects the first wiring level 304 to the upper level or second wiring level 326 of the BEOL layers. However, in areas corresponding to the MIMcap device 300, the metal interconnect 328B electrically connects the various electrodes to each other. Specifically, the right one of the metal interconnects 328B electrically connects the first electrode 306 to the third electrode 318, and the left one of the metal interconnects 328B electrically connects the second electrode 314 to the fourth electrode 322.

[0038] In certain embodiments, all of the electrodes (i.e., 306, 310, 314, 318, and 322) are all vertically aligned. In this case, through holes larger than the via size are required on the electrodes where there is no electrode-to-via contact to allow the via 328 to penetrate. In these embodiments, through holes are formed where electrode-to-via contact is required.

[0039] 3M, another capping layer or second insulating layer 330 is formed on the second wiring level 326 and the surrounding second interlayer dielectric layer 324. In this way, a four-plate MIMcap device 300 is formed, with two of the four electrodes connecting on the right side and the other two of the electrodes connecting to each other on the left side. Also, in certain embodiments, only one additional mask (i.e., for the formation of the metal plate 310) and only four additional processing steps are required to incorporate the MIMcap device 300 structure into the open space between the wiring of the BEOL layer. In other embodiments, multiple additional masks may be required if, in addition to patterning the metal plate 310, the third electrode 318 and the second high-k dielectric layer 320 also need to be patterned. In these embodiments, there may be more than four additional processing steps.

[0040] Referring now to FIG. 4, an exemplary embodiment is shown illustrating a method of fabricating a five-plate MIM capacitor (MIMcap) device 400. Most of the processing of the MIMcap device 400 of FIG. 4 is the same as that described above with respect to FIGS. 3A to 3M and will not be repeated here. However, there are some differences. First, the position of the metal plate 310 is shifted to the right compared to the embodiment of FIGS. 3A to 3M. Second, a portion of the first interlayer dielectric layer 312 is disposed between the metal plate 310 and the second electrode 314 to electrically isolate these layers from each other. Third, the etch depth for the metal interconnect 428 in the area corresponding to the MIMcap device 400 is different. Specifically, the metal interconnect 428 on the left side of the MIMcap device is formed down to a depth corresponding to the top surface of the first electrode 306, thereby electrically connecting the first electrode 306, the second electrode 314, and the fourth electrode 322. Additionally, a metal interconnect 428 on the right side of the MIMcap device 400 is formed down to a depth corresponding to the top surface of the metal plate 310, thereby electrically connecting the metal plate 310 to the third electrode 318. Thus, there are a total of five conductive layers in this MIMcap device 400, three on the left side and two on the right side. The metal plate 310 can be considered the fifth electrode in this embodiment.

[0041] In this example, the fourth electrode 322 has a stepped surface shape that corresponds to the surface shape of the underlying second high-k dielectric layer 320 (i.e., because the second high-k dielectric layer 320 is conformally formed over all surfaces), and the third electrode 318 has a stepped surface shape that corresponds to the surface shape of the underlying first high-k dielectric layer 316 (i.e., because the first high-k dielectric layer 316 is conformally formed over all surfaces).

[0042] Referring now to FIG. 5, an exemplary embodiment is shown illustrating a method of fabricating another five-plate MIM capacitor (MIMcap) device 500. Most of the processing of the MIMcap device 500 of FIG. 5 is the same as that described above with respect to FIG. 4 and will not be repeated here. However, there are some differences. Specifically, a third high-k dielectric layer 502 is formed between the metal plate 310 and the first interlayer dielectric layer 312. In certain embodiments, the third high-k dielectric layer 502 is formed on the metal plate 310, which are later patterned together. In other embodiments, the third high-k dielectric layer 502 is not patterned and covers the entire surface similar to other high-k dielectric layers described herein. Thus, in the embodiment shown in FIG. 5, there is a bilayer dielectric structure between the metal plate 310 and the second electrode 314, which bilayer dielectric structure includes both the first interlayer dielectric layer 312 and the third high-k dielectric layer 502.

[0043] The description of various embodiments is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements over the art in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. [Explanation of symbols]

[0044] 100 Semiconductor Devices 200 MIM Capacitor Devices 300 4-plate MIM capacitor (MIMcap) device 400 5-plate MIM capacitor (MIMcap) device 500 5-plate MIM capacitor (MIMcap) device

Claims

1. 1. An integrated circuit structure comprising: a lower level back-end-of-line (BEOL) wiring layer including a lower level metal line; and an upper level back-end-of-line (BEOL) wiring layer including an upper level metal line, the lower level metal line and the upper level metal line being interconnected and extending in a first direction in a plan view, the lower level metal line and the upper level metal line defining filled feature regions in the plan view between the lower level metal lines that do not include elements of the lower level BEOL wiring layer; The integrated circuit structure further comprises: a metal-insulator-metal (MIM) capacitor formed in said fill feature region, said MIM capacitor extending at least partially through a thickness of said integrated circuit structure from said lower level BEOL wiring layer to said upper level BEOL wiring layer but not overlapping in said plan view with said lower level metal lines; an integrated circuit structure, wherein a first electrode of the MIM capacitor is formed at the same level as the lower level metal line in the thickness direction, and all remaining portions of the MIM capacitor are formed between the lower level metal line and the upper level metal line in the thickness direction.

2. The MIM capacitor is The first electrode; a first dielectric layer formed on the first electrode; a second electrode formed on the first dielectric layer; a second dielectric layer formed on the second electrode; a third electrode formed on the second dielectric layer; a third dielectric layer formed on the third electrode; a fourth electrode formed on the third dielectric layer; a first metal interconnect electrically connecting the first electrode and the third electrode; a second metal interconnect electrically connecting the second electrode to the fourth electrode; right sides of the first and third electrodes extend further to the right than right sides of the second and fourth electrodes; 2. The integrated circuit structure of claim 1 wherein the left sides of said second and fourth electrodes extend further to the left than the left sides of said first and third electrodes.

3. 3. The integrated circuit structure of claim 2 wherein said first dielectric layer is a capping layer comprising at least one material selected from the group consisting of AlN, SiN, and SiCN.

4. 3. The integrated circuit structure of claim 2, wherein the third electrode has a stepped surface topography corresponding to a topography of the underlying second dielectric layer, and the fourth electrode has a stepped surface topography corresponding to a topography of the underlying third dielectric layer.

5. The first dielectric layer, the second dielectric layer, and the third dielectric layer are each made of HfO. ２ and Al ２ O ３ and ZrO ２ and lanthanum oxide (La ２ O ３ 3. The integrated circuit structure of claim 2 comprising at least one material selected from the group consisting of:

6. the first metal interconnect extends vertically through the third dielectric layer, the third electrode, the second dielectric layer, and the first dielectric layer to contact the first electrode; 3. The integrated circuit structure of claim 2, wherein said second metal interconnect extends vertically through said fourth electrode, said third dielectric layer, and said second dielectric layer to contact said second electrode.

7. The MIM capacitor is The first electrode; a first dielectric layer formed on the first electrode; a second electrode formed on the first dielectric layer; an interlevel dielectric layer formed on the second electrode; a third electrode formed on the interlevel dielectric layer; a second dielectric layer formed on the third electrode; a fourth electrode formed on the second dielectric layer; a third dielectric layer formed on the fourth electrode; a fifth electrode formed on the third dielectric layer; a first metal interconnect electrically connecting the first electrode, the third electrode, and the fifth electrode; 2. The integrated circuit structure of claim 1, further comprising: a second metal interconnect electrically connecting said second electrode and said fourth electrode.

8. 8. The integrated circuit structure of claim 7 further comprising a fourth dielectric layer formed between said second electrode and said interlevel dielectric layer.

9. the left sides of the first, third and fifth electrodes extend further to the left than the left sides of the second and fourth electrodes; 8. The integrated circuit structure of claim 7 wherein right sides of said second and fourth electrodes extend further to the right than right sides of said third and fifth electrodes.

10. 8. The integrated circuit structure of claim 7 wherein said first dielectric layer is a capping layer comprising at least one material selected from the group consisting of AlN, SiN, and SiCN.

11. 8. The integrated circuit structure of claim 7, wherein the fourth electrode has a stepped surface profile corresponding to a surface profile of the second dielectric layer, and the fifth electrode has a stepped surface profile corresponding to a surface profile of the third dielectric layer.

12. The first dielectric layer, the second dielectric layer, the interlayer dielectric layer, and the third dielectric layer are each made of HfO. ２ and Al ２ O ３ and ZrO ２ and lanthanum oxide (La ２ O ３ 8. The integrated circuit structure of claim 7 comprising at least one material selected from the group consisting of:

13. the first metal interconnect extends vertically through the fifth electrode, the third dielectric layer, the second dielectric layer, the third electrode, the interlevel dielectric layer, and the first dielectric layer to contact the first electrode; 8. The integrated circuit structure of claim 7, wherein said second metal interconnect extends vertically through said third dielectric layer, said fourth electrode, said third dielectric layer and said interlevel dielectric layer to contact said second electrode.

14. 1. A method of manufacturing an integrated circuit structure, comprising the steps of: forming a lower level back-end-of-line (BEOL) wiring layer including a lower level metal line and an upper level back-end-of-line (BEOL) wiring layer including an upper level metal line, the lower level metal line and the upper level metal line being interconnected and extending in a first direction in a plan view, the lower level metal line and the upper level metal line defining filled feature regions in the plan view between the lower level metal lines that are free of elements of the lower level BEOL wiring layer; The method further comprises: forming a metal-insulator-metal (MIM) capacitor in said fill feature region, said MIM capacitor extending at least partially through a thickness of said integrated circuit structure from said lower level BEOL wiring layer to said upper level BEOL wiring layer but not overlapping in said plan view with said lower level metal lines; a first electrode of the MIM capacitor is formed at the same level as the lower level metal line in the thickness direction, and all remaining portions of the MIM capacitor are formed between the lower level metal line and the upper level metal line in the thickness direction.

15. forming the first electrode; forming a first dielectric layer on the first electrode; forming a second electrode on the first dielectric layer; forming a second dielectric layer on the second electrode; forming a third electrode on the second dielectric layer; forming a third dielectric layer on the third electrode; forming a fourth electrode on the third dielectric layer; forming a first metal interconnect to electrically connect the first electrode and the third electrode; forming a second metal interconnect to electrically connect the second electrode to the fourth electrode; forming the MIM capacitor; right sides of the first and third electrodes extend further to the right than right sides of the second and fourth electrodes; The method of claim 14 , wherein the left sides of the second and fourth electrodes extend further to the left than the left sides of the first and third electrodes.

16. 16. The method of claim 15, wherein the third electrode has a stepped surface profile corresponding to a surface profile of the underlying second dielectric layer, and the fourth electrode has a stepped surface profile corresponding to a surface profile of the underlying third dielectric layer.

17. the first metal interconnect is formed to extend vertically through the third dielectric layer, the third electrode, the second dielectric layer, and the first dielectric layer to contact the first electrode; 16. The method of claim 15, wherein the second metal interconnect is formed to extend vertically through the fourth electrode, the third dielectric layer, and the second dielectric layer to contact the second electrode.

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