System and method for partially compiling variational algorithms for quantum computers

Abstract

The quantum computer system of the present disclosure comprises a classical memory storing computer-executable instructions for performing the steps of: (i) receiving a gate circuit representing a quantum program for a variational algorithm that interleaves computation and compilation for each iteration; (ii) identifying a plurality of blocks within the gate circuit, each block of the plurality of blocks including a sub-gate circuit from the gate circuit, leaving one or more remaining sub-gate circuits of the gate circuit outside the plurality of blocks; (iii) pre-compiling each block of the plurality of blocks with a pulse generator program to generate a plurality of pre-compiled blocks, each pre-compiled block including a control pulse configured to execute the associated block on the quantum processor; and (iv) iteratively executing the quantum program on the quantum processor using the pre-compiled blocks as static during execution, recompiling one or more remaining sub-gate circuits on the classical processor during each iteration.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 900,120, entitled "System and method of partial compliation with variational algorithms for quantum computers," filed September 13, 2019, the entire contents of which are incorporated herein by reference.

[0002] (STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT) This invention was made with United States Government support under Grant Nos. CCF1730449 and PHY1818914 awarded by the National Science Foundation. The United States Government has certain rights in this invention.

[0003] (Technical field) The present disclosure relates generally to quantum computing, and more particularly to systems and methods for partial compilation with variational algorithms for quantum computers. [Background technology]

[0004] Recent developments in quantum computing have brought quantum computers closer to solving classically intractable problems. Existing quantum programming languages ​​and compilers use quantum assembly languages ​​consisting of one- and two-qubit ("qubit") gates to prepare and execute primitive operations on quantum computers. Recent advances in hardware and software include devices such as IBM's 50-qubit quantum machine and Google's 72-qubit machine, as well as hybrid classical-quantum algorithms tuned for noisy intermediate-scale quantum ("NISQ") machines, such as quantum approximate optimization algorithms (QAOA) and variational quantum eigensolvers (VQE).

[0005] Some of the most promising algorithms for these NISQ machines are variational algorithms. Traditional variational algorithms in quantum computing combine classical optimization with quantum hardware to evaluate the quality of each candidate solution. Recent work has used gradient ascent pulse engineering (GRAPE) to translate quantum programs into highly optimized machine-controlled pulses, resulting in significant reductions in program execution time. While such optimizations are also commonly important in classical computing, they become much more important in quantum computing, as these machines can only support short execution times before failing.

[0006] However, GRAPE suffers from high compilation latency. For example, running GRAPE control on a circuit with only four qubits can take many minutes, even with modern hardware and graphics processing unit (GPU) acceleration. For longer circuits (e.g., more gates) and larger scale (e.g., more qubits), compilation can take hours or days. In the NISQ era, quantum hardware with hundreds or thousands of qubits is expected. Such high compilation costs are an additional burden for variational algorithms, where computation is interleaved with compilation at run time, resulting in multiple recompilations during execution.

[0007] Therefore, there is a need for a compilation strategy that improves the compilation time of variational algorithms. Summary of the Invention [Means for solving the problem]

[0008] In one aspect, a quantum computer system is provided for compiling and executing instructions on a quantum processor. The quantum computer system of the present disclosure includes a quantum processor including a plurality of qubits. The quantum computer system of the present disclosure also includes a classical memory having a quantum program stored therein. The quantum program defines a plurality of instructions in a source language. The quantum computer system of the present disclosure further includes a classical processor communicatively connected to the classical memory. The classical memory stores computer-executable instructions that, when executed by the classical processor, cause the classical processor to execute. The computer-executable instructions include receiving a gate circuit representing a quantum program for a variational algorithm that interleaves computation and compilation for each iteration. The computer-executable instructions also include identifying a plurality of blocks in the gate circuit. Each block of the plurality of blocks includes a sub-gate circuit from the gate circuit, leaving one or more residual sub-gate circuits of the gate circuit outside the plurality of blocks. The computer-executable instructions also include pre-compiling each block of the plurality of blocks with a pulse generator to generate a plurality of pre-compiled blocks. Each pre-compiled block includes a control pulse configured to execute an associated block on the quantum processor. The computer-executable instructions also include executing the quantum program iteratively on a quantum processor using the precompiled blocks as static during execution, recompiling one or more residual subgate circuits on a classical processor during each iteration.

[0009] In another embodiment, a computer-implemented method for compiling and executing instructions on a quantum computer is provided. The disclosed method is implemented using a classical processor in communication with a classical memory. The disclosed method includes receiving a gate circuit representing a quantum program for a variational algorithm. The disclosed method also includes identifying a plurality of blocks in the gate circuit. Each block of the plurality of blocks includes a sub-gate circuit from the gate circuit, leaving one or more residual sub-gate circuits of the gate circuit outside the plurality of blocks. The disclosed method also includes pre-compiling each block of the plurality of blocks using gradient rising pulse engineering to generate a plurality of pre-compiled blocks. Each pre-compiled block includes a control pulse configured to execute the associated block on the quantum processor. The disclosed method also includes iteratively executing the quantum program on the quantum processor using the pre-compiled blocks as static during execution, recompiling one or more residual sub-gate circuits on the classical processor during each iteration.

[0010] In yet another embodiment, a computer-readable storage medium is provided having stored thereon computer-executable instructions that, when executed by at least one classical processor, cause the processor to execute. The computer-executable instructions include receiving a gating circuit representing a quantum program for a variational algorithm. The computer-executable instructions further include identifying a plurality of blocks in the gating circuit. Each block of the plurality of blocks includes a sub-gate circuit from the gating circuit, leaving one or more residual sub-gate circuits of the gating circuit outside the plurality of blocks. The computer-executable instructions further include pre-compiling each block of the plurality of blocks using gradient rising pulse engineering to generate a plurality of pre-compiled blocks. Each pre-compiled block includes a control pulse configured to execute the associated block on the quantum processor. The computer-executable instructions further include iteratively executing the quantum program on the quantum processor using the pre-compiled blocks as static during execution, recompiling the one or more residual sub-gate circuits on the classical processor during each iteration. [Brief description of the drawings]

[0011] [Figure 1] 1-4C illustrate exemplary embodiments of the methods and systems described herein: Figure 1 illustrates an exemplary quantum computing system for executing a variational quantum program on a quantum computing device. [Diagram 2] FIG. 2 is a component diagram of the compilation engine 114 shown in FIG. [Diagram 3] FIG. 3 is an example of a variational circuit for the variational quantum program shown in FIG. [Figure 4A] FIG. 4A illustrates the results of a blocking analysis (eg, blocking subcircuits that do not depend on θi, or Rx(θi) gates that depend on the parameterization). [Figure 4B]FIG. 4B shows another view of blocking, where for purposes of illustration, the details of the parameterization-independent gates within each fixed block are omitted. [Figure 4C] FIG. 4C illustrates blocking of a parameterized subcircuit that depends only on a single variational parameter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The following detailed description describes example embodiments of the present disclosure, but not by way of limitation. The present disclosure is intended to have general application to quantum computing.

[0013] Existing quantum programming languages ​​and compilers use a quantum assembly language consisting of one-qubit and two-qubit gates. A quantum compiler framework converts this quantum assembly language into control pulses, typically electrical signals that execute a specified computation on a particular quantum computing device. Such quantum programs ("non-variational quantum algorithms") are typically compiled once and then executed on a quantum computing device. Because typical non-variational quantum algorithms are fully specified at compile time, they can be fully optimized by static compilation tools before execution. However, variational algorithms (or "hybrid quantum-classical algorithms") interleave computation and compilation, and therefore require recompilation at runtime (e.g., as the program iterates toward a solution). Each iteration of a variational algorithm depends on the results of the previous iteration. In this way, compilation is interleaved with computation. Even small instances of variational algorithms typically run thousands of iterations, so the compilation latency for each iteration becomes a significant constraint, creating a significant gap from traditional non-variational quantum algorithms. Examples of such variational algorithms include molecular ground state estimation, MAXCUT approximation, and prime factorization. GRAPE compilation of non-variational algorithms is known to outperform gate-based compilation, but GRAPE-based compilation incurs a significant cost in compilation time. For variational algorithms, GRAPE-based compilation can be augmented by iterative recompilation.

[0014] To address these issues, a quantum computer system and associated methods are disclosed herein. The quantum computer system of the present disclosure includes a compilation engine (e.g., running on a classical computing device) configured to prepare and optimize a quantum program for execution on a quantum processor. In some examples, the quantum processor has tens or hundreds of qubits for use in executing the quantum program, and in the future, is expected to have thousands of qubits. The compilation engine is configured to prepare and execute a variational algorithm on the quantum processor using a pre-runtime partial compilation strategy that can improve compilation latency at runtime (e.g., improved compilation efficiency at runtime, reduced compilation time at runtime).

[0015] As used herein, the term "classical" refers to conventional transistor-based computing technology. The term is used to distinguish conventional computing devices or associated hardware, software, algorithms, etc., from "quantum" computers, as appropriate. Quantum computers or associated hardware, software, algorithms, etc., are generally distinguished from classical computing devices in that they rely on the quantum phenomena of quantum mechanics to perform processing operations. Examples of classical computers include conventional personal computers, servers, tablets, smartphones, x86-based processors, random access memory ("RAM") modules, and the like. Examples of quantum computers include IBM's "IBM Q" devices, Google's "Bristlecone" quantum computers, Intel's "Tangle Lake" quantum computers, and D-Wave's "2000Q". The term "classical bit" or "cbit" is used herein to refer to a bit in a classical computer. The term "qubit" is used herein to refer to a quantum bit in a quantum computer.

[0016] 1 illustrates an exemplary quantum computing system 100 for optimizing instructions for execution on a quantum computing device 130. The quantum computing system 100 includes a control computing device 110 configured to prepare (e.g., compile and optimize) a variational quantum program 112 for execution on the quantum computing device 130. The control computing device 110 includes a classical processor 102 (e.g., a central processing unit ("CPU"), an x86-based processor, etc.) configured to execute classical processor instructions, and a classical memory 104 (e.g., random access memory ("RAM"), memory SIMMs, DIMMs, etc., including classical bits of memory). The quantum computing device 130 includes a number of qubits 134 representing a quantum processor 132 that executes the variational quantum program 112. In an exemplary embodiment, the variational quantum program 112 is a variational quantum program that interleaves compilation and computation at run time, and the quantum processor 132 includes 50 or 100 qubits. It should be understood that the present disclosure is contemplated as applicable and beneficial to quantum processors having tens, hundreds, or even more qubits 134.

[0017] The fundamental unit of quantum computing is the quantum bit, or qubit 134. In contrast to a classical bit (cbit), a quantum bit (qubit) can exist in a superposition of logical states, denoted herein as |0〉 and |1〉. A typical quantum state of a qubit is represented as follows:

[0018]

number

[0019] In the formula, α and β are |α| 2 +|β| 2 = 1. When measured in the 0 / 1 basis, the above quantum states are respectively |α| 2 and |β| 2, |0〉 or |1〉 with probability |0〉. The qubits 134 can be visualized as points on a three-dimensional sphere called the Bloch sphere. The qubits 134 can be realized on a variety of quantum information processing (QIP) platforms, including ion traps, quantum dot systems, and in this exemplary embodiment, superconducting circuits. The number of quantum logical states grows exponentially with the number of qubits 134 in the quantum processor 132. For example, a system with three qubits 134 can have eight logical states (|000〉, |001〉, |01〉, |011〉, ..., |111〉). This property is the basis for quantum speedups over classical computation. In other words, an exponential number of correlated logical states can be stored and processed simultaneously by the quantum computer system 100 with a linear number of qubits 134.

[0020] Quantum algorithms can be written in terms of quantum circuits. During quantum compilation, the variational quantum program 112 is first decomposed into a set of one-qubit and two-qubit discrete quantum operations, called logical quantum gates. These quantum gates are represented in matrix form as unitary matrices. A one-qubit gate corresponds to a rotation along a particular axis of the Bloch sphere. In the example of the quantum ISA, the set of one-qubit gates includes rotations along the x-, y-, and z-axes of the Bloch sphere. These gates are referred to herein as R, R, and R, respectively. x Gate, R y Gate, and R z In addition, quantum ISAs may also include Hadamard gates that correspond to rotations about the diagonal x+z axis. One example of a two-qubit logic gate in a quantum ISA is the controlled NOT (CNOT) gate. This CNOT gate flips the state of a target qubit when the control qubit is |1〉 and leaves the state of the target qubit unchanged when the control qubit is |0〉. For example, a CNOT gate can change |10〉 to |11〉 and |11〉 to |10〉, while preserving all other logical states.

[0021] Furthermore, it should be understood that the general logical assembly instructions typically used during the compilation of the variational quantum program 112 are designed without directly considering the variations in the types of physical hardware that may be used. Therefore, there is often a mismatch between the logical instructions and the performance of a particular QIP platform. For example, in some QIP platforms, it may not be clear how to directly implement a CX gate on that particular physical platform. Therefore, the CX gate may be further decomposed into multiple physical gates in a standard gate-based compilation. As other exemplary physical quantum gates for various architectures, for example, in a platform with a Heisenberg interaction Hamiltonian, such as quantum dots, a directly implementable two-qubit physical gate is the √SWAP gate (which performs SWAP when applied twice). In a platform with a ZZ interaction Hamiltonian, such as a superconducting system of Josephson flux qubits or an NMR quantum system, the physical gate is the CPhase gate, which is identical to the CX gate up to the rotation of a single qubit. In platforms with an XY interacting Hamiltonian, such as capacitively coupled Josephson charge qubits (e.g., transmon qubits), the two-qubit physical gate is the iSWAP gate. In ionic platforms with dipole-chain interactions, two common two-qubit physical gates are the geometric phase gate and the XX gate.

[0022] The quantum processor 132 can be continuously driven by external physical operations to any state in the space spanned by the logical states. The physical operations, called control fields, are specific to the underlying system, and the control fields and the properties of the system control a unique time-dependent quantity, called the Hamiltonian. The Hamiltonian determines the evolution path of the quantum state. For example, in a superconducting system such as the exemplary quantum computing device 130, the qubits 134 can be driven to rotate continuously on the Bloch sphere by applying a microwave electrical signal. The speed of rotation of the qubits 134 can be manipulated by varying the strength of the microwave signal. The ability to manipulate the Hamiltonian system in real time allows the quantum computing system 100 to direct the qubits 134 to a desired quantum state through precise control of the associated control fields. Thus, quantum computing can be achieved by constructing a quantum system whose evolved Hamiltonians coincide with a high probability upon the final measurement of the qubits 134. In the context of quantum control, a quantum gate can be viewed as a set of pre-programmed control fields executed on the quantum processor 132.

[0023] In operation, the control computing device 110 executes quantum algorithms and attempts to create quantum circuits that are as efficient as possible. Efficiency can be in terms of circuit width (e.g., number of qubits) and depth (e.g., length of the critical path, or runtime of the circuit). In some embodiments, the compilation engine 114 optimizes various circuits or subcircuits using the IBM Qiskit transpiler, which applies various circuit identities (e.g., aggressive cancellation of CX gates and Hadamard gates). In some embodiments, the compilation engine 114 also performs additional merging of rotate gates (e.g., R x (α) followed by R x If (β) continues, R x (α+β)).

[0024] At the lowest level of hardware, quantum computers are controlled by analog pulses. Thus, quantum compilation translates high-level quantum algorithms down to sequences of control pulses 120. Once a quantum algorithm is decomposed into a quantum circuit consisting of one-qubit and two-qubit gates, gate-based compilation can be performed by concatenating sequences of pulses corresponding to each gate. In particular, a lookup table maps from each gate in a gate set to the sequence of control pulses that execute that gate. Pure gate-based compilation offers the advantage of short pulse compilation times, since the lookup and concatenation of pulses can be accomplished very quickly. Some known methods of compilation for variational algorithms are x (θ) and R z A gate-based approach is used for compilation, using parameterized gates such as (φ). However, a pure gate-based compilation approach prevents gate-spanning pulses from being optimized, since there may be a global pulse for the entire circuit that is shorter and more accurate than the concatenated pulses. The quality of the concatenated pulses is highly dependent on efficient gate decomposition of the quantum algorithm. GRAPE is a compilation strategy that numerically finds the best control pulses required to execute a quantum circuit or subcircuit, following a gradient descent method. In contrast to gate-based approaches, GRAPE is not subject to the limitations imposed by gate decomposition. Instead, GRAPE-based approaches directly search for optimal control pulses for the entire input circuit. Some embodiments described herein utilize GRAPE for part of the compilation, as described in more detail below.

[0025] In this exemplary embodiment, the control computing device 110 includes a compilation engine 114. The compilation engine 114 is configured, during operation, to compile (e.g., from source code) the variational quantum program 112 into an optimized physical schedule 116. The quantum computing device 130 is a superconducting device, and the signal generator 118 is an arbitrary waveform generator ("AWG") configured to execute optimized control pulses 120 on the quantum processor 132 (e.g., via microwave pulses transmitted to the qubits 134, the axis of rotation being determined by quadrature amplitude modulation of the signal, and the angle of rotation being determined by the pulse length of the signal). The optimized physical schedule 116 represents a set of control instructions and associated schedules that, when transmitted as optimized control pulses 120 (e.g., pre-programmed control fields) from the signal generator 118 to the quantum computing device 130, cause the quantum computing device 130 to execute the variational quantum program 112 and produce an execution result 140. In an exemplary embodiment, the iterative execution results 140 are sent back to the compilation engine 114, which performs additional compilation to create a new optimized physics schedule for the next iteration. It should be understood that other quantum computing architectures may have different supporting hardware.

[0026] In some exemplary embodiments, the variational quantum program 112 may be a variational quantum eigensolver (VQE). The quantum computer system 100 may use VQE to determine the ground state energy of a molecule. This task is typically exponentially difficult on classical computers, but can be solved efficiently on a quantum computer. Estimating the ground state of a molecule has important applications in chemistry, such as determining reaction rates and molecular structure. A conventional quantum algorithm for solving this problem is the quantum phase estimation (QPE) algorithm. Note that for a target precision ε, QPE generates quantum circuits of depth O(1 / ε), while the VQE algorithm solves the O(1 / ε) problem for a circuit of depth O(1). 2) iterations. The latter assumes that the greater the circuit depth, the more likely errors are to occur at the end of the circuit, and therefore the fidelity requirements for qubit and gate operations are relaxed. At a high level, VQE can be conceptualized as an iterative guess-check algorithm, where the compilation engine 114 recompiles at each iteration for the next guess based on the results of the previous run. The check phase involves preparation of the quantum state corresponding to the guess. This preparation phase is done in polynomial time on a quantum computer, but is exponentially costly on a classical computer (e.g., 2 N due to the scaling of the state vector of

[0027] In some exemplary embodiments, the variational quantum program 112 may be a quantum approximate optimization algorithm (QAOA). The quantum computer system 100 may use QAOA to generate approximate solutions to problems that are difficult to solve exactly. QAOA may be understood as an alternating pattern of mixing and cost optimization steps. In each mixing step, QAOA applies diffusion to explore all possible states in the quantum superposition. In each cost optimization step, a bias is applied to increase the size of the quantum state that minimizes the cost function. Then, by measuring, a near-optimal approximate solution can be obtained with high probability. Similar to VOE, QAOA is an iterative guess-check algorithm. The number of alternating mixing and cost optimization rounds is p. For QAOA, the guess corresponds to the size of the mixing between iteration 1≦i≦p and the size of the cost optimization between iteration 1≦i≦p. Thus, the number of parameters of the QAOA circuit is 2p, a scalar for the size of the mixing and a scalar for the size of the cost optimization for each of the p rounds. Even for small p, QAOA has shown results that are competitive with classical approximation methods. For example, for p=1, QAOA applied to the NP-hard MAX-CUT problem achieves a size cut that is at least 69% of the optimal cut size. For p=5, simulations demonstrate that QAOA achieves average parity with the best-known classical algorithm, Goemans-Williamson, for 10-node graphs. For large p, QAOA outperforms classical approximation algorithms even to the worst-case limit. QAOA is particularly interesting in the near future because recent work has shown it to be computationally universal. Furthermore, QAOA has experimentally shown immunity to noise. For at least these reasons, QAOA is a strong candidate for quantum supremacy, the use of quantum computers to solve classically infeasible problems.

[0028] Figure 2 is a component diagram of the compilation engine 114 shown in Figure 1. The modules shown in Figure 2 pre-compile the variational quantum program 112 and prepare the optimized physical schedule 116 for execution. In an exemplary embodiment, the compilation engine 114 includes a partial compilation blocking module 210, a parameter monotonicity blocking module 212, a hyperparameter optimization module 214, a GRAPE compilation module 216, a pre-compilation module 218, and a runtime compilation module 220.

[0029] The partial compilation blocking module 210, in an exemplary embodiment, is configured to analyze a variational circuit of the variational quantum program 112 shown in FIG. 1 and identify blocks of parameter-independent gates. Parameter-independent blocking is described below with reference to FIG. 4A and FIG. 4B. The parameter monotonicity blocking module 212 is configured to analyze the variational circuit and generate parameter monotonic blocks of gates. Parametric monotonicity blocking is described below with reference to FIG. 4C. The hyperparameter optimization module 214 is configured to determine a set of hyperparameters for the parameter monotonicity blocks. Hyperparameter optimization is described below with reference to FIG. 4C.

[0030] In an exemplary embodiment, the GRAPE compilation module 216 is configured to generate control pulses for various circuits and subcircuits, such as blocks of parameter independent gates identified by the partial compilation blocking module 210 or parameter monotonicity blocks identified by the parameter monotonicity blocking module 212. The pre-compilation module 218 is configured to invoke the partial compilation blocking module 210, the parameter monotonicity blocking module 212, the hyperparameter optimization module 214, and the GRAPE compilation module 216 during compilation (e.g., before runtime) to prestage various aspects of the algorithms described herein. The runtime compilation module 220 is configured to perform recompilation of various subcircuits or reassembly of components of the circuit during runtime.

[0031] Figure 3 is an example of a variational circuit 300 of the variational quantum program 112 shown in Figure 1. In the example shown, the variational circuit 300 is decomposed into various one-input and two-input quantum gates for the six-qubit quantum processor 132. The basic unit of quantum computation is the qubit (e.g., qubit 134). A qubit has two basis states, which can be represented by a state vector as follows:

[0032]

number

[0033] Unlike classical bits, the state of a qubit can be a superposition of both |0〉 and |1〉. Specifically, the valid qubit state space is |α| 2 +|β| 2 = 1. When we measure a qubit, its quantum state collapses into a state where |0〉 or |1〉 occurs with probability α 2 and probability β 2 It is measured in.

[0034] A two-qubit system has four basis states.

[0035]

number

[0036] Any two-qubit state can be expressed as a superposition α|00〉+β|01〉+γ|10〉+δ|11〉, which means that |α| 2 +|β| 2 +|γ| 2 +|δ| 2 = 1. More generally, an N qubit system is normalized to 2 N Therefore, to describe the state of a general N-qubit system, we use a 2 N This exponential scaling raises both the difficulty of classically simulating quantum systems and the possibility that quantum computers will exponentially outperform classical computers in certain applications.

[0037] In Figure 3, each of six horizontal lines 302 (not individually numbered) represents a particular qubit 134 of quantum processor 132. Figure 3 also shows several one-qubit and two-qubit gates that operate on the qubits. Quantum gates can be represented as square matrices, and the operation of the gate is to left-multiply the state vector of the qubit by the matrix of gates. Since the quantum states are normalized by the measurement probabilities, these matrices are 2 The norm is preserved. This set of corresponding matrices is unitary (orthogonal). The unitary matrices of two important 1-qubit gates are expressed as follows:

[0038]

number

[0039] At θ=π, R xThe (π) gate has the following matrix which functions as a NOT gate (e.g., left multiplication with it flips the |0> and |1> states):

[0040]

number

[0041] This bit-flip gate is referred to herein as an "X" gate (not shown). Similarly, at φ=π, the Rz(π) gate has the following matrix, which multiplies the amplitude of |1〉 by -1:

[0042]

number

[0043] This type of gate is specific to the quantum setting where the amplitude is negative (e.g., complex numbers). This phase-flip gate is referred to herein as a "Z" gate 308.

[0044] The "CX" gate 306 is a controlled NOT (or CNOT) gate represented as follows:

[0045]

number

[0046] CX gate 306 applies an operation controlled by a first input (e.g., the first qubit, identified in FIG. 3 as a shaded dot on the qubit connected to CX gate 306 by control line 312). If the first input is |0〉, then CX gate 306 has no effect. If the first input is |1〉, then CX gate 306 applies an operation controlled by X=R x(π) to the second qubit. The CX gate 306 is an entangling gate, meaning that its effect cannot be decomposed into independent gates acting separately on the two qubits. An important result in quantum computing has shown that the set of all one-qubit gates and a single entangling gate is sufficient for universality. R x (θ) and R z The gate in (φ) spans the set of all one-qubit gates, so {R x (θ), R z (φ),CX} is a set of universal gates.

[0047] During operation, quantum computer system 100 prepares a quantum algorithm for execution, maximizing the efficiency of the quantum circuit in various respects (e.g., in terms of "circuit width" or number of qubits, and "depth" or length of the critical path). For example, quantum circuit 300 may be optimized by iteratively applying gate identities that reduce the resources consumed by circuit 300. In some embodiments, circuit 300 or various subcircuits are transpiled using the IBM Qiskit transpiler that applies various circuit identities (e.g., aggressive cancellation of CX gates and Hadamard gates), as well as customized compiler passes (e.g., R x (α) followed by R x (followed by β) can be used to optimize the

[0048] In typical gate-based compilation, once a quantum program is decomposed into a quantum circuit, such as circuit 300 shown herein, the gate-based compilation simply concatenates sequences of pulses corresponding to each gate (e.g., using a lookup table that maps each gate to a sequence of control pulses that execute that gate). An advantage of the gate-based approach is that pulse lookup and concatenation can be accomplished very quickly, resulting in short pulse compilation times. However, as previously discussed, gate-based compilation prevents pulses that cross gates from being optimized.

[0049] In a typical GRAPE compilation (referred to herein as a "full" GRAPE compilation), GRAPE numerically determines, according to gradient descent, efficient control pulse sequences required to run the entire quantum circuit 300, represented here as circuit 320. However, as previously mentioned, this compilation is computationally expensive when performed on the entire circuit 320, and the computational cost is exacerbated for variational algorithms where the compilation is performed again at each iteration.

[0050] In an exemplary embodiment, quantum computer system 100 addresses the shortcomings of gate-based compilation and full GRAPE compilation. For example, in the "strict partial compilation" and "soft partial compilation" methods described herein, quantum computer system 100 can analyze circuit 300 to determine blocks of fixed gates that do not change between iterations. These fixed blocks can be pre-compiled and optimized separately (e.g., using GRAPE, referred to herein as "partial" compilation), and then reused across various iterations. These methods are described in more detail below.

[0051] 4A and 4B show an example of a blocking map 400 of the circuit 300 identified by the compilation engine 114 prior to execution. In exemplary embodiments of the strict and flexible partial compilation methods, the compilation engine 114 executes the blocks of the circuit 300 prior to execution (e.g., at compile time). Many variational algorithms include a set of gates that do not change between iterations. More specifically, the compilation engine 114 executes the blocks of the circuit 300 prior to execution (e.g., at compile time) based on the variational parameters θ i We identify a block (or simply a “fixed block”) 402 (e.g., one or more gates) of gates (e.g., parameterized independent gates or subcircuits) that do not depend on the variational parameters θ. All other variational parameterized dependent gates (or subcircuits) 404 are excluded from the fixed block 402 but are still part of the circuit. i may be specific to the type of variational algorithm. i may be a relatively small (e.g. polynomial) number of parameters in the Ansatz that represent different fundamental meanings, or may simply add degrees of freedom that allow the exploration of larger states. In QAOA, the variational parameters θ i may correspond to the magnitude of exploration versus exploitation (EVA) performed in each of the p rounds. In VQE, the variation parameter θ i can be written as capturing the deviation from a standard estimate (e.g., Hartree-Fock) of the ground state of a molecule.

[0052] FIG. 4A shows the results of a blocking analysis (e.g., θ i A subcircuit that does not depend on, or a parameterization-dependent R x (θ i ) blocking gates). Figure 4B shows another view of blocking, where for purposes of illustration, the details of the parameterization independent gates within each fixed block 402 are omitted.

[0053] In strict partial compilation, once the compilation engine 114 has performed the blocking and generated the illustrated blocking map 400, the compilation engine 114 pre-compiles each of the fixed blocks 402. In an exemplary embodiment, the compilation engine 114 uses GRAPE on each fixed block 402 (e.g., as a subcircuit) to pre-compute the shortest pulse sequence required to execute each fixed subcircuit. These static pre-compiled pulse sequences can be defined as micro-instructions in a low level assembly such as eQASM. The compilation engine 114 stores the pre-compiled fixed block pulse sequences in a fixed block lookup table for use during run-time. Additionally, the compilation engine 114 pre-compiles the parameterized dependent portions (e.g., parameterized dependent gates 404, R z (θ i ) gates). More specifically, the compilation engine 114 generates non-fixed lookup tables for R z (θ i ) gate pulse, θ i = 90, 45, 22.5, 11.25, 5.625, etc. (in degrees, e.g., divided by 2). Then, at run time, the compilation engine 114 precompiles x For angles summed up to, any R can be calculated by summing pulses stored from a non-fixed lookup table. z (θ x ) can be generated. In this way, a pulse sequence for any parameterization can be generated by combining a pre-calculated pulse sequence for the fixed blocks 402 from the fixed block lookup table and a parameterization-dependent portion (e.g., parameterization-dependent gates 404, R z (θ i ) gate) and a control pulse for θ i The optimal pulse for can be solved analytically (e.g., R z(For a simple gate of a single qubit such as . Because each fixed block 402 was compiled by GRAPE, the resulting pulse duration is shorter than if the fixed blocks 402 had been compiled by gate-based compilation. Thus, strict partial compilation achieves faster pulses compared to gate-based compilation while minimizing the increase in compilation latency.

[0054] FIG. 4C illustrates the blocking of parameterized subcircuits that depend only on a single variational parameter. Flexible partial compilation allows for the blocking of slightly parameterized (e.g., θ i In an exemplary embodiment, the compilation engine 114 creates a subcircuit that is a set of consecutive fixed blocks with the same variational parameters θ i , and all of the parameter-dependent gates or subcircuits in the θ i For example, block 410A depends only on θ1, block 410B depends only on θ2, and block 410C depends only on θ3.

[0055] In this embodiment, for example, in the VQE circuit and the QAOA circuit, θ i Once the dependent gate appears, θ i The occurrence of the dependent gate is monotonic in i, and the subsequent parameterized dependent gates are θ for j ≥ i. j Note that, as a result, θ iFor example, the order of angles of parameterized dependent gates may be [θ1, θ1, θ2, θ3] or [θ1, θ2, θ3, θ1]. The parameter monotonicity of VQE / UCCSD and QAOA arises because their circuit configurations sequentially apply the circuit corresponding to each parameter only once. For example, in QAOA, each parameter corresponds to the magnitude of the mixing or cost optimization during the ith round. Once the corresponding mixing or cost optimization has been applied, the circuit becomes independent of that parameter. The circuit configuration or optimization can be applied to the individual θ i The dependent gate is -θ i or θ i Since the variational circuit is transformed into a gate parameterized by / 2, the parametric monotonicity is not immediately apparent from visual inspection of the variational circuit.

[0056] In an exemplary embodiment, these potential dependencies are tracked and resolved by tagging the dependent parameters during the variational circuit construction phase. More specifically, the new θ i Each time a is created, its θ i is added to the list of independent parameters to be tracked. j is added to the list of independent parameters to be tracked. i Subsequent operations on the effective angle θ i From θ i / 2 , θ i / 3 θ i References to these known θ i is not a new angle. For example, assume a quantum circuit with two parameters θ1 and θ2. After circuit optimization, R z (θ 1 / 2 ) gate, where θ1=10 degrees and θ2=30 degrees. The quantum circuit has three angles: 5 degrees, 10 degrees, and 30 degrees. However, the 5 degree rotation is still tagged as dependent on θ1, so the 5 degree rotation falls into the same parameter-dependent block (e.g., dependent on θ1) as the 10 degree rotation.

[0057] Once the compilation engine 114 analyzes the circuit 300 and performs parameter monotonicity blocking, the compilation engine 114 can perform angle approximation or hyper-parameter optimization based on the parameter monotonicity blocking.

[0058] In the angle approximation method, the compilation engine 114 precompiles circuits for various angles (e.g., 0, 15, 30, 45, ..., 345 degrees) for each of the parameter monotonicity blocks 410. At run time, the precompiled circuit closest to the current angle is used as the initial guess (e.g., seed). The solver converges to the actual solution faster with a more accurate guess. As a result, the pulse sequence is closer and converges faster when the angles are closer. In some embodiments, the compilation engine 114 can precompile circuits for various sets of two or more angles. For example, the compilation engine 114 can precompile circuits for various angle pairs such as (0,0), (0,15), (0,30), ..., (0,345), (15,0), (15,15), (15,30), ..., (345,345).

[0059] In the hyperparameter optimization method, the compilation engine 114 pre-computes hyperparameters for each parameter monotonicity block 410 that can be used at run time to make each block 410 converge to an optimal pulse sequence faster. In GRAPE, the optimal control pulse is one that minimizes a set of cost functions corresponding to the control amplitude, the infidelity of the target state, and the evolution time. To obtain the optimal control pulse, the GRAPE algorithm manipulates a set of time-discrete control fields acting on the quantum system. The gradients of the cost function that is minimized with respect to the control fields can be analytically calculated. These gradients are used to update the control fields in optimizers such as ADAM and L-BFGS-B. In contrast to the control fields, which are parameters manipulated by GRAPE, these optimizers have their own parameters, such as the learning rate and the learning rate decay. These parameters are called "hyperparameters" because they are set before the start of the learning process. Since they are the inputs to the learning process, there is no closed-form expression for the hyperparameters and the cost function that the learning model minimizes. In an exemplary embodiment, the GRAPEADAM optimizer employs hyper-parameter optimization to achieve faster convergence to a desired error rate and significantly reduce compilation delay compared to the baseline.

[0060] Thus, in an exemplary embodiment, the compilation engine 114 pre-computes hyper-parameter configurations for each of the single-angle parameterized subcircuits (e.g., each block 410) and uses those hyper-parameter configurations during each compilation. For each iteration of the variational algorithm, i Although the arguments of the dependency gates vary, the same hyperparameters are specified to the GRAPE optimizer, maintaining the same reduced compilation latency.

[0061] As will be appreciated based on the description herein above, the above-described embodiments of the present disclosure may be implemented using computer programming or engineering techniques, including computer software, firmware, hardware, or any combination or subset thereof, the technical effect of which is to compile and optimize a variational quantum program for execution on a quantum processor. Any such program having computer readable code means may be embodied or provided by one or more computer readable media, thereby producing a computer program product (i.e., an article of manufacture) in accordance with the described embodiments of the present disclosure. The computer readable medium may be, for example, but not limited to, a fixed (hard) drive, a diskette, an optical disk, a magnetic tape, a semiconductor memory such as a read-only memory (ROM), and / or any transmission / reception medium, such as the Internet or other communications network or link. An article of manufacture including the computer code may be produced and / or used by executing the code directly from one medium, by copying the code from one medium to another medium, or by transmitting the code over a network.

[0062] In some embodiments, a quantum computer system is provided for compiling and executing instructions on a quantum processor. The quantum computer system of the present disclosure includes a quantum processor including a plurality of qubits, a classical memory storing a quantum program defining a plurality of instructions in a source language, and the classical processor communicatively coupled to the classical memory. The classical memory stores computer-executable instructions that, when executed by the classical processor, cause the classical processor to execute. The computer executable instructions include: (i) receiving a gate circuit representing a quantum program for a variational algorithm that interleaves computation and compilation for each iteration; (ii) identifying a plurality of blocks within the gate circuit, each block of the plurality of blocks including a sub-gate circuit from the gate circuit, leaving one or more residual sub-gate circuits of the gate circuit outside the plurality of blocks; (iii) pre-compiling each block of the plurality of blocks with a pulse generator to generate a plurality of pre-compiled blocks, each pre-compiled block including a control pulse configured to execute an associated block on a quantum processor; and (iv) iteratively executing the quantum program on the quantum processor using the pre-compiled blocks as static during execution, recompiling the one or more residual sub-gate circuits on the classical processor during each iteration.

[0063] In some embodiments, the step of iteratively executing the quantum program includes, at each iteration, (a) compiling each circuit of one or more residual subgate circuits to generate a plurality of compiled residual subgate circuits; (b) concatenating the plurality of precompiled blocks and the plurality of compiled residual subgate circuits based on their relative positions in the gating circuit, thereby generating a control pulse for the current iteration; and (c) executing the control pulse for the current iteration on the quantum processor. In some embodiments, the step of compiling each circuit of one or more residual subgate circuits to generate a plurality of compiled residual subgate circuits includes compiling a first residual subgate circuit using gradient rising pulse engineering. In some embodiments, the step of identifying a plurality of blocks in the gating circuit includes identifying blocks in the gating circuit based on variational parameter independence. In some embodiments, the step of identifying blocks in the gating circuit further includes blocking all variational parameter independent gates between two variational parameter dependent gates. In some embodiments, the computer-executable instructions further include causing a classical processor to identify a plurality of parametric monotonic blocks based on sub-gate circuits in the gating circuit that depend on at least one variational parameter of the variational algorithm. In some embodiments, the computer-executable instructions further include causing a classical processor to pre-compute hyper-parameter configurations for each block of the plurality of parametric monotonic blocks for use during the iterative execution.

[0064] In some embodiments, a computer-implemented method for compiling and executing instructions on a quantum computer is provided. The disclosed method is implemented using a classical processor in communication with a classical memory. The disclosed method includes: (i) receiving a gate circuit representing a quantum program for a variational algorithm; (ii) identifying a plurality of blocks in the gate circuit, each block of the plurality of blocks including a sub-gate circuit from the gate circuit, leaving one or more residual sub-gate circuits of the gate circuit outside the plurality of blocks; (iii) pre-compiling each block of the plurality of blocks using gradient rising pulse engineering to generate a plurality of pre-compiled blocks, each pre-compiled block including a control pulse configured to execute the associated block on the quantum processor; and (iv) iteratively executing the quantum program on the quantum processor using the pre-compiled blocks as static during execution, recompiling one or more residual sub-gate circuits on the classical processor during each iteration.

[0065] In some embodiments, the step of iteratively executing the quantum program includes, at each iteration, (a) compiling each circuit of one or more residual subgate circuits to generate a plurality of compiled residual subgate circuits; (b) concatenating the plurality of precompiled blocks and the plurality of compiled residual subgate circuits based on their relative positions in the gating circuit, thereby generating a control pulse for the current iteration; and (c) executing the control pulse for the current iteration on the quantum processor. In some embodiments, the step of compiling each circuit of one or more residual subgate circuits to generate a plurality of compiled residual subgate circuits includes compiling a first residual subgate circuit using gradient rising pulse engineering. In some embodiments, the step of identifying a plurality of blocks in the gating circuit includes identifying blocks in the gating circuit based on variational parameter independence. In some embodiments, the step of identifying blocks in the gating circuit further includes blocking all variational parameter independent gates between two variational parameter dependent gates. In some embodiments, the disclosed method further includes identifying a plurality of parametric monotonic blocks based on sub-gate circuits within the gating circuit that depend on at least one variational parameter of the variational algorithm. In some embodiments, the disclosed method further includes pre-computing hyper-parameter configurations for each block of the plurality of parametric monotonic blocks for use during iterative execution.

[0066] In some embodiments, a computer-readable storage medium is provided having stored thereon computer-executable instructions that, when executed by at least one classical processor, cause the processor to execute a program comprising: (i) receiving a gating circuit representing a quantum program for a variational algorithm, (ii) identifying a plurality of blocks within the gating circuit, each block of the plurality of blocks including a sub-gate circuit from the gating circuit, leaving one or more residual sub-gate circuits of the gating circuit outside the plurality of blocks, (iii) pre-compiling each block of the plurality of blocks using gradient rising pulse engineering to generate a plurality of pre-compiled blocks, each pre-compiled block including a control pulse configured to execute the associated block on the quantum processor, and (iv) iteratively executing the quantum program on the quantum processor using the pre-compiled blocks as static during execution, recompiling the one or more residual sub-gate circuits on the classical processor during each iteration.

[0067] In some embodiments, the step of iteratively executing the quantum program includes, at each iteration, (a) compiling each circuit of one or more residual subgate circuits to generate a plurality of compiled residual subgate circuits; (b) concatenating the plurality of precompiled blocks and the plurality of compiled residual subgate circuits based on their relative positions in the gating circuit, thereby generating a control pulse for the current iteration; and (c) executing the control pulse for the current iteration on the quantum processor. In some embodiments, the step of compiling each circuit of one or more residual subgate circuits to generate a plurality of compiled residual subgate circuits includes compiling a first residual subgate circuit using gradient rising pulse engineering. In some embodiments, the step of identifying a plurality of blocks in the gating circuit includes identifying blocks in the gating circuit based on variational parameter independence. In some embodiments, the computer executable instructions further include causing the classical processor to identify a plurality of parameter monotonic blocks based on subgate circuits in the gating circuit that depend on at least one variational parameter of the variational algorithm. In some embodiments, the computer-executable instructions further include causing the classical processor to pre-compute hyper-parameter configurations for each block of the plurality of parameter monotonicity blocks for use during the iterative execution.

[0068] These conventional computer programs (also referred to as "programs", "software", "software applications", "applications", "code") include machine instructions for conventional programmable processors and may be implemented by high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device (e.g., magnetic disks, optical disks, memory, programmable logic devices (PLDs)) used to provide machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. However, the terms "machine-readable medium" and "computer-readable medium" do not include transitory signals. The term "machine-readable signal" refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0069] This specification uses examples to disclose the invention including the best mode and to enable any person skilled in the art to practice the invention, including making and using any device or system, and practicing any method incorporating the same. The patentable scope of the invention is defined by the claims, and may include alternative embodiments that occur to those skilled in the art. Such alternative embodiments are within the scope of the claims if they include elements that do not differ from the literal language of each claim, or if they include equivalent elements that do not differ substantially from the literal language of each claim.

Claims

1. A quantum computer system for compiling instructions and executing the compiled instructions on a quantum processor, comprising: a quantum processor including a plurality of qubits; a classical memory that stores a quantum program, the quantum program defining a number of instructions in a source language; a classical processor communicatively connected to the classical memory; the classical memory stores computer-executable instructions that, when executed by the classical processor, cause the classical processor to execute; The computer executable instructions include: receiving a gate circuit representing said quantum program for a variational algorithm that interleaves computation and compilation for each iteration; identifying a plurality of blocks within the gating circuit, each block of the plurality of blocks including a sub-gate circuit from the gating circuit, leaving one or more remaining sub-gate circuits of the gating circuit outside of the plurality of blocks; pre-compiling each block of the plurality of blocks with a pulse generator to generate a plurality of pre-compiled blocks, each pre-compiled block including a control pulse configured to execute an associated block on the quantum processor; iteratively executing the quantum program on the quantum processor using the precompiled blocks as static during execution, recompiling the one or more remainder subgate circuits on the classical processor during each iteration; Including, the system.

2. 2. The quantum computer system of claim 1, The step of repeatedly executing the quantum program includes: During each iteration, compiling each of the one or more remainder sub-gate circuits to generate a plurality of compiled remainder sub-gate circuits; linking the precompiled blocks and the compiled remainder sub-gating circuits based on their relative positions within the gating circuit, thereby generating control pulses for a current iteration; executing, on the quantum processor, the control pulse for the current iteration.

3. 3. The quantum computer system of claim 2, said step of compiling each of said one or more remainder sub-gate circuits to generate a plurality of compiled remainder sub-gate circuits comprising: The system includes compiling a first remainder sub-gate circuit using ramp-up pulse engineering.

4. A quantum computer system according to any one of claims 1 to 3, The step of identifying a plurality of blocks within the gate circuit comprises: The system includes identifying blocks in the gating circuit based on variational parameter independence.

5. 5. The quantum computer system of claim 4, The system, wherein the step of identifying blocks in the gate circuit further comprises the step of blocking all variational parameter independent gates between two variational parameter dependent gates.

6. A quantum computer system according to any one of claims 1 to 5, The computer-executable instructions further include causing the classical processor to identify a plurality of parametric monotonic blocks based on sub-gate circuits within the gating circuit that are dependent on at least one variational parameter of the variational algorithm.

7. 7. The quantum computer system of claim 6, The computer-executable instructions further include causing the classical processor to pre-compute hyper-parameter configurations for each block of the plurality of parametric monotonicity blocks for use during iterative execution.

8. A method of compiling instructions and executing the compiled instructions on a quantum processor, comprising the steps of: The method is implemented using a classical processor in communication with a classical memory; The method comprises: receiving a gate circuit representing a quantum program for a variational algorithm; identifying a plurality of blocks within the gating circuit, each block of the plurality of blocks including a sub-gate circuit from the gating circuit, leaving one or more remaining sub-gate circuits of the gating circuit outside of the plurality of blocks; pre-compiling each block of the plurality of blocks using gradient rising pulse engineering to generate a plurality of pre-compiled blocks, each pre-compiled block including a control pulse configured to execute an associated block on a quantum processor; iteratively executing the quantum program on the quantum processor using the precompiled blocks as static during execution, recompiling the one or more remainder subgate circuits on the classical processor during each iteration; A method comprising:

9. 9. The method of claim 8, The step of repeatedly executing the quantum program includes: During each iteration, compiling each of the one or more remainder sub-gate circuits to generate a plurality of compiled remainder sub-gate circuits; linking the precompiled blocks and the compiled remainder sub-gating circuits based on their relative positions within the gating circuit, thereby generating control pulses for a current iteration; executing, on the quantum processor, the control pulse for the current iteration.

10. 10. The method of claim 9, said step of compiling each of said one or more remainder sub-gate circuits to generate a plurality of compiled remainder sub-gate circuits comprising: The method includes compiling a first remainder sub-gate circuit using ramp-up pulse engineering.

11. The method according to any one of claims 8 to 10, The step of identifying a plurality of blocks within the gate circuit comprises: The method includes identifying blocks in the gating circuit based on variational parameter independence.

12. 12. The method of claim 11, The method, wherein the step of identifying blocks in the gate circuit further comprises the step of blocking all variational parameter independent gates between two variational parameter dependent gates.

13. A method according to any one of claims 8 to 12, comprising: The method further includes identifying a plurality of parametric monotonic blocks based on sub-gating circuits within the gating circuit that are dependent on at least one variational parameter of the variational algorithm.

14. 14. The method of claim 13, The method further comprising the step of pre-computing hyper-parameter configurations for each block of the plurality of parameter monotonicity blocks for use during iterative execution.

15. A non-transitory computer-readable medium storing computer-executable instructions that, when executed by at least one classical processor, cause the processor to execute the The computer executable instructions include: receiving a gate circuit representing a quantum program for a variational algorithm; identifying a plurality of blocks within the gating circuit, each block of the plurality of blocks including a sub-gate circuit from the gating circuit, leaving one or more remaining sub-gate circuits of the gating circuit outside of the plurality of blocks; pre-compiling each block of the plurality of blocks using gradient rising pulse engineering to generate a plurality of pre-compiled blocks, each pre-compiled block including a control pulse configured to execute an associated block on a quantum processor; iteratively executing the quantum program on the quantum processor using the precompiled blocks as static during execution, recompiling the one or more remainder subgate circuits on the classical processor during each iteration; A non-transitory computer readable medium comprising:

16. 16. The non-transitory computer readable medium of claim 15, The step of repeatedly executing the quantum program includes: During each iteration, compiling each of the one or more remainder sub-gate circuits to generate a plurality of compiled remainder sub-gate circuits; linking the precompiled blocks and the compiled remainder sub-gating circuits based on their relative positions within the gating circuit, thereby generating control pulses for a current iteration; and executing, on the quantum processor, the control pulse for the current iteration.

17. 17. The non-transitory computer readable medium of claim 16, said step of compiling each of said one or more remainder sub-gate circuits to generate a plurality of compiled remainder sub-gate circuits comprising:

11. A non-transitory computer readable medium comprising compiling a first remainder sub-gate circuit using gradient rising pulse engineering.

18. A non-transitory computer readable medium according to any one of claims 15 to 17, comprising: The step of identifying a plurality of blocks within the gate circuit comprises:

11. A non-transitory computer readable medium comprising identifying blocks in the gating circuit based on variational parameter independence.

19. A non-transitory computer readable medium according to any one of claims 15 to 18, comprising: The non-transitory computer-readable medium, wherein the computer-executable instructions further include causing the classical processor to identify a plurality of parametric monotonic blocks based on sub-gate circuits within the gating circuit that are dependent on at least one variational parameter of the variational algorithm.

20. 20. The non-transitory computer readable medium of claim 19, The non-transitory computer-readable medium, wherein the computer-executable instructions further include causing the classical processor to pre-compute hyper-parameter configurations for each block of the plurality of parametric monotonicity blocks for use during iterative execution.

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