METHOD FOR MANUFACTURING A WAFER LAYER AND SUPPORT ELEMENT - Patent application

Abstract

The present invention relates to a method for producing a wafer layer, comprising the following method steps: A. providing a support element; B. porosifying the support element to create a separation layer on at least one surface; C. depositing a wafer layer on the separation layer of the support element using an epitaxy method; and D. peeling the wafer layer off the support element, wherein method steps B to D are repeated at least once, preferably several times, using the support element. The present invention is characterized in that method step A comprises the further method steps: A1. providing a support substrate; and A2. depositing a seed layer on at least one surface and at least one side of the support substrate using an epitaxy method to produce the support element. The present invention further relates to support elements and intermediate products for producing wafer layers.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a wafer layer according to the preamble of claim 1 and to a support element for manufacturing a wafer layer according to claim 12. [Background technology]

[0002] Large-area electronic components, such as large-area light-emitting devices or large-area photovoltaic cells, or mass-produced products, such as semiconductor diodes, require electronically high-quality and low-cost semiconductor wafers, since the material cost of these devices accounts for a large proportion of the overall product cost. In semiconductor wafer production, a method is known in which semiconductor wafers are produced from silicon blocks (ingots) by sawing. This produces high-value, especially monocrystalline, semiconductor wafers. However, the production costs are high and material losses occur during the sawing process of the silicon blocks.

[0003] Therefore, an alternative method has been developed in which a wafer layer is deposited on a support element and then peeled off from the support element, resulting in a semiconductor wafer for fabricating electronic devices.

[0004] In the prior art, a method is known in which a porous separation layer is formed on a partial surface of a support substrate, after which a wafer layer is deposited on the support substrate in an epitaxial process. To separate the wafer layer from the support substrate, a laser beam is used to separate and cut the wafer layer, which cuts completely through the semiconductor layer and at least partially into the separation layer or into the support substrate.

[0005] However, it has proven to be a drawback that in the edge regions of the support substrate parts of the wafer layer remain on the support substrate and are difficult to remove.Moreover, the separation cut also damages the support substrate or the separation layer, so that in many cases the support substrate cannot be reused for the production of further wafer layers or has limited reusability despite the need for expensive conditioning.

[0006] An optimization of a known method for producing semiconductor layers is known, for example, from DE 10 2015 118 042 A1, in which a separation layer is formed over at least one processing surface of the support substrate before the application of a wafer layer to the support substrate, and a wafer layer is applied onto the processing surface and onto at least one edge side of the support substrate in an overlapping manner, the overlapping areas of the wafer layer being removed when the wafer layer is separated from the support substrate.

[0007] The overlapping deposition causes the wafer layer to be completely peeled off from the separation layer or the support substrate. In order to increase the reusability of the support substrate, it is important that no residue of the wafer layer remains on the support substrate after peeling. To achieve this, the overlapping area of ​​the support substrate must also be trimmed during separation, by removing a few micrometers, resulting in a reduction in the lateral dimensions of the support substrate each time it is used. If the support substrate falls below a minimum dimension, it cannot be used as a support substrate for the manufacture of further wafer layers.

[0008] Industrial applications require cost reduction during wafer layer manufacturing, especially the reusability of the supporting substrate. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] DE 102015118042 Summary of the Invention [Problem to be solved by the invention]

[0010] It is therefore an object of the present invention to increase the reusability of the support substrate and reduce the manufacturing costs of the wafer layer.

[0011] It is a further object of the present invention to further improve the quality in the production of wafer layers, in particular to reduce errors caused by the support substrate or the separating layer. [Means for solving the problem]

[0012] This and further objects are achieved by a method for producing a wafer layer according to claim 1, a support element for producing a wafer layer according to claim 12 and an intermediate product according to claim 16. Advantageous embodiments of the method are as set forth in claims 2 to 11. Advantageous embodiments of the support element for producing a wafer layer are as set forth in claims 13 to 15.

[0013] The method for producing a semiconductor layer according to the invention comprises the following method steps.

[0014] A first method step A comprises providing a support element. Method step B comprises porosifying the support element on at least one surface thereof in order to form a separation layer. In particular, by said porosifying, the separation layer may also be formed at least partially along one or more sides of the support element. In method step C, a wafer layer is deposited on the separation layer of the support element by an epitaxy method. In a further method step D, the wafer layer is peeled off from the support element. A further feature of the method is that method steps B to D are repeated at least once, preferably several times, on the support element.

[0015] This method step is known in the prior art.The released wafer layers are used in the manufacture of electronic devices, and in particular in the manufacture of photovoltaic cells.

[0016] A feature of the method according to the invention is that method step A comprises further method steps A1 and A2, whereby in method step A1 a support substrate is provided and in method step A2 a seed layer is deposited by epitaxy on at least one front surface and at least one side surface of said support substrate in order to produce said support element.

[0017] In particular, the method according to the invention allows the support element to be used multiple times for wafer layer production without compromising the quality of the wafer layer.

[0018] In particular, the method according to the invention allows a more frequent use of the support substrate compared to the prior art, since the epitaxial seed layer and the separation layer can be regenerated on the support substrate. When the support element reaches a minimum dimension, which corresponds at least to the dimension of the support substrate, the seed layer can be epitaxially deposited on the support substrate again and the support element can be readjusted. This is possible in particular because the quality and properties of the support substrate, in particular the dimensions, do not change at all or only to a small extent throughout the method.

[0019] Furthermore, the method according to the invention makes it possible to adapt the support element, in particular the epitaxial seed layer, to the required properties for subsequent method steps, such as porosification, thereby eliminating the need for special, often expensive, and often poor quality support substrates due to their special properties.

[0020] In particular, the epitaxial seed layer has high quality and homogeneity, especially with regard to crystal structure and electronic properties, compared to supporting substrates produced by zone melting or crystal growth methods.

[0021] The frequent use of the support substrate for manufacturing a large number of wafer layers may result in the use of particularly highly valuable support substrates, particularly with regard to their crystalline quality and surface. Any errors in the crystalline structure and / or the surface of the support substrate will directly affect the quality of the epitaxial seed layer and the wafer layer. In particular, any errors in the crystalline structure and / or the surface of the support substrate may induce further errors in the crystalline structure of the seed layer and the wafer layer.

[0022] The use of an expensive support substrate thus leads to a higher quality and a higher yield in the manufacturing process when further layers are deposited using epitaxy methods, in particular the high cost of the expensive support substrate is amortized by frequent use of the support substrate for the manufacture of wafer layers and by readjustment of support elements based on said support substrate, so that an overall cost reduction in the manufacture of wafer layers can be achieved.

[0023] Advantageously, method steps B to D are carried out at least 10 times, preferably at least 20 times, particularly preferably at least 30 times, with one support element.

[0024] In particular, a support element, which comprises a support substrate and an epitaxial seed layer, is used for the production of a wafer layer up to or slightly below a predetermined minimum dimension of the support element, particularly preferably less than 10 μm, particularly preferably less than 5 μm, most preferably less than 3 μm.

[0025] The minimum dimension refers to the lateral dimension of the support element and particularly preferably also includes the vertical dimension.

[0026] In particular, the dimensions of the support substrate may indicate the smallest dimension of the support element in the lateral and, particularly preferably, in the vertical direction.

[0027] Advantageously, when the support elements reach or fall below a minimum dimension, they can be reconditioned and then subsequently used as support elements in wafer layer fabrication.

[0028] Preferably, the reconditioning of the support element is carried out by carrying out method step A2 on a previously used support substrate.

[0029] For support elements that have already been used, before method step A2 is carried out again, a first adjustment is carried out on this support element or the support substrate, so that it may be possible to form a quality-high seed layer again on the support elements that have already been used.

[0030] In particular, a support element or a support substrate prepared for reuse can be conditioned prior to method step A2 by a mechanical treatment such as polishing or grinding, or a chemical treatment such as etching, or a combination of chemical and mechanical treatments, so that it has a particularly high-value surface on which the seed layer is deposited.

[0031] By readjusting the support element, the original support substrate can be used many times more frequently for the production of the wafer layer. In particular, by using the support substrate many times more frequently, a support substrate of high quality can be used, which can simultaneously increase the quality of the wafer layer. Even if the support substrate of high quality has a high cost, the production costs of the individual wafer layers are reduced by using the support substrate many times more frequently, in particular by readjusting the support element which includes the support substrate.

[0032] The epitaxy of the seed layer and the wafer layer is preferably performed in the same epitaxy apparatus, alternatively the seed layer and the wafer layer may be performed in different epitaxy apparatus.

[0033] Preferably, the support substrate is used for producing at least 50, preferably at least 100, particularly preferably at least 150 wafer layers within the support element.

[0034] In particular, the support substrate may have a smoothly ground or polished surface. The quality of the epitaxial seed layer and the wafer layer may thus be further improved.

[0035] Overall, by the method according to the invention the quality of the wafer layer can be improved, in particular with regard to crystal structure and electronic properties, while at the same time costs can be reduced due to the reusability and reproducibility of the support elements during production.

[0036] The epitaxial seed layer and the epitaxial wafer layer are deposited by chemical or physical vapor phase reactions or a mixture of these. In particular, the deposition of the seed layer and the wafer layer is carried out by chemical vapor phase epitaxy. Epitaxy allows the production of high quality layers, in particular with regard to the crystal structure and with low contamination.

[0037] The separating layer is preferably formed as a porous layer in a manner known per se. In particular, to form the separating layer, the supporting substrate is advantageously made porous in a manner known per se, in particular by an etching process as described, for example, in DE 10 2013 219 839 A1.

[0038] In a preferred embodiment, a seed layer is deposited covering one surface and all sides of the support substrate.

[0039] Thus, a uniform, particularly homogeneous, surface of one material can be provided for the production of the wafer layer as a nucleation layer and potential sources of error can be avoided outside the seed layer, in particular at the supporting substrate.

[0040] Furthermore, the coating of the support substrate, at least on one surface and on all sides, makes it possible to avoid non-uniformities during the porosification of method step B.

[0041] In particular, the seed layer may be deposited on all surfaces and all sides of the support substrate to completely cover the support substrate, such that the support substrate is completely surrounded by the seed layer.

[0042] Also, advantageously, coating the support substrate may protect it from damage on at least one surface and all sides, and this may further increase reusability.

[0043] An advantageous embodiment of the method is characterized in that said support substrate and said seed layer are or are made of silicon, germanium or gallium arsenide.

[0044] The use of silicon for the support substrate is particularly suitable because silicon is available in high quality, large quantities and large area applications, and preferably the seed layer on the silicon support is also formed of silicon in order to form the support element in one material.

[0045] Preferably the supporting substrate is lightly doped.

[0046] A lightly doped support substrate can be manufactured with high quality, because light doping can introduce traces of impurities in addition to the original dopants, which can cause errors in the lattice structure of the support substrate in particular and induce further errors in the structure of the epitaxial seed layer.

[0047] In an alternative embodiment of the method, the support substrate is n-doped or p-doped, with a doping concentration of 5×10 19 cm -3 in the range of less than 1 x 10 18 cm -3 less than 1×10 17 cm -3 in the range of less than 5×10 15 cm -3 is in the range.

[0048] If the doping concentration of the support substrate is low in the above mentioned ranges, the properties of the seed layer are positively influenced, especially if the seed layer is doped with the same dopant at a higher doping concentration.

[0049] Preferably, the support substrate has a low doping concentration and therefore a low concentration of other impurities, so that the seed layer and the wafer layer also have a low impurity concentration, thereby improving layer quality.

[0050] Preferably, boron, phosphorus, gallium or arsenic are used as dopants for doping the support substrate made of silicon or germanium.

[0051] The conductivity of said support substrate is in particular below a value of 10 Ohmcm.Preferably, the conductivity of the support substrate is desirably in the range of 2 mOhmcm to 3000 mOhmcm, preferably in the range of 10 mOhmcm to 200 mOhmcm, in particular around 100 mOhmcm.

[0052] A feature of a preferred embodiment of the method is that the seed layer is deposited on at least one surface of the support substrate with a layer thickness in the range of 10 μm to 250 μm, preferably in the range of 25 μm to 100 μm, particularly preferably in the range of 40 μm to 80 μm.

[0053] Alternatively or additionally, a seed layer is applied to at least one side of the support substrate with a layer width in the range of 10 μm to 600 μm, preferably in the range of 25 μm to 400 μm, particularly preferably 50 μm to 250 μm.

[0054] During the detachment of the wafer layer from the support element, the layer thickness and layer width can be reduced, in particular by trimming the detached wafer layer and by making the support element porous. With an appropriate layer thickness or layer width, in order to produce a wafer layer on the same support element, the cycle of method steps B to D can be carried out again and again until the minimum dimension of the support element is reached.

[0055] In particular, the seed layer is formed so that its width is greater than its thickness.

[0056] In order to reuse the support element, it is necessary to completely peel off the previously deposited wafer layer before forming another wafer layer. In order to completely peel off the wafer layer from the support element, it is usually necessary to trim the support element slightly, especially in the range of 2 μm to 20 μm, every time a wafer layer is peeled off.

[0057] When the wafer layer is peeled off from the support element, the support element shrinks slightly in its dimensions, in particular in the range of 2 μm to 20 μm. However, usually, the layer width shrinks more than the layer thickness during peeling of the wafer layer. By increasing the layer width, therefore, the cycle of method steps B to D can be performed more times until the minimum dimension of the layer width as well as the layer thickness is reached.

[0058] Due to the layer width being greater than the layer thickness, trimming of the wafer layer edges can be performed with greater tolerances and with correspondingly less expensive equipment, since the excess material from the support element is cut off accordingly even before the wafer layer is peeled off.

[0059] In an alternative embodiment of the method, the seed layer is 1×10 16 cm -3 ~5×10 19 cm -3 in the range of 1×10 17 cm -3 ~3×10 19 cm -3 range, especially 1×10 18 cm -3 ~1×10 19 cm -3 The films are n-doped or p-doped during deposition with a doping concentration in the range of

[0060] By doping the seed layer during epitaxy, the seed layer can be improved in quality due to the higher purity of the dopants. In particular, the intrusion of impurities, especially metals, can be reduced by more than 10 times, especially more than 50 times, compared to support elements cut from blocks produced using crystal growth methods such as zone melting or Czochralski. The reduced amount of intrusion of impurities improves the quality of the seed layer and therefore also the quality of the wafer layer.

[0061] Furthermore, since impurities can also affect the process of forming and porosifying the separation layer, reduced intrusion of impurities also has a positive effect here on the homogeneous formation of the separation layer, especially on the surface.

[0062] Furthermore, the doping of the seed layer allows for good electrical contact of the seed layer to the support element during porosification, which has a beneficial effect on the etching process.

[0063] Advantageously, the dopants boron, phosphorus, gallium or arsenic are used to dope a seed layer made of silicon or germanium.

[0064] The conductivity of the seed layer is desirably in the range of 2 mOhmcm to 500 mOhmcm, preferably in the range of 5 mOhmcm to 25 mOhmcm, and particularly around 15 mOhmcm.

[0065] Preferably, a contact layer is deposited, formed or placed on a surface of the support substrate opposite the seed layer before, during or after deposition of the seed layer.

[0066] The contact layer allows a good contact, especially a dry contact, with the support element, which is particularly important for the porosification process. The properties of the contact layer here can be adapted to the respective situation, independently of the properties of the support element, the support substrate and / or the seed layer. Preferably, the contact layer has metal or metal-like electrical properties.

[0067] An advantageous embodiment of the method is characterized in that the contact layer is formed in the support substrate by diffusion from a diffusion layer onto the surface of the support substrate opposite the seed layer, the diffusion layer being formed in particular by a holding element for holding the support substrate during method step A2 or being deposited on the surface of the support substrate opposite the seed layer prior to method step A2.

[0068] By solid-state diffusion, the contact layer can already be produced cost-effectively during the production of the seed layer, so that no further method steps, such as a separate deposition or deposition of the contact layer, are necessary.

[0069] A further advantageous embodiment of the method is characterized in that the contact layer is or is made of a polycrystalline semiconductor material, in particular polysilicon.

[0070] Polycrystalline materials have the advantages of low cost and good dry contact of the support elements.

[0071] Preferably, a polycrystalline or highly doped contact layer, in particular doped with phosphorus as dopant, allows contaminants, in particular from the supporting substrate, to be gettered away or immobilized, whereby the quality of the seed layer is further improved.

[0072] Alternatively or additionally, the contact layer is formed or arranged to protrude above the supporting substrate.

[0073] Preferably, the contact layer has a thickness in the range of 0.1 to 20 μm, in particular in the range of 1 to 12 μm. The thickness of the contact layer is particularly adapted to its role and properties, in particular the preferred thickness of the contact layer ensures good contact and sufficient stability of the support element.

[0074] An alternative embodiment of the method is characterized in that the seed layer is deposited on the support substrate with a non-uniform layer thickness, particularly preferably the layer thickness increases or decreases towards at least one, preferably two opposing side surfaces of the support substrate.

[0075] More preferably, the change in layer thickness from the center to the sides of the seed layer may be particularly continuous.

[0076] By providing a non-uniform layer thickness, non-uniformities during the porosification process are mitigated, particularly with respect to applied current and electric field.

[0077] The invention further relates to a support element for manufacturing a wafer layer as claimed in claim 12.

[0078] The support element comprises a support substrate, in particular made of silicon, germanium or gallium arsenide, an epitaxial seed layer deposited on at least one surface and at least one side of the support substrate, and a separation layer formed by porosifying at least one surface of the epitaxial seed layer.

[0079] Preferably, the seed layer covers one surface and all sides of the support substrate.

[0080] In particular, the seed layer is deposited on all surfaces and all sides of the support substrate, so that the support substrate can be completely covered.

[0081] Thus, the support substrate can be protected from external influences that affect the reusability of the support substrate.

[0082] An advantageous embodiment of the support element is characterized in that the seed layer has a layer thickness on at least one surface of the support substrate in the range of 10 μm to 250 μm, preferably in the range of 25 μm to 100 μm, particularly preferably in the range of 40 μm to 80 μm.

[0083] Alternatively or additionally, the seed layer has a layer width on at least one side of the support substrate in the range of 10 μm to 600 μm, preferably in the range of 25 μm to 400 μm, more preferably in the range of 50 μm to 250 μm.

[0084] When the wafer layer is detached from the support element, the layer thickness and layer width can be reduced, in particular by trimming the detached wafer layer and by making the support element porous. With a suitable layer thickness or layer width, the cycle of method steps B to D can be carried out again and again in order to produce a wafer layer on the same support element, until the minimum dimension of the support element is reached.

[0085] Advantageously, a contact layer, preferably made of a polycrystalline semiconductor material, in particular polysilicon, is arranged on the surface of the support substrate facing away from the seed layer.

[0086] The contact layer may be formed, in particular by solid-state diffusion, from a holding element which holds the support element during production of the seed layer or from a dopant-containing layer deposited on the surface of the support substrate facing away from the seed layer, which allows for a cost-effective production of the contact layer without a separate method step for depositing or arranging the contact layer on the support element.

[0087] The contact layer provides good contact with the support element, especially during porosification.

[0088] The support element according to the invention is preferably used for the production of a semiconductor layer according to the method according to the invention, in particular according to one advantageous embodiment thereof.

[0089] The invention further relates to an intermediate product in the manufacturing process of a wafer layer as claimed in claim 16.

[0090] The intermediate product comprises a support element according to the invention as described above, in particular an advantageous embodiment of the support element, and an epitaxial wafer layer arranged on the separating layer.

[0091] The abovementioned intermediate products are preferably used for the production of semiconductor layers according to the method according to the invention, in particular according to one advantageous embodiment thereof.

[0092] Further advantageous features and embodiments are explained below with reference to the examples and figures. [Brief description of the drawings]

[0093] [Figure 1a] 1A to 1C are diagrams illustrating an embodiment of a method for manufacturing a wafer layer according to the present invention. [Figure 1b] 1A to 1C are diagrams illustrating an embodiment of a method for manufacturing a wafer layer according to the present invention. [Figure 1c] 1A to 1C are diagrams illustrating an embodiment of a method for manufacturing a wafer layer according to the present invention. [Figure 1d] 1A to 1C are diagrams illustrating an embodiment of a method for manufacturing a wafer layer according to the present invention. [Diagram 2] FIG. 2 shows an embodiment of a support element according to the invention. [Figure 3a] 4 shows a further embodiment of a support element according to the invention; FIG. [Figure 3b] 4 shows a further embodiment of a support element according to the invention; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0094] All figures are schematic and not drawn to scale. In the figures, identical or functionally identical elements are given the same reference numerals. Figures 1 to 3 show the surface of a support substrate 2 or a surface of a support element 1 on which a seed layer 3 is deposited, which is always on the top.

[0095] 1a) to 1d) show a method for manufacturing a wafer layer according to the present invention.

[0096] As shown in Fig. 1a), in method step A2 a seed layer 3 is epitaxially deposited on a support substrate 2 provided in method step A1 to form a support element 1, which is used to produce a wafer layer 5. The seed layer 3 completely covers the upper and side surfaces of the support substrate 2. The lower surface of the support substrate 2 opposite the upper surface is not covered by the seed layer 3.

[0097] The support substrate 2 is a semiconductor, particularly made of silicon, manufactured by a zone melting method or a crystal growth method. The thickness of the support substrate 2 is in the range of 250 μm to 1000 μm. The support substrate 2 has a basic shape of a square, and the length of the side edge of the support substrate is 100 mm to 300 mm, particularly 140 to 170 mm. In addition to the basic shape of a square, the support substrate 2 can also have a pseudo-square shape with chamfered / rounded corners, or a circular, elliptical or rectangular shape.

[0098] The support substrate 2 has a lateral dimension 12 to which the layer width 9 of the seed layer 3 is connected on the side of the support substrate 2, so that the support element 1 has an overall lateral dimension 11.

[0099] On the surface of said support substrate 2 a seed layer 3 is deposited having a layer thickness 8. As shown in FIG. 1 a), said layer thickness 8 is substantially the same as said layer width 9.

[0100] The seed layer 3 is deposited by epitaxy, in particular by chemical vapor deposition, on the support substrate 2. By means of epitaxy a qualitatively high-quality layer is formed which is an important starting point for producing a correspondingly qualitatively high-quality seed layer 3. In particular, by means of epitaxy the seed layer 3 can be adapted to the required requirements in the subsequent processes, in particular with regard to crystal quality and electrical properties.

[0101] In a method step B following the production of the support element 1, a porous separation layer 4 is formed on the surface of the support element 1 and at least partly on the lateral edges, and therefore on the surface and at least partly on the surface of the seed layer 3 and at least partly on the lateral edges, as shown in FIG. 1b). The separation layer 4 has a thickness or thickness of up to 3 μm, in this case about 2 μm. The separation layer 4 is formed on the support element 1 by etching, in particular porosification, and can be carried out, for example, as described in DE 10 2013219886 A1. By the above-mentioned method, the separation layer 4 can be formed all over the surface of the support element 1.

[0102] In a further method step C, an epitaxial wafer layer 5 is deposited on the separating layer 4 of the support element 1. The wafer layer 5 partially overlaps the side surface of the support element 1 and may even extend over part of the side surface of the support element 1. The extensive application of the wafer layer 5 ensures a high quality right up to the edge regions of the wafer layer 5. This is shown in FIG. 1c).

[0103] The product comprising the support element 1 and the wafer layer 5 is also called intermediate product 10 .

[0104] In a further method step, the intermediate product 10 thus produced, comprising the support element 1 and the wafer layer 5, is trimmed at the side of the support element 1. By trimming, parts 7 of the wafer layer 5 protruding beyond the support element 1 and possibly also further parts of the wafer layer 5 attached to the side of the support element 1 are removed, as shown in FIG. 1d).

[0105] The trimming is performed by means of a laser beam. Alternatively, trimming can also be performed by mechanical processes such as sawing or grinding. In particular, trimming makes it possible to remove the part of the wafer layer 5 attached to the support element 1, thus allowing the support element 1 to be reused. However, this usually also requires the removal of a minimum of material from the sides of the support element 1, resulting in a lateral dimension 11' that is smaller than the lateral dimension 11 in method step A.

[0106] After trimming of the intermediate product 10, in method step D the wafer layer 5 is peeled off from the support element 1.

[0107] After detachment of the wafer layer 5, the method steps B to D are again carried out on the support element 1 as shown in FIGS. 1b) to 1d) in order to produce a further wafer layer 5.

[0108] The smaller lateral dimension 11' of the support element 1 does not adversely affect the production of the wafer layer 5, as long as the support element 1 is free of residues of a previously deposited wafer layer 5 and the smaller lateral dimension 11' of the support element 1, particularly preferably the thickness 11 of the support element, does not fall below a minimum dimension. The cycle of method steps B to D is therefore repeated any number of times until the support element 1 reaches or falls slightly below a minimum dimension.

[0109] The lower limit of the minimum dimension is the lateral dimension 12 and the thickness of the support substrate 2. When the lateral dimension 11′ approaches the lateral dimension 12 or the corresponding thickness of the support element 1 approaches the thickness of the support substrate 2, the support element 1 is adjusted by performing method step A2 and thus a new seed layer 3 is deposited on the support element 1 or on the support substrate 2.

[0110] Before method step A2 is carried out anew, a first conditioning is carried out on an already used support element 1 with this support element 1 or with the support substrate 2, so that a qualitatively high-value seed layer 3 can be formed again on the already used support element 1. For that purpose, the support element 1 or the support substrate 2 prepared for reuse can be conditioned before method step A2 by mechanical treatments such as polishing or grinding, or chemical treatments such as etching, or a combination of chemical and mechanical treatments, so that it has a particularly high-value surface on which the seed layer 3 is deposited.

[0111] In order to recondition the support element 1, when the dimension 11' of the support element 1 is substantially equal to the dimension 12 of the support substrate 2, a new seed layer 3 is formed on the previously used support substrate 2 so that it is reconditioned to the original lateral dimension 11 of the support element 1, as shown in FIG. 1a). The reconditioned support element 1 is now used again for the production of a wafer layer 5, without the need to use a new support substrate 2. By reconditioning the support element 1, the support substrate 2 can be used at least 50 times for the production of a wafer layer 5, as shown in FIGS. 1b) to 1d).

[0112] Both the layer thickness 8 and the layer width 9 of the seed layer 3 are in the range of 10 μm to 250 μm, preferably in the range of 25 μm to 100 μm, particularly preferably in the range of 40 μm to 80 μm. As mentioned above, both the layer thickness 8 and the layer width 9 of the seed layer 3 have the advantage that a seed layer 3 of high quality can be produced, which can be produced in the time allowed by the corresponding process.

[0113] Depending on given parameters, such as the quality for the wafer layer 5 manufacturing, the support substrate 2 as well as the seed layer 3 can be doped or undoped.

[0114] In particular, the support substrate 2 has a thickness of 5×10 19 cm -3 in the range of less than 1 x 10 18 cm -3 less than 1×10 17 cm -3 in the range of less than 5×10 15 cm -3 The doping concentration ranges from 1.5×10 to 1.5×10. 16 cm -3 , p-doped using boron as dopant. In the manufacture of the doped support substrate 2 using zone melting or crystal growth techniques, impurities may be introduced into the crystal structure, in particular impurities such as metals, oxides, nitrides or carbides, and agglomerates may form, which ultimately reduces the overall quality and value of said support substrate 2 due to uneven distribution of impurities and dopants.

[0115] The starting point for the qualitatively high-value layers is the support substrate 2 and the seed layer 3, which are already qualitatively high-value. Therefore, a qualitatively high-value, and therefore usually also expensive, substrate must be used as the support substrate 2, since the quality of the support substrate 2 ultimately also decisively influences the quality of the wafer layer 5. For this reason, it is preferable to use a support substrate 2 with a low doping concentration. If the support substrate 2 is doped, it is p-doped, in particular with the element boron.

[0116] By repeatedly using the support substrate 2 up to 150 times or more to manufacture a large number of wafer layers 5, the high initial cost of the expensive support substrate 2 becomes less of an issue, thereby achieving further cost reduction while improving the quality of the wafer layers 5.

[0117] However, it is advantageous for the formation of the separating layer 4 if the support element 1 is doped, particularly in method step B.

[0118] This is made possible here by doping, in particular p-doping, of the seed layer 3, of which the separation layer 4 is formed by porosification. The seed layer has a doping density of 1×10 16 cm -3 ~5×10 19 cm -3 in the range of 1×10 17 cm -3 ~3×10 19 cm -3 range, especially 1×10 18 cm -3 ~1×10 19 cm -3 Here, elemental boron is used as the dopant at a concentration of 5×10 18 cm -3 The p-doped material used in this study is presented.

[0119] The epitaxial formation of the seed layer 3 results in a more uniform and up to 100 times less incorporation of impurities than doping of the seed layer with dopant elements, since in the epitaxy the dopant elements or substances are present in a particularly high purity. Furthermore, the incorporation of oxygen, which is a cause of stacking errors induced in the wafer layer 5, is up to 20 times less than in the epitaxy crystalline structure. Due to the uniform doping, the formation of the separation layer 4 on the seed layer 3 is also more uniform, which also has a positive effect on the quality of the wafer layer 5 produced thereon.

[0120] 2 shows a special embodiment of a support element 1. The support element 1 likewise comprises a support substrate 2 and a seed layer 3, the seed layer 3 being deposited on the support substrate 2 with a layer width 9 which is greater than the layer thickness 8.

[0121] After each production step of a wafer layer 5, in method steps B to D, the lateral dimension 11 of the support element 1 as well as the layer thickness 8 of the seed layer are reduced. The lateral dimension 11' of the support element 1 is reduced, in particular by trimming the wafer layer 5 or the support element 1, in order to completely remove the wafer layer 5 before the production of a further wafer layer 5. The layer thickness 8 of the seed layer 3 is also reduced with each etching step in method step B.

[0122] Due to the trimming, the lateral dimension 11 of the support elements 1 is significantly reduced in each wafer layer 5 compared to the layer thickness 8 of the seed layer 3 due to porosification. In particular, the trimming of the side surfaces of the support elements is subject to greater variations and also depends on the corresponding trimming device. In order to reduce the production costs of the wafer layer 5, in particular trimming devices are also used which have a larger tolerance range for the removal of the side surfaces of the support elements 1, which is in the range of 2 μm to 20 μm, here about 5 μm. In order to realize the maximum possible number of wafer layer 5 production cycles with only one support element 1 before the support element 1 is adjusted, it is advantageous to form the layer width 9 of the seed layer 3 to be thicker compared to the layer thickness 8 of the seed layer 3.

[0123] In FIGS. 3 a ) and 3 b ), one support element 1 is respectively shown, which comprises a contact layer 6 on the surface of the support substrate 1 opposite the seed layer 3 .

[0124] The contact layer 6 is already deposited on or connected to the support substrate 2 by gas phase reaction or diffusion before the deposition of the seed layer 3. However, it is also within the scope of the invention to deposit the contact layer 6 during or after the deposition of the seed layer 3. The deposition of the contact layer 6 takes place before method step B, since good contact with the support element 1 is important for the porosification process in method step B.

[0125] The contact layer 6 is formed of a polycrystalline semiconductor material, in particular polysilicon, which materials allow good dry contact during porosification of the support element 1. For good contact, in particular good dry contact, of the contact layer 6, these materials have electrical properties at least similar to those of metals.

[0126] The lateral dimension of the contact layer 6 is approximately equal to or exceeds the lateral dimension 12 of the support substrate 2. In particular, the lateral dimension of the contact layer 6 may be smaller than the lateral dimension 11 of the support element 1. The thickness of the contact layer 6 is in the range of 0.1 to 20 μm, here about 10 μm, and is therefore significantly less than the thickness of the support substrate 2 and less than the layer thickness 8.

[0127] As shown in FIG. 3 a), the contact layer 6 has a lateral dimension that is larger than the support substrate 2, which dimension is the same as the lateral dimension 11 of the support element 1. This results in a significantly larger layer width 9 compared to the layer thickness 8. During the cycle of method steps B-D, the lateral reduction due to trimming of the support element 1 and the subsequent detachment of the wafer layer 5 is larger than the reduction in layer thickness 8. It is therefore advantageous if the support element 1 is deposited on the support substrate 1 with a layer width 9 that is larger compared to the layer thickness 8.

[0128] Due to the fact that the contact layer 6 is applied over the entire surface, a good, in particular dry, contact is always ensured, independent of a reduction in the lateral dimension 11 of the support element 1 after the wafer layer 5 has been peeled off. [Explanation of symbols]

[0129] 1 Supporting elements 2 Support substrate 3 Seed layer 4 separation layer 5 Wafer Layer 6 Contact layer 7 parts 8 layer thickness 9 layer width 10 Intermediate products 11 Support element dimensions 11' Support element dimensions 12 Support board dimensions

Claims

1. A method for manufacturing a wafer layer (5) comprising the following method steps: A. Preparation of the support element (1), B. Porosification of said support element (1) to create a separating layer (4) on at least one surface; C. Deposition of a wafer layer (5) on the separating layer (4) of the support element (1) using an epitaxy method; and D. peeling off the wafer layer (5) from the support element (1), whereby method steps B to D are repeated at least once using the support element (1), In a manufacturing method comprising the steps of: Method step A A1 Preparation of a supporting substrate (2), and A2. To produce the support element (1), a seed layer (3) is deposited on at least one surface and at least one side of the support substrate (2) by epitaxy; The method comprises the steps of: A method, characterized in that the seed layer (3) is deposited with a layer width (9) that is greater than its layer thickness (8).

2. The method according to claim 1, characterized in that method steps B to D are repeated multiple times using the support element (1).

3. 3. The method according to claim 1 or 2, characterized in that the seed layer (3) is deposited covering one surface and all sides of the support substrate (2).

4. 4. A method according to any one of claims 1 to 3, characterized in that the support substrate (2) and the seed layer (3) are or are made of silicon, germanium or gallium arsenide.

5. The support substrate (2) is n-doped or p-doped, with a doping concentration of 5×10 １９ cm －３ The method according to any one of claims 1 to 4, characterized in that the ratio is in the range of less than 1:

1.

6. 6. The method according to claim 1, characterized in that the seed layer (3) is deposited on at least one surface of the support substrate (2) with a layer thickness (8) in the range of 10 μm to 250 μm and / or the seed layer (3) is deposited on at least one side of the support substrate (2) with a layer width (9) in the range of 10 μm to 600 μm.

7. The method according to claim 6, characterized in that the seed layer (3) is deposited on at least one surface of the supporting substrate (2) with a layer thickness (8) in the range of 40 μm to 80 μm.

8. The method according to claim 6, characterized in that the seed layer (3) is deposited on at least one side of the supporting substrate (2) with a layer width (9) in the range of 50 μm to 250 μm.

9. The seed layer (3) is 1×10 １６ cm －３ ~5×10 １９ cm －３ 9. The method according to claim 1 , wherein the doping concentration is in the range of 0.5 to 1000 .mu.m.

10. The method according to claim 9, characterized in that the seed layer (3) is p-doped during deposition.

11. A method described in any one of claims 1 to 10, characterized in that a contact layer (6) is deposited, formed or placed on the surface of the support substrate (2) opposite the seed layer (3) before, during or after deposition of the seed layer (3).

12. 12. The method according to claim 11, characterized in that the contact layer (6) is or is made of a polycrystalline semiconductor material and / or that the contact layer (6) is or is arranged protruding from the support substrate (2).

13. The method according to claim 12, characterized in that the contact layer (6) is or is made of polysilicon.

14. Method according to any one of claims 11 to 13, characterized in that the contact layer (6) has a thickness in the range of 0.1 to 20 μm.

15. 15. The method according to claim 11, characterized in that the contact layer (6) is formed in the support substrate (2) by diffusion from a diffusion layer on the surface of the support substrate (2) opposite the seed layer (3).

16. A method according to claim 15, characterized in that the diffusion layer is formed by a holding element for holding the support substrate (2) during method step A2 or is deposited on the surface of the support substrate (2) opposite the seed layer (3) prior to method step A2.

17. 17. The method according to any one of the preceding claims, characterized in that the seed layer (3) is deposited on the support substrate (2) with a non-uniform layer thickness (8).

18. A supporting substrate (2), an epitaxial seed layer (3) deposited on at least one surface and at least one side of the support substrate (2); and a separation layer (4) formed by porosifying at least one surface of the epitaxial seed layer (3); A support element (1) for producing a wafer layer (5), wherein said seed layer (3) has a layer width (9) that is greater than its layer thickness (8).

19. The supporting substrate (2) is made of silicon, germanium or gallium arsenide, and The epitaxial seed layer (3) is deposited on one surface and all sides of the support substrate (2); A support element (1) according to claim 18.

20. Support element (1) according to claim 18 or 19, characterized in that the seed layer (3) has a layer thickness (8) in the range of 10 μm to 250 μm on at least one surface of the support substrate (2) and / or the seed layer (3) has a layer width (9) in the range of 10 μm to 600 μm on at least one side of the support substrate (2).

21. A support element (1) as described in claim 20, characterized in that the seed layer (3) has a layer thickness (8) in the range of 40 μm to 80 μm on at least one surface of the support substrate (2) and / or the seed layer (3) has a layer width (9) in the range of 50 μm to 250 μm on at least one side of the support substrate (2).

22. A support element (1) described in any one of claims 18 to 21, characterized in that a contact layer (6) is arranged on the surface of the support substrate (2) opposite the seed layer (3).

23. A support element (1) as described in claim 22, wherein the contact layer (6) is made of polysilicon.

24. An intermediate product (10) comprising a support element (1) according to any one of claims 18 to 23 and an epitaxial wafer layer (5) arranged on said separating layer (4).

25. The intermediate product (10) described in claim 24, wherein the epitaxial wafer layer (5) is made of silicon.

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