High density logic fabrication using multi-dimensional laser annealing

Abstract

A method for forming a transistor device is disclosed, comprising: forming a first transistor plane on a substrate, the first transistor plane having at least one layer of epitaxial film suitable for forming a channel of a field effect transistor; depositing a first insulator layer on the first transistor plane; depositing a first layer of polysilicon on the first insulator layer; and annealing the first layer of polysilicon using laser heating, which increases the grain size of the first layer of polysilicon. The method further comprises forming a second transistor plane on the first layer of polysilicon, the second transistor plane being suitable for forming a channel of a field effect transistor; depositing a second insulator layer on the second transistor plane; depositing a second layer of polysilicon on the second insulator layer; and annealing the second layer of polysilicon using laser heating.

Description

[Technical field]

[0001] This application claims the benefit of priority to PCT International Application No. PCT / US2020 / 043986, filed July 29, 2020, and U.S. Provisional Application No. 62 / 883,192, filed August 6, 2019, the contents of which are incorporated herein by reference in their entireties.

[0002] This application relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, including microfabrication methods. [Background technology]

[0003] The "Background" discussion provided in this application is intended to generally present the context of the present disclosure. The work of the presently named inventors is not expressly or impliedly admitted as prior art to the present invention to the extent described in this Background, and in the manner described that is not otherwise qualified as prior art at the time of filing.

[0004] The present disclosure relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication.

[0005] In the fabrication of semiconductor devices (especially at a microscale), various fabrication processes such as film formation deposition, etch mask formation, patterning processes, material etching and removal, and doping processes are performed. These processes are performed repeatedly to form the desired semiconductor device elements on a substrate. Historically, in microfabrication, transistors are formed on one side and wiring / metallization is formed on the active device side, and thus is characterized as a two-dimensional (2D) circuit or 2D fabrication. Although scaling efforts have significantly increased the number of transistors per unit area in 2D circuits, scaling efforts face greater challenges as scaling enters single-digit nanometer-scale semiconductor device manufacturing nodes. Thus, while signal propagation speeds improve in conventional CMOS processes, scaling from current fabrication and chip design techniques is becoming more difficult and costly. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.

[0006] 3D integration, or the vertical stacking of multiple devices, aims to overcome the scaling limitations imposed by planar devices by increasing transistor density in volume rather than area. Device stacking has been demonstrated and implemented by the flash memory industry with 3D NAND, but its application to random logic designs is substantially more challenging. 3D integration of logic chips (CPUs (Central Processing Units), GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays, SoCs (System on Chip)) is being pursued. To make the most of the vertically stacked silicon base area, there is a need for 3D logic circuits for future high density logic circuits. Summary of the Invention [Problem to be solved by the invention]

[0007] One object of the present disclosure is to provide a method for forming multiple levels of transistors. Another object is to apply a laser annealing process to convert polycrystalline silicon to single crystalline silicon. The amount and time of heating is targeted to the polysilicon layer such that the underlying layers are not heated beyond a predetermined temperature. [Means for solving the problem]

[0008] In one embodiment, 1. A method of forming a transistor device, comprising: forming a first transistor plane on a substrate, the first transistor plane having a plurality of field effect transistors; depositing a first insulator layer on the first transistor plane; depositing a first layer of polycrystalline silicon over the first insulator layer; annealing the first layer of polycrystalline silicon using laser heating, the laser heating increasing a grain size of the first layer of polycrystalline silicon; A method is provided comprising:

[0009] In another embodiment, 1. A method of forming a transistor device, comprising: forming a first transistor plane on a substrate, the first transistor plane having at least one layer of epitaxial film suitable for forming a channel of a field effect transistor; depositing a first insulator layer on the first transistor plane; depositing a first layer of polycrystalline silicon on the first insulator layer; annealing the first layer of polycrystalline silicon using laser heating, the laser heating increasing a grain size of the first layer of polycrystalline silicon; forming a second transistor plane on the first layer of polysilicon having the increased grain size, the second transistor plane being suitable for forming a channel of a field effect transistor; depositing a second insulator layer on the second transistor plane; depositing a second layer of polycrystalline silicon on the second insulator layer; annealing the second layer of polycrystalline silicon using laser heating, the laser heating increasing a grain size of the second layer of polycrystalline silicon; A method is provided comprising:

[0010] It is noted that this summary does not identify each embodiment and / or incrementally novel aspects of the disclosed or claimed invention. Rather, this summary merely provides a preliminary discussion of different embodiments and corresponding novel points over the prior art. The reader is directed to the detailed description of the disclosure and corresponding drawings for additional details and / or envisioned perspectives of the invention and embodiments, as discussed hereinafter.

[0011] A more complete application of the present disclosure and many of the attendant advantages thereof will be readily obtained and better understood by reference to the following detailed description, when considered in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a schematic cross-sectional view of an example substrate segment of the present application. [Diagram 2] FIG. 2 shows a layer of silicon dioxide deposited on a first transistor plane. [Diagram 3] FIG. 13 illustrates a laser anneal exposure that converts polysilicon to epitaxial silicon after laser anneal. [Figure 4] FIG. 1 shows an example of the result after polishing a layer of epitaxial silicon. [Diagram 5] FIG. 2 shows a second transistor planar surface formed on the annealed and polished layer of crystalline silicon. [Figure 6] FIG. 13 illustrates how the technique can be repeated for any number of transistor planes. [Figure 7] FIG. 1 illustrates the use of polysilicon converted to epitaxial silicon to aid in the growth of a new stack of silicon layers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In the figures, like reference numerals designate the same or corresponding parts throughout the several views. Furthermore, as used herein, terms such as "a" and "an" generally have the meaning of "one or more" unless otherwise noted. The drawings are generally drawn to scale unless otherwise noted or when schematic structures or flow charts are depicted.

[0014] Additionally, the terms "approximately," "approximately," "about," and similar terms generally represent ranges that include the identified value within a margin of 20%, 10%, or preferably 5%, and any value therebetween.

[0015] Aspects of the present disclosure include a method for forming multiple planes of transistors. This allows for 3D nano-planes of over 20 high quality silicon-based substrates, followed by processing including laser processing, cleaning, CMP (chemical mechanical polishing), and future epitaxial stacks in some optional embodiments. The multiple transistor planes described herein allow for the laser annealing process to change the polycrystalline silicon by increasing the grain size, making the polycrystalline silicon function more like epitaxial silicon or single crystal silicon. This allows for additional epitaxial layers to be grown for more transistor planes, including gate-all-around transistor devices. Each transistor plane can include a film stack that constitutes a CFET (nmos over pmos) nano-plane layer. Each additional layer begins with a step of capping with oxide or other insulator, followed by a step of depositing polycrystalline silicon, converting it to epitaxial silicon using a laser anneal, and then forming the desired transistor plane, which can be logic and / or memory. In this disclosure, epitaxial silicon refers to a silicon crystalline layer on which epitaxial crystal growth can occur. Epitaxial silicon may be any crystalline silicon capable of functioning as epitaxial silicon, including single crystal silicon, also referred to as monocrystalline silicon.

[0016] It should be understood that the order of description of the different steps described is presented for clarity. Generally, these steps can be performed in any suitable order. Also, in this application, although different features, techniques, configurations, etc. may each be described in different parts of this disclosure, it is intended that each concept can be implemented independently of each other or in combination with each other. Thus, the present invention can be embodied and realized in many different ways.

[0017] 3D integrated circuits address the challenges of scaling by stacking 2D dies and connecting them in three dimensions. A common form of 3D integrated circuit design is wafer bonding. Wafer bonding is a method of bonding several thin film devices additively, allowing many device layers. The method involves fabricating separate devices on separate wafers, reducing the thickness of the wafer, providing front and back leads, and connecting the thinned dies to each other. This method is used to fabricate 3D integrated circuits with three or more active layers. 3D integrated circuits are currently used for NAND flash memory in mobile devices. However, the desire for smaller packages and the migration of logic, similar to memory, to multi-dimensional planes requires alternative approaches to manufacturing.

[0018] As an alternative to wafer bonding, monolithic 3D integrated circuits are built up layer by layer on a single semiconductor wafer. No alignment, thinning, bonding, or drilling of silicon vias is required for monolithic 3D integrated circuits. However, low temperature bonding is used to create multiple thin layers of defect-free silicon, and layers must be placed on top of the active transistor circuitry.

[0019] To build a multi-dimensional plane of logic and memory, a first transistor plane is formed on a substrate. In practice, single crystal silicon is produced from a seed crystal, and then the resulting single crystal ingot is sliced ​​into wafers and polished. This is a costly and time-consuming process. A transistor plane is formed through a microfabrication process. This transistor plane is preferably for any type of transistor or logic or memory. After forming the first transistor plane, polycrystalline silicon is deposited on this first transistor plane. However, polysilicon is not a desirable material for integrated circuits. Single crystals are important for electronic circuits. This is because grain boundaries, impurities, and crystallographic defects have a significant effect on the local electronic properties of the material, thereby disrupting their preferred operation, thereby affecting the function, properties, and reliability of logic devices.

[0020] In 2D semiconductor manufacturing, single crystal substrates are used for epitaxial growth and transistor channel formation. In particular, semiconductor films are epitaxially grown on semiconductor substrate wafers. For epitaxial growth of a planar film on a substrate wafer, the lattice of the epitaxial film has a specific orientation with respect to the crystal lattice of the substrate wafer, such that the

[0001] Miller indices of the film are aligned with the

[0001] Miller indices of the substrate.

[0021] Continuing the fabrication process for additional transistor layers requires control of the crystal orientation above the transistor layers. As a solution, a laser annealing process has been developed that allows the polysilicon to be converted to single crystal silicon without affecting the transistor layers below the polysilicon. In an embodiment, multiple transistor planes disclosed herein can convert the polysilicon by increasing the grain size through a laser annealing process, making the polysilicon function more like epitaxial silicon or single crystal silicon. This allows the growth of additional epitaxial layers for more transistor planes including gate-all-around transistor devices.

[0022] In one embodiment, a first transistor plane is formed on a substrate in a conventional 2D manufacturing process. This transistor plane may be for any type of transistor or logic or memory. After forming the first transistor plane, polysilicon is deposited on the first transistor plane. The polysilicon is converted to epitaxial silicon on the upper base substrate surface using a laser annealing process. Subsequent transistor planes may then be formed, capped with polysilicon, and converted to epitaxial silicon. This process may be repeated for any number of transistor planes.

[0023] In one example embodiment, in a CFET manufacturing process, a silicon substrate is used and alternating layers of SiGe and Si are epitaxially grown, up to a total of 8-12 layers. Limiting the height and / or number of layers in the epitaxial stack can be significant in terms of higher quality films. The SiGe is then removed in the stack sandwich, leaving 4-6 layers of transistor planes available for logic formation as gate-all-around (GAA) field effect transistors. Two nano-planes of transistors can be interconnected to form NMOS or PMOS devices. Thus, the manufacturing process is only possible for a total of three actual transistor planes. In other words, a vertical stack of three FETs can be maintained within the required quality specifications. However, three levels of transistors are insufficient to fully enable 3D logic formation in a cost-effective solution. More layers of transistors are required due to volumetric scaling.

[0024] The techniques disclosed herein allow for 3D planes of transistors at least 20 planes, or greater than the level of high quality FETs. Each plane of transistors can be used to form any type of transistor, including but not limited to CFET, planar, FinFET, and memory. The techniques are then expanded with increasing volumetric scaling.

[0025] An embodiment will now be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of an exemplary substrate segment. A silicon substrate or SOI (silicon on insulator) substrate 101 is received. A first transistor plane (circuit plane) 103 is formed on the substrate 101. This first plane can include field effect transistors fully formed via metal layer 1 routing, or this transistor plane includes layers after which the channels of the transistor devices are formed. The transistor plane can be a CFET device, FinFet, memory, logic, or any device. If necessary, the CFET plane is formed before etching a given transistor plane, or the entire stack of multiple isolated transistor planes. Thus, in a preferred embodiment, no limitations are imposed on the growth temperature of the epitaxial stack. Each plane of silicon can be used for any type of transistor or memory element without limitations. In one example, forming this first transistor plane can include growing 8-12 layers of alternating SiGe / Si using an epitaxial growth process with substantially no temperature limitations.

[0026] After forming the first transistor plane 103, an insulator is deposited on the first transistor plane. FIG. 2 shows a layer of silicon dioxide 105 deposited on the first transistor plane 103. Other types of oxides or dielectric films may be selected. For most applications, the insulator is deposited with a preferred thickness of 500-3000 angstroms. Next, polycrystalline silicon (also called polysilicon) is deposited. The deposition temperature is preferably less than 580° C. The polysilicon 107 can be deposited using LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), sputter deposition, or any polysilicon deposition method (even at room temperature).

[0027] At this point, the first transistor plane 103 is formed and isolated, and polysilicon 107 is now on the active surface of the substrate. However, polysilicon is not sufficient material for epitaxial growth and the channel material of the transistor. For epitaxial growth, single crystal silicon is required. In the described technique, a scanning laser crystallization process is performed. In this laser annealing process, the grain size of the polysilicon is increased, so that the resulting layer has sufficiently large grain boundaries. As a result, the resulting layer acts essentially like a layer of single crystal silicon, supporting the epitaxial growth of additional silicon layers. Figure 3 shows the laser annealing exposure, which converts the polysilicon into epitaxial silicon after laser annealing. Any type of laser can be selected and used for the scanning laser crystallization process. Exemplary wavelengths for silicon processing are typically 100 nm to 800 nm. The wafer is fixed and the laser is scanned across the wafer, or the laser remains fixed in place and the substrate (wafer) is rotated or moved past the laser. Such a scanning motion allows any type of laser system to be used. It is clear that the amount of energy delivered, the scanning speed, and the laser system depend on the given stack / area to be recrystallized.

[0028] In a non-limiting specific example, the laser wavelength (l) and process conditions for rapidly heating silicon or polysilicon are: wavelength 532 nm, pulse width 10-15 ns, scan speed 14-45 cm / s, power 1 W-7 W, and beam size 2-3 mm, 40-80 μm. The scan time and duration can be adjusted for a given polysilicon film thickness, or area to be scanned. The laser scan is performed such that only the polysilicon area receives energy (heating effect). The laser scan is performed such that the layers, materials, and devices underneath the oxide insulator are kept below 400° C. In other words, the heating amount and duration are targeted to the polysilicon layer such that the underlying layers are not heated above a predetermined temperature.

[0029] The laser beam 301 melts the polysilicon 107a, which then recrystallizes to a substantially larger grain size. In one embodiment, the grain size is 4-10 times larger after the laser process (for normal single crystal grains). It is noted that for improved 3D CFET channels on the order of 5 nm, the laser kneeling technique achieves substantially single crystal film properties by modifying the grain size to over 100 nanometers. Thus, the majority of the channels formed with recrystallized polysilicon do not have a single grain boundary. Also, if the laser beam 301 is a coherent source, there is no dispersion or significant diffusion of the laser beam, or loss of energy. Thus, for channel scales on the order of one or two nanometers, the layer of polysilicon 107a has a sufficiently large grain size to act as single crystal silicon for a given channel.

[0030] In laser annealing, air may be used as a medium 303 between the laser beam 301 and the polysilicon layer 107a to be annealed. Using air as the medium 303 is convenient considering wafer handling. However, it is noted that other media may be used. For example, the substrate may be used immersed in water or oil or other fluids, since many different media are available for coherent laser sources. In an embodiment, water or cold water may be used. Water has a relatively high specific heat capacity, so using cold water is beneficial in terms of cooling the substrate. The use of other media (such as cold water) may act as a cooling effect for the wafer substrate underneath the polysilicon. Thus, the use of such cold water provides two advantages. The cooling medium allows protection of the underlying transistor plane, and allows higher annealing temperatures, resulting in further increase in grain size.

[0031] In another embodiment, a cryogenic wafer chuck 305 is used to obtain the maximum temperature gradient between the laser beam and the silicon substrate on the polysilicon layer to be annealed. A wafer chuck is a device for holding a wafer. Wafer chucks are usually circular and slightly larger than the wafer size. However, their shape and size may vary depending on the shape and size of the wafer. The wafer chuck may hold the wafer in place by drawing a vacuum on the backside of the wafer. In another embodiment, a variable temperature is used, ranging from 400K (127C) to 30K (-243K) in the laser annealing system. Exemplary coolants for the laser system include both liquid nitrogen and liquid helium with two cooling centers (depending on the desired temperature window), which allows for effective wafer cycling. The laser scan may be limited to a specific area of ​​the substrate or may be the entire wafer surface.

[0032] If necessary, a polishing and / or planarization step can be performed after the laser treatment. Figure 4 shows an example of the result after polishing the epitaxial silicon layer. For example, as one planarization option, a CMP (Chemical Mechanical Polishing) step can be performed. The CMP step can modify the polysilicon channel area and modify the relatively thick layer with large grain size to obtain a relatively thin epitaxial silicon channel 401. The planarization / polishing process is beneficial because the surface roughness after the laser annealing is large. This roughness can be reduced by an order of magnitude by the CMP and cleaning steps, which allows the annealed polysilicon layer to be thinned. An example of the cleaning process may include: (1) immersing the CMP-polished poly-Si film in two mixed solutions (NH4OH:H2O2:H2O=1:4:20 and HCl:H2O2:H2O=1:1:6) at 75°C for 10 minutes to remove most of the residues from CMP; (2) immersing the substrate in pure H2O2 for 10 minutes to form a sacrificial oxide on the poly-Si surface; and (3) using a diluted HF solution (HF:H2O=1:10) to remove the sacrificial oxide for 5 minutes.

[0033] Once the first transistor plane 103 is formed, the insulator 105 is formed, and the polysilicon layer is converted to large grain epitaxial crystalline silicon 401, any number of additional transistor planes may be formed. FIG. 5 shows a second transistor plane 501 formed on top of the annealed and polished layer of crystalline silicon. Any type of transistor may be formed. For example, a second plane of CFETs may be formed. Each transistor plane may have its own stack of transistors. Thus, in one example, a second set of 8-12 layers of alternating SiGe / Si may be grown on the substrate. This growth may be performed using current epitaxial growth processes at low temperatures of about 300-400° C. It is noted that these are the second 12 layers on the substrate, thus making a total of 24 nanoplanes (12 silicon nanoplanes in total, 12 SiGe nanoplanes in total). Thus, each transistor plane may have multiple FETs. For example, the first transistor plane 103 may be fabricated to have a vertical stack of four FETs. Also, the second transistor plane 501 can have a vertical stack of four FETs (or two or six...). Thus, by forming two transistor planes, the substrate can have a total of 12 vertical stacks of FETs, which greatly increases the number of transistors per unit area (due to the increased transistor volume).

[0034] 6 shows how the technique can be repeated for any number of transistor planes. Each transistor plane can have a single transistor or a stack of transistors or channels. If there are multiple transistors per transistor plane, each additional transistor plane (N+1) 605 can significantly increase the total number of planes or levels of transistors on the substrate.

[0035] FIG. 7 shows that polysilicon converted to epitaxial silicon 401 is used to support the growth of a new stack of silicon layers. For example, epitaxial growth is performed to form alternating layers of silicon 701b and silicon germanium 701a, which are grown from epitaxial silicon 401. After growing this stack of silicon layers, the entire nanoplanar stack 701 can be etched to form the channel and future source / drain regions. In an exemplary embodiment, the nanoplanar stack is grown and etched in one flow with alternating layers of SiGe / Si / SiGe / Si. The channel regions are cut in the y-direction to form the future source / drain regions. The SiGe layers are then removed, leaving the Si planes. The adjacent regions of silicon are left open so that a 360-degree dielectric (called GAA - gate-all-around) is formed in each channel region, followed by the formation of metal gate electrodes designed for NMOS and PMOS devices. The source / drain regions are then made to terminate the channel.

[0036] Thus, the described technique allows multiple transistor planes, which increases density in 3D CFET and other advanced logic applications. The technique can be integrated with CFET flows, finFET flows, memory flows, and other flows. Many types of laser systems can be used for annealing, with the option to keep the substrate stationary during the laser anneal or move the substrate through the wafer beam. The technique provides high quality and reliability of microfabrication. Better silicon formation results from better silicon properties for improved mobility, Idsat, Idoff, Vtc control, and other beneficial properties. On each new plane of epitaxial silicon formed by the laser anneal, any type of logic, transistor type (including, for example, CFET, PLANER, Finfet) may be fabricated. The process described herein continues the stacking vertically to achieve the required 3D density for N+1 transistor / logic / memory planes. In the foregoing description, specific details are described, such as the specific configuration of the processing system and a description of the various components and processes used therein. However, it should be understood that the technology of the present application may be practiced in other embodiments that deviate from these specific details, and such details are for the purpose of explanation and not limitation. The disclosed embodiments are described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials, and configurations are described for a thorough understanding. However, the embodiments may be practiced without including such specific details. Components having substantially the same functional configuration are represented by similar reference numerals, and therefore any redundant description may be omitted.

[0037] To aid in understanding various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order described. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0038] As used herein, "substrate" or "target substrate" generally refers to an object to be processed by the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor device or other electronic device, for example a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying a base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular base structure, underlying or overlying layer, patterned or unpatterned, but rather is considered to include any such layer or base structure, and any combination of layers and / or base structures. In the description, reference may be made to a particular type of substrate, but this is for illustrative purposes only.

[0039] It will also be appreciated by those skilled in the art that many variations may be made to the operation of the above-described techniques while still achieving the same objectives of the present invention. Such variations are intended to be covered within the scope of the present disclosure. Accordingly, the above description of the embodiments of the present invention is not intended to be limiting. Rather, any limitations to the embodiments of the present invention are presented in the following claims.

Claims

1. 1. A method of forming a transistor device, comprising: forming a first transistor plane on a substrate as a transistor-based circuit device, the circuit device having a plurality of field effect transistors; depositing a first insulator layer on the first transistor plane; depositing a first layer of polycrystalline silicon over the first insulator layer; annealing the first layer of polycrystalline silicon using laser heating, where the laser heating increases a grain size of the first layer of polycrystalline silicon to form a first epitaxial-like silicon layer having a controlled crystal orientation; having The method, wherein the laser heating uses a pulsed laser, which is scanned at a scanning speed of 14-45 cm / s, and the temperature of the circuit device is maintained below 400° C.

2. moreover, forming a second transistor plane on the first epitaxial silicon layer, the second transistor plane having a channel of a field effect transistor; depositing a second insulator layer on the second transistor plane; depositing a second layer of polycrystalline silicon over the second insulator layer; annealing the second layer of polycrystalline silicon using laser heating, where the laser heating increases a grain size of the second layer of polycrystalline silicon to form a second epitaxial silicon layer having a crystal orientation independent of the crystal orientation of the first epitaxial silicon layer; 2. The method of claim 1, comprising:

3. 3. The method of claim 2, further comprising planarizing the first layer of polysilicon prior to depositing the second transistor planar step.

4. 3. The method of claim 2, wherein the first transistor plane has multiple levels of transistors, with one field effect transistor located directly above a second field effect transistor.

5. 10. The method of claim 1, wherein annealing the first layer of polycrystalline silicon comprises increasing a grain size such that the first layer of polycrystalline silicon is sufficiently converted into a single crystal silicon film.

6. 10. The method of claim 1, further comprising growing alternating layers of SiGe and Si on the first layer of polycrystalline silicon that has been converted to epitaxial silicon.

7. 10. The method of claim 1 , wherein annealing the first layer of polycrystalline silicon using laser heating comprises laser heating using cold water as a medium between the pulsed laser and the first layer of polycrystalline silicon.

8. The substrate is held by a wafer chuck; 10. The method of claim 1, wherein annealing the first layer of polycrystalline silicon using laser heating comprises performing laser heating while the first layer of polycrystalline silicon is in a coolant.

9. The method of claim 8 , wherein the coolant is at a temperature in the range of 400K to 30K.

10. 1. A method of forming a transistor device, comprising: forming a first transistor plane on a substrate as a first transistor based circuit device, the first transistor based circuit device having a channel of a field effect transistor; depositing a first insulator layer on the first transistor plane; depositing a first layer of polycrystalline silicon on the first insulator layer; annealing the first layer of polycrystalline silicon using laser heating, which increases grain size and provides a controlled crystal orientation in the first layer of polycrystalline silicon, using a pulsed laser scanned at a scanning speed of 14-45 cm / s, and maintaining a temperature of the first transistor-based circuit device below 400° C.; forming a second transistor plane on the first layer of polysilicon having the increased grain size as a second transistor based circuit device, the second transistor based circuit device having a channel of a field effect transistor; depositing a second insulator layer on the second transistor plane; depositing a second layer of polycrystalline silicon on the second insulator layer; annealing the second layer of polycrystalline silicon using laser heating, where the laser heating increases grain size and provides a controlled crystal orientation in the second layer of polycrystalline silicon; The method comprising:

11. 11. The method of claim 10, wherein the first transistor plane comprises a plurality of epitaxial layers sufficient to form one field effect transistor disposed directly above a second field effect transistor.

12. 11. The method of claim 10, wherein annealing the first layer of polycrystalline silicon comprises increasing a grain size such that the first layer of polycrystalline silicon is sufficiently converted into a single crystal silicon film.

13. 11. The method of claim 10, wherein the second transistor plane has multiple levels of transistors, with one field effect transistor located directly above a second field effect transistor.

14. 11. The method of claim 10, further comprising growing alternating layers of SiGe and Si on the second layer of polycrystalline silicon that has been converted to epitaxial silicon.

15. 11. The method of claim 10, wherein annealing the second layer of polycrystalline silicon using laser heating comprises performing laser heating using cold water as a medium between the pulsed laser and the second layer of polycrystalline silicon.

16. The substrate is held by a wafer chuck; 11. The method of claim 10, wherein annealing the second layer of polycrystalline silicon using laser heating comprises performing laser heating while the second layer of polycrystalline silicon is in a coolant.

17. The method of claim 16, wherein the coolant is at a temperature in the range of 400K to 30K.

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