INTERFACE FOR IMPROVED MEDIA ACCESS AND RELATED SYSTEMS, METHODS AND DEVICES

Abstract

Systems and devices are disclosed for interfacing a media access tuning circuit that implements collision handling or traffic shaping with a reduced media independent interface (RMII). In some embodiments, the interface circuit manages an emulated signal generated by the media access tuning circuit in response to detecting that the emulated signal would cause incorrect operation of the RMII. Also disclosed is a physical layer (PHY) device for a multi-drop network. In some embodiments, the PHY device implements a physical layer collision technique and is operable to communicate with a media access control (MAC) device over the RMII, where the MAC is configured for carrier sense multiple access (CSMA), CSMA / collision detect (CSMA / CD), or CSMA / collision avoidance (CSMA / CA). Also disclosed is a process for managing signaling in a PHY that implements physical layer collision avoidance (PLCA) or traffic shaping, as the case may be.

Description

[Technical field]

[0001] (Priority Claim) This application claims the benefit of Chinese Patent Application No. 201910784657.4, filed on August 23, 2019, and U.S. Patent Application No. 16 / 587,583, filed on September 30, 2019, the disclosures of each of which are incorporated herein by reference in their entireties.

[0002] (Technical field) The disclosed embodiments relate generally to physical layer devices, and more specifically, some embodiments relate to media access tuning in single-pair Ethernet physical layer devices. [Background technology]

[0003] Interconnects are widely used to facilitate communication between devices in a network. Generally speaking, electrical signals are transmitted over a physical medium (e.g., a bus, coaxial cable, or twisted pair - commonly referred to as just a "line") by devices coupled to that physical medium.

[0004] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., the electrical signal is a discrete electrical pulse) to transmit data packets and ultimately messages communicated between network devices. According to the OSI model, a dedicated circuit called a physical layer (PHY) device or controller is used to interface between the analog domain of the line and the digital domain of the data link layer, which operates according to packet signaling. Although the data link layer may include one or more sublayers, in Ethernet-based computer networking, the data link layer typically includes at least a media access control (MAC) layer, which provides a control abstraction of the physical layer. As an example, when transmitting data to another device in the network, the MAC controller may prepare a frame for the physical media, add error correction elements, and perform collision avoidance. Additionally, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare the frame for higher layers.

[0005] There are various network topologies that implement the physical layer and data link layer (among others). The Peripheral Component Interconnect (PCI) standard and the Parallel Advanced Technology Attachment (ATA) have both implemented a multi-drop bus topology since the early 1990s. Since the early 2000s, the trend has been to use a point-to-point bus topology; for example, the PCI Express standard and the Serial ATA (SATA) standard implement a point-to-point topology.

[0006] A typical point-to-point bus topology may implement circuits between each device (e.g., dedicated point-to-point) or circuits between the devices and a switch (e.g., switched point-to-point). In a multi-drop topology, however, the physical medium is a shared bus and each network device is coupled to the shared bus via circuitry that is selected based on, for example, the type of physical medium (e.g., without limitation, coax or twisted pair).

[0007] Point-to-point bus topologies, such as dedicated point-to-point or switched point-to-point topologies, require more wires and more expensive materials than multi-drop topologies, due in part to the larger number of links between devices. In certain applications, such as automobiles, there may be physical constraints that make it difficult to directly connect devices, and thus topologies that do not require, or do not require as many, direct connections within a network or sub-network (e.g., multi-drop topologies) may be less susceptible to such constraints.

[0008] Devices in a baseband network share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission. As a result, only one device in a baseband network may transmit at a given moment. Therefore, media access control methods are used to handle contention for the shared transmission medium.

[0009] In a bus network topology where the physical transmission medium is shared, one technique used to avoid collisions (i.e., when two or more devices try to transmit simultaneously on the shared bus) is Carrier-Sense Multiple Access (CSMA), a MAC protocol that runs at the data link layer. With CSMA, a node verifies that there is no other traffic before transmitting on the shared bus. More specifically, a node checks the common bus for a carrier and, if it detects a carrier, waits until the carrier is no longer detected (i.e., the channel is idle) before beginning transmission. CSMA is sometimes extended to include Collision Detection (CSMA / Collision Detection, CD), whereby a node not only detects and responds to collisions that occur while transmitting, but also tries to avoid collisions.

[0010] Another option is to implement collision avoidance in the PHY. Physical Layer Collision Avoidance (PLCA) is a technique whereby the PHY transmits only frames received from the MAC during an assigned transmission opportunity. As an example, transmission opportunities may be allocated according to a scheduling scheme (e.g., round robin, weighted round robin, deficit round robin, first-in-first-out, priority-based, or multi-level queue Precision Time Protocol (PTP) scheduling). In such a scenario, at a given transmission opportunity, only the PHY that owns the particular transmission opportunity is allowed / expected to transmit data. 10SPE (i.e., 10Mbps Single Pair Ethernet) is a network technology currently under the IEEE 802.3cg™ specification, and the 10SPE specification includes an optional PLCA reconciliation sublayer, which theoretically could be used to avoid collisions on a multi-drop bus. While the disclosure concludes with claims that particularly point out and distinctly claim certain embodiments, the various features and advantages of embodiments within the scope of the present disclosure can be more readily ascertained from the following description when read in conjunction with the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of a multi-drop network in accordance with one or more embodiments of the present disclosure. [Diagram 2] FIG. 1 is a timing diagram illustrating a collision handling process in a physical layer device in accordance with one or more embodiments of the present disclosure. [Figure 3A] FIG. 2 is a timing diagram illustrating data transmission in a physical layer device in accordance with one or more embodiments of the present disclosure. [Figure 3B] 3B is a timing diagram illustrating a set of signals for the data transmission of FIG. 3A in accordance with one or more embodiments of the present disclosure. [Figure 4] FIG. 1 is a timing diagram illustrating data reception at a physical layer device in accordance with one or more embodiments of the present disclosure. [Diagram 5] FIG. 2 is a block diagram of a physical layer device in accordance with one or more embodiments of the present disclosure. [Figure 6] FIG. 2 is a block diagram of an emulation circuit for correcting the propagation of an emulated signal generated by a media access tuning circuit in accordance with one or more embodiments of the present disclosure. [Figure 7] 1 is a flowchart of a process for managing a carrier sense signal in accordance with one or more embodiments of the present disclosure. [Figure 8] 1 is a flowchart of a process for managing carrier sense signaling in a receiving physical layer device / system after a collision on a shared transmission medium in accordance with one or more embodiments of the present disclosure. [Figure 9] 1 is a flowchart of a process for managing a carrier sense signal in a transmit PHY in accordance with one or more embodiments of the present disclosure. [Figure 10]1 is a flowchart of a process for managing a carrier sense signal in a time-aware or traffic-shaping receive PHY in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific exemplary embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be used, and structure, materials, and processes may be changed without departing from the scope of the present disclosure.

[0013] The figures presented herein are not intended to be actual diagrams of any particular method, system, device, or structure, but merely idealized representations used to describe embodiments of the present disclosure. The figures presented herein are not necessarily drawn to scale. Similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0014] It will be readily understood that the components of the embodiments as generally described and illustrated in the Figures herein could be arranged and designed in a wide variety of different configurations, and thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments.

[0015] The following description may include examples to assist those skilled in the art in enabling the disclosed embodiments to be practiced. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory, and the scope of the disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the embodiments or the scope of the disclosure to specific components, steps, features, functions, etc.

[0016] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic between various blocks are exemplary specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted, and such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of one skilled in the art.

[0017] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout this specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signals as a single signal for clarity of presentation and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0018] As used herein, the terms "substantially" and "about" when referring to a given parameter, characteristic, or condition mean and include the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition satisfies some degree of variation, such as within acceptable manufacturing tolerances. For example, a parameter that is substantially or about a particular value may be at least about 90% of the particular value, at least about 95% of the particular value, at least about 99% of the particular value, or even at least about 99.9% of the particular value.

[0019] Any reference to elements herein using designations such as "first," "second," etc., should be understood not to limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. Also, unless otherwise stated, a set of elements may include one or more elements. Similarly, an element sometimes referred to in the singular form may also include one or more instances of the element.

[0020] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, although alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer, and the general purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0021] It should also be noted that the embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in another sequence, in parallel, or substantially simultaneously. Additionally, the order of the acts may be rearranged. A process may correspond to, but is not limited to, a method, a thread, a function, a procedure, a subroutine, and / or a subprogram. Furthermore, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0022] As used herein, a "buffer" refers to an area of ​​physical memory used to temporarily store data. As a non-limiting example, a buffer may be used to temporarily store data while it is being moved from one location (e.g., in memory, in a system, in a network) to another location or from one device to another. The buffers of the disclosed embodiments may implement algorithms such as first-in-first-out (FIFO). The buffers of the disclosed embodiments may be timed or untimed by design, i.e., data may be written to the memory at a first rate and data may be read from the memory at a second rate, where the first rate and the second rate may be the same or different.

[0023] It is often desirable to use a simplified interface that reduces the number of connections between the PHY and the MAC. Techniques for reducing multiple data connections are to multiplex the signals onto one line and use a higher clock frequency. Similar techniques can be used for control signals, but assumptions often need to be made about which control signals are needed / used at a given time under given conditions.

[0024] The Reduced Media Independent Interface™ (RMII™) or “RMI interface” is an example of a simplified interface that may be used to connect a PHY to a MAC. The RMII Consortium specification (version 1.2 published March 20, 1998) specifies an additional reconciliation layer to the IEEE 802.3 Media Independent Interface (MII) specification. RMII specifies the convolution of the Carrier Sense (CRS) and Receive Data Valid (DV) signals onto one pin (carrying the CRS_DV signal). RMII further specifies that CRS_DV should be asserted by the PHY whenever a carrier is sensed on the receive media (i.e., the receive media is non-idle). The DV signal informs the MAC that the incoming data on RXD[1:0] (the MAC's receive data pins) (i.e., coming into the MAC) is valid data.

[0025] The CRS and DV are typically multiplexed into one signal that appears on a single pin on alternating clock cycles. For example, in a 10BASE-T or 100BASE-X network, the multiplexed signals might alternate at 2.5 MHz (10 Mb / s mode) or 25 MHz (100 b / s mode), respectively.

[0026] RMII specifies that loss of carrier in the receive medium results in deassertion of CRS_DV. If the PHY has additional bits presented on RXD[1:0] following the first deassertion of CRS_DV, the PHY asserts CRS_DV on the cycle of REF_CLK that presents the second dibit of each nibble and deasserts CRS_DV on the cycle of REF_CLK that presents the first dibit of the nibble.

[0027] RMII also specifies that when CRS_DV is asserted, the data on the receive line (RXD[1:0]) is considered valid, but because the assertion of CRS_DV is asynchronous to the reference clock, a "no valid data present code" (e.g., two bytes of zeros or "00") is inserted on RXD[1:0] until proper receive signal decoding occurs. Thus, both the no valid data present code on RXD[1:0] and a deasserted CRS_DV may be used by the RMII MAC to infer that the medium is idle, the asserted CRS_DV and the no data valid present code on RXD[1:0] may be used by the RMII MAC to infer that reception is about to begin, and the asserted CRS_DV and the change from the no valid data present code to another code (e.g., a preamble byte) may be used by the RMII MAC to infer that valid data is arriving.

[0028] RMII also specifies an elastic buffer on the receive line to account for differences between the recovered clock and the local clock for received data (i.e., clock alignment), enabling domain crossing.

[0029] For data transmission, RMII assumes that the transmit enable (TX_EN) pin is an accurate indication of transmission, that the MAC can infer collisions from TX_EN (TX_EN is asserted by the MAC synchronously with the first nibble of the preamble of the first transmitted frame), and that the recovered CRS (i.e., recovered from CRS_DV) - an asserted CRS indicates that the receive media is active.

[0030] The inventors of the present disclosure have appreciated that it would be advantageous if a simplified interface, such as RMII, could be used to communicate between a PHY configured to perform CSMA / CDMAC and medium access tuning in accordance with, by way of non-limiting example, PLCA, time aware protocols, traffic shaping, and / or combinations thereof.

[0031] When a PHY implements media access tuning, certain internal signals may be emulated. For example, the media access tuning circuitry may generate emulated signals based on internal logic instead of faithfully replicating (i.e., propagating) internal signals, for example, because it is attempting to cause a particular behavior at the link layer.

[0032] An emulated version of the carrier sense signal (i.e., a signal indicating the presence or absence of a carrier on the shared transmission medium), which determines the assertion / deassertion of CRS_DV at the RMI interface, may disrupt correct operation of the CSMA / CD MAC, the RMI interface, or both. In other words, differences between the emulated signal generated by the media access tuning circuitry and the emulated internal signal may disrupt correct operation of the RMII MAC, the RMI interface, or both.

[0033] Furthermore, RMII was written for a network topology with separate transmission media for receiving and transmitting (either two separate lines or one line with two signals superimposed on one line). According to RMII, an asserted carrier sense signal means that there is an active carrier on the receiving medium. As described herein, the media access tuning protocol described in this disclosure assumes that an asserted carrier sense signal means that there is an active carrier on the shared transmission medium and does not make a distinction between the medium for receiving and the medium for transmitting.

[0034] One or more embodiments of the present disclosure generally relate to managing signaling between a media access tuning circuit and an RMI interface to ensure correct operation of the RMI interface, a CSMA / CD MAC communicated over the RMI interface, or both.

[0035] As used herein, the term "assert" used in connection with a signal is intended to encompass a signal that transitions to an active state, a signal that is in an active state, and a signal that transitions to an active state and then is in an active state. As used herein, the term "deassert" used in connection with a signal is intended to encompass a signal that transitions to an inactive state, a signal that is in an inactive state, and a signal that transitions to an inactive state and then is in an inactive state. As a non-limiting example, for a pin that is in an active high state, when asserted, a signal that is in a logic high state (e.g., 3.3 volts or 5 volts) will appear, and when deasserted, a signal that is in a logic low state (e.g., but not limited to, 0 volts) will appear. Other arrangements, such as an active low state, are within the scope of this disclosure.

[0036] 1 is a functional block diagram of a multi-drop network 100 including at least two media access control (MAC) devices, MAC device 102 and MAC device 106. As non-limiting examples, multi-drop network 100 may be, be part of, or include one or more of a microcontroller-based embedded system, a user-type computer, a computer server, a notebook computer, a tablet, a handheld device, a mobile device, a wireless earphone or headphone device, a wired earphone or headphone device, an appliance subsystem, a lighting subsystem, an audio subsystem, a building control system, a home surveillance system (e.g., but not limited to, for security or utility use), an elevator system or elevator subsystem, a public transportation control system (e.g., but not limited to, for above-ground trains, underground trains, streetcars, or buses), an automobile system or automobile subsystem, or an industrial control system.

[0037] PHY device 104 and PHY device 108 are configured to interface a shared transmission medium 110 with MAC device 102 and MAC device 106, respectively. As a non-limiting example, PHY device 108 and PHY device 104 may be chip packages including memory and / or logic configured to perform all or a portion of the embodiments described herein.

[0038] Shared transmission medium 110 is the physical medium that is the communication path for nodes that are part of multi-drop network 100, including nodes including MAC device 102 and MAC device 106.

[0039] 1, PHY devices 104 and 108 are configured to manage access to shared transmission medium 110 (e.g., according to a PLCA, time-aware protocol, or traffic shaping protocol), and MAC devices 102 and 106 are configured to implement collision detection (e.g., according to CSMA / CD or CSMA). PHY devices 104 and 108 are configured to provide signaling (as described more fully herein) to ensure correct operation of MAC devices 102 and 106, respectively. Additionally, PHY devices 104 and 108 communicate with MAC devices 102 and 106, respectively, via their respective RMI interfaces.

[0040] Figures 2 and 3 A, Figure 3B 2 and 3 are timing diagrams illustrating signals asserted at the pins of the RMI interfaces of PHY device 104 and PHY device 108 during an exemplary process. A, 3B, and 4 show signals asserted for transmit enable (TX_EN), emulated carrier sense (CRS), data valid (RDV), (CRS_DV), and receive data (RXD[1:0] or simply "RXD"). For PHY device 108, the signal at the collision pin (COL) is also shown in FIG. 2 and is internal to PHY device 108. Additionally, a second emulated carrier sense (second emulated CRS) signal is shown and is internal to PHY devices 104 and 108, and corresponds, for example, to second emulated carrier sense signal 522 of FIG. 5.

[0041] Figures 2 and 3 A, Figure 3B , and in FIG. 4, the "no valid data present" code (here, "0") is transmitted via the RXD line 220 (FIG. 2), 310 (FIG. 3) A ), and 410 (FIG. 4), and the PHY devices 104 and 108 do not transmit receive data or preamble codes to the MAC devices 102 and 106, respectively. Also, signals for receive data valid (RDV), particularly RDV232 (FIG. 2), RDV332 (FIG. 3), A ), and RDV 446 (FIG. 4), are illustrated, each being an internal signal to PHY device 104 or 108, as the case may be. The RDV signal is illustrated to show when the DV portion of CRS_DV is asserted. In some embodiments, the RDV signal may be generated internally and used to generate the CRS_DV signal. In other embodiments, PHY devices 104 and 108 may be configured to monitor RDX and deassert the DV portion of CRS_DV in response to a no valid data present code, and assert the DV portion of CRS_DV in response to detecting the presence of valid data.

[0042] Those skilled in the art will appreciate that unless specific timing considerations are described herein for a particular embodiment, FIG. A ,Figure 3 B, and it will be understood that variations in the timing shown and described with reference to FIG. 4 may be made without departing from the scope of the embodiments described in this disclosure and their legal equivalents.

[0043] 2 is a detailed timing diagram of an embodiment of a process 200 for performing media access tuning during data reception after detecting a collision in a PLCA PHY. In the operations contemplated by FIG. 2, PHY device 108 is a PLCA PHY that detects a collision when its MAC device 106 attempts to transmit during a transmission opportunity 210. After detecting the collision, PHY device 108 receives data from a data transmission from PHY device 104.

[0044] At time 202 , TX_EN 216 is asserted in the PHY device 108 .

[0045] At time 204, the PHY device 108 asserts CRS_DV 218 in response to detecting a carrier on line 224 as reflected by asserted signal RDV 232 (time 204 substantially corresponds to the start of the transmission opportunity 210). At time 206, the PHY device 108 detects a collision as indicated by the assertion of internal signal COL. The PHY device 108 continues to assert CRS_DV 218 while receiving data. At time 212, the PHY device 108 detects the end of the receive data received during the transmission opportunity 210 and signal RDV 232 is deasserted.

[0046] The PHY device 108 is configured to detect the end of the received data based on detecting a carrier going idle (i.e., a transition from an active state to an idle state on line 224). At time 212, the PHY device 108 deasserts CRS_DV 218 for a period of time and then reasserts CRS_DV 218 to form a gap 214 in CRS_DV 218.

[0047] The gap 214 on the CRS_DV 218 indicates the end of valid data that is detectable by the CSMA / CD MAC (i.e., it is an "end of valid data signal"). In one embodiment, a gap width is selected for the gap 214 such that the gap 214 has a period that is short enough that the CSMA / CD MAC does not initiate a data transmission.

[0048] In one embodiment, the gap 214 in the CRS_DV 218 is generated in response to a gap 230 formed beginning at time 228 in the second emulated CRS 226. In one embodiment, the gap 230 is formed at time 228 in response to a first emulated CRS signal (not shown) generated by a media access tuning circuit of the PHY device 108 configured for PLCA. The second emulated CRS 226 (i.e., the signal including the gap) is provided to the RMI interface of the PHY device 108. The RMI interface generates the gap 214 in the CRS_DV 218 to indicate the end of data reception to the MAC device 106, along with a no valid data present code 222 on RxD 220 (zero "0" in FIG. 2) to indicate the end of the received data. In one embodiment, the width of gap 230 is selected such that the gap 214 generated in CRS_DV 218 in response to gap 230 is short enough that the CSMA / CD MAC does not initiate a data transmission.

[0049] After inserting the end of valid data indicator, i.e., gap 214, in CRS_DV 218, the PHY device 108 continues to assert CRS_DV 218 until it initiates a transmit opportunity 208 at time 228, which is the next transmit opportunity for the PHY device 108. In one embodiment, CRS_DV 218 is asserted because the second emulated CRS 226 is asserted, so the RMI interface of the PHY device 108 infers an active carrier on line 224. Additionally, while waiting to initiate the transmit opportunity 208, the PHY device 108 inserts a no valid data present code 222 (here, "0") and the second emulated CRS 226 is asserted.

[0050] FIG. 3A is a detailed timing diagram of a process 300 for performing media access tuning during data transmission, according to a disclosed embodiment. A In the operation contemplated by the present invention, the PHY device 104 is a PLCA PHY and is a CSMA / CD M Transmission is handled by AC.

[0051] At time 312, the PHY device 104 deasserts CRS_DV 308 after detecting the absence of a carrier on the line 302. At time 314, TX_EN 306 is asserted (e.g., by the MAC device 102) at the PHY device 104. Notably, the transmit opportunity 304 is the next transmit opportunity for the PHY device 104 and does not start until time 316. In this embodiment, the PHY device 104 includes a delay line (described later in this specification) for the transmit data, so that even though TX_EN 306 is asserted at time 314, the PHY device 104 does not start moving the transmit data to the line 302 until time 316 (i.e., the start of the transmit opportunity 304).

[0052] As mentioned above, RMII was written for networks with separate transmission media for receiving and transmitting (either two separate lines or one line with two signals superimposed on one line). An "active" medium, according to RMII, means that the receiving medium is active. If the PLCA circuit generates an asserted CRS that is propagated by RMII to the RMII MAC as CRS_DV 308, the RMII MAC will interpret the asserted CRS_DV 308 at time 314 as meaning that the receiving medium is active and will infer a collision. Therefore, in the disclosed embodiment, the PHY device 104 may be configured to suppress the asserted emulated CRS (not shown in FIG. 3A ) generated by the PLCA while waiting for a transmission opportunity to begin. In the example shown in FIG. 3A , this occurs between time 314 when TX_EN is asserted and time 318 when TX_EN is deasserted.

[0053] Figure 3B illustrates the CRS_DV 308 and second emulated CRS 326 of Figure 3A along with the first emulated CRS 332 and actual CRS 334 between time 314 and time 324, i.e., between the assertion of TX_EN 306 and the end of the transmission opportunity 304. In the embodiment illustrated in Figure 3B, the actual CRS 334 corresponds to a carrier sense signal (such as signal 518 in Figure 5) generated by a carrier sense circuit monitoring the shared transmission medium. For ease of explanation, timing labels for the assertion and deassertion of TX_EN 306 and the transmission opportunity 304 of line 302 are illustrated in Figure 3B and used in the associated explanation.

[0054] Assume that at time 314, PLCA of PHY device 104 generates an asserted emulated CRS 332 in response to TX_EN 306 being asserted to indicate to CSMA / CD MAC that line 302 is active (i.e., to trick CSMA / CD MAC that transmission data is being moved to line 302), and PLCA will ignore CSMA / CD MAC for collision handling purposes. During time period 336, i.e., from time 314 to time 316, PHY device 104 suppresses PLCA emulated CRS 332 from being transmitted to MAC device 102, i.e., in other words, PHY device 104 generates a second emulated CRS 326 that is deasserted during time period 336, and thus CRS_DV 310, which is asserted / deasserted in response to the second emulated CRS 326, is also deasserted during time period 336. At time 316, the actual CRS 334 is asserted in response to the PHY device 104 moving data onto the line 302 at the beginning of the transmission opportunity 304. The PLCA-emulated CRS 332 continues to be asserted at time 316 and remains asserted until the PHY device 104 completes moving the transmission data onto the line 302 at time 324, i.e., until the end of the transmission opportunity 304. During time period 338, i.e., the period from time 316 to time 318, the PHY device 104 suppresses the PLCA-emulated CRS 332 from being transmitted to the MAC device 102 to avoid CSMA / CDMAC inferring a collision, which may be characterized as suppressing the actual CRS 334 from being transmitted to the MAC device 102. In response to the second emulated CRS 326 being deasserted during period 336 and during period 338, CRS_DV 310 is deasserted from time 314 until time 318 (when TX_EN 306 is asserted). Returning to Figure 3B, at time 318, TX_EN 306 is deasserted to indicate that the MAC device 102 has completed providing data for transmission to the PHY device 104.Notably, the PHY device 104 does not finish moving the transmit data onto the line 302 until time 324, i.e., the end of the transmit opportunity 304. Thus, in response to detecting TX_EN 306 being deasserted (i.e., transitioning from high to low) at time 318, and in response to detecting data still waiting to be transmitted in the transmit delay line, the PHY device 104 “pulses” CRS_DV 308 from time 318 to time 322 (i.e., asserts CRS_DV 308 at time 320 and then deasserts CRS_DV 308 at time 322), which substantially corresponds to the period from time 324 when the MAC deasserts TX_EN 306 to time 324 when the PHY device 104 finishes moving the transmit data onto the line 302.

[0055] 3A and 3B, the PHY device 104 pulses the CRS_DV 308 (FIG. 3A) in response to the second emulated CRS 326 being asserted from time 328 to time 330. The period during which the second emulated CRS 326 is asserted is shown in FIG. 3B as period 342, which is from time 318 to time 324.

[0056] 3B, the second emulated CRS 326 pulses during a period 342 in response to TX_EN 306 being deasserted at time 318 while the transmit data remains in the transmit delay line. Pulsing CRS_DV 308 signals the CSMA / CD MAC of the MAC device 102 that initiating another transmission would cause a collision on line 302, and thus the collision avoidance logic in such MAC device 102 prevents the MAC device 102 from initiating another transmission while CRS_DV 308 is high.

[0057] At time 320, when CRS_DV 308 is asserted, a no valid data code (here a "0" code) is inserted at RxD 310, otherwise the CSMA / CD MAC may begin data reception and begin receiving its own data. As noted above, using the exemplary operation shown in Figure 3B, the RMII provisions dictate that the MAC will look for a transition from "00" to "not 00" in combination with an asserted CRS_DV to begin data reception.

[0058] 4 is a detailed timing diagram of a media access process 400 in accordance with one or more embodiments of the present disclosure. In the scenario illustrated in FIG. 4, the PHY device 108 is configured to be time-aware (or to use traffic shaping, as described in more detail below), i.e., the transmission opportunities of the PHY device 108 are scheduled based on the network's master clock, using, as a non-limiting example, the Precision Time Protocol ("PTP") under the IEEE 1588™ specification. Of note, TX_EN 406 is shown for informational purposes and does not limit the generality of FIG. 4.

[0059] In the embodiment shown in Figure 4, the PHY device 108 is configured to keep the MAC in a deferral state by asserting CRS_DV 408 with no valid data present on RxD 410 code "0" except for its assigned transmission window, here transmission window 446, in which case CRS_DV 410 should be deasserted. Thus, in the exemplary operation contemplated by Figure 4, the PHY device 108 asserts CRS_DV 408 while waiting for a possible reception within the transmission window 404 to begin at time 414. At time 416 (substantially corresponding to time 414), the PHY device 108 deasserts CRS_DV 408 in response to detecting the start of a received frame (e.g., detecting a preamble) and then reasserts CRS_DV 408 at time 418, i.e., creating a gap 444 after a predetermined gap time.

[0060] In one embodiment, the PHY device 108 generates a gap 444 in the CRS_DV 408 from time 416 to time 418 in response to the gap 432 generated in the second emulated CRS 428 from time 430 to time 434. More specifically, the RMI interface of the PHY device 108 interprets the high-to-low transition of the second emulated CRS 428 at time 430 as meaning that an active carrier is not present on the line 402, and therefore deasserts the CRS_DV 408. When the second emulated CRS 428 is reasserted at time 434, the RMI interface interprets the low-to-high transition at time 434 as meaning that an active carrier is present on the line 402, and therefore asserts the CRS_DV at time 418. The width of the gap 432 created in the second emulated CRS 428 may be selected such that the width of the gap 444 in the CRS_DV 408 is short enough that the MAC does not begin transmitting while CRS_DV 408 is deasserted.

[0061] Notably, the gap 444 from time 416 to time 418, and more particularly the low-to-high transition at time 418, is interpreted by the CSMA / CD MAC to mean that if the "no valid data code" 422 changes to another code, it (the MAC) may begin receiving data. As a non-limiting example, the CSMA / CD MAC will infer that the PHY device 108 may begin transmitting a receive frame (i.e., detect that data reception may begin) in response to the assertion of CRS_DV 408 at time 418 and the "00" data on RXD 410, and will infer the start of data reception upon detecting the preamble of a data frame (not shown) on RXD 410. Thus, the gap 444 in CRS_DV 408 beginning at time 416 allows for appropriate signaling to the CSMA / CD MAC so that it can wait to receive data after being held in a deferred state by the time-aware PHY device 108.

[0062] At time 424, the PHY device 108 inserts a gap 440 in the CRS_DV 408 at the end of the receive data transfer (i.e., inserts the gap 440 from time 424 to time 426), and RxD 410 is 0 at time 420, which is substantially the same as at time 424. In one embodiment, the PHY device 108 inserts the gap 440 in the CRS_DV 408 in response to the gap 442 from time 438 to time 436 being generated in the second emulated CRS 428. The RMI interface of the PHY device 108 interprets the gap in the second emulated CRS 428 as meaning that data reception has ended, and therefore generates a CRS_DV 408 in which the gap 440 starts at time 424 and ends at time 426. Notably, the gap 440 is inserted in the CRS_DV 408 in which the gap 440 starts at time 424 and ends at time 426. 08 If the CSMA / CD MAC was not inserted into RxD 410, the CSMA / CD MAC would continue to receive data on RxD 410. In other words, the MAC would receive the "00" code starting at time 420 as if it were valid data.

[0063] The same timing diagram shown in FIG. 4 also applies to the media access process, in which the PHY device 108 shapes traffic by holding its MAC in a deferred state until its internal shaping algorithm (instead of an external PTP-based scheduling algorithm) indicates a transmission opportunity for the MAC.

[0064] 5 is a simplified block diagram of a physical layer system 500 including a Collision Avoidance (CA) interface circuit 508 configured to enable use of a media access tuning circuit 516 with link layer devices, more specifically, link layer devices configured to operate according to CSMA, CSMA CA, CSMA / CD, or a combination thereof. In the embodiment shown in FIG. 5, the physical layer system 500 includes a media access tuning circuit 516, an interface circuit 508, and an RMI interface 506, as well as a carrier sense circuit 502 and a transmit circuit 504. The carrier sense circuit 502 and the transmit circuit 504 are operably coupled to a shared transmission medium 534.

[0065] The media access tuning circuitry 516 may generally be configured to perform, among other things, collision handling, traffic shaping, or both. In the embodiment shown in Figure 5, the media access tuning circuitry 516 is configured to manage access (e.g., for transmission and reception) to the shared transmission medium 534 according to a media access protocol, by way of non-limiting example, a collision handling protocol, a traffic shaping protocol, or both.

[0066] 5, the media access tuning circuit 516 includes a first emulation circuit 528, a transmit buffer 512, and a receive buffer 510. The first emulation circuit 528 is configured to generate a first emulated carrier sense signal 520 in response to the carrier sense signal 518 generated by the carrier sense circuit 502 and the applicable media access protocol of the media access tuning circuit 516. In some cases, the first emulated carrier sense signal 520 generated by the emulation circuit 528 may not be a faithful replica of the carrier sense signal 518. As a non-limiting example, the media access tuning circuit 516 may be configured to provide the first emulated carrier sense signal 520 when the carrier sense signal 518 does not indicate the presence of a carrier on the shared transmission medium 534. As a non-limiting example, the first emulation circuit 528 may be configured to generate the first emulated carrier sense signal 520 in accordance with a physical layer collision handling protocol, whereby the first emulated carrier sense signal 520 is provided while waiting for the next assigned transmission window or the next transmission opportunity (as the case may be).

[0067] The interface circuit 508 may include a second emulation circuit 530 configured to generate a second emulated carrier sense signal 522 in response to the first emulated carrier sense signal 520 provided by the media access tuning circuit 516 and certain detected conditions related to generating correct signaling at the RMI interface 506. The interface circuit 508 may be configured to add signaling to the first emulated carrier sense signal 520, i.e., modify the first emulated carrier sense signal 520 to include the added signaling. In a disclosed embodiment, the second emulation circuit 530 may be configured to monitor the media access tuning circuit 516 and the RMI interface 506. In the embodiment shown in FIG. 5, the second emulation circuit 530 is configured to monitor the transmit buffer 512 and the receive buffer 510 of the media access tuning circuit 516, as well as monitor the transmit enable 524 of the RMI interface 506.

[0068] The physical layer system 500 may be configured to transmit a no valid data present code to the MAC while the physical layer system 500 is not transmitting a received or sync frame. In one embodiment, the interface circuit 508 is configured to insert a no valid data present code into the receive buffer 510 while the physical layer system 500 is not transmitting a received or sync frame to the MAC. The interface circuit 508 may include an insertion circuit for inserting a no valid data present code into the receive buffer 510 as described with reference to Figures 2, 3A, 3B, and 4. In one embodiment, the second emulation circuit 530 may be configured to insert a no valid data present code into the receive buffer 510 or, alternatively, into the receive data 532 (an alternative embodiment is indicated in Figure 5 by dashed lines from the second emulation circuit 530 to the receive buffer 510 and the receive data 532).

[0069] The second emulation circuit 530 may be configured to generate a second emulated carrier sense signal 522 in response to a detected condition (i.e., without limitation, “empty”, “buffering”, “active” or “inactive”, “active to inactive” or “inactive to active”) or content (e.g., without limitation, a predefined code) from such monitoring, including enabling correct signaling of the RMI interface 506, such as the CRS_DV signal described with reference to Figures 2, 3B, and 4. Additionally or alternatively, the second emulation circuit 530 may be configured to monitor the transmit data 526 and receive data 532 in addition to or instead of monitoring the transmit buffer 512 and receive buffer 510, respectively.

[0070] The RMI interface 506 is configured to receive a second emulated carrier sense signal 522 from the interface circuit 508 and provide it to the carrier and data 514. In a disclosed embodiment, the carrier and data 514 may be associated with an output pin of one or more input / output (I / O) pins of the physical layer system 500. The output pin may be associated with a carrier sense signal (e.g., CRS_DV) as described herein. In one embodiment, the RMI interface 506 provides a carrier sense signal (illustrated as an input signal 536 to the carrier and data 514). 5 5. In one embodiment, the RMI interface 506 may include multiplexing circuitry for multiplexing the second emulated carrier sense signal 522 along with the DV signal (shown in FIG. 5) on the carrier and data 514. In another embodiment, the RMI interface 506 may include circuitry for asserting a CRS signal corresponding to the second emulated carrier sense signal 522 on the carrier and data 514 and asserting a DV signal on each alternate clock cycle.

[0071] 6 is a functional block diagram of an emulation circuit 600, which may be, for example, an implementation of the second emulation circuit 530 (FIG. 5), in accordance with one or more embodiments of the present disclosure. In the embodiment shown in FIG. 6, the emulation circuit 600 includes a correction circuit 604 and a signal generation circuit 610.

[0072] The correction circuit 604 is generally configured to control the signal generation circuit 610 to generate a second emulated carrier sense signal 612. The correction logic 608 of the correction circuit 604 may be configured to detect that the first emulated carrier sense signal 602 would cause inaccurate signaling, for example, at the RMII interface 506, and to control the signal generation circuit 610 to generate the second emulated carrier sense signal 612 to correct at least some of the possible errors. The register 606 may be configured to store parameters for detecting the condition and / or for generating the second emulated carrier sense signal 612. The parameters for generating the second emulated carrier sense signal 612 may be configured to be different for different use cases (e.g., FIG. 2, FIG. 3). A, Figure 3B , and the case described with reference to FIG. 4 ), may include a predetermined gap size or multiple predetermined gap sizes.

[0073] In some embodiments, the compensation logic 608 may be configured based on the type of collision avoidance protocol used in the PHY device that includes the emulation circuit 600. As a non-limiting example, the compensation logic 608 may be configured to detect conditions related to media access tuning, collision avoidance, traffic shaping, or a combination thereof. The parameters stored in the registers 606 may also be selected based on the type of collision avoidance protocol. Furthermore, in some embodiments, the registers 606 may be reconfigurable. As a non-limiting example, the gap size may be pre-set to conform to a standard and then later reconfigured to conform to a different standard. In one embodiment, the registers 606 may allow tuning the compensation circuit 604 to the characteristics of different devices (e.g., MACs from different suppliers, PHY components from different suppliers, or PHYs with different architectures).

[0074] FIG. 7 illustrates a process 700 for managing signaling at a physical layer device in accordance with one or more embodiments of the present disclosure. At operation 702, a carrier of a shared transmission medium is sensed at a physical layer device. At operation 704, a first emulated carrier sense signal is received. The first emulated carrier sense signal is generated by a media access tuning circuit, such as, for example, but not limited to, media access tuning circuit 516 (performing PLCA). At operation 706, a second emulated carrier sense signal is generated. In various embodiments, the second emulated carrier sense signal may be generated in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling at the RMII. As a non-limiting example, the second carrier sense signal may be generated by modifying a portion of the first emulated carrier sense signal.

[0075] At operation 708, a second emulated carrier sense signal is provided to the RMII. At operation 710, one of one or more input / output (I / O) pins of the physical layer device at which the output signal appears is asserted or deasserted. The output pin may be associated with the carrier sense signal of the RMII. In one embodiment, the output pin is associated with a multiplexed carrier sense and data valid signal of the RMII (i.e., signal CRS_DV). Such multiplexed carrier sense and data valid signal may be asserted / deasserted in response to the second emulated carrier sense signal provided to the RMII at operation 708.

[0076] In the disclosed embodiment, the second emulated carrier sense signal 522 may be generated using any suitable technique known to one of ordinary skill in the art. As a first non-limiting example, the second emulated carrier sense signal 522 may be generated by modifying the first emulated carrier sense signal 520. Modifying a signal may involve, as a non-limiting example, modifying another signal using filtering techniques. As another non-limiting example, modifying a new signal may involve generating a new signal using the first emulated carrier sense signal as a reference signal. The new signal may be substantially identical in all respects to the reference signal except for the modified portion. As a second non-limiting example, the second emulated carrier sense signal may be generated as a new signal in response to logic such as the correction logic 608 of FIG. 6.

[0077] 8 illustrates a process 800 for managing carrier sense signaling in a receiving physical layer device / system, such as, but not limited to, the physical layer system 500, after a collision on a shared transmission medium, according to one or more disclosed embodiments. In operation 802, the physical layer system 500 receives data (e.g., receives a transmission frame) associated with a data transmission to the shared transmission medium 534. In operation 804, a collision is detected on the shared transmission medium 534. The physical layer system 500, and more specifically the media access tuning circuitry 516, may detect the collision, as a non-limiting example, in response to transmit enable 524 being asserted (e.g., by a MAC device), and a carrier sense signal 518 (indicating the presence of a carrier on the shared transmission medium 534) is generated. Of note, a CSMA link layer device (not shown) coupled to the physical layer system 500 may implement aspects of its collision detection protocol (e.g., transmit a short jam sequence of frames and back off for a random period of time).

[0078] In operation 806, the physical layer system 500 receives a data frame associated with a data reception from the shared transmission medium 534 (i.e., receives a "received frame"). As a non-limiting example, the received frame of the data reception in operation 806 may be associated with a collision detected in operation 804. For example, the received frame of the data reception may be from the physical layer device / system that owns the current transmission opportunity, or may simply correspond to a detected carrier that caused the collision to be detected.

[0079] 8, a first emulation circuit 528 of the media access tuning circuit 516 generates a first emulated carrier sense signal 520 in response to collision handling logic and the carrier sense signal 518. In contemplated operation, depending on its collision handling logic, the first emulation circuit 528 may generate a first emulated carrier sense signal 520 that either faithfully replicates the carrier sense signal 518 or that differs from the carrier sense signal 518.

[0080] In operation 808, the interface circuit 508 receives the first emulated carrier sense signal 520 from the media access tuning circuit 516. In operation 810, the interface circuit 508 determines whether the receive buffer 510 is empty. Notably, in this embodiment, if the receive buffer 510 is empty, that is a condition that triggers the interface circuit 508 to modify the first emulated carrier sense signal 520 to enable correct signaling at the RMI interface 506. If the receive buffer 510 is not empty (i.e., still stores received frames), in operation 812, the second emulated carrier sense signal 522 generated by the interface circuit 508 is a faithful replica of the first emulated carrier sense signal 520, and the process 800 loops back to operation 808. If the receive buffer 510 is empty (e.g., no frames remain in the receive buffer 510), then in operation 814 the interface circuit 508 generates a second emulated carrier sense signal 522 to be a modified emulated carrier sense signal. In one embodiment, the second emulated carrier sense signal 522 generated by the interface circuit 508 includes a gap that is an end-of-data signal indicating the end of data reception.

[0081] At operation 816, an output signal is asserted and / or deasserted in response to the generated second emulated carrier sense signal. In one embodiment, the asserted and / or deasserted signal appears on an output pin associated with carrier and data 514 to generate the CRS_DV signal that includes gap 214 of FIG.

[0082] In operation 818, after generating the gap of operation 814, the interface circuit 508 generates a second emulated carrier sense signal 522 that is a faithful replica of the first emulated carrier sense signal 520; in other words, the interface circuit 508 generates a faithful replica of the emulated carrier sense signal generated by the media access tuning circuit 516 as the second emulated carrier sense signal 522.

[0083] 9 illustrates a process 900 for managing carrier sense signaling in a transmit PHY in accordance with one or more disclosed embodiments. At operation 902, the physical layer system 500 detects that the transmit enable 524 is asserted and begins storing transmit data in the transmit buffer 512.

[0084] In operation 904, the interface circuit 508 determines whether a transmit opportunity has begun. If a transmit opportunity has not begun, in operation 906, the interface circuit 508 suppresses the first emulated carrier sense signal 520 generated by the media access tuning circuit 516. In operation 908, the RMII carrier sense signal is deasserted in response to the suppressed first emulated carrier sense signal 520 of operation 906.

[0085] After detecting the start of a transmission opportunity, in operation 910, the interface circuit 508 continues to fill the transmit buffer 512 with second transmit data and begins moving the first transmit data from the transmit buffer 512 to the shared transmission medium 534.

[0086] In operation 912, the interface circuit 508 determines whether the transmit enable 524 is deasserted, based on which the interface circuit 508 infers that the link layer device, i.e., the connected MAC layer, has completed sending the transmit data. If the transmit enable 524 is not deasserted, in operation 914, the interface circuit 508 suppresses the first emulated carrier sense signal 520 received from the media access tuning circuit 516. In operation 916, the carrier sense signal of the RMII is deasserted in response to the suppressed first emulated carrier sense signal 520 of operation 914.

[0087] If the transmit enable 524 is deasserted, in operation 918, the interface circuit 508 generates a second emulated carrier sense signal 522 that is a faithful replica of the first emulated carrier sense signal 520 while the physical layer system 500 completes the movement of the transmission data from the transmit buffer 512 to the shared transmission medium 534.

[0088] In operation 920, the interface circuit 508 inserts a data valid null code into the data 532, at least while faithfully replicating the first emulated carrier sense signal 520, i.e., while asserting the second emulated carrier sense signal 522.

[0089] Although not shown in FIG. 9, the carrier sense signal of the RMII may be asserted and / or deasserted in response to the generated second emulated carrier sense signal of operation 918.

[0090] 10 illustrates a process 1000 for managing carrier sense signaling at a receiving PHY configured to enforce time-aware deferral and / or traffic shaping, according to one or more disclosed embodiments. In operation 1002, the interface circuit 508 receives a first emulated carrier sense signal 520 from the media access tuning circuit 516, which is asserted because the first emulated carrier sense signal 520 is received while the media access tuning circuit 516 is waiting for the next transmission opportunity. In operation 1004, the interface circuit 508 checks whether a synchronization byte is present in the receive buffer 510. As a non-limiting example, the synchronization byte may be a preamble of an Ethernet frame. If the synchronization byte is not present, in operation 1006, the interface circuit 508 faithfully replicates the first emulated carrier sense signal 520 received from the media access tuning circuit 516 as a second emulated carrier sense signal 522, and the process 1000 loops back to operation 1002.

[0091] If a sync byte is present in the receive buffer, then in operation 1008, before the sync byte is sent to the MAC, the interface circuit 508 generates a second emulated carrier sense signal 522 having a first gap indicating that data reception is about to begin. The first gap 432 is shown in process 400 of FIG. 4 for times 430 and 434.

[0092] In operation 1010, an output carrier sense signal (e.g., carrier and data 514) of the RMI interface 506 is asserted and / or deasserted in response to the generated second emulated carrier sense signal having a first gap to signal the start of data reception. In one embodiment, the asserted and / or deasserted carrier and data 514 generates the CRS_DV signal that includes gap 444 of FIG.

[0093] In operation 1012, the interface circuit 508 determines whether data reception is complete. If data reception is not complete, in operation 1014, the interface circuit 508 faithfully replicates the first emulated carrier sense signal 520 generated by the media access tuning circuit 516 as a second emulated carrier sense signal 522 while the physical layer system 500 transmits the received frame from the receive buffer to the MAC. If data reception is complete, in operation 1016, the interface circuit 508 generates a second emulated carrier sense signal having a gap indicating the end of data reception. The second gap 444 is shown in the process 400 of FIG. 4 for times 436 and 438.

[0094] In operation 1018, an output carrier sense signal of the RMI interface 506 (e.g., output by carrier and data 514) is asserted and / or deasserted in response to the generated second emulated carrier sense signal having the first gap to signal the end of data reception. In one embodiment, carrier and data 514 generates a CRS_DV signal that includes gap 440 of FIG. 4.

[0095] In connection with certain embodiments, PHY devices and systems such as PHY device 104, PHY device 108, and physical layer system 500 may be shown or described as having interface circuitry that includes an RMI interface. Those skilled in the art will appreciate that the disclosed embodiments are equally applicable to arrangements in which a PHY device implements a Media Independent Interface (MII) and is coupled to an RMI interface implemented on a separate chip between the PHY device and a MAC device. As a non-limiting example, RMI interface 506 of FIG. 5 may be implemented in the same chip package as interface circuitry 508 or in a different chip package.

[0096] In this disclosure, characterizations of something as "typical," "conventional," or "known" do not necessarily mean that the discussed aspects are disclosed in the prior art or are recognized in the prior art, nor do they necessarily mean that they are widely known, well understood, or routinely used in the relevant field.

[0097] While the present disclosure has been described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the present invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below together with their legal equivalents. In addition, features from one embodiment can be combined with features of another disclosed embodiment as contemplated by the inventor and still fall within the scope of the present disclosure.

[0098] Further non-limiting embodiments of the present disclosure are as follows.

[0099] Embodiment 1: A method comprising: in a physical layer device, detecting a carrier of a shared transmission medium; and in response to the detected carrier, asserting or deasserting an output signal associated with a carrier sense signal of a reduced media independent interface (RMII) of the physical layer device.

[0100] Embodiment 2: The method of embodiment 1, wherein the step of asserting or deasserting an output signal associated with a carrier sense signal of the RMII includes a step of asserting the output signal during at least a portion of the period during which the sensed carrier is idle.

[0101] Embodiment 3: A method as described in embodiment 1 or 2, wherein the step of asserting or deasserting an output signal associated with the carrier sense signal of the RMII includes a step of deasserting the output signal during at least a portion of the period during which the sensed carrier is in an active state.

[0102] Embodiment 4: A method according to any one of embodiments 1 to 3, further comprising: receiving a first emulated carrier sense signal generated by a media access tuning circuit; generating a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in a reduced media independent interface (RMII); and providing the second emulated carrier sense signal to the RMII.

[0103] Embodiment 5: The method according to any one of embodiments 1 to 4, wherein the step of generating a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in the RMII includes: detecting an end of data reception following a collision in the shared transmission medium; and generating the second emulated carrier sense signal in response to detecting the end of data reception by modifying the first emulated carrier sense signal generated by the media access tuning circuit to include an end of data reception signal.

[0104] Embodiment 6: The method according to any one of embodiments 1 to 5, further comprising: replicating a first emulated carrier sense signal generated by the media access tuning circuit during data reception; and replicating the first emulated carrier sense signal generated by the media access tuning circuit after providing a second emulated carrier sense signal to the RMII.

[0105] Embodiment 7: A method according to any one of embodiments 1 to 6, wherein the step of generating a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in the RMII includes the step of suppressing assertion of the first emulated carrier sense signal while waiting for the link layer device to finish providing the transmission data.

[0106] Embodiment 8: A method according to any one of embodiments 1 to 7, wherein the step of suppressing assertion of the first emulated carrier sense signal while waiting for the link layer device to finish providing the transmission data includes the steps of detecting the start of data transmission by the link layer device, and suppressing assertion of the first emulated carrier sense signal while the transmission buffer is filled with the first transmission data received from the link layer device.

[0107] Embodiment 9: A method according to any one of embodiments 1 to 8, wherein the step of suppressing assertion of the first emulated carrier sense signal while waiting for the link layer device to finish providing the transmission data further includes the step of suppressing assertion of the first emulated carrier sense signal while the transmission buffer is filled with second transmission data received from the link layer device and the first transmission data is moved from the transmission buffer to the shared transmission medium.

[0108] Embodiment 10: A method according to any one of embodiments 1 to 9, wherein the step of suppressing assertion of the first emulated carrier sense signal while waiting for the link layer device to finish providing the transmission data further includes the steps of filling a receive buffer with a code indicating that no valid data is present, and replicating the first emulated carrier sense signal generated by the media access tuning circuit while the second transmission data is moved from the transmit buffer to the shared transmission medium.

[0109] Embodiment 11: A method according to any one of embodiments 1 to 10, wherein the step of generating a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in the RMII includes: detecting a synchronization byte in a receive buffer of the media access tuning circuit; and generating the second emulated carrier sense signal in response to detecting the synchronization byte in the receive buffer of the media access tuning circuit by modifying the first emulated carrier sense signal generated by the media access tuning circuit to include a start of data receive signal.

[0110] Embodiment 12: A method according to any one of embodiments 1 to 11, further comprising replicating the first emulated carrier sense signal generated by the media access tuning circuit until a synchronization byte is detected in a receive buffer of the media access tuning circuit.

[0111] Embodiment 13: The method of any one of embodiments 1 to 12, further comprising providing a second emulated carrier sense signal to the RMII before the synchronization byte is provided to the link layer device.

[0112] Embodiment 14: The method of any one of embodiments 1 to 13, further comprising providing a second emulated carrier sense signal to the RMII after all receive buffer bytes have been provided to the link layer device.

[0113] Embodiment 15: The method according to any one of embodiments 1 to 14, further comprising the step of replicating the first emulated carrier sense signal generated by the media access tuning circuit after providing the second emulated carrier sense signal to the RMII.

[0114] Embodiment 16: The method of any one of embodiments 1 to 15, wherein the step of generating the second emulated carrier sense signal includes a step of modifying the first emulated carrier sense signal to include a gap.

[0115] Embodiment 17: A method according to any one of embodiments 1 to 16, wherein the step of generating the second emulated carrier sense signal includes a step of adapting a portion of the first emulated carrier sense signal to have a detectable shape.

[0116] Embodiment 18: A physical layer (PHY) device comprising: a transmission circuit configured to transmit and receive data from a shared transmission medium; a detection circuit configured to detect a carrier of the shared transmission medium; and one or more input / output (I / O) pins, one output pin of the one or more I / O pins being associated with an output signal of a carrier sense signal of a reduced media independent interface (RMII).

[0117] Embodiment 19: The device of embodiment 18, wherein the output signal is assertable during at least a portion of the period during which the sensed carrier is idle.

[0118] Embodiment 20: A device as described in embodiment 18 or 19, wherein the output signal is deassertable during at least a portion of the period during which the sensed carrier is in an active state.

[0119] Embodiment 21: A device as described in any one of embodiments 18 to 20, further comprising: a media access tuning circuit configured to generate a first emulated carrier sense signal; and an interface circuit configured to receive the first emulated carrier sense signal generated by the media access tuning circuit, and in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in the RMII, generate a second emulated carrier sense signal, and provide the second emulated carrier sense signal to the RMII.

[0120] Embodiment 22: A device as described in any one of embodiments 18 to 21, wherein the interface circuit is configured to generate a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in the RMII, the generating being performed by: detecting an end of data reception following a collision in the shared transmission medium; and, in response to detecting the end of data reception, generating the second emulated carrier sense signal by modifying the first emulated carrier sense signal generated by the media access tuning circuit to include the end of data reception signal.

[0121] Embodiment 23: A device as described in any one of embodiments 18 to 22, wherein the interface circuit is configured to replicate a first emulated carrier sense signal generated during data reception, and to replicate a first emulated carrier sense signal generated by the media access tuning circuit after providing a second emulated carrier sense signal to the RMII.

[0122] Embodiment 24: A device described in any one of embodiments 18 to 23, wherein the interface circuit is configured to generate a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in the RMII, the generating being performed by suppressing the first emulated carrier sense signal while waiting for the link layer device to finish providing the transmission data.

[0123] Embodiment 25: A device as described in any one of embodiments 18 to 24, wherein the interface circuit is configured to suppress the first emulated carrier sense signal while waiting for the link layer device to finish providing the transmission data, the suppressing being performed by detecting the start of data transmission by the link layer device and suppressing the first emulated carrier sense signal while the first transmission data is received from the link layer device and the transmission buffer is filled with the first transmission data.

[0124] Embodiment 26: A device described in any one of embodiments 18 to 25, wherein the interface circuit is further configured to suppress the first emulated carrier sense signal while waiting for the link layer device to finish providing the transmission data, the configuring being performed by suppressing the first emulated carrier sense signal while second transmission data is received from the link layer device and the transmission buffer is filled with the second transmission data.

[0125] Embodiment 27: A device as described in any one of embodiments 18 to 26, wherein the interface circuit is configured to: fill a receive buffer with a code indicating valid data while the transmission circuit moves second transmission data from the transmission buffer to the shared transmission medium; and replicate a first emulated carrier sense signal generated by the media access tuning circuit while the transmission circuit moves the second transmission data from the transmission buffer to the shared transmission medium.

[0126] Embodiment 28: A device described in any one of embodiments 18 to 27, wherein the interface circuit is configured to generate a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause inaccurate signaling in the RMII, the generating being performed by: detecting a synchronization byte in a receive buffer of the media access tuning circuit; and, in response to detecting the synchronization byte in the receive buffer of the media access tuning circuit, generating the second emulated carrier sense signal by modifying the first emulated carrier sense signal generated by the media access tuning circuit to include a start of data receive signal.

[0127] Embodiment 29: A device described in any one of embodiments 18 to 28, wherein the interface circuit is configured to provide a second emulated carrier sense signal to the RMII before the synchronization byte is provided to the link layer device.

[0128] Embodiment 30: A device described in any one of embodiments 18 to 29, wherein the interface circuit is configured to replicate the first emulated carrier sense signal generated by the media access tuning circuit until a synchronization byte is detected in the receive buffer of the media access tuning circuit.

[0129] Embodiment 31: A device described in any one of embodiments 18 to 30, wherein the interface circuit is configured to provide a second emulated carrier sense signal to the RMII after all data from the receive buffer has been transferred to the link layer device.

[0130] Embodiment 32: A device described in any one of embodiments 18 to 31, wherein the interface circuit is configured to provide a second emulated carrier sense signal to the RMII and then replicate the first emulated carrier sense signal generated by the media access tuning circuit.

[0131] Embodiment 33: A device described in any one of embodiments 18 to 32, wherein the interface circuit is configured to generate the second emulated carrier sense signal by modifying the first emulated carrier sense signal to include a gap.

[0132] Embodiment 34: A device described in any one of embodiments 18 to 33, wherein the interface circuit is configured to generate a second emulated carrier sense signal by modifying the first emulated carrier sense signal to include a pulse.

[0133] Embodiment 35: A device described in any one of embodiments 18 to 34, wherein the interface circuit is configured to generate a second emulated carrier sense signal by adapting a portion of the first emulated carrier sense signal to have a detectable shape.

Claims

1. 1. A method comprising: receiving a first emulated carrier sense signal generated by a media access tuning circuit to emulate sensing of a carrier of a shared transmission medium; generating a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause incorrect signaling in a Reduced Media Independent Interface (RMII) of a physical layer device; and in response to the second emulated carrier sense signal, asserting or deasserting an output signal associated with the RMII carrier sense signal of the physical layer device.

2. The step of asserting or deasserting the output signal associated with the carrier sense signal of the RMII comprises:

2. The method of claim 1, further comprising asserting said output signal during at least a portion of a period during which said sensed carrier is idle.

3. The step of asserting or deasserting the output signal associated with the carrier sense signal of the RMII comprises:

2. The method of claim 1, further comprising: deasserting the output signal during at least a portion of the time period during which the sensed carrier is active.

4. generating the second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause incorrect signaling in the RMII of the physical layer device, comprising: detecting an end of data reception following a collision on the shared transmission medium; and generating the second emulated carrier sense signal by modifying the first emulated carrier sense signal generated by the media access tuning circuitry to include an end of data reception signal in response to the detecting the end of the data reception.

5. replicating the first emulated carrier sense signal generated by the media access tuning circuit during the data reception; and replicating the first emulated carrier sense signal generated by the media access tuning circuit after providing the second emulated carrier sense signal to the RMII of the physical layer device.

6. generating the second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause incorrect signaling in the RMII of the physical layer device, comprising:

2. The method of claim 1, further comprising the step of: suppressing assertion of the first emulated carrier sense signal while waiting for a link layer device to finish providing transmitted data.

7. suppressing the assertion of the first emulated carrier sense signal while waiting for the link layer device to finish providing transmission data, detecting an initiation of data transmission by the link layer device; and suppressing assertion of the first emulated carrier sense signal while a transmit buffer is being filled with first transmit data received from the link layer device.

8. suppressing the assertion of the first emulated carrier sense signal while waiting for the link layer device to finish providing transmission data, 8. The method of claim 7, further comprising suppressing assertion of the first emulated carrier sense signal while the transmit buffer is filled with second transmit data received from the link layer device and the first transmit data is moved from the transmit buffer to the shared transmission medium.

9. The step of suppressing assertion of the first emulated carrier sense signal while waiting for the link layer device to complete providing transmission data comprises: filling a receive buffer with a code indicating that valid data is not present; and replicating the first emulated carrier sense signal generated by the media access tuning circuitry while the second transmission data is being moved from the transmission buffer to the shared transmission medium.

10. generating the second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause incorrect signaling in the RMII of the physical layer device, comprising: detecting a synchronization byte in a receive buffer of the media access tuning circuit; and generating the second emulated carrier sense signal by modifying the first emulated carrier sense signal generated by the media access tuning circuit to include a start of data receive signal in response to the detection of the synchronization byte in the receive buffer of the media access tuning circuit.

11. 11. The method of claim 10, comprising replicating the first emulated carrier sense signal generated by the media access tuning circuit until detecting the synchronization byte in the receive buffer of the media access tuning circuit.

12. 12. The method of claim 11, further comprising providing the second emulated carrier sense signal to the RMII of the physical layer device before the synchronization byte is provided to a link layer device.

13. 13. The method of claim 12, further comprising providing the second emulated carrier sense signal to the RMII of the physical layer device after all receive buffer bytes have been provided to the link layer device.

14. 14. The method of claim 13, further comprising the step of replicating the first emulated carrier sense signal generated by the media access tuning circuit after providing the second emulated carrier sense signal to the RMII of the physical layer device.

15. 2. The method of claim 1, wherein generating the second emulated carrier sense signal comprises modifying the first emulated carrier sense signal to include a gap.

16. 2. The method of claim 1, wherein generating the second emulated carrier sense signal comprises adapting a portion of the first emulated carrier sense signal to have a detectable shape.

17. 1. A physical layer (PHY) device, comprising: a transmission circuit for transmitting and receiving data to and from a shared transmission medium; a detection circuit for detecting a carrier of the shared transmission medium; a media access tuning circuit that generates a first emulated carrier sense signal; An interface circuit, comprising: receiving the first emulated carrier sense signal generated by the media access tuning circuit; generating a second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause incorrect signaling in a reduced media independent interface (RMII); providing the second emulated carrier sense signal to the RMII; and 1. A physical layer device comprising: one or more inputs / outputs, wherein one output of the one or more inputs / outputs is associated with an output signal of an RMII carrier sense signal.

18. 20. The physical layer device of claim 17, wherein the output signal is assertable during at least a portion of a period during which a sensed carrier is idle.

19. 20. The physical layer device of claim 17, wherein the output signal is deassertable during at least a portion of the time period during which a sensed carrier is in an active state.

20. The interface circuit generates the second emulated carrier sense signal in response to the detection that the first emulated carrier sense signal would cause incorrect signaling in the RMII, the generating comprising: detecting an end of data reception following a collision on the shared transmission medium; generating the second emulated carrier sense signal by modifying the first emulated carrier sense signal generated by the media access tuning circuitry including an end of data receive signal responsive to the detection of the end of the data reception.

21. The interface circuit includes: replicating the first emulated carrier sense signal generated during the data reception; and replicating the first emulated carrier sense signal generated by the media access tuning circuitry after providing the second emulated carrier sense signal to the RMII.

22. The interface circuit generates the second emulated carrier sense signal in response to detecting that the first emulated carrier sense signal would cause incorrect signaling in the RMII, the generating comprising:

20. The physical layer device of claim 17, wherein the suppression is accomplished by suppressing the first emulated carrier sense signal while waiting for a link layer device to finish providing transmitted data.

23. The interface circuitry suppresses the first emulated carrier sense signal while waiting for the link layer device to finish providing data for transmission, the suppression comprising: detecting an initiation of data transmission by the link layer device; and suppressing the first emulated carrier sense signal while first transmission data is received from the link layer device and a transmit buffer is filled with the first transmission data.

24. The interface circuitry suppresses the first emulated carrier sense signal while waiting for the link layer device to finish providing data for transmission, the suppression comprising:

24. The physical layer device of claim 23, wherein said suppression is accomplished by suppression of said first emulated carrier sense signal while second transmission data is being received from said link layer device and said transmit buffer is being filled with said second transmission data.

25. The interface circuit includes: filling a receive buffer with a code indicating that valid data is not present while a transmission circuit moves the second transmission data from the transmit buffer to the shared transmission medium; 25. The physical layer device of claim 24, wherein the transmission circuit replicates the first emulated carrier sense signal generated by the media access tuning circuit while moving the second transmission data from the transmission buffer to the shared transmission medium.

26. The interface circuit generates the second emulated carrier sense signal in response to the detection that the first emulated carrier sense signal would cause incorrect signaling in the RMII, the generating comprising: detecting a synchronization byte in a receive buffer of the media access tuning circuit; and generating the second emulated carrier sense signal by modifying the first emulated carrier sense signal generated by the media access tuning circuit including a start of data receive signal responsive to the detection of the synchronization byte in the receive buffer of the media access tuning circuit.

27. 27. The physical layer device of claim 26, wherein the interface circuitry provides the second emulated carrier sense signal to the RMII before the synchronization byte is provided to a link layer device.

28. The interface circuit includes:

28. The physical layer device of claim 27, further comprising: a media access tuning circuit configured to replicate the first emulated carrier sense signal generated by the media access tuning circuit up to the detection of the synchronization byte in the receive buffer of the media access tuning circuit.

29. 30. The physical layer device of claim 28, wherein the interface circuit provides the second emulated carrier sense signal to the RMII after all of the data from the receive buffer has been transferred to the link layer device.

30. The interface circuit includes:

30. The physical layer device of claim 29, further comprising: a media access tuning circuit that replicates the first emulated carrier sense signal generated by the media access tuning circuit after providing the second emulated carrier sense signal to the RMII.

31. 20. The physical layer device of claim 17, wherein the interface circuit generates the second emulated carrier sense signal by modifying the first emulated carrier sense signal to include a gap.

32. 20. The physical layer device of claim 17, wherein the interface circuit generates the second emulated carrier sense signal by modifying the first emulated carrier sense signal to include a pulse.

33. 20. The physical layer device of claim 17, wherein the interface circuit generates the second emulated carrier sense signal by adapting a portion of the first emulated carrier sense signal to have a detectable shape.

Images