Semiconductor device and method for manufacturing the same

Abstract

To suppress increase in recovery loss of an RC-IGBT.SOLUTION: In a semiconductor device, an IGBT region comprises a base layer of a second conductivity type on a surface layer of a drift layer. A diode region comprises an anode layer of the second conductivity type on the surface layer of the drift layer. A termination region comprises a well layer of the second conductivity type on the surface layer of the drift layer. A profile of the impurity concentration of the base layer and a profile of the impurity concentration of the anode layer in a direction along a top surface of the drift layer periodically fluctuate. The profile of the impurity concentration of the base layer and the profile of the impurity concentration of the anode layer are different from each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses a reverse conducting insulated gate bipolar transistor (RC-IGBT). Here, the RC-IGBT is an IGBT in which an IGBT and a free-wheeling diode (FWD) are formed on a single semiconductor substrate.

[0003] On the front surface side of the RC-IGBT disclosed in Patent Document 1, a P-type base layer is formed in the IGBT region, a P-type anode layer is formed in the diode region, and a P-type well layer is formed in the termination region, and the P-type base layer in the IGBT region and the P-type anode layer in the diode region are formed flat and of uniform depth. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2021-136311 A Summary of the Invention [Problem to be solved by the invention]

[0005] In an RC-IGBT, which is an integrated structure of an IGBT and a diode, holes, which are carriers, flow from the IGBT region to the diode region. This increases the power loss during the recovery operation of the diode, i.e., the recovery loss.

[0006] In addition, in the RC-IGBT shown in Patent Document 1, the impurity concentration of the P-type anode layer in the diode region is the same as the impurity concentration of the P-type base layer in the IGBT region, so the P-type anode layer has an impurity concentration optimized for the IGBT characteristics. This causes an increase in the inflow of holes from the P-type anode layer, which also increases the recovery loss of the diode.

[0007] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology for suppressing an increase in recovery loss in an RC-IGBT. [Means for solving the problem]

[0008] A semiconductor device according to a first aspect of the technology disclosed in the present specification is an RC-IGBT in which an IGBT region and a diode region, which are active regions, and a termination region surrounding the active region in a planar view are provided on a single semiconductor substrate, and a drift layer of a first conductivity type is provided on an upper surface of the semiconductor substrate, the IGBT region includes a base layer of a second conductivity type in a surface layer of the drift layer, the diode region includes an anode layer of the second conductivity type in a surface layer of the drift layer, the termination region includes a well layer of the second conductivity type in a surface layer of the drift layer, and Layer Yo Before The anode layer , depth and impurity concentration fluctuates periodically, and the base Layers and The anode layer and of Depth and impurity concentration is different. Effect of the Invention

[0009] According to at least the first aspect of the technology disclosed in the present specification, by configuring the impurity concentration profiles of the base layer and the anode layer to vary periodically, it is possible to reduce the inflow of holes and suppress an increase in recovery loss.

[0010] Furthermore, objects, features, aspects and advantages associated with the technology disclosed herein will become more apparent from the detailed description set forth below and the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view illustrating an example of the configuration of an RC-IGBT, which is a semiconductor device according to the present embodiment. [Diagram 2] 1 is a cross-sectional view showing an example of a process for forming a P-type semiconductor layer in the configuration of an RC-IGBT according to the present embodiment. FIG. [Diagram 3] 1 is a cross-sectional view showing an example of a process for forming a P-type semiconductor layer in the configuration of an RC-IGBT according to the present embodiment. FIG. [Figure 4] 1 is a cross-sectional view showing an example of a process for forming a P-type semiconductor layer in the configuration of an RC-IGBT according to the present embodiment. FIG. [Diagram 5] 5 is a diagram showing an example of a boron concentration distribution at a point A-A' in a P-type base layer of the IGBT region shown in FIG. 4. [Figure 6] 5 is a diagram showing an example of a boron concentration distribution at a point B-B' in the P-type anode layer of the diode region shown in FIG. 4. [Figure 7] 1 is a cross-sectional view showing a schematic example of the configuration of an RC-IGBT which is a semiconductor device according to the present embodiment. [Figure 8] 1 is a cross-sectional view illustrating an example of the configuration of an RC-IGBT, which is a semiconductor device according to the present embodiment. [Figure 9] 1 is a cross-sectional view showing a schematic example of the configuration of an RC-IGBT which is a semiconductor device according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but they are merely examples and are not necessarily all essential features for enabling the embodiments to be implemented.

[0013] The drawings are schematic, and for the convenience of explanation, the configuration may be omitted or simplified as appropriate. The size and positional relationship of the configurations shown in different drawings are not necessarily described accurately, and may be changed as appropriate. Hatching may be added to drawings such as plan views that are not cross-sectional views, in order to make it easier to understand the contents of the embodiment.

[0014] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted to avoid duplication.

[0015] Furthermore, in the description in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0016] Furthermore, even if ordinal numbers such as "first" or "second" are used in the description of this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the orders that may result from these ordinal numbers.

[0017] In addition, in the explanations given in this specification, expressions indicating relative or absolute positional relationships, such as "in one direction," "along one direction," "parallel," "orthogonal," "center," "concentric," or "coaxial," are intended to include cases in which the positional relationship is strictly indicated, as well as cases in which the angle or distance is displaced within a tolerance or a range in which equivalent functionality is obtained, unless otherwise specified.

[0018] Furthermore, in the explanations given in this specification, expressions indicating an equal state, such as "same," "equal," "uniform," or "homogeneous," are intended to include cases where an equal state is strictly observed, as well as cases where a difference exists within a tolerance or within a range where the same level of functionality is obtained, unless otherwise specified.

[0019] Furthermore, although the descriptions in this specification may use terms indicating specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," these terms are used for convenience to facilitate understanding of the contents of the embodiments, and do not relate to the positions or directions in which the embodiments are actually implemented.

[0020] In addition, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is stated, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. In other words, for example, when it is stated that "B is provided on the upper surface of A," it does not prevent another component "C" from being interposed between A and B.

[0021] <First embodiment> A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described below. In the following description, the first conductivity type is N-type and the second conductivity type is P-type. However, the correspondence between these may be reversed, with the first conductivity type being P-type and the second conductivity type being N-type.

[0022] <Configuration of semiconductor device> 1 is a cross-sectional view showing an example of the configuration of an RC-IGBT, which is a semiconductor device according to the present embodiment. The IGBT region, the diode region, and the termination region in FIG. - The transistors are formed in a single semiconductor substrate having a drift layer 7 of the same type. The IGBT region and the diode region form the active region.

[0023] In the IGBT region, N - The surface layer of the drift layer 7 of the mold is - An N-type carrier stored (CS) layer 18 having a higher impurity concentration than the N-type drift layer 7 is formed. - A P-type base layer 5 is formed above the N-type CS layer 18 in the surface layer of the drift layer 7. In addition, the surface layer of the P-type base layer 5 has an N - The impurity concentration is higher than that of the drift layer 7 of the N type. + The P type source layer 3 and the P type base layer 5 have a higher impurity concentration. + A mold contact layer 4 is formed.

[0024] In addition, the N - The upper surface of the drift layer 7 of the type (i.e., N + (top surface of source layer 3) from N + The N-type source layer 3, the P-type base layer 5, and the N-type CS layer 18 are connected to the - A trench 100 is formed so as to reach the drift layer 7 of the type. A gate oxide film 15 is formed on the side wall of the trench 100. The gate oxide film 15 is made of N + The gate electrode 16 is formed in the trench 100 and is connected to the N-type base layer 5 via the gate oxide film 15. + a P-type source layer 3, a P-type base layer 5, an N-type CS layer 18, and an N - The gate electrode 16 faces the drift layer 7 of the mold.

[0025] In addition, the N + The top surface of the source layer 3 of the mold and P + A barrier metal 2 is formed on the upper surface of the mold contact layer 4. A front electrode 1 is formed covering the upper surface of the insulating film 11 and the upper surface of the barrier metal 2.

[0026] N in the IGBT region - The bottom surface of the drift layer 7 of the mold is N -An N-type buffer layer 8 having a higher impurity concentration than the P-type drift layer 7 is formed. + A collector layer 9 of the P type is formed. + Below the mold collector layer 9 a back electrode 17 is formed.

[0027] In the diode region, N - The surface layer of the drift layer 7 of the mold is - The N-type CS layer 18 having a higher impurity concentration than the N-type drift layer 7 is formed. - A P-type anode layer 6 is formed above the N-type CS layer 18 in the surface layer of the N-type drift layer 7. - Above the P-type anode layer 6 in the surface layer of the drift layer 7, a P + A mold contact layer 4 is then formed.

[0028] Also, the N - The top surface of the drift layer 7 of the mold (i.e., P + (top surface of contact layer 4) to P + The N-type contact layer 4, the P-type anode layer 6, and the N-type CS layer 18 are connected to the N - A trench 101 is formed so as to reach the drift layer 7 of the type. A gate oxide film 15 is formed on the side wall of the trench 101. A gate electrode 16 is formed in the trench 101 and is connected to the P + a P-type contact layer 4, a P-type anode layer 6, an N-type CS layer 18, and an N - The drift layer 7 faces the mold.

[0029] In addition, the P + A barrier metal 2 is formed on the upper surface of the P-type contact layer 4 and on the upper surface of the P-type anode layer 6. A front electrode 1 is formed covering the upper surface of the insulating film 11 and the upper surface of the barrier metal 2.

[0030] N in the diode region - The bottom surface of the drift layer 7 of the mold is N- An N-type buffer layer 8 having an impurity concentration higher than that of the N-type drift layer 7 is formed. Under the N-type buffer layer 8, an N + A cathode layer 10 of the N type is formed. + Beneath the mold cathode layer 10 a back electrode 17 is formed.

[0031] In the termination region, N - A P-type well layer 12 is formed on the surface of the N-type drift layer 7. In addition, an N-type well layer 12 is formed on the outermost periphery away from the IGBT region. - In this case, an N-type channel stopper layer 13 having a higher impurity concentration than the N-type drift layer 7 is formed.

[0032] In addition, the N - An insulating film 11 is formed on the upper surface of the drift layer 7, a part of the upper surface of the P-type well layer 12, and a part of the upper surface of the N-type channel stopper layer 13. The upper surface of the P-type well layer 12 exposed from the insulating film 11, the upper surface of the N-type channel stopper layer 13 exposed from the insulating film 11, and the upper surface of the N-type channel stopper layer 13 are - A front surface electrode 1 is formed covering the upper surface of the P-type drift layer 7. The front surface electrode 1 is in contact with a part of the upper surface of the P-type well layer 12 and a part of the upper surface of the N-type channel stopper layer 13. In addition, a mixed insulating film 14, which is a mixture of a semi-insulating film and an insulating film, is formed covering the front surface electrode 1 and the insulating film 11 exposed from the front surface electrode 1.

[0033] N in the terminal area - The bottom surface of the drift layer 7 of the mold is N - An N-type buffer layer 8 having an impurity concentration higher than that of the N-type drift layer 7 is formed. Under the N-type buffer layer 8, an N + A cathode layer 10 of the N type is formed. + Beneath the mold cathode layer 10 a back electrode 17 is formed.

[0034] Among the above, the P-type base layer 5 in the IGBT region is not formed flat with a uniform depth. - The mold is formed so that the depth and concentration change at a constant cycle in the direction along the top surface (first main surface) of drift layer 7 of the mold.

[0035] Moreover, the P-type base layer 5 in the diode region is also not formed flat and with a uniform depth. Specifically, the P-type base layer 5 in the diode region is formed so that the depth and concentration change in a constant cycle different from that of the P-type base layer 5 in the IGBT region in the direction along the first main surface.

[0036] <About the manufacturing method of semiconductor device> 2, 3 and 4 are cross-sectional views showing examples of processes for forming P-type semiconductor layers (specifically, a P-type base layer 5, a P-type anode layer 6 and a P-type well layer 12) in the configuration of an RC-IGBT according to this embodiment.

[0037] First, as shown in FIG. 2, an N-type semiconductor substrate 19 (for example, a resistivity ρ of 23 Ω·cm and a thickness of 725 μm) is prepared. Next, a N - A mold drift layer 7 is formed.

[0038] As shown in FIG. 3, the N type semiconductor substrate 19 - A photolithography process is performed using a photomask 20 (photoresist) over the IGBT region, the diode region and the termination region of the drift layer 7 of the mold.

[0039] Here, in the conventional manufacturing method, no openings in the photomask 20 were arranged in the portions that will become the IGBT region and the diode region, but in the present embodiment, openings in the photomask 20 are arranged partially in the portions that will become the IGBT region and the diode region, in addition to the portions that will become the termination region.

[0040] For example, a photoresist pattern is formed in which cutouts and remaining portions are repeated to form a stripe shape in a plan view. The cutout width in the IGBT region (width X1 shown in FIG. 3) is set to, for example, 0.6 μm, and the remaining portion width in the IGBT region (width X2 shown in FIG. 3) is set to, for example, 1.4 μm. The cutout width in the diode region (width X3 shown in FIG. 3) is set to, for example, 0.4 μm, and the remaining portion width in the diode region (width X4 shown in FIG. 3) is set to, for example, 0.9 μm. In this embodiment, the opening width periodically formed in the IGBT region and the opening width periodically formed in the diode region are different.

[0041] After forming the above-mentioned photoresist pattern, an ion implantation process (e.g., boron implantation process) is performed. The boron implantation amount is, for example, 3×10 14 atoms / cm 2 ) and doping with N - The implantation takes place in the drift layer 7 of the mold.

[0042] A heat treatment (e.g., 1100° C. for 60 minutes) can then be performed to activate the dopants implanted in the IGBT, diode and termination regions and to diffuse them to the desired depth.

[0043] At this time, the implanted dopant diffuses not only in the implantation depth direction but also in a direction perpendicular to the implantation depth direction, so that the P-type base layer 5 in the IGBT region and the P-type anode layer 6 in the diode region, and the P-type anode layer 6 in the diode region and the P-type well layer 12 in the termination region are connected to each other, as shown in the example of FIG. 4.

[0044] Fig. 5 is a diagram showing an example of the boron concentration distribution at the point A-A' in the P-type base layer 5 of the IGBT region shown in Fig. 4. In Fig. 5, the vertical axis represents the boron concentration [atoms / cm 3 ], and the horizontal axis represents the distance [μm] toward the outer periphery of the IGBT region.

[0045] 5, the change in the boron concentration in the base layer 5 is repeated at a certain period. The period of the change in the boron concentration is determined by the width of the cutout portion of the photomask 20, the width of the remaining portion, the boron implantation conditions, the heat treatment conditions, etc.

[0046] Fig. 6 is a diagram showing an example of the boron concentration distribution at the B-B' point in the P-type anode layer 6 in the diode region shown in Fig. 4. In Fig. 6, the vertical axis represents the boron concentration [atoms / cm 3 ], and the horizontal axis represents the distance [μm] toward the outer periphery of the diode region.

[0047] 6, the change in the boron concentration in the anode layer 6 is repeated at a certain period. However, because the width of the cutout portion and the width of the remaining portion of the photomask 20 are different from those of the IGBT region, the period of the change in the boron concentration in the diode region is different from that of the IGBT region. Specifically, the period of the change in the boron concentration in the diode region is shorter than that of the IGBT region.

[0048] The period of change in the boron concentration can be controlled by adjusting the ratio of the cut-out width to the remaining width (i.e., the aperture ratio of the photomask 20). Thus, by making the above adjustments, the concentration distribution of the P-type base layer 5 in the IGBT region and the concentration distribution of the P-type anode layer 6 in the diode region can each be controlled, achieving appropriate concentration distributions for each.

[0049] In this way, in the RC-IGBT according to this embodiment, the P-type base layer 5 in the IGBT region, the P-type anode layer 6 in the diode region, and the P-type well layer 12 in the termination region can be formed in one photolithography process (i.e., one photomask 20), thereby reducing the manufacturing cost of the RC-IGBT.

[0050] <Second embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiment are shown with the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0051] FIG. 7 is a cross-sectional view that illustrates a schematic example of the configuration of an RC-IGBT that is a semiconductor device according to this embodiment.

[0052] The IGBT region of the RC-IGBT shown in FIG. - A N-type drift layer 7, an N-type CS layer 18, and an N + A source layer 3 of the mold, P + A contact layer 4 of the N type is formed. - A P-type base layer 5A is formed above an N-type CS layer 18 in the surface layer of a P-type drift layer 7. In the IGBT region, a trench 100, a gate oxide film 15, an insulating film 11, a barrier metal 2, a surface electrode 1, an N-type buffer layer 8, and a P-type + A mold collector layer 9 and a back electrode 17 are formed.

[0053] The diode region of the RC-IGBT shown in FIG. - In addition, an N-type drift layer 7 and an N-type CS layer 18 are formed. - A P-type anode layer 6A is formed above the N-type CS layer 18 in the surface layer of the drift layer 7. + A contact layer 4, a trench 101, a gate oxide film 15, a barrier metal 2, a surface electrode 1, an N-type buffer layer 8, and an N + A mold cathode layer 10 and a back electrode 17 are formed.

[0054] In the RC-IGBT shown in Fig. 7, the impurity concentration (dopant concentration) per unit area of ​​the P-type base layer 5A in the IGBT region is higher than the impurity concentration (dopant concentration) per unit area of ​​the P-type anode layer 6A in the diode region. Also, in the RC-IGBT shown in Fig. 7, the formation depth of the P-type base layer 5A in the IGBT region is deeper than the formation depth of the P-type anode layer 6A in the diode region.

[0055] For example, when ion implantation processing is performed with the cut-out width of the photomask 20 for forming the P-type base layer 5A in the IGBT region being 0.6 μm and the remaining width being 1.4 μm, and with the cut-out width of the photomask 20 for forming the P-type anode layer 6A in the diode region being 0.4 μm and the remaining width being 1.6 μm, the impurity concentration (dopant concentration) per unit area of ​​the P-type base layer 5A in the IGBT region will be 1.5 times the impurity concentration (dopant concentration) per unit area of ​​the P-type anode layer 6A in the diode region.

[0056] The impurity concentration (dopant concentration) of the P-type base layer 5A in the IGBT region is designed based on the design value of the IGBT threshold voltage. On the other hand, in order to ensure the current blocking capability at turn-off (RBSOA: Reverse Blocking Safe Operation Area) and prevent latch-up, it is necessary to reduce the resistance value of the P-type base layer 5A. In this case, it is desirable to set the impurity concentration (dopant concentration) of the P-type base layer 5A in the IGBT region high.

[0057] Here, if the impurity concentration (dopant concentration) of the P-type anode layer 6A in the diode region is increased, the efficiency of hole injection from the P-type anode layer 6A when the diode is turned on increases, and the N - The carrier concentration accumulated in the drift layer 7 of the semiconductor device becomes high, and therefore the recovery loss becomes large.

[0058] Therefore, in an RC-IGBT that requires a reduction in recovery loss for high frequency operation, it is desirable to set the concentration of the P-type anode layer 6A in the diode region low.

[0059] In the RC-IGBT according to this embodiment, the impurity concentration (dopant concentration) of the P-type base layer 5A in the IGBT region is higher than the impurity concentration (dopant concentration) of the P-type anode layer 6A in the diode region. Therefore, it is possible to reduce the recovery loss of the diode while maintaining the threshold voltage and current blocking capability required for the IGBT characteristics at turn-off.

[0060] <Third embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiment are shown with the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0061] FIG. 8 is a cross-sectional view illustrating a schematic example of the configuration of an RC-IGBT, which is a semiconductor device according to the present embodiment.

[0062] The IGBT region of the RC-IGBT shown in FIG. - A N-type drift layer 7, an N-type CS layer 18, and an N + A source layer 3 of the mold, P + A contact layer 4 of the N type is formed. - A P-type base layer 5B is formed above an N-type CS layer 18 in the surface layer of the drift layer 7. In the IGBT region, a trench 100, a gate oxide film 15, an insulating film 11, a barrier metal 2, a surface electrode 1, an N-type buffer layer 8, and a P-type base layer 5B are formed. + A mold collector layer 9 and a back electrode 17 are formed.

[0063] 8, the impurity concentration per unit area of ​​the P-type base layer 5B in the IGBT region at a position close to the trench 100 is lower than the impurity concentration per unit area of ​​the P-type base layer 5B near the center of the mesa portion between the trenches 100. Such a concentration distribution can be formed, for example, by aligning the remaining portion of the photomask 20 for forming the P-type base layer 5B in the IGBT region with the position where the gate electrode 16 is to be formed.

[0064] The threshold voltage of the IGBT is affected by the impurity concentration (dopant concentration) of the P-type base layer 5B at a position in contact with the gate oxide film 15, which is the sidewall of the trench 100. In order to increase the current blocking capability at turn-off, it is desirable to increase the impurity concentration of the P-type base layer 5B in the IGBT region to decrease the resistance value, but if the impurity concentration of the P-type base layer 5B is made uniformly high, it will also affect the threshold voltage.

[0065] In the RC-IGBT according to this embodiment, in the P-type base layer 5B in the IGBT region, the impurity concentration (dopant concentration) in the center of the P-type base layer 5B (near the center of the mesa portion) is higher than the impurity concentration in the P-type base layer 5B at a position closer to the trench 100. Therefore, it is possible to improve the current blocking capability at the time of turn-off while maintaining the threshold voltage required for the IGBT characteristics.

[0066] <Fourth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiment are shown with the same reference numerals, and detailed description thereof will be omitted as appropriate.

[0067] 9 is a cross-sectional view showing an example of the configuration of an RC-IGBT, which is a semiconductor device according to the present embodiment. The IGBT region, the diode region, the boundary region, and the termination region in FIG. -The semiconductor device is formed in a single semiconductor substrate having a drift layer 7 of the same type. The boundary region is located between the IGBT region and the diode region.

[0068] In the boundary region of the RC-IGBT shown in FIG. - The surface layer of the drift layer 7 of the mold is - The N-type CS layer 18 having a higher impurity concentration than the N-type drift layer 7 is formed. - A P-type boundary base layer 21 is formed above the N-type CS layer 18 in the surface layer of the drift layer 7. In addition, the surface layer of the P-type boundary base layer 21 has an N - The impurity concentration is higher than that of the drift layer 7 of the N type. + The impurity concentration of the P-type source layer 3 is higher than that of the P-type boundary base layer 21. + A mold contact layer 4 is formed.

[0069] Also, the boundary region N - The upper surface of the drift layer 7 of the type (i.e., N + (top surface of source layer 3) from N + The N-type source layer 3, the P-type boundary base layer 21, and the N-type CS layer 18 are connected to the - A trench 102 is formed so as to reach the N-type drift layer 7. A gate oxide film 15 is formed on the side wall of the trench 102. A gate electrode 16 is formed in the trench 102 and is connected to the N-type drift layer 7 via the gate oxide film 15. + A P-type source layer 3, a P-type boundary base layer 21, an N-type CS layer 18, and an N - The gate electrode 16 faces the drift layer 7 of the mold.

[0070] In addition, the N + The top surface of the source layer 3 of the mold and P + A barrier metal 2 is formed on the upper surface of the mold contact layer 4. A front electrode 1 is formed covering the upper surface of the insulating film 11 and the upper surface of the barrier metal 2.

[0071] Boundary area N - The bottom surface of the drift layer 7 of the mold is N -An N-type buffer layer 8 having a higher impurity concentration than the P-type drift layer 7 is formed. + A collector layer 9 of the P type is formed. + Below the mold collector layer 9 a back electrode 17 is formed.

[0072] Here, the impurity concentration per unit area of ​​the P-type boundary base layer 21 in the boundary region is higher than the impurity concentration per unit area of ​​the P-type base layer 5 in the IGBT region. Also, the impurity concentration per unit area of ​​the P-type boundary base layer 21 in the boundary region is higher than the impurity concentration per unit area of ​​the P-type anode layer 6 in the diode region.

[0073] Furthermore, the impurity concentration profile of the P-type boundary base layer 21 varies periodically in the direction along the upper surface of the drift layer 7. In the present embodiment, the variation period of the impurity concentration profile of the P-type boundary base layer 21 is different from that of the impurity concentration profile of the P-type base layer 5 or the impurity concentration profile of the P-type anode layer 6.

[0074] In Fig. 1, the P-type base layer 5 of the IGBT region in contact with the diode region serves as the P-type anode layer 6 of the diode to form a parasitic pn-diode, which affects the recovery characteristics of the diode. This parasitic pn-diode is also affected by the gate voltage of the IGBT.

[0075] For example, when a positive voltage is applied to the gate electrode 16 and an n-channel is formed on the side wall of the trench, an electron current flows through this n-channel. This reduces the efficiency of hole injection from the P-type base layer 5, and the N - As a result, the carrier concentration accumulated in the n-type drift layer 7 decreases, and the forward voltage (VF) increases.

[0076] As a means of suppressing this phenomenon, + The collector layer 9 of the N-type is extended to the diode region side.- By making the injection efficiency from the lower surface side of the drift layer 7 of the mold to be nearly zero, the diode operation near the boundary with the IGBT region is suppressed.

[0077] However, in this case, the N - The lower surface of the drift layer 7 of the mold is P + However, there is a problem in that the region in which the collector layer 9 is formed cannot be effectively used as a diode.

[0078] On the other hand, in the RC-IGBT according to this embodiment, a boundary region is provided between the IGBT region and the diode region, and the impurity concentration of the P-type boundary base layer 21 in the boundary region is made higher than the impurity concentration of the P-type base layer 5 in the IGBT region. This makes the threshold voltage of the transistor in the boundary region higher than the threshold voltage of the transistor in the IGBT region, increasing the n-channel resistance when a gate voltage is applied in the boundary region and suppressing the electron current. This reduces the gate voltage dependency of the forward voltage of the diode.

[0079] Although the channel resistance becomes higher, the boundary region can also be used as an IGBT, so that each region can be effectively utilized.

[0080] <Effects of the above-described embodiment> Next, examples of effects produced by the above-described embodiments are shown. In the following description, the effects are described based on the specific configurations shown as examples in the above-described embodiments, but they may be replaced with other specific configurations shown as examples in the present specification as long as the same effects are produced. In other words, for convenience, only one of the corresponding specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another corresponding specific configuration.

[0081] Furthermore, the replacement may be made across a number of embodiments, that is, configurations shown as examples in different embodiments may be combined to produce the same effect.

[0082] According to the embodiment described above, the semiconductor device is an RC-IGBT in which an IGBT region and a diode region, which are active regions, and a termination region surrounding the active region in a plan view are provided on a single semiconductor substrate 19. A first conductivity type (N - The IGBT region is provided with a N - The diode region includes a base layer 5 of a second conductivity type (P type) (or a P type base layer 5A or a P type base layer 5B) on the surface of a N type drift layer 7. - The terminal region includes an anode layer 6 of a second conductivity type (P type) (or a P type anode layer 6A) on the surface of a N type drift layer 7. - The well layer 12 of the second conductivity type (P type) is provided on the surface of the drift layer 7 of the N type. - The impurity concentration profile of the P-type base layer 5 and the impurity concentration profile of the P-type anode layer 6 vary periodically in a direction along the top surface of the P-type drift layer 7. The impurity concentration profile of the P-type base layer 5 and the impurity concentration profile of the P-type anode layer 6 are different from each other.

[0083] According to this configuration, by configuring the impurity concentration profiles of the base layer and the anode layer to vary periodically, it is possible to reduce the inflow of holes and suppress an increase in recovery loss.

[0084] Furthermore, the same effect can be achieved even if other configurations, examples of which are shown in this specification, are appropriately added to the above configuration, i.e., even if other configurations in this specification that were not mentioned as the above configuration are appropriately added.

[0085] Moreover, according to the embodiment described above, the fluctuation period of the impurity concentration profile of the P-type base layer 5 is different from that of the P-type anode layer 6. With such a configuration, the degree of freedom of the concentration distribution is increased, thereby reducing the inflow of holes and suppressing an increase in recovery loss.

[0086] Moreover, according to the embodiment described above, the impurity concentration per unit area in plan view of the P-type base layer 5A is higher than the impurity concentration per unit area in plan view of the P-type anode layer 6A. With this configuration, it is possible to reduce diode recovery loss while maintaining the threshold voltage and breakdown voltage of the IGBT.

[0087] Moreover, according to the embodiment described above, the depth at which the P-type base layer 5A is formed is deeper than the depth at which the P-type anode layer 6A is formed (i.e., the P-type anode layer 6A is thinner than the P-type base layer 5A). With this configuration, the impurity concentration profiles of the base layer and the anode layer are periodically changed, thereby reducing the inflow of holes and suppressing an increase in recovery loss.

[0088] According to the embodiment described above, the IGBT region is formed of the N + A source layer 3 of N type + Type source layer 3 and N - The IGBT includes a gate oxide film 15 formed in contact with a P-type base layer 5B sandwiched between the P-type drift layer 7 and the P-type drift layer 7, and a gate electrode 16 formed in contact with the gate oxide film 15. The P-type base layer 5B has a lower impurity concentration per unit area at a position farther from the gate electrode 16 than at a position closer to the gate electrode 16. With this configuration, the pinch resistance can be reduced while maintaining a desired threshold voltage (Vth) in the IGBT. Thus, the breakdown voltage (RBSOA) can be improved.

[0089] Furthermore, according to the embodiment described above, the semiconductor device includes a boundary region located between the IGBT region and the diode region. The boundary region includes a boundary base layer 21 of the second conductivity type in the surface layer of the drift layer 7. The impurity concentration of the boundary base layer 21 is higher than the impurity concentration of the P-type base layer 5 and the impurity concentration of the P-type anode layer 6. With this configuration, it is possible to reduce the gate voltage dependency of the forward voltage (VF) in the diode.

[0090] Furthermore, according to the embodiment described above, the impurity concentration profile of the P-type boundary base layer 21 varies periodically in the direction along the top surface of the drift layer 7. The variation period of the impurity concentration profile of the P-type boundary base layer 21 differs from that of the impurity concentration profile of the P-type base layer 5 or the impurity concentration profile of the P-type anode layer 6. With such a configuration, the degree of freedom of the concentration distribution is increased, thereby reducing the inflow of holes and suppressing an increase in recovery loss.

[0091] According to the embodiment described above, in the method for manufacturing a semiconductor device, a drift layer 7 of a first conductivity type is formed on the upper surface of a semiconductor substrate 19. Then, a P-type base layer 5 of a second conductivity type is formed on the surface layer of the drift layer 7 in the IGBT region, a P-type anode layer 6 of a second conductivity type is formed on the surface layer of the drift layer 7 in the diode region, and a well layer 12 of a second conductivity type is formed on the surface layer of the drift layer 7 in the termination region, using a common mask (for example, a photomask 20). The photomask 20 has periodically arranged openings whose widths are different in at least a region corresponding to the P-type base layer 5 and a region corresponding to the P-type anode layer 6. Then, the impurity concentration profile of the P-type base layer 5 and the impurity concentration profile of the P-type anode layer 6 in the direction along the upper surface of the drift layer 7 vary periodically. Also, the impurity concentration profile of the P-type base layer 5 and the impurity concentration profile of the P-type anode layer 6 are different from each other.

[0092] According to this configuration, by configuring the impurity concentration profiles of the base layer and the anode layer to vary periodically, it is possible to reduce the inflow of holes and suppress an increase in recovery loss.

[0093] Furthermore, even when multiple P-type semiconductor layers are formed with different concentrations or depths, the P-type semiconductor layers (specifically, the P-type base layer 5, the P-type anode layer 6, and the P-type well layer 12) can be formed in one photolithography process (i.e., one photomask) without using multiple photomasks (i.e., without performing multiple photolithography processes). This allows the manufacturing cost of the RC-IGBT to be reduced.

[0094] Unless otherwise specified, the order in which the processes are performed may be changed.

[0095] Furthermore, even if other configurations, examples of which are shown in this specification, are appropriately added to the above configuration, i.e., other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be produced.

[0096] <Modifications of the above-described embodiments> In the embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may be described, but these are merely examples in all respects and are not limiting.

[0097] Therefore, countless modifications and equivalents not shown as examples are assumed within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0098] In addition, in the embodiments described above, when a material name is mentioned without being specifically specified, it is understood that the material may contain other additives, such as an alloy, unless a contradiction arises.

[0099] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, it is understood that "one or more" of that component may be provided.

[0100] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, where one component corresponds to a part of a structure, and even where multiple components are provided in one structure.

[0101] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0102] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art. [Explanation of symbols]

[0103] 3 source layer, 5 base layer, 5A base layer, 5B base layer, 6 anode layer, 6A anode layer, 7 drift layer, 11 insulating film, 12 well layer, 16 gate electrode, 19 semiconductor substrate, 21 boundary base layer.

Claims

1. an RC-IGBT in which an IGBT region and a diode region, which are active regions, and a termination region surrounding the active region in a plan view are provided on a single semiconductor substrate; a drift layer of a first conductivity type is provided on an upper surface of the semiconductor substrate; the IGBT region includes a base layer of a second conductivity type on a surface layer of the drift layer, the diode region includes an anode layer of a second conductivity type on a surface of the drift layer, the termination region includes a well layer of a second conductivity type on a surface layer of the drift layer, the depth and the impurity concentration of the base layer and the anode layer vary periodically in a direction along an upper surface of the drift layer, the base layer and the anode layer have different depths and impurity concentrations; Semiconductor device.

2. 2. The semiconductor device according to claim 1, The base layer and the anode layer have different depths and different periods of impurity concentration fluctuation. Semiconductor device.

3. 3. The semiconductor device according to claim 1, an impurity concentration per unit area in a plan view of the base layer is higher than an impurity concentration per unit area in a plan view of the anode layer; Semiconductor device.

4. A semiconductor device according to any one of claims 1 to 3, The depth at which the base layer is formed is deeper than the depth at which the anode layer is formed. Semiconductor device.

5. A semiconductor device according to any one of claims 1 to 4, The IGBT region is a first conductive type source layer on the surface of the base layer; a gate insulating film formed in contact with the base layer sandwiched between the source layer and the drift layer; a gate electrode formed in contact with the gate insulating film, an impurity concentration per unit area of ​​the base layer is lower at a position farther from the gate electrode than at a position closer to the gate electrode; Semiconductor device.

6. A semiconductor device according to any one of claims 1 to 5, a boundary region located between the IGBT region and the diode region, the boundary region includes a boundary base layer of a second conductivity type on a surface of the drift layer, an impurity concentration of the boundary base layer is higher than an impurity concentration of the base layer and an impurity concentration of the anode layer; Semiconductor device.

7. 7. The semiconductor device according to claim 6, a depth and an impurity concentration of the boundary base layer in a direction along an upper surface of the drift layer vary periodically, the depth and impurity concentration of the boundary base layer are different from the depth and impurity concentration of the base layer or the anode layer; Semiconductor device.

8. A method for manufacturing a semiconductor device in which an IGBT region and a diode region, which are active regions, and a termination region surrounding the active regions in a plan view are provided on a single semiconductor substrate, forming a drift layer of a first conductivity type on an upper surface of the semiconductor substrate; forming a base layer of a second conductivity type on a surface layer of the drift layer in the IGBT region, an anode layer of a second conductivity type on a surface layer of the drift layer in the diode region, and a well layer of a second conductivity type on a surface layer of the drift layer in the termination region, using a common mask; the mask has periodically arranged openings, the openings having different widths at least in an area corresponding to the base layer and an area corresponding to the anode layer; the depth and the impurity concentration of the base layer and the anode layer vary periodically in a direction along an upper surface of the drift layer, the base layer and the anode layer have different depths and impurity concentrations; A method for manufacturing a semiconductor device.

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