Resistive random access memory and memory mini-arrays with improved reliability.

Abstract

To provide a resistive random access memory with improved reliability and a memory mini array.SOLUTION: In a memory mini array 800, a memory 100 includes first to fourth switch transistors 110 to 140 and first and second resistive memory elements 151 and 152. Each of the first to fourth switch transistors includes a drain terminal, a source terminal and a gate terminal. The drain terminal of the third switch transistor is coupled to the source terminal of the first switch transistor. The drain terminal of the fourth switch transistor is coupled to the source terminal of the second switch transistor. The first resistive memory element is coupled with the source terminal of the fourth switch transistor and the source terminal of the first switch transistor. The second resistive memory element is coupled with the source terminal of the third switch transistor and the source terminal of the second switch transistor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates to resistive random access memories and memory mini-arrays, and more particularly to resistive random access memories and memory mini-arrays with improved reliability. [Background technology]

[0002] With the development of memory technology, resistive random access memories (RRAM) are now available. The resistive memory may include a resistive memory element. By applying a voltage, the resistance of the resistive memory element can be changed to write data to the resistive memory element and erase data from the resistive memory element.

[0003] On the other hand, current resistive memory elements have many drawbacks. For example, it is difficult to distinguish the resistance of traditional resistive memory after many writes and reads (for example, 100,000 times). Therefore, it is difficult to correctly read the data stored in the memory after multiple accesses, leading to poor reliability. In addition, in the case of current resistive memory, the same electrodes of multiple different resistive memory elements are formed on both ends, which involves a large number of complex traces and makes it difficult to reduce the area of ​​the memory. [Prior art documents] [Patent documents]

[0004] US Patent No. US 10,461,126 B2 US Patent No. US 9,496,048 B2 U.S. Patent No. US 9,401,198 B1 US Patent No. US 9,356,598 B2 US Patent No. US 9,054,702 B2 Summary of the Invention

[0005] One embodiment provides a memory including a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistive memory element, and a second resistive memory element. The first switch transistor may include a drain terminal, a source terminal, and a gate terminal. The second switch transistor may include a drain terminal, a source terminal, and a gate terminal. The third switch transistor may include a drain terminal, a source terminal, and a gate terminal coupled to a source terminal of the first switch transistor. The fourth switch transistor may include a drain terminal, a source terminal, and a gate terminal coupled to a source terminal of the second switch transistor. The first resistive memory element may include a first terminal coupled to a source terminal of the fourth switch transistor and a second terminal coupled to a source terminal of the first switch transistor. The second resistive memory element may include a first terminal coupled to a source terminal of the third switch transistor and a second terminal coupled to a source terminal of the second switch transistor.

[0006] Another embodiment provides a memory, the memory including a first diffusion layer, a second diffusion layer, a first polysilicon layer, a second polysilicon layer, a first resistive memory element, and a second resistive memory element. The first diffusion layer may be formed along a first direction. The second diffusion layer may be formed along the first direction. The first polysilicon layer may be formed along a second direction and may at least partially overlap the first diffusion layer and the second diffusion layer, the first direction being substantially perpendicular to the second direction. The second polysilicon layer may be formed along the second direction and may at least partially overlap the first diffusion layer and the second diffusion layer. The first resistive memory element may be formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the first diffusion layer. A second resistive memory element may be formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the second diffusion layer.

[0007] Another embodiment provides a memory mini-array, the memory mini-array including a first diffusion layer, a second diffusion layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, a fourth polysilicon layer, a first resistive memory element, a second resistive memory element, a third resistive memory element, and a fourth resistive memory element. The first diffusion layer may be formed along a first direction. The second diffusion layer may be formed along the first direction. The first polysilicon layer may be formed along a second direction and may at least partially overlap the first diffusion layer and the second diffusion layer, the first direction being substantially perpendicular to the second direction. The second polysilicon layer may be formed along the second direction and may at least partially overlap the first diffusion layer and the second diffusion layer. The third polysilicon layer may be formed along the second direction and may at least partially overlap the first diffusion layer and the second diffusion layer. The fourth polysilicon layer may be formed along the second direction and may at least partially overlap the first diffusion layer and the second diffusion layer, and the third polysilicon layer is formed between the second polysilicon layer and the fourth polysilicon layer. The first resistive memory element may be formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the first diffusion layer. The second resistive memory element may be formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the second diffusion layer. The third resistive memory element may be formed between the third polysilicon layer and the fourth polysilicon layer, at least partially overlapping the first diffusion layer. The fourth resistive memory element may be formed between the third polysilicon layer and the fourth polysilicon layer, at least partially overlapping the second diffusion layer. The first polysilicon layer, the second polysilicon layer, the first resistive memory element, and the second resistive memory element may correspond to a first memory. The third polysilicon layer, the fourth polysilicon layer, the third resistive memory element, and the fourth resistive memory element may correspond to a second memory. The memory mini-array may include a first memory and a second memory.

[0008] Another embodiment provides a memory, the memory including a first diffusion layer, a second diffusion layer, a first conductive layer, a second conductive layer, a first resistive memory element, and a second resistive memory element. The first conductive layer may be formed above the first diffusion layer. The second conductive layer may be formed above the second diffusion layer. The first resistive memory element may be formed above the first conductive layer. The second resistive memory element may be formed above the second conductive layer. The first conductive layer and the second first conductive layer may be formed from the same conductive layer. [Brief description of the drawings]

[0009] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0010] [Figure 1] 1 illustrates a memory write operation according to one embodiment. [Diagram 2] 2 illustrates a memory read operation in FIG. [Diagram 3] 1 illustrates a circuit including two memories according to one embodiment. [Figure 4] 2 illustrates a layout diagram of a manufacturing process for the memory of FIG. 1 according to one embodiment. [Diagram 5] 2 illustrates a layout diagram of a manufacturing process for the memory of FIG. 1 according to one embodiment. [Figure 6] 2 illustrates a layout diagram of a manufacturing process for the memory of FIG. 1 according to one embodiment. [Figure 7] 2 illustrates a layout diagram of a manufacturing process for the memory of FIG. 1 according to one embodiment. [Figure 8]2 illustrates a layout diagram of a manufacturing process for the memory of FIG. 1 according to one embodiment. [Figure 9] 9 is a cross-sectional view of the memory in FIG. 8 along section line 9-9'. [Figure 10] 1 illustrates a read window for reading data from multiple memories according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In order to increase the possible number of accesses to the memory and reduce the memory area, a memory and a memory mini-array are provided according to several embodiments. In this context, when object A is formed at least partially overlapping object B, such overlap means that at least a part of object A may overlap at least a part of object B, or object A completely overlaps object B in plan view. In this context, a conductive via (also known as a VIA) may be a conductive connection path formed by drilling a hole and plating the hole with one or more conductive materials. Each of the memories 100 and 200 referred to in this specification may be a bit cell of a resistive random-access memory (RRAM).

[0012] Figures 1 and 2 illustrate a memory 100 according to one embodiment. Figure 1 illustrates a write operation of memory 100. Figure 2 illustrates a read operation of memory 100.

[0013] 1 and 2, the memory 100 may include a first switch transistor 110, a second switch transistor 120, a third switch transistor 130, a fourth switch transistor 140, a first resistive memory element 151, and a second resistive memory element 152. The first switch transistor 110 may include a drain terminal, a source terminal, and a gate terminal. The second switch transistor 120 may include a drain terminal, a source terminal, and a gate terminal. The third switch transistor 130 may include a drain terminal, a source terminal, and a gate terminal, and the drain terminal of the third switch transistor 130 may be coupled to the source terminal of the first switch transistor 110. The fourth switch transistor 140 may include a drain terminal, a source terminal, and a gate terminal, and the drain terminal of the fourth switch transistor 140 may be coupled to the source terminal of the second switch transistor 120.

[0014] The first resistive memory element 151 may include a first terminal and a second terminal. The first terminal of the first resistive memory element 151 may be coupled to a source terminal of the fourth switch transistor 140. The second terminal of the first resistive memory element 151 may be coupled to a source terminal of the first switch transistor 110. The second resistive memory element 152 may include a first terminal and a second terminal. The first terminal of the second resistive memory element 152 may be coupled to a source terminal of the third switch transistor 130. The second terminal of the second resistive memory element 152 may be coupled to a source terminal of the second switch transistor 120.

[0015] As shown in FIG. 1 and FIG. 2 , each of the first resistive memory element 151 and the second resistive memory element 152 may include a top electrode (TE), a bottom electrode (BE), and a transition metal oxide layer (TMO). The top electrode TE of the first resistive memory element 151 may be coupled to a first terminal of the first resistive memory element 151. The bottom electrode BE of the first resistive memory element 151 may be coupled to a second terminal of the first resistive memory element 151. The transition metal oxide layer TMO of the first resistive memory element 151 may be formed between the top electrode TE and the bottom electrode BE of the first resistive memory element 151. Similarly, the top electrode TE of the second resistive memory element 152 may be coupled to a first terminal of the second resistive memory element 152. A bottom electrode BE of the second resistive memory element 152 may be coupled to a second terminal of the second resistive memory element 152. A transition metal oxide layer TMO of the second resistive memory element 152 may be formed between the top electrode TE and the bottom electrode BE of the second resistive memory element 152.

[0016] As shown in FIG. 1 and FIG. 2, a drain terminal of the first switch transistor 110 may be coupled to a first bit line (BL1). A gate terminal of the first switch transistor 110 may be coupled to a read word line (RWL). A drain terminal of the second switch transistor 120 may be coupled to a second bit line (BL2). A gate terminal of the second switch transistor 120 may be coupled to the read word line RWL. A gate terminal of the third switch transistor 130 may be coupled to a write word line (WWL). A source terminal of the third switch transistor 130 may be coupled to a second source line (SL2). A gate terminal of the fourth switch transistor 140 may be coupled to the write word line WWL. A source terminal of the fourth switch transistor 140 may be coupled to a first source line (SL1).

[0017] 1, data can be written to the memory 100 through the first source line SL1 and the second source line SL2 when the first switch transistor 110 and the second switch transistor 120 are turned off and the third switch transistor 130 and the fourth switch transistor 140 are turned on. As shown in FIG. 1, data can be written to the first resistive memory element 151 and the second resistive memory element 152 through paths P11 and P12.

[0018] In FIG. 1, when writing a logic 0 to memory 100, the first source line SL1 may have a high voltage level (expressed in the text as VH), the second source line SL2 may have a low voltage level (expressed in the text as VL) lower than the high voltage level VH, the first resistive memory 151 may be set to have a high resistance (expressed in the text as RH), and the second resistive memory element 152 may be set to have a low resistance (expressed in the text as RL) lower than the high resistance RH.

[0019] In FIG. 1, when writing a logic 1 to memory 100, the first source line SL1 may have a low voltage level VL, the second source line SL2 may have a high voltage level VH, the first resistive memory element 151 may be set to have a low resistance RL, and the second resistive memory element 152 may be set to have a high resistance RH.

[0020] 2, data can be read from memory 100 when first switch transistor 110 and second switch transistor 120 are turned on and third switch transistor 130 and fourth switch transistor 140 are turned off. As shown in FIG 2, data can be read from first resistive memory element 151 and second resistive memory element 152 through path P21 and path P22.

[0021] 2, when reading a logic 0 from memory 100, the first source line SL1 may have a high voltage level VH and the second source line SL2 may have a high voltage level VH. In FIG. 2, when reading a logic 1 from memory 100, the first source line SL1 may have a high voltage level VH and the second source line SL2 may have a high voltage level VH.

[0022] The above write and read operations of memory 100 may be illustrated in Table 1. [Table 1]

[0023] FIG. 3 illustrates a circuit including memory 100 and memory 200 according to an embodiment. As shown in FIG. 3, memory 100 may be coupled to memory 200, which may be coupled to a first bit line BL1, a second bit line BL2, a first source line SL1, and a second source line SL2. By coupling memory 100 to memory 200, the circuit area is reduced. In FIG. 2, memory 100 may include first switch transistor 110 to fourth switch transistor 140, first resistive memory element 151, and second resistive memory element 152, as mentioned above, and therefore will not be described repeatedly. Similar to the first switch transistor 110 to the fourth switch transistor 140, the first resistive memory element 151, and the second resistive memory element 152 in memory 100, memory 200 may include a fifth switch transistor 210, a sixth switch transistor 220, a seventh switch transistor 230, an eighth switch transistor 240, a third resistive memory element 251, and a fourth resistive memory element 252. The coupling and operation of the components of memory 200 may be similar to the coupling and operation of the components of memory 100, and will not be described repeatedly.

[0024] 1 to 3, the same electrodes of the first resistive memory element 151 and the second resistive memory element 152 are formed at the same end, for example, the bottom electrodes BE of the first resistive memory element 151 and the second resistive memory element 152 are coupled to the sources of the first switch transistor 110 and the second switch transistor 120, respectively, thereby simplifying the associated connections of the components of memory 100.

[0025] As shown in Fig. 3, memory 100 and memory 200 may share a first bit line BL1, a second bit line BL2, a first source line SL1, and a second source line SL2. In terms of semiconductor layout, memory 100 and memory 200 may be integrated into a memory mini-array 800 during layout as shown in Fig. 8.

[0026] 4 to 8 show layout diagrams of a manufacturing process of memory 100 according to an embodiment. In the manufacturing process of memory 100, the layout diagrams may be shown sequentially in chronological order, such as in FIG. 4, FIG. 5, FIG. 6, FIG. 7, and FIG. 8.

[0027] As shown in FIG. 4, the memory 100 may include a diffusion layer DF1, a diffusion layer DF2, a polysilicon layer PLY1, a polysilicon layer PLY2, a polysilicon layer PLY3, and a polysilicon layer PLY4. The polysilicon layer PLY1, the polysilicon layer PLY2, the polysilicon layer PLY3, and the polysilicon layer PLY4 may correspond to a gate terminal of a transistor, such as a gate terminal of a field effect transistor (FET). The diffusion layer DF1 and the diffusion layer DF2 may be formed along a first direction D1. The polysilicon layers PLY1 to PLY4 may be formed along a second direction D2 that is substantially perpendicular to the first direction D1. Each of the polysilicon layers PLY1 to PLY4 may be formed at least partially overlapping with the diffusion layer DF1 and the diffusion layer DF2. In FIG. 4, the diffusion layer DF1 and the diffusion layer DF2 may be formed from the same diffusion layer. For example, a trench may be formed to separate the diffusion layer DF1 from the diffusion layer DF2. 4, a plurality of contact elements CT may be formed in the diffusion layers DF1 and DF2, and in a plan view, each of the contact elements CT may be disposed between two polysilicon layers.

[0028] 1, and the polysilicon layer PLY2 in FIG. 4 corresponds to the gate terminals of the third switch transistor 130 and the fourth switch transistor 140 in FIG. 1, the polysilicon layer PLY1 may be coupled to the read word line RWL in FIG. 1, and the polysilicon layer PLY2 in FIG. 4 may be coupled to the write word line WWL in FIG. 1.

[0029] In FIG. 5, a conductive layer M1, a plurality of conductive vias VA, and a plurality of resistive memory elements RSE1, RSE2, RSE3, and RSE4 may be formed on the diffusion layer DF1 and the diffusion layer DF2. One of the resistive memory elements RSE1, RSE2, RSE3, and RSE4 may correspond to one of the first resistive memory element 151, the second resistive memory element 152, the third resistive memory element 251, and the fourth resistive memory element 252 mentioned in FIG. 1 to FIG. 3. As shown in FIG. 5, in the plan view, the resistive memory element RSE1 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2, at least partially overlapping with the diffusion layer DF1. The resistive memory element RSE2 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2, at least partially overlapping with the diffusion layer DF2.

[0030] 6, a conductive layer M2 may be further formed on the diffusion layer DF1 and the diffusion layer DF2. In a plan view, the conductive layer M2 may not overlap with the resistive memory elements RSE1, RSE2, RSE3, and RSE4.

[0031] As shown in FIG. 7, a conductive layer M3 and a plurality of conductive vias V2 may be further formed on the conductive layer M2 and the resistive memory elements RSE1-RSE4.

[0032] As shown in FIG. 8, a conductive layer M4 and a plurality of conductive vias V3 may be further formed on the conductive layer M3.

[0033] 8, the first switch transistor 110, the second switch transistor 120, the third switch transistor 130, the fourth switch transistor 140, the resistive memory element RSE1, and the resistive memory element RSE2 may be used to form a memory including four switch transistors and two resistive memory elements, which may be referred to as a 4T2R memory (e.g., such as memory 100 mentioned above). The fifth switch transistor 210, the sixth switch transistor 220, the seventh switch transistor 230, the eighth switch transistor 240, the resistive memory element RSE3, and the resistive memory element RSE4 may be used to form another memory including four switch transistors and two resistive memory elements, which may be referred to as a 4T2R memory (e.g., such as memory 200 mentioned above). During layout, memory 100 and memory 200 may be used to form memory mini-array 800, and memory 100 and memory 200 may share bit and source lines, as shown in FIG.

[0034] Fig. 9 is a cross-sectional view of memory 100 along section line 9-9' in Fig. 8. As shown in Fig. 8, memory 100 may include diffusion layer DF1, diffusion layer DF2, conductive layer M11, conductive layer M12, contact element CT1, contact element CT2, conductive via VA1, conductive via VA2, resistive memory element RSE1, resistive memory element RSE2, conductive layer M21, conductive via V21, conductive via V22, conductive via V23, conductive layer M31, conductive layer M32, conductive layer M41, conductive layer M42, conductive layer M43, conductive layer M44, and conductive via V31.

[0035] In FIG. 9, a trench T1 may be used to separate the diffusion layer DF1 from the diffusion layer DF2. The conductive layer M11 may be formed at least partially overlapping the diffusion layer DF1. In the plan view, the conductive layer M11 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The conductive layer M12 may be formed at least partially overlapping the diffusion layer DF2. In the plan view, the conductive layer M12 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The conductive layer M11 and the conductive layer M12 in FIG. 9 may be formed from the same conductive layer, such as the conductive layer M1 in FIG. 5. As shown in FIG. 9, the conductive layer M11 may be formed above the first diffusion layer DF1. The conductive layer M12 may be formed above the diffusion layer DF2. The resistive memory element RSE1 may be formed above the conductive layer M11. The resistive memory element RSE2 may be formed above the conductive layer M12.

[0036] The contact element CT1 may be formed between the diffusion layer DF1 and the conductive layer M11, may be coupled to the diffusion layer DF1 and the conductive layer M11, and may at least partially overlap the diffusion layer DF1. In the plan view, the contact element CT1 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The contact element CT2 may be formed between the diffusion layer DF2 and the conductive layer M12, may be coupled to the diffusion layer DF2 and the conductive layer M12, and may at least partially overlap the diffusion layer DF2. In the plan view, the contact element CT2 may be formed between the polysilicon layer PLY1 and the polysilicon layer PLY2. The contact elements CT1 and CT2 may correspond to the contact elements CT in FIG. 4.

[0037] The conductive via VA1 may be formed between the conductive layer M11 and the resistive memory element RSE1, may be coupled to the conductive layer M11 and the resistive memory element RSE1, and may at least partially overlap with the resistive memory element RSE1.

[0038] Conductive via VA2 may be formed between conductive layer M12 and resistive memory element RSE2, may be coupled to conductive layer M12 and resistive memory element RSE2, and may at least partially overlap resistive memory element RSE2. Conductive via VA1 and conductive via VA2 may correspond to conductive via VA in FIG.

[0039] The resistive memory element RSE1 and the resistive memory element RSE2 may correspond to the first resistive memory element 151 and the second resistive memory element 152 in FIGS.

[0040] 9, the conductive layer M21 may be formed between the resistive memory element RSE1 and the resistive memory element RSE2 in a plan view. The conductive layer M31 may be formed on top of the resistive memory element RSE1 and may at least partially overlap with the resistive memory element RSE1.

[0041] The conductive layer M32 may be formed on the resistive memory element RSE2 and the conductive layer M21. The conductive layer M32 may be formed at least partially overlapping the resistive memory element RSE2 and the conductive layer M21. The conductive layer M21 may be formed from the conductive layer M2 in FIG. 6. The conductive layer M31 and the conductive layer M32 may be formed from the same conductive layer, such as the conductive layer M3 in FIG. 7.

[0042] In FIG. 9, conductive via V21 may be formed between resistive memory element RSE1 and conductive layer M31, may be coupled to resistive memory element RSE1 and conductive layer M31, and may at least partially overlap resistive memory element RSE1.

[0043] Conductive via V22 may be formed between conductive layer M21 and conductive layer M32, may be coupled to conductive layer M21 and conductive layer M32, and may at least partially overlap conductive layer M21.

[0044] Conductive via V23 may be formed between resistive memory element RSE2 and conductive layer M32, may be coupled to resistive memory element RSE2 and conductive layer M32, and may at least partially overlap resistive memory element RSE2. Conductive via V21, conductive via V22, and conductive via V23 in FIG. 9 may correspond to conductive via V2 in FIG.

[0045] 9, a conductive layer M41, a conductive layer M42, a conductive layer M43, and a conductive layer M44 may be formed on the conductive layer M31 and the conductive layer M32. The conductive layer M41 may be formed to at least partially overlap the conductive layer M32.

[0046] Conductive via V31 may be formed between conductive layer M32 and conductive layer M41, may be coupled to conductive layer M32 and conductive layer M41, and may at least partially overlap conductive layer M32. Conductive via V31 in Figure 9 may correspond to conductive via V3 in Figure 8. Conductive layer M41, conductive layer M42, conductive layer M43, and conductive layer M44 in Figure 9 may be formed from the same conductive layer, such as conductive layer M4 in Figure 8.

[0047] 1 and 2, the conductive layer M31 in FIG. 9 may be coupled to the first source line SL1 in FIG. 1, the conductive layer M41 in FIG. 9 may be coupled to the second source line SL2 in FIG. 1, the conductive layer M11 in FIG. 9 may be coupled to the source terminal of the first switch transistor 110 in FIG. 1, and the conductive layer M12 in FIG. 9 may be coupled to the source terminal of the second switch transistor 120 in FIG. 1.

[0048] FIG. 10 illustrates a read window for reading data from multiple memories according to one embodiment. In FIG. 10, the horizontal axis represents the current in the memory, and the vertical axis represents the statistical number of memories generated after normalization. In the horizontal axis of FIG. 10, the level HR may be the current level, where the resistive memory elements of the memory are set to have a high resistance value, and a logic 0 is written to the memory. The level LR may be the current level, where the resistive memory elements of the memory are set to have a low resistance value, and a logic 1 is written to the memory. The level NR may be the reference current level when the machine is used to measure the memory.

[0049] When the memory 100 provided by the embodiment is not used, the memory may be read according to the current of a single resistive memory element, and the read operation corresponds to a single mode operation. Therefore, the window corresponding to high resistance may be WH in Fig. 10, and the window corresponding to low resistance may be WL in Fig. 10. The windows may be expressed as WH=|NR-HR| and WL=|LR-NR|.

[0050] When the memory 100 provided by the embodiment is in use, the memory may be read according to the difference in current of the two resistive memory elements, and the read operation corresponds to a differential mode of operation. Therefore, the window corresponding to high resistance and low resistance may be expressed as W=|LR-HR|. Since |LR-HR| is larger than |NR-HR| and |LR-HR| is larger than |LR-NR|, the window may be expressed as W>WH and W>WL. As a result, when the memory 100 is in use, the read window is larger. Using a larger read window allows the data stored in the memory 100 to be effectively determined as 0 or 1 even when the memory 100 is written and read many times (for example, but not limited to, 100,000 times), improving the read accuracy of the memory and the reliability of the memory.

[0051] In summary, by using the memory 100 of the embodiment, the two resistive memory elements are arranged in the same direction, so that the connection between multiple components is simplified. The differential mode is used to expand the read window, and therefore improve the accuracy of reading the memory and the reliability of the memory after many accesses to the memory. In addition, with appropriate circuit design, layout design, and semiconductor structure, two memory cells (such as the memory 100 and the memory 200 in FIG. 3) can be coupled together to further reduce the circuit area. Therefore, the memory and memory mini-array of the embodiment are useful in this field.

[0052] Those skilled in the art will readily appreciate that numerous modifications and variations of the devices and methods may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A memory, a first switch transistor including a drain terminal, a source terminal, and a gate terminal; a second switch transistor including a drain terminal, a source terminal, and a gate terminal; a third switch transistor including a drain terminal coupled to the source terminal of the first switch transistor, a source terminal, and a gate terminal; a fourth switch transistor including a drain terminal coupled to the source terminal of the second switch transistor, a source terminal, and a gate terminal; a first resistive memory element including a first terminal coupled to the source terminal of the fourth switch transistor and a second terminal coupled to the source terminal of the first switch transistor; a second resistive memory element including a first terminal coupled to the source terminal of the third switch transistor and a second terminal coupled to the source terminal of the second switch transistor; Memory.

2. 2. The memory of claim 1, wherein the first switch transistor and the second switch transistor are turned off, and the third switch transistor and the fourth switch transistor are turned on when writing data to the memory.

3. 2. The memory of claim 1, wherein when reading data from the memory, the first switch transistor and the second switch transistor are turned on, and the third switch transistor and the fourth switch transistor are turned off.

4. the drain terminal of the first switch transistor is coupled to a first bit line and the gate terminal of the first switch transistor is coupled to a read word line; the drain terminal of the second switch transistor is coupled to a second bit line and the gate terminal of the second switch transistor is coupled to the read word line; the gate terminal of the third switch transistor is coupled to a write word line and the source terminal of the third switch transistor is coupled to a second source line; 2. The memory of claim 1, wherein the gate terminal of the fourth switch transistor is coupled to the write word line and the source terminal of the fourth switch transistor is coupled to a first source line.

5. 5. The memory of claim 4, wherein when writing a logic 0 to the memory, the first and second switch transistors are turned off and the third and fourth switch transistors are turned on, the first source line has a high voltage level, and the second source line has a low voltage level that is lower than the high voltage level.

6. 6. The memory of claim 5, wherein when writing the logic 0 to the memory, the first resistive memory element is set to have a high resistance and the second resistive memory element is set to have a low resistance lower than the high resistance.

7. 5. The memory of claim 4, wherein when reading a logic 0 from the memory, the first and second switch transistors are turned on and the third and fourth switch transistors are turned off, the first source line has a high voltage level, and the second source line has the high voltage level.

8. 5. The memory of claim 4, wherein when writing a logical 1 to the memory, the first switch transistor and the second switch transistor are turned off and the third switch transistor and the fourth switch transistor are turned on, the first source line has a low voltage level and the second source line has a high voltage level higher than the low voltage level.

9. 9. The memory of claim 8, wherein when writing the logical 1 to the memory, the first resistive memory element is set to have a low resistance and the second resistive memory element is set to have a high resistance that is higher than the low resistance.

10. 5. The memory of claim 4, wherein when reading a logic one from the memory, the first and second switch transistors are turned on and the third and fourth switch transistors are turned off, the first source line has a high voltage level, and the second source line has the high voltage level.

11. the first resistive memory element includes a top electrode coupled to the first terminal of the first resistive memory element, a bottom electrode coupled to the second terminal of the first resistive memory element, and a transition metal oxide layer formed between the top electrode of the first resistive memory element and the bottom electrode of the first resistive memory element; 5. The memory of claim 4, wherein the second resistive memory element includes a top electrode coupled to the first terminal of the second resistive memory element, a bottom electrode coupled to the second terminal of the second resistive memory element, and a transition metal oxide layer formed between the top electrode of the second resistive memory element and the bottom electrode of the second resistive memory element.

12. 1. A memory including a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistive memory element, and a second resistive memory element, wherein the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the first resistive memory element, and the second resistive memory element in the memory are A first diffusion layer (DF1) formed along a first direction; a second diffusion layer (DF2) formed along the first direction; a first polysilicon layer (PLY1) formed along a second direction and at least partially overlapping the first diffusion layer and the second diffusion layer, the first direction being substantially perpendicular to the second direction; a second polysilicon layer (PLY2) formed along the second direction and at least partially overlapping the first diffusion layer and the second diffusion layer; a first resistive memory element (RSE1) formed between the first polysilicon layer and the second polysilicon layer at least partially overlapping the first diffusion layer, the first resistive memory element (RSE1) including a first terminal and a second terminal; a second resistive memory element (RSE2) formed between the first polysilicon layer and the second polysilicon layer at least partially overlapping the second diffusion layer, the second resistive memory element (RSE2) including a first terminal and a second terminal; a first conductive layer (M11) formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the first diffusion layer; a second conductive layer (M12) formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the second diffusion layer; a first conductive via (VA1) coupled to the first conductive layer (M11) and the second terminal of the first resistive memory element (RSE1) and formed at least partially overlapping the first resistive memory element; a second conductive via (VA2) coupled to the second conductive layer (M12) and the second terminal of the second resistive memory element (RSE2) and formed at least partially overlapping the second resistive memory element; a fourth conductive layer (M31) formed at least partially overlapping the first resistive memory element; a fifth conductive layer (M32) formed at least partially overlapping the second resistive memory element and the third conductive layer (M21); a third conductive via (V21) coupled to the first terminal of the first resistive memory element (RSE1) and to the fourth conductive layer (M31) and formed to at least partially overlap the first resistive memory element; a fifth conductive via (V23) coupled to the first terminal of the second resistive memory element (RSE2) and to the fifth conductive layer (M32) and formed at least partially overlapping the second resistive memory element; the first conductive layer (M11) is coupled to a source terminal of the first switch transistor and a drain terminal of the third switch transistor, the fourth conductive layer (M31) is coupled to a first source line (SL1) which is coupled to a source terminal of the fourth switch transistor; the second conductive layer (M12) is coupled to a source terminal of the second switch transistor and a drain terminal of the fourth switch transistor, and the fifth conductive layer (M32) is coupled to a second source line (SL2) that is coupled to a source terminal of the third switch transistor; Memory.

13. The memory of claim 12 , wherein the first diffusion layer and the second diffusion layer are formed using a same diffusion layer.

14. The first conductive layer and the second conductive layer are formed from the same conductive layer, and the component comprises: a first contact element (CT1) coupled to the first diffusion layer and the first conductive layer, at least partially overlapping the first diffusion layer, and formed between the first polysilicon layer and the second polysilicon layer; a second contact element (CT2) coupled to the second diffusion layer and the second conductive layer, at least partially overlapping the second diffusion layer, and formed between the first polysilicon layer and the second polysilicon layer; The memory of claim 12 further comprising:

15. The fourth conductive layer and the fifth conductive layer are formed from the same conductive layer, and the component comprises: a third conductive layer formed between the first resistive memory element and the second resistive memory element; a fourth conductive via coupled to the third conductive layer and the fifth conductive layer and formed to at least partially overlap the third conductive layer; The memory of claim 14 further comprising:

16. A memory mini-array including a first memory and a second memory, the first memory including a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistive memory element, and a second resistive memory element, the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the first resistive memory element, and the second resistive memory element in the first memory being A first diffusion layer (DF1) formed along a first direction; a second diffusion layer (DF2) formed along the first direction; a first polysilicon layer (PLY1) formed along a second direction and at least partially overlapping the first diffusion layer and the second diffusion layer, the first direction being substantially perpendicular to the second direction; a second polysilicon layer (PLY2) formed along the second direction and at least partially overlapping the first diffusion layer and the second diffusion layer; a first resistive memory element (RSE1) formed between the first polysilicon layer and the second polysilicon layer at least partially overlapping the first diffusion layer, the first resistive memory element (RSE1) including a first terminal and a second terminal; a second resistive memory element (RSE2) formed between the first polysilicon layer and the second polysilicon layer at least partially overlapping the second diffusion layer, the second resistive memory element (RSE2) including a first terminal and a second terminal; a first conductive layer (M11) formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the first diffusion layer; a second conductive layer (M12) formed between the first polysilicon layer and the second polysilicon layer, at least partially overlapping the second diffusion layer; a first conductive via (VA1) coupled to the first conductive layer (M11) and the second terminal of the first resistive memory element (RSE1) and formed at least partially overlapping the first resistive memory element; a second conductive via (VA2) coupled to the second conductive layer (M12) and the second terminal of the second resistive memory element (RSE2) and formed at least partially overlapping the second resistive memory element; a fourth conductive layer (M31) formed at least partially overlapping the first resistive memory element; a fifth conductive layer (M32) formed at least partially overlapping the second resistive memory element and the third conductive layer (M21); a third conductive via (V21) coupled to the first terminal of the first resistive memory element (RSE1) and to the fourth conductive layer (M31) and formed to at least partially overlap the first resistive memory element; a fifth conductive via (V23) coupled to the first terminal of the second resistive memory element (RSE2) and to the fifth conductive layer (M32) and formed at least partially overlapping the second resistive memory element; the first conductive layer (M11) is coupled to a source terminal of the first switch transistor and a drain terminal of the third switch transistor, the fourth conductive layer (M31) is coupled to a first source line (SL1) which is coupled to a source terminal of the fourth switch transistor; the second conductive layer (M12) is coupled to a source terminal of the second switch transistor and a drain terminal of the fourth switch transistor, and the fifth conductive layer (M32) is coupled to a second source line (SL2) that is coupled to a source terminal of the third switch transistor; Memory mini array.

17. the second memory includes a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, an eighth switch transistor, a third resistive memory element, and a fourth resistive memory element, the fifth switch transistor, the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, the third resistive memory element, and the fourth resistive memory element being a third polysilicon layer formed along the second direction and at least partially overlapping the first diffusion layer and the second diffusion layer; a fourth polysilicon layer formed along the second direction and at least partially overlapping the first diffusion layer and the second diffusion layer, the third polysilicon layer being formed between the second polysilicon layer and the fourth polysilicon layer; a third resistive memory element formed between the third polysilicon layer and the fourth polysilicon layer at least partially overlapping the first diffusion layer; and a fourth resistive memory element formed between the third polysilicon layer and the fourth polysilicon layer at least partially overlapping the second diffusion layer.

18. 1. A memory including a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistive memory element, and a second resistive memory element, wherein the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the first resistive memory element, and the second resistive memory element in the memory are A first diffusion layer (DF1); A second diffusion layer (DF2); a first polysilicon layer (PLY1) formed along a second direction, the first direction in which the first diffusion layer and the second diffusion layer are formed being substantially perpendicular to the second direction; a second polysilicon layer (PLY2) formed along the second direction; a first resistive memory element (RSE1) formed on a first conductive layer, the first resistive memory element (RSE1) including a first terminal and a second terminal; a second resistive memory element (RSE2) formed on the second conductive layer, the second resistive memory element (RSE2) including a first terminal and a second terminal; a first conductive layer (M11) formed on the first diffusion layer and coupled to the second terminal of the first resistive memory element (RSE1); a second conductive layer (M12) formed on the second diffusion layer and coupled to the second terminal of the second resistive memory element (RSE2); a fourth conductive layer (M31) coupled to the first terminal of the first resistive memory element (RSE1); a fifth conductive layer (M32) coupled to the first terminal of the second resistive memory element (RSE2); the first conductive layer (M11) is coupled to a source terminal of the first switch transistor and a drain terminal of the third switch transistor, the fourth conductive layer (M31) is coupled to a first source line (SL1) which is coupled to a source terminal of the fourth switch transistor; the second conductive layer (M12) is coupled to a source terminal of the second switch transistor and a drain terminal of the fourth switch transistor, and the fifth conductive layer (M32) is coupled to a second source line (SL2) that is coupled to a source terminal of the third switch transistor; Memory.

19. The components include: a first contact element coupled to the first diffusion layer and the first conductive layer and formed between the first diffusion layer and the first conductive layer; a second contact element coupled to the second diffusion layer and the second conductive layer and formed between the second diffusion layer and the second conductive layer; a first conductive via coupled to the first conductive layer and the first resistive memory element and formed between the first conductive layer and the first resistive memory element; 20. The memory of claim 18, further comprising: a second conductive via coupled to the second conductive layer and the second resistive memory element and formed between the second conductive layer and the second resistive memory element.

20. The components include: further comprising a third conductive layer; the fourth conductive layer (M31) is formed on the first resistive memory element; the fifth conductive layer (M32) is formed on the second resistive memory element and the third conductive layer; The components include: a third conductive via coupled to the first resistive memory element and the fourth conductive layer and formed between the first resistive memory element and the fourth conductive layer; a fourth conductive via coupled to the third conductive layer and the fifth conductive layer and formed between the third conductive layer and the fifth conductive layer; a fifth conductive via coupled to the second resistive memory element and to the fifth conductive layer and formed between the second resistive memory element and the fifth conductive layer; 20. The memory of claim 19, wherein the fourth conductive layer and the fifth conductive layer are formed from the same conductive layer.

21. a sixth conductive layer formed on the fifth conductive layer; and 21. The memory of claim 20, further comprising: a sixth conductive via coupled to the fifth conductive layer and the sixth conductive layer and formed between the fifth conductive layer and the sixth conductive layer.

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