Semiconductor device, semiconductor integrated circuit, and method for manufacturing semiconductor device

Abstract

To provide a smaller semiconductor element that can be manufactured easily at low cost and can obtain large on current, a semiconductor integrated circuit, and a manufacturing method for the semiconductor element.SOLUTION: A semiconductor element 10 includes an element structure of a tunnel field effect transistor. A channel part 13 formed of an indirect transition type semiconductor is configured as a plate-shaped part having one end connected to a source part 14 and the other end connected to a drain part 15. At least a pair of opposing surfaces among two pairs of first opposing surfaces and second opposing surfaces which form the channel part 13 and oppose each other in directions orthogonal to a direction where current flows from the source part 14 to the drain part 15 is formed so that electron confinement surfaces that a direct transition type semiconductor band structure can provide in a pseudo manner to the indirect transition type semiconductor by the restriction of electron movement are disposed with a space of 15 nm therebetween at maximum.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a tunnel field effect transistor structure, a semiconductor integrated circuit, and a method for manufacturing the semiconductor device. [Background technology]

[0002] In recent years, there have been many attempts to reduce the power consumption of LSIs. One of these attempts is to reduce the operating voltage, but with the MOS transistors used in conventional circuits, it is difficult to significantly reduce the voltage due to physical limitations. Therefore, in order to reduce the power consumption of LSIs, the development of low-voltage switching devices based on a different operating principle is desired.

[0003] One such transistor is a tunnel field effect transistor that utilizes the band-to-band tunneling phenomenon of semiconductors, and uses the tunneling phenomenon as a different operating principle from that of MOS transistors. The band-to-band tunneling phenomenon is a phenomenon in which even electrons with an energy level that is too low to cross a potential barrier pass through to the other side of the barrier with a certain probability. This potential barrier is called a tunnel barrier.

[0004] Due to the operating principle of the tunnel field effect transistor, the speed at which electrons pass through the tunnel barrier, i.e., the magnitude of the tunnel current, can be controlled by the gate voltage, and a prototype that can operate at a lower voltage than the MOS transistor has been reported (for example, see Non-Patent Document 1). However, in the prototype, the tunnel resistance that determines the amount of the tunnel current is large, so there is a problem that the current in the on state (on current) is small. To solve this problem, it is possible to simply increase the area of ​​the tunnel junction that forms the tunnel barrier, i.e., the area where the band-to-band tunneling phenomenon occurs, to increase the current per element even at a low current density. However, this configuration would result in an element that is large in size and is impractical for use in forming integrated circuits. In order to obtain a highly integrated and practical integrated circuit, it is necessary to reduce the size of the element.

[0005] By the way, there are two types of semiconductor materials for manufacturing the tunnel field effect transistor: direct transition type semiconductors and indirect transition type semiconductors. The former mainly includes compound semiconductors, and the latter mainly includes Group IV semiconductors. Generally, the probability of the band-to-band tunneling phenomenon occurring is higher in direct transition semiconductors than in indirect transition semiconductors, so the use of compound semiconductors is considered to be effective in increasing the on-current (see Non-Patent Document 2). However, the method of using compound semiconductors has a problem in that it is not possible to use many of the existing semiconductor device manufacturing facilities for manufacturing the tunnel field effect transistors, and therefore new capital investment is required, resulting in high manufacturing costs.

[0006] On the other hand, typical materials of the Group IV semiconductor are silicon and germanium, and the tunnel field-effect transistor can be manufactured using existing semiconductor device manufacturing facilities. However, the probability of the band-to-band tunneling phenomenon occurring is low, and there remains a problem of increasing the on-current. To address this issue, the present inventors have reported a tunnel field effect transistor in which the on-current is increased by introducing an isoelectronic trap forming impurity into the indirect transition semiconductor (see Patent Document 1). The method of introducing isoelectronic trap forming impurities is one method of solving the problem.

[0007] As another method, it has been reported that the on-current can be increased by introducing a silicon nanowire structure, in which silicon is processed into a wire shape with a diameter of about 3 nm (see Non-Patent Document 3). This report also reports that the silicon nanowire structure makes silicon, which is originally an indirect transition semiconductor, a pseudo-direct transition semiconductor. However, the silicon nanowires with a diameter of 3 nm are difficult to process, which increases the manufacturing cost, especially since the cross section of the silicon nanowire is a perfect circle and the gate electrode is disposed so as to uniformly cover the entire circumference of the silicon nanowire, which increases the difficulty of the manufacturing process and the manufacturing cost. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 6253034 [Non-patent literature]

[0009] [Non-Patent Document 1] WY Choi et al., IEEE Electron Device Letters vol.28, p743(2007), “Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60mV / dec” [Non-Patent Document 2] G. Dewey et al., 2011 International Electron Devices Meeting Technical Digest, 33.6, “Fabrication, characterization, and physics of III-V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing” [Non-Patent Document 3] Mathieu Luisier et al., Journal of Applied Physics vol.107, p.084507 (2010), “Simulation of nanowire tunneling transistors: From the Wentzel-Kramers-Brillouin approximation to full-band phonon-assisted tunneling” Summary of the Invention [Problem to be solved by the invention]

[0010] The present invention aims to solve the above-mentioned problems in the prior art and to achieve the following object: That is, the present invention aims to provide a semiconductor element, a semiconductor integrated circuit, and a method for manufacturing the semiconductor element that are small, can be manufactured easily and at low cost, and can provide a large on-current. [Means for solving the problem]

[0011] The means for solving the above problems are as follows. <1> A semiconductor element having a tunnel field effect transistor element structure, wherein a channel portion formed of an indirect transition type semiconductor is configured with a plate-shaped portion having one end connected to a source portion and the other end connected to a drain portion, and at least one pair of opposing surfaces of first opposing surfaces and second opposing surfaces that constitute the plate-shaped portion and that face each other in a direction perpendicular to a direction in which a current flows from the source portion to the drain portion are formed by arranging electron confinement surfaces at an opposing distance of at most 15 nm, the electron confinement surfaces enabling the indirect transition type semiconductor to be given a band structure of a direct transition type semiconductor in a pseudo manner by restricting electron motion. <2> All four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces are constituted by electron confinement surfaces. <1> The semiconductor element according to claim 1. <3> The gate portion constituting the element structure of the tunnel field effect transistor is arranged so as to cover at most three of the four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces, in whole or in part. <1> from <2> 2. The semiconductor device according to claim 1 , <4> The indirect transition semiconductor is silicon, and the electron confinement surface is a {100} surface. <1> from <3> 2. The semiconductor device according to claim 1 , <5> The indirect transition semiconductor is germanium, and the electron confinement surface is a {111} surface. <1> from <3> 2. The semiconductor device according to claim 1 , <6> The indirect transition semiconductor is a mixed crystal of silicon and germanium, and when the germanium content is less than 85 atomic %, the electron confinement surface is a {100} surface, and when the germanium content is 85 atomic % or more, the electron confinement surface is a {111} surface. <1> from <3> 2. The semiconductor device according to claim 1 , <7> The tunnel junction formed in the tunnel field effect transistor is composed of a semiconductor junction. <1> from <6> 2. The semiconductor device according to claim 1 , <8> The tunnel junction formed in the tunnel field effect transistor is a Schottky junction. <1> from <6> 2. The semiconductor device according to claim 1 , <9> The above <1> from <8> 2. A semiconductor integrated circuit comprising the semiconductor element according to claim 1 . <10> The above <1> from <8> A method for manufacturing a semiconductor device according to any one of the preceding claims, A method for manufacturing a semiconductor element, comprising: forming a channel portion having a plate-shaped portion using an indirect transition semiconductor, one end of which is connected to a source portion and the other end of which is connected to a drain portion; and forming at least one pair of opposing surfaces of two pairs of opposing surfaces, i.e., first opposing surfaces and second opposing surfaces that face each other in a direction perpendicular to the direction of current flow from the source portion to the drain portion, constituting the plate-shaped portion, by arranging the opposing surfaces at an opposing distance of at most 15 nm to form electron confinement surfaces that can impart a pseudo-band structure of a direct transition semiconductor to the indirect transition semiconductor by regulating electron motion. Effect of the Invention

[0012] According to the present invention, it is possible to solve the above-mentioned problems in the conventional technology, and to provide a semiconductor element, a semiconductor integrated circuit, and a method for manufacturing the semiconductor element that are small, can be manufactured easily and at low cost, and can provide a large on-current. [Brief description of the drawings]

[0013] [Figure 1(a)] FIG. 2 is a diagram showing the energy band of an indirect transition semiconductor in a bulk state. [Figure 1(b)] FIG. 1 is a diagram showing an energy band of an indirect transition semiconductor that has been pseudo-direct transition semiconductor. [Diagram 2] FIG. 1 is an explanatory diagram for explaining a state in which an indirect transition semiconductor is pseudo-changed into a direct transition semiconductor. [Diagram 3] FIG. 2 is a diagram showing an example of an N-type tunnel field effect transistor, in which a tunnel current increases. [Figure 4] 1 is an exploded perspective view of a semiconductor element according to a first embodiment. [Figure 5(a)] 5 is a cross-sectional view taken along a direction perpendicular to the direction in which current flows (the X direction in FIG. 4). [Figure 5(b)] 5(a) is a cross-sectional view taken along line AA in a direction parallel to the direction of current flow (Y direction in FIG. 4). [Figure 6(a)] FIG. 2 is a diagram showing an iso-energy surface near the bottom of the conduction band of silicon in a bulk state. [Figure 6(b)] FIG. 2 is a diagram showing an isoenergy surface near the bottom of the conduction band of germanium in a bulk state. [Figure 7] FIG. 11 is an exploded perspective view of a semiconductor element according to a second embodiment. [Figure 8(a)] 8 is a cross-sectional view in a direction perpendicular to the direction in which current flows (X direction in FIG. 7). [Figure 8(b)] 8(a) is a cross-sectional view taken along line AA in a direction parallel to the direction of current flow (Y direction in FIG. 7). [Figure 9(a)]1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device 10 according to a first embodiment. [Figure 9(b)] 9(a) is a cross-sectional view taken along line AA in FIG. 9(a), showing a manufacturing process of the semiconductor element 10 according to the first embodiment. [Figure 10(a)] 2 is a diagram showing a manufacturing process of the semiconductor device 10 according to the first embodiment. FIG. [Figure 10(b)] 10(a) is a cross-sectional view taken along line AA in FIG. 10(a), showing a second diagram of the manufacturing process of the semiconductor element 10 according to the first embodiment. [Figure 11(a)] 3 is a diagram showing a manufacturing process of the semiconductor device 10 according to the first embodiment. FIG. [Figure 11(b)] 11(a) is a cross-sectional view taken along line AA in FIG. 11(a), showing a third diagram of the manufacturing process of the semiconductor element 10 according to the first embodiment. [Figure 12(a)] FIG. 4 is a diagram showing a manufacturing process of the semiconductor device 10 according to the first embodiment. [Figure 12(b)] 12(a) is a cross-sectional view taken along line AA in FIG. 12(a), showing a fourth diagram of the manufacturing process of the semiconductor device 10 according to the first embodiment. [Figure 13(a)] FIG. 5 is a diagram (5) showing a manufacturing process of the semiconductor device 10 according to the first embodiment. [Figure 13(b)] 13(a) is a cross-sectional view taken along line AA in FIG. 13(a), showing a fifth diagram of the manufacturing process of the semiconductor device 10 according to the first embodiment. [Figure 14(a)] FIG. 6 is a diagram showing a manufacturing process of the semiconductor device 10 according to the first embodiment. [Figure 14(b)] 14(a) is a cross-sectional view taken along line AA in FIG. 14(a), showing a sixth diagram of a manufacturing process for the semiconductor device 10 according to the first embodiment. [Figure 15(a)] 7 is a diagram showing a manufacturing process of the semiconductor device 10 according to the first embodiment. [Figure 15(b)] 15(a) is a cross-sectional view taken along line AA in FIG. 15(a), showing a seventh diagram of a manufacturing process for the semiconductor device 10 according to the first embodiment. [Figure 16(a)] 1A to 1C are diagrams illustrating an outline of a method for forming a channel portion using an SOI substrate having a (100) plane as a main surface. [Figure 16(b)] FIG. 1 is a diagram showing an outline of a method for forming a channel portion using a GOI substrate having a (110) plane as its principal surface. [Figure 17(a)] 1A to 1C are diagrams (1) illustrating a manufacturing process for a semiconductor element of the present invention related to a semiconductor element 20 according to a second embodiment. [Figure 17(b)] FIG. 17(a) is a cross-sectional view taken along line AA in FIG. 17(a), showing a manufacturing process of the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment. [Figure 18(a)] 10A to 10C are diagrams (2) illustrating a manufacturing process for a semiconductor element of the present invention related to a semiconductor element 20 according to a second embodiment. [Figure 18(b)] 18(a) is a cross-sectional view taken along line AA of FIG. 18(a), showing a manufacturing process for the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment (2). [Figure 19(a)] 3A to 3C are diagrams illustrating a manufacturing process for a semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment. [Figure 19(b)] 19(a) is a cross-sectional view taken along line AA of FIG. 19(a), showing a manufacturing process for the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment (3). [Figure 20(a)] FIG. 2 is a diagram showing the energy band structure of bulk silicon. [Figure 20(b)] FIG. 1 is a diagram showing the energy band structure of a silicon plate having a thickness of about 1.1 nm. [Figure 21] FIG. 1 is a diagram showing the correlation between the energy band structure of silicon and the silicon film thickness. [Figure 22] FIG. 1 is an explanatory diagram for explaining the configuration of a thin-film TFET that is the subject of a simulation test. [Figure 23] FIG. 13 is a diagram showing the results of a simulation test of band-to-band tunneling current. [Figure 24] FIG. 13 is a diagram showing a scanning electron microscope image taken from above of the semiconductor element according to Example 4. [Diagram 25] FIG. 11 is a diagram showing the switching characteristics of a semiconductor element according to Example 4. [Figure 26]FIG. 13 is a diagram showing the relationship between the tunnel current and the Fin width. [Figure 27] FIG. 13 is a graph showing the relationship between tunnel current density and Fin width. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] (Semiconductor device and its manufacturing method) The semiconductor element of the present invention has an element structure of a tunnel field effect transistor, and is characterized in that a channel portion formed of an indirect transition type semiconductor is configured with a plate-shaped portion having one end connected to a source portion and the other end connected to a drain portion, and at least one of two pairs of opposing surfaces, i.e., first opposing surfaces and second opposing surfaces that oppose each other in a direction perpendicular to the direction in which a current flows from the source portion to the drain portion, that constitute the plate-shaped portion are formed so that electron confinement surfaces are arranged at an opposing distance of at most 15 nm.

[0015] Furthermore, the method for manufacturing a semiconductor element of the present invention is a method for manufacturing the semiconductor element of the present invention, and is characterized in that it includes a channel portion formation step of forming the channel portion having a plate-shaped portion having one end connected to the source portion and the other end connected to the drain portion using the indirect transition semiconductor, and forming at least one pair of opposing surfaces of the first opposing surfaces and the second opposing surfaces that constitute the plate-shaped portion and that face each other in a direction perpendicular to the direction in which a current flows from the source portion to the drain portion, with the electron confinement surfaces being disposed at an opposing distance of at most 15 nm.

[0016] Due to these features, the behavior of the electrons trapped in the electron confinement surface is controlled in the plate-shaped portion made of the indirect transition semiconductor in the same manner as in the direct transition semiconductor, thereby increasing the tunneling current of the semiconductor element. Also, by forming the channel portion through which the tunneling current flows with the plate-shaped portion that can be manufactured small, easily, and at low cost using existing manufacturing equipment, the semiconductor element can be manufactured small, easily, and at low cost.

[0017] The mechanism by which the tunnel current increases will now be described in detail. A distinctive feature of the indirect transition semiconductor is that the momentum at the top of the valence band does not coincide with the momentum at the bottom of the conduction band. That is, as shown in Fig. 1(a), the momentum of electrons at the top of the valence band is zero, whereas the momentum of electrons at the bottom of the conduction band is not zero. In other words, there is a difference in momentum between the electrons at the top of the valence band and the electrons at the bottom of the conduction band. Note that Fig. 1(a) shows the energy band of the indirect transition semiconductor in a bulk state. In the transition of electron states from the valence band to the conduction band accompanying band-to-band tunneling, the law of conservation of momentum must be satisfied. Due to the limitations of the law of conservation of momentum, it is difficult to obtain a large tunnel current in the tunnel field effect transistor using the indirect transition semiconductor having a momentum shift.

[0018] However, by converting the indirect transition semiconductor into a pseudo-direct transition semiconductor, it is possible to increase the tunnel current even in the tunnel field effect transistor using the indirect transition semiconductor, and the configuration required for this is a configuration in which the plate-shaped portion is provided to the channel portion. In the plate-shaped portion, when the following two conditions are satisfied: (1) at least one pair of opposing surfaces, i.e., first opposing surfaces and second opposing surfaces opposing surfaces in a direction perpendicular to the direction in which the current flows from the source portion to the drain portion, is composed of electron confinement surfaces; and (2) the electron confinement surfaces are arranged at an extremely short opposing distance of at most 15 nm, the indirect transition semiconductor is made into a pseudo-direct transition semiconductor. That is, as shown in Fig. 1(b), the plate-shaped portion satisfying the two conditions loses the characteristic features of the indirect transition semiconductor described above, and the momentum of the electrons at the top of the valence band and the bottom of the conduction band are both zero. Fig. 1(b) is a diagram showing the energy band of the indirect transition semiconductor that has been pseudo-formed into a direct transition semiconductor.

[0019] This will be described with reference to FIG. As shown in the example of FIG. 2, when the distance between the opposing electron confinement surfaces is shortened, that is, the k x As the thickness in the direction is reduced, electrons are confined to a narrow region. When the thickness is 15 nm or less, k x The momentum of the electrons in the direction is lost. Therefore, a state occurs in which the momentum of the electrons at the top of the valence band and the bottom of the conduction band are both zero (the transition state of the direct transition type semiconductor). At this time, the direction in which the current flows from the source section to the drain section is k y Direction (or k z The indirect transition semiconductor 1 is arranged in a direction parallel to the direction of the y Direction (or k z direction) and the perpendicular direction k x If the opposing surfaces facing each other in the direction are configured as the electron confinement surfaces, the restriction due to the law of conservation of momentum is alleviated, and the tunneling probability of electrons directly transitioning from the valence band to the conduction band is increased, resulting in a large tunneling current. Hereinafter, the effect of obtaining a large tunneling current based on the control of this electron motion is referred to as the "folding effect" after the way electrons are folded into local positions depending on the thickness. FIG. 2 is an explanatory diagram for explaining how the indirect transition semiconductor is pseudo-changed into a direct transition semiconductor.

[0020] The phenomenon of light emission from the indirect transition semiconductor can be cited as a physical phenomenon that suggests the thinning of the indirect transition semiconductor into a pseudo direct transition semiconductor. Although it is not possible to obtain a large amount of light emission from the indirect transition semiconductor, it is known that the light emission intensity increases exponentially by thinning the layer (see Reference 1 below). This is because the indirect transition semiconductor becomes a pseudo direct transition semiconductor, and electron-hole pairs easily recombine at the point of zero momentum. Reference 1: JP 2007-294628 A

[0021] Although the light emission phenomenon and the band-to-band tunneling phenomenon are different phenomena, in the present invention, the thinning of the indirect transition semiconductor to form a pseudo direct transition semiconductor is applied to a tunnel field effect transistor utilizing the band-to-band tunneling phenomenon. By satisfying the above-mentioned two conditions for the plate-shaped portion, an increase in the tunnel current in the tunnel field effect transistor can be obtained. FIG. 3 is a diagram showing a schematic diagram of an increase in tunnel current using an N-type tunnel field effect transistor as an example. As shown in the example of FIG. 3, the p + When passing through the tunnel barrier of the tunnel junction 2 formed between the source region and the n-type channel region, in the plate-shaped indirect transition semiconductor 1', the convolution effect causes a state in which the momentum of the electrons at the top of the valence band and the bottom of the conduction band both become zero, thereby easing the restriction due to the law of conservation of momentum and increasing the tunneling probability. Next, each component of the semiconductor device of the present invention will be described in detail.

[0022] <Element structure of tunnel field effect transistor> The element structure of the tunnel field effect transistor is composed of the source portion, the channel portion arranged adjacent to the source portion and having the boundary as the tunnel junction where the tunnel barrier is formed, the drain portion arranged adjacent to the channel portion, and a gate portion arranged so as to cover all or a part of the exposed portion of the channel portion. In the semiconductor element of the present invention, the specific structure of the channel portion in the element structure has the above-mentioned features.

[0023] <Source and drain parts> The source section and the drain section are formed in the same manner as known source and drain regions formed by introducing impurities into a semiconductor, or known source and drain electrodes formed from a metal material.

[0024] When the source section and the drain section are formed as the source region and the drain region, the source region is formed of a first conductivity type, which is either a P type or an N type, and the drain region is formed of a second conductivity type, which is the conductivity type different from the first conductivity type. Furthermore, the source region forms a semiconductor junction composed of a semiconductor junction with the channel section formed of the indirect transition semiconductor, and the tunnel junction is composed of the semiconductor junction. The method for forming the tunnel junction in the semiconductor junction is not particularly limited, and may be a known method such as providing a steep concentration profile of an impurity substance between the source region and the channel region. The semiconductor forming the source region and the drain region is not particularly limited as long as it is a material capable of forming a tunnel junction with the channel portion, and any known semiconductor material can be used, but from the viewpoint of manufacturing, it is preferable to form the source region and the drain region from the same semiconductor material as the indirect transition semiconductor constituting the channel portion. That is, in this case, a typical manufacturing method can be applied in which the impurity is doped into one semiconductor substrate by ion implantation or the like to form the source region and the drain region. The impurities are not particularly limited, and known impurities such as boron, phosphorus, and arsenic can be used. When the semiconductor element is operated as a P-type tunnel field effect transistor, the source region is made to be an N-type (N + ) semiconductor region, and the drain region is a P-type (P + On the other hand, when the semiconductor element is operated as an N-type tunnel field effect transistor, the source region is configured as a P-type (P + ) semiconductor region, and the drain region is an N-type (N + ) semiconductor region.

[0025] When the source section and the drain section are formed as the source electrode and the drain electrode, the source electrode and the channel section are joined by a Schottky junction to form a tunnel junction. The source electrode and the drain electrode are not particularly limited, and may be made of a known metal material. For example, when the channel portion is made of silicon, NiSi 2 When the channel portion is made of germanium, examples of the metal germanides include NiGe, and when the channel portion is made of a mixed crystal of silicon and germanium, examples of the alloys include alloys containing Ni, Si, and Ge, such as an alloy of NiSi and NiGe. The method for forming the source electrode and the drain electrode is not particularly limited, and examples of the method include known methods using the metal materials, such as sputtering and CVD.

[0026] <Channel section> As described above, the channel portion is made of the indirect transition semiconductor and has the plate-shaped portion having one end connected to the source portion and the other end connected to the drain portion. Based on the two conditions described above, the plate-shaped portion is formed such that at least one pair of opposing surfaces, consisting of the first opposing surfaces and the second opposing surfaces that face each other in a direction perpendicular to the direction in which the current flows from the source portion to the drain portion, has the electron confinement surfaces spaced apart from each other by a distance of at most 15 nm.

[0027] The plate-shaped portion may be any portion present in the channel portion, and may be formed of the entire channel portion or a part of the channel portion. The band-to-band tunneling phenomenon occurs when electrons pass through the tunnel junction formed between the source region and the channel portion, so that the entire channel portion, including the portion not involved in the tunnel junction, does not need to be thinned. Furthermore, the channel portion may be formed of one of the plate-shaped portions, or may be formed of a plurality of the plate-shaped portions.

[0028] When all four constituent surfaces that constitute the first opposing surfaces and the second opposing surfaces are made up of the electron confinement surfaces, the restrictions imposed by the law of conservation of momentum are further relaxed, and the tunneling probability can be further increased. In addition, when both pairs of the first opposing surfaces and the second opposing surfaces constituted by the electron confinement surfaces are formed by arranging the electron confinement surfaces at an opposing distance of at most 15 nm, the restriction due to the law of conservation of momentum is further alleviated, and the tunneling probability can be further increased.

[0029] The electron confinement surface is a surface that can impart a pseudo band structure of the direct transition semiconductor to the indirect transition semiconductor by restricting the electron motion, and differs for each type of indirect transition semiconductor. The electron confinement surface can be described by the crystal plane of each type of indirect transition semiconductor. Specifically, the electron confinement plane is determined for each type of indirect transition semiconductor from the band structure specific to the bulk material shown in Fig. 1(a), and for example, the {100} plane corresponds to the electron confinement plane for silicon, and the {111} plane corresponds to the electron confinement plane for germanium. In addition, in the case of a mixed crystal of silicon and germanium, if the germanium content is less than 85 atomic %, the {100} plane corresponds to the electron confinement plane, and if the germanium content is 85 atomic % or more, the {111} plane corresponds to the electron confinement plane.

[0030] The distance between the opposing surfaces (the electron confinement surfaces) for obtaining the folding effect is not particularly limited as long as it is 15 nm or less, but from the viewpoint of obtaining a larger tunnel current while reducing the size, it is preferably 10 nm or less, more preferably 8 nm or less, more preferably 6 nm or less, and particularly preferably 4 nm or less. Note that the lower limit is about 1 nm from the viewpoint of reducing the amount of current due to the surface roughness of the channel portion.

[0031] The method for forming the channel portion is not particularly limited and can be appropriately selected from among the methods for forming the channel portion in existing semiconductor equipment. Examples of the method include electron beam lithography processing and epitaxial growth in which the growth time is controlled. The channel portion may be formed of the indirect transition semiconductor, and the material used may have a single crystal structure, and may be an intrinsic semiconductor or one doped with a low concentration of the impurity.

[0032] <Gate section> The gate portion is a portion configured such that a gate electrode covers the whole or a part of the exposed portion of the channel portion via a gate insulating film. The material for forming the gate insulating film is not particularly limited and can be appropriately selected depending on the purpose. For example, HfO 2 , Al 2 O 3 , ZrO 2 etc. The method for forming the gate insulating film is not particularly limited and can be appropriately selected depending on the purpose. Examples of the method include ALD, sputtering, and CVD using the above-mentioned forming material. The material for forming the gate electrode is not particularly limited and can be appropriately selected depending on the purpose. Examples of the material include TiN, TaN, and NiSi. The method for forming the gate electrode is not particularly limited and may be appropriately selected depending on the purpose. Examples of the method include ALD, sputtering, and CVD using the above-mentioned formation material.

[0033] The specific configuration of the gate portion is not particularly limited and can be selected appropriately depending on the purpose. For example, it can be configured as an all-around structure that covers all of the four constituent surfaces that constitute the first opposing surface and the second opposing surface in the plate-shaped portion of the channel portion. However, it is not necessary to cover all of the constituent surfaces, and from the viewpoint of small, simple, and low-cost manufacture, it is preferable that the gate portion be arranged to cover the whole or part of at most three of the four constituent surfaces that constitute the first opposing surface and the second opposing surface.

[0034] [First embodiment] A semiconductor device according to a first embodiment of the present invention will now be described with reference to the drawings. Fig. 4 is an exploded perspective view of the semiconductor element according to the first embodiment. Fig. 5(a) is a cross-sectional view in a direction perpendicular to the direction of current flow (X direction in Fig. 4), and Fig. 5(b) is a cross-sectional view taken along line AA in a direction parallel to the direction of current flow in Fig. 5(a) (Y direction in Fig. 4).

[0035] As shown in FIG. 4, the semiconductor element 10 is composed of a source portion 14, a channel portion 13 arranged adjacent to the source portion 14 and having the boundary as the tunnel junction where the tunnel barrier is formed, a drain portion 15 arranged adjacent to the channel portion 13, and a gate portion G arranged so as to cover all or part of the exposed portion of the channel portion 13, and has the element structure of the tunnel field effect transistor. This semiconductor element 10 can be formed on any substrate in which a surface insulating layer 12 is formed on a semiconductor layer 11, such as an SOI (Silicon-on-insulator) substrate, as shown in Figures 5(a) and (b). However, the semiconductor layer 11 and the surface insulating layer 12 are optional structures that are not involved in the operation of the semiconductor element 10.

[0036] The channel portion 13 is an intrinsic semiconductor or a semiconductor having a low concentration of the impurity (for example, 1×10 13 cm -3 ~1×10 16 cm -3The plate-shaped portion is formed of silicon doped with a dopant (about 1000 .mu.m) and is connected at one end to a source portion 14 and at the other end to a drain portion 15. Of the two pairs of opposing surfaces, the first opposing surfaces and the second opposing surfaces, which are opposed in a direction perpendicular to the direction of current flow from the source section 14 to the drain section 15 and which constitute the plate-shaped portion of the channel section 13, one pair of opposing surfaces (opposing surfaces opposed in the X direction in FIG. 4) is formed of {100} planes in silicon and constitutes the electron confinement surface. The thickness D of the channel section 13 in the X direction in FIG. 4, which governs the opposing distance between these electron confinement surfaces, is 1 (see FIG. 5(a)) is set to be at most 15 nm, and the channel portion 13 is configured so as to obtain the folding effect.

[0037] The source section 14 and the drain section 15 are formed by doping silicon with the impurity. of High concentration (e.g., 1 × 10 19 cm -3 ~1×10 21 cm -3 The source and drain regions are formed by doping the source region to a thickness of about 1000 .mu.m (about 1000 .mu.m), and the tunnel junction is formed at the semiconductor junction between the channel portion 13 and the source portion 14.

[0038] The gate portion G is configured such that the gate electrode 17 covers all or a part of the exposed portion of the channel portion 13 via the gate insulating film 16, and specifically, is arranged so as to cover three of the four constituent surfaces that constitute the first opposing surface and the second opposing surface. Note that the element structure of a transistor in which the three surfaces of the plate-like channel portion 13 are covered with the gate portion G in this manner is known as a Fin-FET, and can be suitably manufactured using existing semiconductor equipment.

[0039] In this example, the thickness D of the channel portion 13 1The band-to-band tunneling phenomenon occurs when electrons pass through the tunnel junction formed by the semiconductor junction between the channel section 13 and the source section 14. Therefore, the distance between the electron confinement surfaces of the channel section 13 and the tunnel junction in the vicinity of the tunnel junction (the portion extending from the one end to the other end at least by about 15 nm) in the channel section 13 in contact with the source section 14 and in the direction from the one end to the drain section 15 (the Y direction in FIG. 4) is uniform. 1 ) is a short distance of at most 15 nm, and in the channel portion 13 on the drain portion 15 side from the neighboring portion, the opposing distance between the electron confinement surfaces (thickness D 1 ) may be configured to exceed 15 nm. In this example, the portion of the source portion 14 that forms the tunnel junction with the channel portion 13 has the same shape as the plate-shaped portion of the channel portion 13. That is, the source portion 14 is formed so as to taper toward the channel portion 13, and the end portion that is joined to the channel portion 13 is formed as a plate-shaped portion on the one end side, and one pair of the opposing surfaces (opposing surfaces that oppose in the X direction in FIG. 4) of the two pairs of opposing surfaces, the first opposing surfaces and the second opposing surfaces that oppose in a direction perpendicular to the direction in which the current flows from the source portion 14 to the drain portion 15, that constitute this plate-shaped portion, are formed of {100} planes in silicon, similar to the plate-shaped portion in the channel portion 13, and constitute the electron confinement surface. In addition, the thickness of the plate-shaped portion in the source portion 14 in the X direction in FIG. 4, which governs the opposing distance between these electron confinement surfaces, is at most 15 nm, and the portion in the vicinity of the tunnel junction formed as the plate-shaped portion in the source portion 14 (the portion extending at least about 10 nm from the one end toward the other end in the direction away from the drain portion 15, which is the opposite direction to the current flow) is configured so as to obtain the convolution effect. In this manner, when the channel portion 13 and the source portion 14 forming the tunnel junction are configured so as to obtain the convolution effect, the tunnel probability at the tunnel junction increases, and a larger tunnel current can be obtained.

[0040] In this example, the channel portion 13 is made of silicon, but when the channel portion 13 is made of germanium, the opposing surfaces (opposing surfaces facing each other in the X direction in FIG. 4) are each formed with a {111} plane of germanium to form the electron confinement surface. When the channel portion 13 is made of a mixed crystal of silicon and germanium, if the germanium content is less than 85 atomic %, the opposing surfaces (opposing surfaces facing each other in the X direction in FIG. 4) are each formed with a {100} plane of the mixed crystal of silicon and germanium to form the electron confinement surface, and when the germanium content is 85 atomic % or more, the opposing surfaces (opposing surfaces facing each other in the X direction in FIG. 4) are each formed with a {111} plane of the mixed crystal of silicon and germanium to form the electron confinement surface.

[0041] The reasons for this are as follows. First, the iso-energy surface near the bottom of the conduction band of bulk silicon is shown in Fig. 6(a). In the case of silicon, the position of the bottom of the conduction band is not a point of zero momentum, but a point with six-fold symmetry. <100> It exists on the axis of the direction. <100> It is most effective to obtain the folding effect by thinning the layer in the direction perpendicular to the X direction. In other words, it is most effective to form the opposing surfaces (opposing surfaces opposing each other in the X direction in FIG. 4) with {100} planes in silicon to form the electron confinement surfaces. Next, Fig. 6(b) shows the iso-energy surface near the bottom of the conduction band of bulk germanium. In the case of germanium, the position of the bottom of the conduction band is not a point of zero momentum, but a point with eight-fold symmetry. <111> It exists on the axis of the direction. <111> It is most effective to obtain the folding effect by thinning the layer in a direction perpendicular to the X direction. In other words, it is most effective to form the opposing surfaces (opposing surfaces opposing each other in the X direction in FIG. 4) with {111} faces of germanium to form the electron confinement surfaces. Next, in the case of a silicon-germanium alloy with a germanium content of less than 85%, when no external stress is applied, the component contributing to silicon is strong, so the position of the conduction band minimum is six-fold symmetric, just like silicon. <100> Therefore, similarly to silicon, it is most effective to form the opposing surfaces (opposing surfaces facing each other in the X direction in FIG. 4) with {100} planes in a mixed crystal of silicon and germanium to form the electron confinement surface. Next, in the case of a silicon-germanium alloy with a germanium content of 85% or more, the component contributing to germanium is strong when no external stress is applied, so the position of the conduction band minimum is eight-fold symmetric, just like germanium. <111> Therefore, similarly to germanium, it is most effective to form the opposing surfaces (opposing surfaces facing each other in the X direction in FIG. 4) with {111} planes in a silicon-germanium mixed crystal to form the electron confinement surface. In this way, the electron confinement surface can be determined by determining a crystal direction that regulates the electron motion from the energy state specific to the material of the indirect transition semiconductor in a bulk state.

[0042] As described above, in the semiconductor device 10, the convolution effect at the tunnel junction and its vicinity where the band-to-band tunneling phenomenon occurs improves the tunneling probability of electrons passing through the tunnel junction to the same level as in the direct transition semiconductor, thereby increasing the tunnel current. Furthermore, the semiconductor device 10 can be manufactured compactly, simply, and at low cost by utilizing existing manufacturing facilities for the indirect transition semiconductor.

[0043] As a modified example of the first embodiment, when the source electrode and the drain electrode are arranged and the source electrode and the channel portion are joined by the Schottky junction to form the tunnel junction, the source portion 14 and the drain portion 15 in the semiconductor element 10 may be constituted by the source electrode and the drain electrode, and the source electrode and the channel portion 13 may be joined by the Schottky junction to form the tunnel junction.

[0044] [Second embodiment] A semiconductor device according to a second embodiment of the present invention will now be described with reference to the drawings. Fig. 7 is an exploded perspective view of a semiconductor device according to a second embodiment. Fig. 8(a) is a cross-sectional view in a direction perpendicular to the direction of current flow (X direction in Fig. 7), and Fig. 8(b) is a cross-sectional view taken along line AA in a direction parallel to the direction of current flow in Fig. 8(a) (Y direction in Fig. 7).

[0045] As shown in FIG. 7, the semiconductor element 20 is composed of a source portion 24, channel portions 23a to 23c arranged adjacent to the source portion 24 and having the boundary as the tunnel junction where the tunnel barrier is formed, a drain portion 25 arranged adjacent to the channel portions 23a to 23c, and a gate portion G arranged so as to cover all or part of the exposed portions of the channel portions 23a to 23c, and has the element structure of the tunnel field effect transistor. This semiconductor element 20 can be formed on any substrate in which a surface insulating layer 22 is formed on a semiconductor layer 21, such as an SOI substrate, as shown in Figures 8(a) and (b). However, the semiconductor layer 21 and the surface insulating layer 22 are optional structures that are not involved in the operation of the semiconductor element 20.

[0046] The semiconductor device 20 according to the second embodiment is structurally different from the semiconductor device 10 according to the first embodiment in that the channel portion 13 is composed of channel portions 23a to 23c. The difference will be described below.

[0047] Each of the channel portions 23a to 23c is made of the indirect transition semiconductor, and is constituted by the plate-shaped portion itself, one end of which is connected to the source portion 24 and the other end of which is connected to the drain portion 25. Of the two pairs of opposing surfaces, the first opposing surfaces and the second opposing surfaces, which are opposed in a direction perpendicular to the direction of the current flow from the source section 24 to the drain section 25 and which constitute the plate-shaped portion of the channel section 23a, at least one pair of the opposing surfaces (opposing surfaces opposed in the Z direction in FIG. 7) constitutes the electron confinement surface. The thickness D of the channel section 23a in the Z direction in FIG. 7, which governs the opposing distance between these electron confinement surfaces, 2 (see FIG. 8(a)) is set to be at most 15 nm, and the channel portion 23a is configured so as to obtain the folding effect. Moreover, the channel portions 23b and 23c each have the same structure as the channel portion 23a, and are disposed so as to be juxtaposed to the channel portion 23a. That is, in the semiconductor element 20, a plurality of the plate-shaped portions that can obtain the convolution effect are arranged, and a larger tunnel current is obtained than with a single plate-shaped portion. The thinning of the channel portions 23a to 23c for obtaining the folding effect provides a space for forming a plurality of the plate-shaped portions in the same formation region as when the channel portions are formed in a bulk state. From this viewpoint, it is preferable that the channel portions 23b and 23c are the plate-shaped portion itself (or the channel portion having the plate-shaped portion) that is arranged alongside the channel portion 23a in the opposing direction (Z direction in FIG. 7) of the opposing surfaces formed by the electron confinement surfaces, with the opposing distance being at most 15 nm, as shown in the figure.

[0048] The exposed portions of the channel portions 23a to 23c configured in this manner, except for the connection surfaces with the source portion 24 and the drain portion 25, are entirely covered with gate insulating films 26a to 26c, and are also covered with a gate electrode 27 via the gate insulating films 26a to 26c. In this example, both of the channel portion 23b and 23c arranged in parallel with the channel portion 23a are configured to obtain the convolution effect, but only one of them may be configured to obtain the convolution effect. In addition, the other points described with respect to the semiconductor device 10 according to the first embodiment can be applied.

[0049] Next, an example of a method for manufacturing the semiconductor device of the present invention will be described with reference to the drawings. 9 to 15 are diagrams (1) to (7) showing the manufacturing process of the semiconductor device 10 according to the first embodiment, and (b) of each diagram is a cross-sectional view taken along line AA in (a).

[0050] First, a SiO 2 film having a thickness of 145 nm is formed on the handle-use Si semiconductor layer 11. 2 An SOI substrate is prepared in which a surface insulating layer (BOX layer) 12 and an SOI layer 13' made of Si and having a thickness of 50 nm are formed in this order (see FIGS. 9(a) and 9(b)). The SOI layer 13' is doped with a p-type impurity of 1×10 15 cm -3 It's doped to some extent. Next, an etching mask 101 is formed to a thickness of 65 nm at a predetermined position on the SOI layer 13' by electron beam lithography, and then reactive ion etching (RIE) is performed using the etching mask 101 as a mask to process the shape of the SOI layer 13' into the shapes of the channel section 13, the source section 14, and the drain section 15 (see FIGS. 10(a) and 10(b)). The plasma used in the reactive ion etching (RIE) includes hydrogen bromide (HBr) plasma, hydrogen bromide (HBr) and chlorine (Cl 2 ) and hydrogen bromide (HBr) and argon (Ar) mixed plasma, etc. are used. Next, after removing the etching mask 101, a SiO 2 film having a thickness of 4 nm is formed on the surface of the SOI layer 13′ for the subsequent ion implantation. 2 A protective oxide film 102 is formed (see FIGS. 11(a) and 11(b)).

[0051] Next, a resist layer 103 having a thickness of 100 nm is formed on the protective oxide film 102 by electron beam lithography. Using this resist layer 103 as a mask, 15 cm -2 At a dose of BF 2Then, ion implantation is performed using a fluorine atom to form a drain portion 15 as the drain region in the SOI layer 13' (see FIGS. 12(a) and 12(b)). Next, the resist layer 103 is removed by oxygen ashing, and the surface is cleaned with SPM (Sulfuric Acid Peroxide Mixture). 2 SO 4 and H 2 O 2 A mixture of these in a ratio of 3:1 is used. Next, a resist layer 104 having a thickness of 100 nm is formed on the protective oxide film 102 cleaned by SPM, and the resist layer 104 is used as a mask to perform ion beam irradiation at an acceleration energy of 5 keV and 2×10 15 cm -2 As is then implanted at a dose of 1000 .mu.m to form a source portion 14 as the source region in the SOI layer 13' (see FIGS. 13(a) and 13(b)). The remaining portion of the SOI layer 13 ′ after the source section 14 and the drain section 15 are formed constitutes the channel section 13 . Next, the resist layer 104 is removed by oxygen ashing, and the surface is subjected to SPM cleaning. 2 SO 4 and H 2 O 2 A mixture of these in a ratio of 3:1 is used. Next, N 2 An activation annealing process is performed at a temperature of 1,000° C. for one second under atmospheric pressure in a gas atmosphere to activate the impurity substances in the source section 14 and the drain section 15 . Next, the protective oxide film 102 is removed using dilute hydrofluoric acid (DHF) with a concentration of 1%.

[0052] Next, SC2 cleaning solution (HCl, H 2 O 2 and H 2 The plate is then immersed in a 1:1:6 mixed solution of 1, 2, and 3 at 70°C for 5 minutes and washed. Next, HfO 2A gate insulating film 16′ having a thickness of 2.4 nm is formed around the channel portion 13 by depositing TaN, and a gate electrode formation layer 17′ having a thickness of 30 nm is formed on the gate insulating film formation film 16′ by a sputtering method (see FIGS. 14(a) and 14(b)). Next, Cl using a mask 2 The gate insulating film forming film 16' and the gate electrode forming layer 17' are shaped by reactive ion etching using plasma to form the gate insulating film 16 and the gate electrode 17 (see FIGS. 15(a) and 15(b)). In this manner, the semiconductor device 10 is manufactured. This manufacturing method shows only one example of a method for manufacturing the semiconductor element 10, and the user can appropriately select suitable manufacturing equipment and manufacture the semiconductor element 10 using a known method.

[0053] An important point in the manufacture of the semiconductor device 10 is to ensure the electron confinement surface in the channel portion 13 . This can be easily achieved by selecting the crystal plane orientation (the direction of the crystal axis perpendicular to the surface of the substrate) of the SOI substrate, which is the starting substrate, and the extension direction of the channel portion 13 . For example, in silicon, as shown in FIG. <100> A structure for obtaining the folding effect in the

[0110] direction can be obtained by using the SOI substrate having a (100) plane as the main surface, and aligning the extension direction of the channel portion 13 at 45 degrees (or equivalent) to a cutout portion (orientation flat or notch, shown by a horizontal line at the bottom of the circle in the figure) in the

[0110] direction in the SOI substrate. For example, in germanium, as shown in FIG. <111> A structure for obtaining the folding effect in the [1-10] direction can be obtained by using a Germanium-on-insulator (GOI) substrate with a (110) plane as the main surface, and aligning the extension direction of the channel portion 13 at 55 degrees (or equivalent) to a cutout portion (orientation flat or notch, shown by a horizontal line at the bottom of the circle in the figure) in the [1-10] direction in the GOI substrate. FIG. 16(a) is a diagram showing an outline of a method for forming a channel section using an SOI substrate having a (100) plane as its main surface, and FIG. 16(b) is a diagram showing an outline of a method for forming a channel section using a GOI substrate having a (110) plane as its main surface.

[0054] Next, an example of a method for manufacturing a semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment will be described with reference to the drawings. 17 to 19 are diagrams (1) to (3) showing the manufacturing process of the semiconductor element of the present invention related to the semiconductor element 20 according to the second embodiment, and (b) of each diagram is a cross-sectional view taken along line AA in (a).

[0055] First, prepare a handle Si substrate 31. By selecting the same crystal plane orientation as the SOI substrate for this substrate 31, as explained with reference to Fig. 16(a) for the SOI substrate, the electron confinement surface can be easily secured in the subsequent process. On this substrate 31, a silicon-germanium sacrificial layer 201a', a Si semiconductor layer 33a, a silicon-germanium sacrificial layer 201b', a Si semiconductor layer 33b, a silicon-germanium sacrificial layer 201c', and a Si semiconductor layer 33c are formed in this order by epitaxial growth (see FIGS. 17(a) and 17(b)). The thickness of each of the Si semiconductor layers 33a to 33c is 1 / 2 times the thickness D of the channel portion 23a in the semiconductor element 20 according to the second embodiment. 2 (see FIG. 8(a)), the thickness is set to 15 nm at most, and this thickness can be controlled by adjusting the epitaxial growth time. Next, the shapes of the silicon-germanium sacrificial layers 201a' to 201c' and the Si semiconductor layers 33a to 33c are processed by lithography using a mask 202 (see FIGS. 18(a) and 18(b)). Next, hydrogen peroxide (H 2 O 2), the center portion of the silicon-germanium sacrificial layer 201a' is selectively etched so as to divide the silicon-germanium sacrificial layer 201a into two silicon-germanium sacrificial layers 201a. At the same time, the silicon-germanium sacrificial layers 201b' and 201c' are similarly etched. At this time, hydrogen peroxide (H 2 O 2 ) is sufficiently slower than the etching rate for the silicon-germanium sacrificial layers 201a'-201c'. As a result, only the Si semiconductor layers 33a-33c are bridged without being separated, making it possible to form the channel portion (see FIGS. 19(a) and 19(b)).

[0056] Other than this, the semiconductor device can be manufactured based on the elements described for the semiconductor element 10 of the first embodiment and / or known semiconductor element manufacturing methods, and has a configuration similar to that of the semiconductor element 20 of the second embodiment.

[0057] (Semiconductor Integrated Circuit) A semiconductor integrated circuit according to the present invention is characterized by comprising the semiconductor element according to the present invention. The method for integrating the semiconductor elements is not particularly limited and can be appropriately selected depending on the purpose, and any known method can be appropriately adopted. EXAMPLES

[0058] (simulation) A simulation was carried out as follows regarding the change in the energy band structure and the change in the band-to-band tunneling current caused by forming silicon, which is an indirect transition semiconductor, into a two-dimensional plate shape.

[0059] <Changes in energy band structure> The thickness direction is <100> Simulation tests were carried out on the change in the energy band structure for two types of silicon: bulk silicon with an infinite thickness, and a plate-like silicon with a thickness of approximately 1.1 nm. Specifically, a simulation test was carried out as follows. First, the energy band structure of silicon was determined by first-principles calculations based on density functional theory. The calculations were performed using the Vienna Ab Initio Simulation Package (VASP) version 5.4 software. The exchange-correlation functional describing the electron interactions uses the generalized gradient approximation (GGA) and the Perdue-Burke-Ernzerhof (PBE) formalism. The wave function of the valence electrons is expressed by a superposition of plane waves, and wave numbers corresponding to a maximum kinetic energy of 500 eV are considered. The interaction of the inner shell electrons with the valence electrons is expressed using pseudopotentials of the PAW (Projector Augmented Wave) method. Here, a silicon plate with a thickness of approximately 1.1 nm was prepared assuming a system in which a structure consisting of eight layers of two atoms per layer was used as the base unit, with the system being repeated infinitely periodically in the in-plane direction. At this time, it was assumed that both the top and bottom surfaces in the thickness direction of the silicon were terminated with hydrogen, and furthermore, a vacuum layer with a thickness of 2 nm or more existed on the outside. On the other hand, bulk silicon was prepared by assuming a system in which a base unit is a structure in which four layers, each consisting of two atoms, are stacked together, and this base unit is repeated infinitely periodically in the in-plane and perpendicular directions.

[0060] The energy band structure of bulk silicon obtained by the simulation test is shown in Figure 20(a), and the energy band structure of a silicon plate with a thickness of about 1.1 nm is shown in Figure 20(b). As shown in Fig. 20(a), in bulk silicon, the top of the valence band is located at the Γ point, which means zero momentum, whereas the bottom of the conduction band is located at a point different from the Γ point. In other words, this shows the distinctive characteristics of the indirect transition semiconductor. On the other hand, as shown in Fig. 20(b), in the case of a silicon plate having a thickness of about 1.1 nm, both the top of the valence band and the bottom of the conduction band are located at the Γ point. In other words, silicon, which is originally an indirect transition semiconductor, is turned into a pseudo direct transition semiconductor by being formed into a thin plate shape.

[0061] Next, the correlation between the energy band structure of silicon and the silicon film thickness, which was obtained using the same method as the first-principles calculation, is shown in Figure 21. However, here, the kinetic energy of the wave number of the plane wave expressing the wave function is assumed to be a maximum of 550 eV, and the thickness of the vacuum layer outside the silicon thin film is assumed to be 1.1 nm. The vertical axis in Figure 21 shows the band gap (energy difference between the top of the valence band and the bottom of the conduction band, Eg thin ) and the band gap of bulk silicon (energy difference between the top of the valence band and the bottom of the conduction band, Eg bulk ) as a ratio to the band gap of bulk silicon (={Eg thin -Eg bulk} / Eg bulk The horizontal axis indicates the thickness of the silicon plate. Since the change in the band gap of silicon occurs due to hybridization of the electronic orbitals of the indirect transition component and the direct transition component, the change in the band gap due to thinning results in an enhancement of the direct transition component. As shown in FIG. 21, when the thickness of the silicon plate is 15 nm or less, a change begins to occur in the band structure of silicon, and it is confirmed that the component related to the direct transition is enhanced.

[0062] <Band-to-band tunneling current> Next, a simulation test was carried out on the change in the band-to-band tunneling current. The subjects of this simulation test were assumed to be two types of thin-film TFET and bulk TFET.

[0063] First, the thin-film TFET has a thickness direction as shown in FIG. <100> The component is a silicon plate 40 having a uniform thickness of 1.1 nm and a {100} surface on both the front and back sides, with a source region 44 formed at one end in the length direction and a drain region 45 formed at the other end, between which a channel region 43 is formed. In this case, it is assumed that both the top and bottom surfaces in the thickness direction are terminated with hydrogen, and furthermore, that an infinitely thick vacuum layer exists outside of them. Here, the source region 44 is made of P-type silicon and has an impurity concentration of approximately 5×10 19 cm -3 The energy of the Fermi level was set to coincide with the top of the valence band. The drain region 45 is made of N-type silicon and has an impurity concentration of about 5×10 19 cm -3 was set so that the energies of the Fermi level and the bottom of the conduction band were equal. The channel region 43 was made of silicon with no impurity material added. The tunnel junction 42 was set as a semiconductor junction formed by a semiconductor-semiconductor junction between a source region 44 and a channel region 43 . Moreover, the source region 44 is connected to a metal electrode (source electrode) not shown, and the junction between the metal electrode and the source region 44 is set as an ideal ohmic junction. Similarly, the drain region 45 is connected to a metal electrode (drain electrode) not shown, and the junction between the metal electrode and the drain region 45 is set as an ideal ohmic junction. FIG. 22 is an explanatory diagram for explaining the configuration of the thin-film TFET that was the subject of the simulation test.

[0064] The thin-film TFET is set to operate by inputting an electric field applied to the channel region 43 by an arbitrary gate insulating film and gate electrode, instead of inputting a gate voltage. The electric field was set to be applied to a portion of the channel region 43 from the position of the tunnel junction 42 to a position 10 nm away in the extension direction of the channel region 43 toward the drain region 45. 4 Based on this setting, the electric field (E) applied to the tunnel junction 42 is set by the following formula: electric field (E) = voltage drop (ΔV) / distance (= 10 nm). In a portion of the channel region 43 that is more than 10 nm away from the position of the tunnel junction 42 in the extension direction, no electric field is applied, and the energies of the Fermi level and the bottom of the conduction band are set to coincide, so that the channel region 43 is connected to the drain region 45 without a barrier.

[0065] Next, the bulk TFET was set in the same manner as the thin-film TFET, except that the thickness of the silicon plate 40 in the thin-film TFET was changed from 1.1 nm to infinity.

[0066] In the simulation test, the band-to-band tunneling currents of these two TFETs are compared using the input value of the electric field as a variable, thereby confirming the band-to-band tunneling currents of these two TFETs. In this simulation test, the band-to-band tunneling current was calculated using the same calculation software used to calculate the band-to-band tunneling current for bulk silicon and compound semiconductors containing intermediate impurity levels in Reference 2 below. Here, the current intensity was found by calculating the transmission coefficient of the non-equilibrium Green's function. The basis for expressing the electron wave function and density was the sp3s* orbital of silicon atoms based on the tight-binding approximation. The electron orbital energy and interatomic jump energy used in the tight-binding approximation were determined to reproduce the band structure of bulk silicon (see Figure 20(a)) and the known band gap energy of silicon (1.1 eV) obtained experimentally. Using this tight-binding approximation, the energy band structure of a 1.1 nm-thick thin film was determined, and the tunneling current was calculated using this. The interaction of electrons tunneling through the pn junction interface was described by the Green's functions of the electrodes, the electrode-semiconductor gap, and the semiconductor itself. Reference 2: Cho, Xianghun, and Takashi Nakayama, “Enhancement of tunneling current due to resonant impurity levels in p / n junctions: Comparison between direct and indirect band gap systems,” Proceedings of the 26th Electron Device Interface Technology Research Meeting, pp.109-113, January 2021.

[0067] The results of a simulation test of the band-to-band tunneling current are shown in Fig. 23. In Fig. 23, -15 The start of tunnel current flow is defined as the conduction of a current of A / μm, and the electric field at which this tunnel current begins to flow is defined as the threshold electric field, 0 MV / cm, and the electric field on the horizontal axis is shown as the difference from this threshold electric field. As shown in FIG. 23, it is confirmed that the band-to-band tunneling current is significantly increased in the thin-film TFET compared to the bulk TFET. As described above, in the semiconductor element of the present invention, the channel portion formed of the indirect transition semiconductor can be pseudo-converted into a direct transition semiconductor, thereby increasing the tunnel current.

[0068] In order to confirm the effectiveness of the simulation results and the effects of the present invention, the semiconductor device was manufactured and its performance was evaluated.

[0069] Example 1 The semiconductor device according to Example 1 was manufactured in accordance with the configuration of the semiconductor device 10 according to the first embodiment shown in FIGS. The semiconductor element according to Example 1 relates to a prototype for confirming effectiveness, and relates to an element having a back-gate structure in which the gate insulating film 16 and the gate electrode 17 are not formed in the semiconductor element 10 according to the first embodiment, and the semiconductor layer 11 (see FIGS. 5(a) and (b)) is used as the gate electrode. The back-gate structure semiconductor element according to Example 1 is expected to have a smaller on-current than the semiconductor element 10 according to the first embodiment having the gate insulating film 16 and the gate electrode 17, but has the same switching characteristics as the semiconductor element 10 according to the first embodiment in terms of the conditions for obtaining a large tunnel current and tunnel current density. The results of confirming the effectiveness of the semiconductor element according to Example 1 strongly support the effectiveness of the semiconductor elements of the present invention, including the semiconductor element 10 according to the first embodiment.

[0070] The semiconductor device according to Example 1 was manufactured as follows by the same manufacturing method as that described with reference to Figures 9 to 13(b). Note that the reference numerals in the description are the same as those in Figures 9 to 13(b). First, a SiO 2 film having a thickness of 145 nm is formed on the handle-use Si semiconductor layer 11. 2 An SOI substrate was prepared in which a surface insulating layer (BOX layer) 12 and an SOI layer 13' made of Si and having a thickness of 50 nm were formed in this order (see FIGS. 9(a) and 9(b)). The SOI layer 13' was doped with a p-type impurity of 1×10 15 cm -3 It's doped to some extent. Here, the SOI substrate used has a (100) plane as its main surface, and in the subsequent manufacturing steps, the extension direction of the channel portion 13 is aligned at 45 degrees to the notch portion in the

[0110] direction of the SOI substrate, so that the formed channel portion 13 has the electron confinement surface (see FIG. 16(a)).

[0071] Next, an etching mask 101 was formed to a thickness of 65 nm at a predetermined position on the SOI layer 13' by electron beam lithography, and then reactive ion etching (RIE) was performed using the etching mask 101 as a mask to process the shape of the SOI layer 13' into the shapes of the channel portion 13, the source portion 14, and the drain portion 15 (see FIGS. 10(a) and (b)). A mixed plasma of hydrogen bromide (HBr) and argon (Ar) was used as the plasma in the reactive ion etching (RIE). Here, the shape of the SOI layer 13' is processed to have a fin width (thickness D in FIG. 5(a)) of the channel section 13 to be formed in a later process. 1 The reactive ion etching (RIE) settings were adjusted so that the thickness of the SiO 2 Considering the thickness of the protective oxide film 102 (4 nm), the settings of the reactive ion etching (RIE) were adjusted so that the thickness of the SOI layer 13' would be 18 nm. Next, after removing the etching mask 101, a SiO 2 film having a thickness of 4 nm is formed on the surface of the SOI layer 13′ for the subsequent ion implantation. 2 A protective oxide film 102 was formed (see FIGS. 11(a) and 11(b)).

[0072] Next, a resist layer 103 having a thickness of 100 nm is formed on the protective oxide film 102 by electron beam lithography. Using this resist layer 103 as a mask, 15 cm -2 As was then implanted at a dose of 1000 .mu.m to form a source portion 14 as the source region in the SOI layer 13'. Next, the resist layer 103 was removed by oxygen ashing, and the surface was cleaned with SPM (Sulfuric Acid Peroxide Mixture). 2 SO 4 and H 2 O 2 A mixture of these in a ratio of 3:1 was used. Next, a resist layer 104 having a thickness of 100 nm is formed on the protective oxide film 102 cleaned by SPM, and the resist layer 104 is used as a mask to perform ion beam irradiation at an acceleration energy of 5 keV and 2×10 15 cm -2 At a dose of BF 2 Ion implantation was performed using fluorine to form a drain section 15 as the drain region in the SOI layer 13' (see FIGS. 12 and 13 for an example of the formation of the source section 14 and the drain section 15). The remaining portion of the SOI layer 13 ′ after the source section 14 and the drain section 15 are formed constitutes the channel section 13 . Next, the resist layer 104 was removed by oxygen ashing, and the surface was subjected to SPM cleaning. 2 SO 4 and H 2 O 2 A mixture of these in a ratio of 3:1 was used. Next, N 2 An activation annealing process was performed at a temperature of 1,000° C. for one second under atmospheric pressure in a gas atmosphere to activate the impurity substances in the source section 14 and the drain section 15 . Next, the protective oxide film 102 was removed using dilute hydrofluoric acid (DHF) with a concentration of 1%.

[0073] In this manner, the semiconductor device according to Example 1 was manufactured. In the semiconductor device according to the first embodiment, the fin width of the channel portion 13 (thickness D in FIG. 5(a)) 1 ) is 14 nm, and the opposing surfaces of the channel portion 13 that regulate the Fin width are made to be the electron confinement surfaces.

[0074] Example 2 The semiconductor device of Example 2 was manufactured in the same manner as Example 1, except that the settings of the reactive ion etching (RIE) were changed to shape the SOI layer 13' so that the fin width was 12 nm.

[0075] Example 3 The semiconductor device of Example 3 was manufactured in the same manner as Example 1, except that the settings of the reactive ion etching (RIE) were changed to shape the SOI layer 13' so that the fin width was 10 nm.

[0076] Example 4 The semiconductor device of Example 4 was manufactured in the same manner as Example 1, except that the settings of the reactive ion etching (RIE) were changed to shape the SOI layer 13' so that the fin width was 8 nm.

[0077] Example 5 The semiconductor device of Example 5 was manufactured in the same manner as Example 1, except that the settings of the reactive ion etching (RIE) were changed to shape the SOI layer 13' so that the fin width was 4 nm.

[0078] Comparative Example 1 A semiconductor device according to Comparative Example 1 was manufactured in the same manner as in Example 1, except that the settings of the reactive ion etching (RIE) were changed to shape the SOI layer 13' so that the fin width was 16 nm.

[0079] Comparative Example 2 A semiconductor device according to Comparative Example 2 was manufactured in the same manner as in Example 1, except that the settings of the reactive ion etching (RIE) were changed to shape the SOI layer 13' so that the fin width was 28 nm.

[0080] Comparative Example 3 A semiconductor device according to Comparative Example 3 was manufactured in the same manner as in Example 1, except that the settings of the reactive ion etching (RIE) were changed to shape the SOI layer 13' so that the fin width was 38 nm.

[0081] <Performance evaluation> In evaluating the performance of each of the semiconductor elements of Examples 1 to 5 and Comparative Examples 1 to 3, each of the semiconductor elements was photographed with an electron microscope to confirm in advance that each setting, including the fin width, had been correctly realized. As an example, a scanning electron microscope image of the semiconductor device according to Example 4 taken from above is shown in FIG.

[0082] (Switching characteristics) Next, the switching characteristics of each of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3 were measured. The switching characteristics were measured as follows. That is, the measurement needles of a manual prober (Micronics Japan, 708fT) connected to a semiconductor device parameter analyzer (Agilent Technologies, B1500) were terminal-connected to the source section 14, drain section 15, and Si semiconductor layer 11 as the gate electrode via a metal plate (an alloy of aluminum (approximately 98% by mass) mixed with small amounts of silicon and copper), and the drain current (tunnel current) was measured by sweeping the gate voltage at a predetermined drain voltage, thereby measuring the switching characteristics. The measurements were performed at room temperature.

[0083] As a result of measuring the switching characteristics of each of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3, it was confirmed that the drain current (tunnel current) switches between the on state and the off state according to the gate voltage. In other words, each of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3 operates as the tunnel field effect transistor. As an example, the switching characteristics of the semiconductor element according to Example 4 are shown in Fig. 25. In Fig. 25, the plots shown with black circles indicate the drain current in a logarithmic scale on the right axis, and the plots shown with white diamonds indicate the drain current in a linear scale on the left axis. -12 The gate voltage at A is V off The voltage shifts to 0V and is displayed as: As shown in FIG. 25, in the semiconductor device according to the fourth embodiment, the gate voltage V offWhen the gate voltage value is increased in the negative direction from the ON state, the device is turned on and a drain current flows. At this time, as can be seen from the transition of the drain current on the logarithmic scale of the right axis, the semiconductor device according to Example 4 exhibits steep switching characteristics in the low voltage region, which is one of the characteristics of the tunnel field effect transistor. These characteristics are common to the semiconductor devices of Examples 2 to 5 and Comparative Examples 1 to 3.

[0084] (Tunnel current and tunnel current density) 26 and 27 show the drain current and drain current density of each of the semiconductor devices of Examples 1 to 5 and Comparative Examples 1 to 3 when the gate voltage in the previous measurement of switching characteristics was −11.5 V. Note that Fig. 26 is a diagram showing the relationship between the tunnel current and the fin width, and Fig. 27 is a diagram showing the relationship between the tunnel current density and the fin width.

[0085] As shown in FIG. 26, when the fin width is 16 nm, the drain current reaches a minimum, and when the fin width is reduced to approximately 15 nm or less, the drain current shows a tendency to increase. This phenomenon indicates that when the fin width becomes 15 nm, the tunnel current increases due to the confinement effect caused by the indirect transition semiconductor being converted into a pseudo direct transition semiconductor, and clearly supports the effectiveness of the simulation results and the effects brought about by the present invention. Moreover, the effect of increasing the drain current is extremely large, as can be seen from the tunnel current density shown in FIG. In each of the semiconductor devices of Examples 1 to 5, the tunnel current is increased by the confinement effect based on the pseudo direct transition semiconductor of the indirect transition semiconductor, and it is clear that a large tunnel current can be obtained in comparison with the tunnel current at the same fin width estimated from the decreasing tendency of the tunnel current with the decrease of the fin width shown in each of the semiconductor devices of Comparative Examples 1 to 3. Therefore, it can be evaluated that the semiconductor device according to the present invention can obtain a large on-current. In addition, in each of the semiconductor elements of Examples 1 to 5, as the fin width decreases, the tunnel current tends to increase conversely, so the semiconductor element of the present invention can simultaneously satisfy the demand for miniaturization of elements, which is necessary for high integration. Furthermore, since each of the semiconductor elements of Examples 1 to 5 can be manufactured using existing manufacturing equipment without any processing difficulties, the semiconductor element of the present invention has the advantage of being easily and inexpensively manufactured using existing manufacturing equipment. [Explanation of symbols]

[0086] 1,1' indirect transition semiconductor 2,42 Tunnel junction 10,20 Semiconductor elements 11,21 Semiconductor layer 12,22 Surface insulation layer 13, 23a, 23b, 23c Channel section 13' SOI layer 14,24 Source section 15,25 Drain section 16, 26a, 26b, 26c Gate insulating film 16' Gate insulating film forming film 17,27 Gate electrode 17' Gate electrode formation layer 31 Substrate 33a,33b,33c Si semiconductor layer 40 Silicon Plate 43 Channel Area 44 Source Region 45 Drain Region 102 Protective oxide film 103,104 Resist layer 201a, 201a', 201b, 201b', 201c, 201c' Silicon-germanium sacrificial layer

Claims

1. In a semiconductor device having a tunnel field effect transistor structure, a channel portion formed of an indirect transition semiconductor having a plate-shaped portion having one end connected to the source portion and the other end connected to the drain portion; A semiconductor element characterized in that at least one pair of opposing surfaces, consisting of first opposing surfaces and second opposing surfaces that face each other in a direction perpendicular to the direction of current flow from the source portion to the drain portion and that constitute the plate-shaped portion, are formed by arranging electron confinement surfaces at an opposing distance of at most 15 nm, which enable the band structure of a direct transition semiconductor to be imparted to the indirect transition semiconductor in a pseudo manner by regulating electron motion.

2. 2. The semiconductor device according to claim 1, wherein all four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces are constituted by electron trapping surfaces.

3. 3. The semiconductor element according to claim 1, wherein a gate portion constituting an element structure of the tunnel field effect transistor is arranged so as to cover the whole or part of at most three of four constituent surfaces constituting the first opposing surfaces and the second opposing surfaces.

4. 4. The semiconductor device according to claim 1, wherein the indirect transition semiconductor is silicon, and the electron confinement plane is a {100} plane.

5. 4. The semiconductor device according to claim 1, wherein the indirect transition semiconductor is germanium, and the electron confinement plane is a {111} plane.

6. 4. The semiconductor device according to claim 1, wherein the indirect transition semiconductor is a mixed crystal of silicon and germanium, and when the germanium content is less than 85 atomic %, the electron confinement surface is a {100} surface, and when the germanium content is 85 atomic % or more, the electron confinement surface is a {111} surface.

7. 7. The semiconductor device according to claim 1, wherein a tunnel junction formed in the tunnel field effect transistor is composed of a semiconductor junction.

8. 7. The semiconductor device according to claim 1, wherein a tunnel junction formed in the tunnel field effect transistor is a Schottky junction.

9. A semiconductor integrated circuit comprising the semiconductor element according to any one of claims 1 to 8.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, comprising the steps of: A method for manufacturing a semiconductor element, comprising: forming a channel portion having a plate-shaped portion using an indirect transition semiconductor, one end of which is connected to a source portion and the other end of which is connected to a drain portion; and forming at least one pair of opposing surfaces, of two pairs of opposing surfaces, i.e., first opposing surfaces and second opposing surfaces which face each other in a direction perpendicular to the direction of current flow from the source portion to the drain portion, constituting the plate-shaped portion, by arranging the opposing surfaces at an opposing distance of at most 15 nm to form electron confinement surfaces which enable the indirect transition semiconductor to be given a band structure of a direct transition semiconductor in a pseudo manner by regulating electron motion.

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