Thin-film transistor

Abstract

To suppress characteristic variation of a transistor.SOLUTION: A transistor comprises a first gate electrode, a second gate electrode overlapping the first gate electrode, a semiconductor layer arranged between the first gate electrode and the second gate electrode, a first insulation layer arranged between the first gate electrode and the semiconductor layer, a second insulation layer arranged between the semiconductor layer and the second gate electrode, and a conductive layer arranged at a distance from the first gate electrode and the second gate electrode and between the first insulation layer and the semiconductor layer. The semiconductor layer has a channel region overlapping the second gate electrode, and at least one low resistance region adjacent to the channel region and in contact with the conductive layer. The low resistance region has an offset region arranged between a region overlapping the second gate electrode and a region overlapping the conductive layer.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] An embodiment of the present invention relates to a pixel structure of a liquid crystal display device. [Background technology]

[0002] A liquid crystal display device has been disclosed as a horizontal electric field type active matrix liquid crystal display device in which video signal lines are covered with a transparent insulator with a dielectric constant of 3.3 or less, and a common electrode for shielding the video signal wiring is formed on top of these elongated insulator bumps using a transparent conductor (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-341465 A Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional liquid crystal display devices, a shield common electrode is provided to shield the electric field of the signal lines. However, a structure provided with a shield electrode has problems in that the layer structure becomes complicated and the aperture ratio of the pixels is reduced. On the other hand, when an attempt is made to simplify the layer structure, a problem arises in that the electric field of the signal lines acts on the liquid crystal layer, reducing long-term reliability. One object of one embodiment of the present invention is to solve such problems. [Means for solving the problem]

[0005] A liquid crystal display device according to one embodiment of the present invention includes a transistor including a first gate electrode on a first substrate, a second gate electrode having an area overlapping with the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, a pixel electrode between the first insulating layer and the second insulating layer, and a common electrode on the second insulating layer having an area overlapping with the pixel electrode. The transistor further includes a first oxide conductive layer and a second oxide conductive layer disposed between the first insulating layer and the oxide semiconductor layer and sandwiching the first gate electrode and the second gate electrode, the pixel electrode is provided continuously from the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected to each other by a first contact hole penetrating the first insulating layer and the second insulating layer in an area outside the oxide semiconductor layer.

[0006] A liquid crystal display device according to one embodiment of the present invention includes a transistor including a first gate electrode on a first substrate, a second gate electrode having an area overlapping with the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode, and a pixel electrode and a common electrode on the second insulating layer. The transistor is disposed between the first insulating layer and the oxide semiconductor layer, and further includes a first oxide conductive layer and a second oxide conductive layer disposed to sandwich the first gate electrode and the second gate electrode, the pixel electrode is electrically connected to the second oxide conductive layer, and the first gate electrode and the second gate electrode are electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in an area outside the oxide semiconductor layer.

[0007] A liquid crystal display device according to one embodiment of the present invention includes a transistor including a first gate electrode on a first substrate, a second gate electrode having a region overlapping with the first gate electrode, an oxide semiconductor layer between the first gate electrode and the second gate electrode, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a second insulating layer between the oxide semiconductor layer and the second gate electrode; The transistor further includes a first pixel electrode between the first insulating layer and the oxide semiconductor layer and a first oxide conductive layer and a second oxide conductive layer arranged to sandwich the first gate electrode and the second gate electrode, the first pixel electrode and the second pixel electrode being electrically connected to a wiring continuing from the second oxide conductive layer, and the first gate electrode and the second gate electrode being electrically connected by a first contact hole penetrating the first insulating layer and the second insulating layer in a region outside the oxide semiconductor layer. Effect of the Invention

[0008] According to one embodiment of the present invention, by providing a dual-gate transistor in a pixel and embedding wiring connected to the transistor in an insulating layer, it is possible to improve the reliability of a liquid crystal display device without providing a shield electrode or the like. [Brief description of the drawings]

[0009] [Figure 1] 1 shows a configuration of a liquid crystal display device according to one embodiment of the present invention. [Diagram 2] 1 shows an example of a circuit configuration of a display unit of a liquid crystal display device according to an embodiment of the present invention. [Diagram 3] 1 shows an example of a data signal line driving circuit of a liquid crystal display device according to one embodiment of the present invention. [Figure 4] 1 is a timing chart illustrating the operation of a liquid crystal display device according to an embodiment of the present invention, in which (A) shows the case of the FFS mode and the IPS mode, and (B) shows the case of the PSVA mode. [Diagram 5] 1 shows a configuration of a liquid crystal display device according to one embodiment of the present invention. [Figure 6] 1 shows an example of a circuit configuration of a display unit of a liquid crystal display device according to an embodiment of the present invention. [Figure 7] 1A and 1B show the structure of a transistor used in a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a planar structure and (B) shows a cross-sectional structure. [Figure 8]1A and 1B show the structure of a transistor used in a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a planar structure and (B) shows a cross-sectional structure. [Figure 9] 1 shows a cross-sectional structure of a transistor used in a liquid crystal display device according to one embodiment of the present invention. [Figure 10] 1 shows a cross-sectional structure of a transistor used in a liquid crystal display device according to one embodiment of the present invention. [Figure 11] 1 shows a cross-sectional structure of a transistor used in a liquid crystal display device according to one embodiment of the present invention. [Figure 12] 1 is an energy band diagram for explaining the structure and operation of a transistor applied to a liquid crystal display device according to one embodiment of the present invention; [Figure 13] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Figure 14] 13A shows a cross-sectional structure of the pixel taken along lines A1-A2 and B1-B2, and FIG. 13B shows a cross-sectional structure taken along line C1-C2. [Figure 15] 1 is a cross-sectional structure of a pixel of a liquid crystal display device according to one embodiment of the present invention, showing a structure in which an element substrate, an opposing substrate, and a liquid crystal layer are arranged. [Figure 16] 1 shows a cross-sectional structure of a pixel of a liquid crystal display device according to one embodiment of the present invention, with (A) and (B) showing the configuration of an input terminal portion. [Figure 17] 13A to 13C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to the A1-A2 and B1-B2 lines shown in FIG. 13, and (B) shows a cross-sectional view corresponding to the C1-C2 line. [Figure 18] 13A to 13C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to the A1-A2 and B1-B2 lines shown in FIG. 13, and (B) shows a cross-sectional view corresponding to the C1-C2 line. [Figure 19]13A to 13C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to the A1-A2 and B1-B2 lines shown in FIG. 13, and (B) shows a cross-sectional view corresponding to the C1-C2 line. [Figure 20] 13A to 13C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to the A1-A2 and B1-B2 lines shown in FIG. 13, and (B) shows a cross-sectional view corresponding to the C1-C2 line. [Figure 21] 13A to 13C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to the A1-A2 and B1-B2 lines shown in FIG. 13, and (B) shows a cross-sectional view corresponding to the C1-C2 line. [Figure 22] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Figure 23] FIG. 22 shows a cross-sectional structure of the pixel, in which (A) shows the cross-sectional structure corresponding to the A3-A4 line and the B3-B4 line, and (B) shows the cross-sectional structure corresponding to the C3-C4 line. [Figure 24] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Diagram 25] 24A and 24B show cross-sectional structures of the pixel, where (A) shows a cross-sectional structure corresponding to line A5-A6, and (B) shows a cross-sectional structure corresponding to line D1-D2. [Figure 26] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Figure 27] 26A and 26B show cross-sectional structures of the pixel taken along line A7-A8 and line C7-C8, respectively. [Figure 28] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Figure 29] 27A to 27C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to lines A9-A10 and B9-B10 shown in FIG. 28, and (B) shows a cross-sectional view corresponding to line C9-C10. [Diagram 30] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Diagram 31] 3A to 3C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to lines A11-12 and B11-B12 shown in FIG. 30, and (B) shows a cross-sectional view corresponding to line C11-C12. [Diagram 32] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Diagram 33] 3A to 3C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to line A13-14 shown in FIG. 32, and (B) shows a cross-sectional view corresponding to line C13-C14. [Diagram 34] 1 is a cross-sectional structure of a pixel of a liquid crystal display device according to one embodiment of the present invention, showing a structure in which an element substrate, an opposing substrate, and a liquid crystal layer are arranged. [Diagram 35] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Diagram 36] 3A to 3C are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to lines A15-A16 and B15-B16 shown in FIG. 35, and (B) shows a cross-sectional view corresponding to line C15-C16. [Figure 37] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Figure 38] 37A and 37B show cross-sectional structures of the pixel, where (A) shows a cross-sectional structure corresponding to line A17-A18, and (B) shows a cross-sectional structure corresponding to line B17-B18. [Figure 39] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Diagram 40] FIG. 39 shows a cross-sectional structure of the pixel, in which (A) shows a cross-sectional structure corresponding to line A19-A20, and (B) shows a cross-sectional structure corresponding to line C19-C20. [Diagram 41] 1 is a cross-sectional structure of a pixel of a liquid crystal display device according to one embodiment of the present invention, showing a structure in which an element substrate, an opposing substrate, and a liquid crystal layer are arranged. [Diagram 42]4 is a graph showing a relationship between a signal voltage applied to a pixel of a liquid crystal display device according to one embodiment of the present invention and a luminance characteristic. [Diagram 43] 39A and 39B are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to line A19-A20 shown in FIG. 39, and (B) shows a cross-sectional view corresponding to line C19-C20. [Diagram 44] 39A and 39B are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to line A19-A20 shown in FIG. 39, and (B) shows a cross-sectional view corresponding to line C19-C20. [Diagram 45] 39A and 39B are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to line A19-A20 shown in FIG. 39, and (B) shows a cross-sectional view corresponding to line C19-C20. [Figure 46] 39A and 39B are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to line A19-A20 shown in FIG. 39, and (B) shows a cross-sectional view corresponding to line C19-C20. [Figure 47] 39A and 39B are diagrams illustrating a manufacturing process for a liquid crystal display device according to one embodiment of the present invention, in which (A) shows a cross-sectional view corresponding to line A19-A20 shown in FIG. 39, and (B) shows a cross-sectional view corresponding to line C19-C20. [Figure 48] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Figure 49] 49 shows a cross-sectional structure of the pixel shown in FIG. 48, taken along line C21-C22. [Figure 50] 1 is a plan view showing a pixel of a liquid crystal display device according to an embodiment of the present invention; [Figure 51] 50, (A) shows the cross-sectional structure corresponding to line A23-A24, and (B) shows the cross-sectional structure corresponding to line C23-C24. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention includes many different aspects, and is not to be interpreted as being limited to the following exemplary embodiments. The drawings attached to this specification may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual aspect in order to make the description clearer, but this is merely an example and does not necessarily limit the contents of the present invention. In addition, in the present invention, when a specific element shown in a drawing and a specific element shown in another drawing are identical or correspond to each other, the same symbol (or a symbol with a, b, etc. added after the number shown as the symbol) may be added, and repeated explanations may be omitted as appropriate. Furthermore, the letters "first" and "second" added to each element are convenient marks used to distinguish each element, and have no further meaning unless otherwise explained.

[0011] In this specification, when a certain member or region is described as being "on (or under)" another member or region, unless otherwise specified, this includes not only the case where it is directly above (or directly below) the other member or region, but also the case where it is above (or below) the other member or region. In other words, it also includes the case where another component is included between the certain member or region and above (or below) the other member or region.

[0012] 1. Liquid crystal display device configuration The circuit configuration of a liquid crystal display device according to an embodiment of the present invention will be described below. In the following, a circuit configuration applicable to a FFS (Fringe Field Switching) system and an IPS (In Plane Switching) system, and a circuit configuration applicable to a PSVA (Polymer Stabilized Vertical Alignment) system will be described. An example of such a circuit configuration will be given below.

[0013] 1-1. FFS and IPS LCDs 1 shows the configuration of an FFS-type and IPS-type liquid crystal display device 200a according to an embodiment of the present invention. The liquid crystal display device 200a has a structure in which a liquid crystal layer (not shown) is provided between a first substrate 100 and a second substrate 102 arranged opposite to each other, and includes a display unit 104 in which an image is displayed by utilizing the electro-optical effect of liquid crystal. The display unit 104 is provided with at least one pixel 106, a scanning signal line 116, a common signal line 117, and a data signal line 118. The at least one pixel 106 is made up of a plurality of pixels. The plurality of pixels 106 are appropriately arranged in the display unit 104. The plurality of pixels 106 are arranged to correspond to, for example, a stripe arrangement, a mosaic arrangement, a delta arrangement, or a pentile arrangement.

[0014] The liquid crystal display device 200a also includes a scanning signal line driving circuit 10 in an area outside the display unit 104. 8, a common signal line drive circuit 109, and a data signal line drive circuit 110 can be appropriately arranged. Scanning signal lines 116 arranged in the display unit 104 are connected to the scanning signal line drive circuit 108, common signal lines 117 are connected to the common signal line drive circuit 109, and data signal lines 118 are connected to the data signal line drive circuit 110. The scanning signal line drive circuit 108 outputs scanning signals to the scanning signal lines 116, the common signal line drive circuit 109 outputs common signals to the common signal lines 117, and the data signal line drive circuit 110 outputs video signals to the data signal lines 118.

[0015] The liquid crystal display device 200a includes an input terminal section 112 provided at an end of the first substrate 100. The input terminal section 112 includes at least one terminal electrode 114. The at least one terminal electrode 114 is made up of a plurality of terminal electrodes 114. The plurality of terminal electrodes 114 are appropriately arranged in the input terminal section 112. The input terminal section 112 is a connection section with an external circuit, and is a portion to which a flexible printed wiring board (not shown) is connected.

[0016] 1 also shows an equivalent circuit of the pixel 106. The pixel 106 includes a transistor 202, a liquid crystal element 204, and a storage capacitor element 206. The transistor 202 has a control terminal called a gate and input / output terminals called a source and a drain. The transistor 202 disposed in the pixel 106 has a gate (control terminal) electrically connected to a scanning signal line 116, one of the source and the drain (first input / output terminal) electrically connected to a data signal line 118, and the other of the source and the drain (second input / output terminal) electrically connected to the liquid crystal element 204 and the storage capacitor element 206. The liquid crystal element 204 and the storage capacitor element 206 are electrically connected to a common signal line 117.

[0017] The on and off states of the transistor 202 are controlled by a scanning signal input to a gate (control terminal) from the scanning signal line 116, and when the transistor 202 is in the on state, a video signal is input to the pixel 106 from the data signal line 118. In this state, a voltage based on the data signal is applied to the liquid crystal element 204, and the storage capacitor element 206 is charged with the voltage based on the data signal. The liquid crystal element 204 includes a pair of electrodes and a liquid crystal layer. One electrode (also called a pixel electrode) of the liquid crystal element 204 is electrically connected to the transistor 202, and the other electrode (common electrode) is electrically connected to the common signal line 117. The orientation of the liquid crystal molecules of the liquid crystal element 204 is controlled by a voltage based on the video signal and a voltage applied to the common signal line 117. The liquid crystal display device 200a has a function of displaying an image on the display unit 104 by individually controlling the orientation state of the liquid crystal in the plurality of pixels 106.

[0018] FIG. 2 shows a circuit configuration of the display unit 104 in the FFS and IPS modes. n R m ), 106( n G m ), 106( n B m+1 ), 106( n R m+1 ), and pixel 106( n+1 R m ), 106( n+1G m ), 106( n+1 B m+1 ), 106( n+1 R m+1 ) are arranged in the pixel. A transistor 202 is provided in each pixel. The transistor 202 provided in each pixel is connected to a scanning signal line 116 and a data signal line 118. Each pixel is provided with a pixel electrode and a common electrode.

[0019] FIG. 2 shows an embodiment in which the pixels are arranged in a stripe pattern. That is, FIG. 2 shows an example in which red (R), green (G), and blue (B) pixels are arranged in each column. Each pixel is arranged as pixel 106 ( n G m ), 106( n R m+1 ) is the first scanning signal line 116 (G An ) and pixel 106( n R m ), 106( n B m+1 ) is the second scanning signal line (G Bn ) and pixel 106( n+1 G m ), 106( n+1 R m+1 ) is the scanning signal line 116 (G An+1 ) and pixel 106( n+1 R m ), 106( n+1 B m+1 ) is the second scanning signal line 116 (G Bn+1 ) is connected to each pixel. In relation to the line 118, pixel 106 ( n R m ), 106( n G m ), 106( n+1 R m ), 106( n+1 G m ) is a first data signal line 118 (D m) and pixel 106( n B m+1 ), 106( n R m+1 ), 106( n+1 B m+ 1), 106( n+1 R m+1 ) is a second data signal line 118 (D m+1 ) is connected to the first common signal line 117 (COM n ), and the pixels arranged in the (n+1)th row have their common electrodes connected to the second common signal line (COM n+1 ) is connected.

[0020] As shown in FIG. 2, by providing two scanning signal lines for each row, the number of data signal lines can be reduced. For example, in the pixel 106 ( n R m ) and pixel 106( n G m ) refers to the first data signal line 118 (D m ) in the nth row, and a video signal is input from the same data signal line. n B m+1 ) and pixel 106( n R m+1 ) refers to the second data signal line 118 (D m+1 ) and the video signal is input from the same data signal line.

[0021] 3 shows an example of the configuration of the data signal line driving circuit 110. FIG. 3 shows an example in which the data signal line driving circuit 110 is configured by a driver IC 111 mounted on a flexible printed wiring board (FPC board) 101 and a demultiplexer 209 formed on the first substrate 100. The FPC 101 is connected by a terminal electrode 114 provided on the first substrate 100. An output signal line 115 connected to the driver IC 111 is input to the demultiplexer 209 and distributed to a plurality of data signal lines. FIG. 3 shows a mode in which one output signal line 115 extending from the driver IC 111 is input to one block of the demultiplexer 209 and distributed to three data signal lines 118 (D1), 118 (D2), and 118 (D3). The number of outputs of the demultiplexer 209 is arbitrary.

[0022] The demultiplexer 209 can be formed of a transistor having the same structure as the transistor 202 provided in the pixel 106. In this way, the video signal processing is performed by the driver IC, which is mounted by COF (Chip On Film) and the demultiplexer 209 is provided on the first substrate 100 on which the display unit 104 is formed to distribute the data signal to the data signal line 118, thereby making it possible to reduce the circuit scale of the driver IC 111. Also, the power consumption of the driver IC 111 can be reduced.

[0023] FIG. 4A shows the first scanning signal line 116 (G An ), the second scanning signal line 116 (G Bn ), the first data signal line 118(D m ), and the common signal line 117 (COM n 4A shows a timing chart of a signal input to the common signal line 117 of the nth row (for example, the first scanning signal line 116 (G An )) is selected, and a video signal is written to the pixels in the even columns. Bn)) turns on half a pulse after the selection signal of the first scanning signal line, the pixels of the odd columns are precharged, and when the selection signal of the first scanning signal line turns off, the video signal is written. In this manner, the video signal is written to the pixels of each row of the display unit 104. In the next frame, the common voltage of the common signal line 117 is inverted, and the voltage level of the video signal is inverted accordingly, and the same operation is performed. In this manner, the FFS type and IPS type liquid crystal display device 200a can apply the frame inversion drive method.

[0024] 1-2.PSVA type liquid crystal display device 5 shows the configuration of a PSVA type liquid crystal display device 200b according to one embodiment of the present invention. The liquid crystal display device 200b has a structure in which a liquid crystal layer (not shown) is provided between a first substrate 100 and a second substrate 102 arranged opposite to each other, and includes a display unit 104 that displays images by utilizing the electro-optical effect of liquid crystal. The liquid crystal display device 200a also has a structure in which a liquid crystal layer (not shown) is provided between a first substrate 100 and a second substrate 102 arranged opposite to each other, and includes a display unit 104 that displays images by utilizing the electro-optical effect of liquid crystal. A scanning signal line driving circuit 108 and a data signal line driving circuit 110 are appropriately arranged in the outer region. Scanning signal lines 116 arranged in the display unit 104 are connected to the scanning signal line driving circuit 108, and the data signal lines 118 are connected to the data signal line driving circuit 110. The scanning signal line driving circuit 108 outputs scanning signals to the scanning signal lines 116, and the data signal line driving circuit 110 outputs video signals to the data signal lines 118. One terminal of each of the liquid crystal element 204 and the storage capacitance element 206 is electrically connected to the transistor 202, and a common voltage is applied to the other terminal.

[0025] FIG. 6 shows a circuit configuration of the display unit 104 in the PSVA system. n R m ), 106( n G m ), 106( n B m+1 ), 106( n R m+1 ), and pixel 106( n+1 R m ), 106( n+1 Gm ), 106( n+1 B m+1 ), 106( n+1 R m+1 2 shows an arrangement of the pixel electrodes 202, 204. Each pixel is provided with a transistor 202 connected to a data signal line 118.

[0026] FIG. 6 shows an embodiment in which the pixels are arranged in a stripe pattern. n G m ), 106( n R m+1 ) is the first scanning signal line 116 (G An ) and pixel 106( n R m ), 106( n B m+1 ) is the second scanning signal line (G Bn ) and pixel 106( n+1 Gm), 106( n+1 R m+1 ) is the scanning signal line 116 (G An+1 ) and pixel 106( n+1 R m ), 106( n+1 B m+1 ) is the second scanning signal line 116 (G Bn+1 ) is connected to the data signal line 118. n R m ), 106( n G m ), 106( n+1 R m ), 106( n+1 G m ) is a first data signal line 118 (D m ) and pixel 106( n B m+1 ), 106( n R m+1 ), 106( n+1 B m+1 ), 106( n+1 R m+1) is a second data signal line 118 (D m+1 6, like the pixel circuits of the FFS method and the IPD method, by providing two scanning signal lines for each row, the number of data signal lines can be reduced.

[0027] FIG. 4B shows the first scanning signal line 116 (G An ), the second scanning signal line 116 (G Bn ), and the first data signal line 118 (D m 4B shows a timing chart of a signal input to the first scanning signal line (for example, the first scanning signal line 116 (G An )) is selected, and a video signal is written to the pixels in the even columns. Next, the second scanning signal line in the nth row (for example, the second scanning signal line (G Bn )) is selected, and a video signal having a polarity opposite to that of the even-numbered columns is input when viewed with the common voltage as a reference. In this way, the PSVA liquid crystal display device 200b can apply a dot inversion driving method.

[0028] 1-3.Challenges to achieving higher resolution The transistor 202 is a thin film transistor whose channel region is formed of a semiconductor thin film. The transistor 202, together with the scanning signal line 116 and the data signal line 118, is fabricated using a fine patterning technique using photolithography. In order to reduce the manufacturing cost of the liquid crystal display devices 200a and 200b, it is considered necessary to reduce the number of photomasks. However, the scanning signal line 116 and the data signal line 118 need to be arranged so as to cross each other. In addition, a part of these lines needs to be arranged so as to cross a seal pattern that seals the liquid crystal layer. The scanning signal line 116 and the data signal line 118 are formed of metal wiring, but since the metal wiring cannot be exposed in the portion overlapping with the seal pattern, it is necessary to cover the wiring with an inorganic insulating film. If the seal material and the metal wiring are in direct contact with each other, moisture (H2O) in the air is likely to penetrate into the liquid crystal layer through the interface between the seal material and the metal wiring, which causes a decrease in reliability.

[0029] The liquid crystal display devices 200a and 200b are able to display high definition images by increasing the density of the pixels 106 arranged in the display section 104. However, as the number of pixels in the display section 104 increases, the signal writing time per frame becomes shorter, and this requires the transistors 202 to operate at high speed. It is generally known that the field effect mobility of a transistor varies depending on the type of semiconductor that forms the channel. For example, the field effect mobility of a thin film transistor using amorphous silicon (amorphous silicon TFT) is 0.5 cm. 2 / Vsec, which is considered the limit for driving a full high-definition (2K) LCD display. On the other hand, for an 8K resolution LCD display, the writing time needs to be shortened to around 1.9μsec, so the driving capacity of amorphous silicon TFTs is insufficient and it is necessary to compensate for the lack of driving capacity by using a split drive (a method of driving the screen by splitting it into multiple areas). However, the split drive method requires a complex drive circuit configuration, which increases the manufacturing cost and power consumption of the LCD display device, which is problematic.

[0030] As pixels become denser, the transistors that make up the pixels are required to be able to operate at high speed. In addition, liquid crystal display devices are required not only to have high performance transistors, but also to have high image quality while keeping manufacturing costs low. An embodiment of a liquid crystal display device that can meet such requirements is shown below.

[0031] 2. Transistor and backplane structure The transistor 202 used in the liquid crystal display devices 200a and 200b according to one embodiment of the present invention will be described in detail below. In this embodiment, the transistor 202 is a thin film transistor, and has at least two types of structures as described below.

[0032] 2-1. First example of transistor structure 7A and 7B show a first structure example of a transistor. Fig. 7A shows a plan view of a transistor 202. Fig. 7B shows a cross-sectional structure of the transistor 202 taken along line X1-X2 in Fig. 7A.

[0033] The transistor 202 includes an oxide semiconductor layer 128, a first gate electrode 120, and a second gate electrode 132. The transistor 202 has a structure in which the first gate electrode 120 is disposed on the first substrate 100 side with respect to the oxide semiconductor layer 128, and the second gate electrode 132 is disposed on the opposite side to the first substrate 100. A first insulating layer 122 is provided between the first gate electrode 120 and the oxide semiconductor layer 128, and a second insulating layer 130 is provided between the oxide semiconductor layer 128 and the second gate electrode 132. The first insulating layer 122 and the second insulating layer 130 function as gate insulating films that insulate the first gate electrode 120 and the second gate electrode 132 from the oxide semiconductor layer 128.

[0034] The transistor 202 has a structure in which the first oxide conductive layer 124a and the second oxide conductive layer 124b are provided between the first insulating layer 122 and the oxide semiconductor layer 128. The first oxide conductive layer 124a and the second oxide conductive layer 124b are arranged such that one end (tip portion) of each of them overlaps with the first gate electrode 120 and the second gate electrode 132. The first oxide conductive layer 124a and the second oxide conductive layer 124b are provided in contact with a surface (first surface) of the oxide semiconductor layer 128 on the first gate electrode 120 side. The first oxide conductive layer 124a and the second oxide conductive layer 124b are formed of a material belonging to the same metal oxide as the oxide semiconductor layer 128. The first oxide conductive layer 124a and the second oxide conductive layer 124b are in ohmic contact with the oxide semiconductor layer 128, and therefore can be regarded as a source electrode and a drain electrode. In addition, since the first oxide conductive layer 124a and the second oxide conductive layer 124b have higher conductivity than the oxide semiconductor layer 128, they can also be considered to form a source region and a drain region at the interface where they are in contact with the oxide semiconductor layer 128.

[0035] One end of the first oxide conductive layer 124a and one end of the second oxide conductive layer 124b are spaced apart, face each other, and are arranged to overlap the first gate electrode 120 and the second gate electrode 132. With this structure, the transistor 202 has a so-called gate overlap structure in which one ends of the source region and the drain region substantially overlap the gate electrode. With this structure, the transistor 202 can obtain a high on-current.

[0036] The first metal layer 126a is disposed between the first oxide conductive layer 124a and the oxide semiconductor layer 128, and the second metal layer 126b is disposed between the second oxide conductive layer 124b and the oxide semiconductor layer 128. The first metal layer 126a and the second metal layer 126b are any members and are provided as appropriate. The first metal layer 126a and the second metal layer 126b are used, for example, as wiring for electrically connecting the transistor 202 to other elements. The first metal layer 126a and the second metal layer 126b are disposed at positions away from a region in which a channel is formed in the oxide semiconductor layer 128. With this structure, the transistor 202 has a structure that can prevent contamination of the channel region by the metals forming the first metal layer 126a and the second metal layer 126b while having a structure that connects to wiring in a circuit.

[0037] 7A is a hole that penetrates the first insulating layer 122 and the second insulating layer 130, and is provided outside a region in which a channel of the oxide semiconductor layer 128 is formed.

[0038] The transistor 202 has a dual gate structure in which gate electrodes are disposed above and below the oxide semiconductor layer 128, and therefore can operate in a fully depleted state. The transistor 202 can also operate in a state (partially depleted) in which channels are formed on both the first surface side (first gate electrode 120 side) and the second surface side (second gate electrode 132 side) of the oxide semiconductor layer 128, even if the transistor 202 is not fully depleted. Whether the transistor 202 operates in a fully depleted state or a partially depleted state, the transistor 202 can eliminate the influence of an electric field from the metal layer 126 present at and in the vicinity of the interface with the insulating layer (first insulating layer 122, second insulating layer 130), and can prevent fluctuations in the threshold voltage.

[0039] As described above, the oxide semiconductor layer 128, the oxide conductive layer 124 (first oxide conductive layer 124a, second oxide conductive layer 124b), the insulating layer (first insulating layer 122, second insulating layer 130), the gate electrode (first gate electrode 120 and second gate electrode 132), and the metal layer 126 (first metal layer 126a and second metal layer 126b) constituting the transistor 202 are shown in detail.

[0040] 2-1-1.Oxide semiconductor layer The oxide semiconductor layer 128 includes one or more elements selected from indium (In), zinc (Zn), gallium (Ga), tin (Sn), aluminum (Al), and magnesium (Mg). For example, a ternary oxide material, a binary oxide material, and a single element oxide material exhibiting semiconductor properties can be used as the oxide semiconductor material forming the oxide semiconductor layer 128. An example of a quaternary oxide material is an In2O3-Ga2O3-SnO2-ZnO-based oxide material. An example of a ternary oxide material is an In2O3-Ga2O3-ZnO-based oxide material, an In2O3-SnO2-ZnO-based oxide material, an In2O3-Al2O3-ZnO-based oxide material, a Ga2O3-SnO2-ZnO-based oxide material, a Ga2O3-Al2O3-ZnO-based oxide material, and a SnO2-Al2O3-ZnO-based oxide material. Examples of binary oxide materials include In2O3-ZnO-based oxide materials, SnO2-ZnO-based oxide materials, Al2O3-ZnO-based oxide materials, MgO-ZnO-based oxide materials, SnO2-MgO-based oxide materials, and In2O3-MgO-based oxide materials. Examples of the oxide material include an In2O3-based metal oxide material, an SnO2-based metal oxide material, and a ZnO-based metal oxide material. These oxide materials may include silicon (Si), nickel (Ni), tungsten (W), hafnium (Hf), titanium (Ti), samarium (Sm), iron (Fe), and tantalum (Ta). The In-Ga-Zn-O-based oxide material described above is an oxide material containing at least In, Ga, and Zn, and there is no particular limitation on the composition ratio. In other words, the oxide semiconductor layer 128 is an oxide material represented by the chemical formula InMO3(ZnO) mA thin film represented by (m>0) can be used, where M represents one or more metal elements selected from Ga, Al, Mg, Ti, Sm, Ta, W, Hf, and Si. The oxides contained in the above-mentioned quaternary oxide materials, ternary oxide materials, binary oxide materials, and single element oxide materials are not limited to those having a stoichiometric composition, and may be composed of an oxide material having a composition deviated from the stoichiometric composition.

[0041] The oxide semiconductor layer 128 is produced by a sputtering method. As a sputtering device, a magnetron sputtering device or a sputtering device using inductively coupled plasma is used. As a sputtering target, a sintered body of the above-mentioned quaternary oxide material, ternary oxide material, binary oxide material, or single-element oxide material is used, and as a sputtering gas, a pure rare gas such as argon (Ar) or xenon (Xe), or a mixed gas of a rare gas and oxygen (O2) or a rare gas, oxygen (O2), and hydrogen (H2) is used. In addition, the oxide semiconductor layer 128 is produced by a coating method (wet method). When the oxide semiconductor layer 128 is produced by a coating method, a composition solution containing the above-mentioned quaternary oxide material, ternary oxide material, binary oxide material, single-element oxide material, or a precursor thereof is applied onto a substrate, and a process of drying and baking is performed.

[0042] The oxide semiconductor layer 128 has a carrier concentration of 1×10 15 / cm 3 ~5×10 18 / cm 3 When the carrier concentration of the oxide semiconductor layer 128 is in this range, a normally-off transistor can be realized. 7 ~10 10 It can be about that.

[0043] 2-1-2.Oxide conductive layer The first oxide conductive layer 124a and the second oxide conductive layer 124b are made of a conductive metal oxide material, a metal nitride material, or a metal oxynitride material. Examples of the metal oxide material include indium tin oxide (In2O3·SnO2: ITO), indium zinc oxide (In2O3·ZnO: IZO), and tin oxide (SnO2). The first oxide conductive layer 124a and the second oxide conductive layer 124b made of such a metal oxide material can form good ohmic contact with the oxide semiconductor layer 128.

[0044] The first oxide conductive layer 124a and the second oxide conductive layer 124b are made of titanium oxide (TiO x ) can be used as a metal nitride material, and titanium nitride (TiN x ), Zirconium nitride (ZrN x ) can be used as the metal oxynitride material, and titanium oxynitride (TiO x N y ), tantalum oxynitride (TaO x N y ), zirconium oxynitride (ZrO x N y ), hafnium oxynitride (HfO x N y ) can be used. These metal oxide materials, metal nitride materials, and metal oxynitride materials may contain a small amount of a metal element that improves electrical conductivity. For example, titanium oxide (TiO x ) may be doped with niobium (TiO x :Nb). By using such a metal oxide material, metal nitride material, or metal oxynitride material, even when it is brought into contact with the first metal layer 126a and the second metal layer 126b, the chemical stability of the contact portion can be ensured. That is, by using the metal oxide material, metal nitride material, or metal oxynitride material exemplified here as the first oxide conductive layer 124a and the second oxide conductive layer 124b, it is possible to prevent an oxidation-reduction reaction (local battery reaction) with a metal having a lower potential (for example, aluminum (Al)).

[0045] 2-1-3.Insulating layer The first insulating layer 122 and the second insulating layer 130 are made of an inorganic insulating material. Examples of inorganic insulating materials include silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The first insulating layer 122 and the second insulating layer 130 have a single-layer structure of an insulating film formed by these inorganic insulating materials, or a laminated structure in which a plurality of insulating films are laminated. For example, the first insulating layer 122 may have a structure in which a silicon nitride film and a silicon oxide film are laminated from the first substrate 100 side. The second insulating layer 130 may have a structure in which a silicon oxide film and a silicon nitride film are laminated from the oxide semiconductor layer 128 side. The first insulating layer 122 and the second insulating layer 130 are laminated with a plurality of inorganic insulating films having different compositions, which can reduce internal stress and improve the barrier properties against water vapor and the like.

[0046] In one embodiment of the present invention, the thickness of the first insulating layer 122 is thicker than the thickness of the second insulating layer 130. This can significantly reduce short circuits between the scanning signal lines 116 and the data signal lines 118, improving the manufacturing yield. Furthermore, this configuration can increase the on-current of the transistor 202. The thickness of the first insulating layer 122 is preferably in the range of 250 nm to 500 nm, and the thickness of the second insulating layer 130 is preferably about half that, for example, in the range of 125 nm to 250 nm. With such a configuration of the insulating layers, good transistor characteristics can be obtained.

[0047] 2-1-4.Gate electrode The first gate electrode 120 and the second gate electrode 132 are made of a metal material such as aluminum (Al), molybdenum (Mo), tungsten (W), zirconium (Zr), etc. For example, the first gate electrode 120 and the second gate electrode 132 are made of a film of aluminum (Al), molybdenum-tungsten (MoW) alloy, etc. Also, the first gate electrode 120 and the second gate electrode 132 may be made of an aluminum alloy, a copper alloy, or a silver alloy. As the aluminum alloy, an aluminum-neodymium alloy (Al-Nd), an aluminum-cerium alloy (Al-Ce), an aluminum-neodymium-nickel alloy (Al-Nd-Ni), an aluminum-carbon-nickel alloy (Al-C-Ni), a copper-molybdenum alloy (Cu-Mo), a copper-manganese alloy (Cu-Mn), etc. are applied. Furthermore, the first gate electrode 120 and the second gate electrode 132 may be made of a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.

[0048] 2-1-5. Metal layer The first metal layer 126a and the second metal layer 126b are made of a metal material with high conductivity, such as aluminum (Al) or copper (Cu). For example, the first metal layer 126a and the second metal layer 126b are made of an aluminum alloy, a copper alloy, or a silver alloy. The aluminum alloy is made of a metal material such as an aluminum-neodymium alloy (Al-Nd), an aluminum-titanium alloy (Al-Ti), an aluminum-silicon alloy (Al-Si), an aluminum-neodymium-nickel alloy (Al-Nd-Ni), an aluminum-carbon-nickel alloy (Al-C-Ni), or a copper-nickel alloy (Cu-Ni). The first metal layer 126a and the second metal layer 126b are made of such a metal material, so that they have heat resistance and can reduce wiring resistance.

[0049] 8(A) and 8(B) show a modification of the first structure of the transistor 202. Fig. 8(A) shows a plan view of the transistor 202. Fig. 8(B) shows a cross-sectional structure of the transistor 202 corresponding to line X1-X2 shown in Fig. 8(A).

[0050] The transistor 202 illustrated in FIGS. 8A and 8B has a layer structure in the oxide semiconductor layer 128. 1 shows a structure in which a low-resistance region 127 is formed in an oxide semiconductor layer 128 by irradiation with X-rays. The low-resistance region 127 is formed in a region outside a region where the oxide semiconductor layer 128 overlaps with the second gate electrode 132.

[0051] The laser light used in this process is preferably a short-wavelength laser light so that the light is absorbed by an oxide semiconductor having a wide band gap. For example, ultraviolet laser light such as KrF excimer laser light (wavelength 248 nm), XeCl excimer laser light (wavelength 308 nm), or XeF excimer laser light (wavelength 351 nm) is preferably used. When the oxide semiconductor layer 128 is irradiated with the laser light, for example, oxygen vacancies (donors) are generated, and the resistance of the region is reduced. Also, the same effect (reduced resistance) can be obtained by irradiating the oxide semiconductor layer 128 with ions of an inert gas such as argon (Ar) instead of irradiating with the laser light.

[0052] The low-resistance region 127 can be formed in a self-aligned manner in the oxide semiconductor layer 128. That is, by irradiating the second gate electrode 132 with laser light, the second gate electrode 132 functions as a mask for blocking the laser light, and the low-resistance region 127 can be formed outside the region where the oxide semiconductor layer 128 overlaps with the second gate electrode 132.

[0053] In addition, by providing the low resistance region 127, the offset width W is set so that the ends of the first oxide conductive layer 124a and the second oxide conductive layer 124b do not overlap with the first gate electrode 120 and the second gate electrode 132. L In this case, the offset width W L can be set to 0.5 μm to 2.0 μm.

[0054] In this manner, by forming the low-resistance region 127 in a self-aligned manner in the oxide semiconductor layer 128, the channel length of the transistor 202 can be controlled in a self-aligned manner, thereby reducing variation in characteristics. Furthermore, since the oxide semiconductor layer 128 is formed in the transistor 202 as a source region and a drain region in which resistance is reduced, the on-state current can be increased.

[0055] 2-2. Second example of transistor structure 9 is a schematic cross-sectional view illustrating a second structure example of the transistor 202. The second structure example differs from the first structure example in the configuration of the oxide semiconductor layer 128. The following description will focus on differences from the first structure example.

[0056] The oxide semiconductor layer 128 includes at least two regions. Specifically, as shown in FIG. 9, the oxide semiconductor layer 128 includes a first region 129a and a second region 129b. In the oxide semiconductor layer 128, the first region 129a exists on the first gate electrode 120 side, and the second region 129b exists on the second gate electrode 132 side. FIG. 9 shows the oxide semiconductor layer 128 as having a clear boundary between the first region 129a and the second region 129b, but the first region 129a and the second region 129b may not have a clear boundary. In the oxide semiconductor layer 128, the first region 129a occupies the majority, and the second region 129b exists as a thin surface region. The second region 129b is a region that is extremely thin compared to the first region 129a. For example, when the first region 129a has a film thickness of 30 nm to 100 nm, the second region 129b has a film thickness of 2 nm to 10 nm, which is one tenth or less.

[0057] In the oxide semiconductor layer 128, the first region 129a and the second region 129b have different physical properties. For example, the carrier concentration (majority carrier concentration) of the oxide semiconductor layer 128 is different between the first region 129a and the second region 129b. Specifically, the carrier concentration of the second region 129b is lower than the carrier concentration of the first region 129a. For example, when the carrier concentration of the first region 129a is 1×10 15 / cm 3 That's it, 5 x 1018 / cm 3 When the carrier concentration of the second region 129b is within the following range, the carrier concentration of the second region 129b is 1×10 11 / cm 3 That's it, 1x 10 15 / cm 3 Correspondingly, the conductivity of the first region 129a is in the range of 1×10 -5 S / cm or more, 1×10 1 S / cm or less, whereas the conductivity of the second region 129b is in the range of 1×10 -10 S / cm or more, 1×10 -5 The range is less than S / cm.

[0058] The oxide semiconductor layer 128 may have a different crystallization rate between the first region 129a and the second region 129b. The first region 129a is amorphous or has a mixed state of amorphous and nanocrystals, whereas the second region 129b is nanocrystals or has a mixed state of nanocrystals and amorphous. When both the first region 129a and the second region 129b are in a mixed state of amorphous and nanocrystals, the second region 129b has a higher ratio of nanocrystals than the first region 129a. The second region 129b may contain faceted crystal grains with a larger grain size in addition to or instead of the nanocrystals.

[0059] The first region 129a and the second region 129b are formed by changing the deposition conditions of sputtering. For example, when the oxide semiconductor layer 128 is formed by sputtering, the first region 129a is formed by using a rare gas such as argon (Ar) as a sputtering gas, whereas the second region 129b is formed by using a rare gas such as argon (Ar) and oxygen (O2) gas as a sputtering gas. When the oxide semiconductor layer 128 is formed by sputtering, the first region 129a and the second region 129b are formed continuously while maintaining glow discharge. However, by increasing the oxygen partial pressure (the ratio of oxygen (O2) to argon (Ar)) when forming the second region 129b, donor defects can be reduced, the crystallization rate can be improved, and a dense region (high density region) can be formed.

[0060] The oxide semiconductor layer 128 may have the same composition in the first region 129a and the second region 129b, and only the crystallization rate may be different. The oxide semiconductor layer 128 may have the same metal oxide in the first region 129a and the second region 129b, but may have different compositions. The first region 129a and the second region 129b may have different compositions and different crystallization rates. For example, when the oxide semiconductor layer 128 is formed of an In2O3-Ga2O3-ZnO-based oxide material, the first region 129a can be made in an amorphous state or a state in which amorphous and nanocrystallites are mixed, and the second region 129b can be made in a nanocrystallite state or a state in which nanocrystallites and polycrystallites are mixed, by changing the sputtering conditions as described above. When both the first region 129a and the second region 129b are in a mixed state of amorphous and nanocrystallites, the proportion of nanocrystallites in the second region 129b can be made greater than that in the first region 129a.

[0061] As shown in FIG. 10, the transistor 202 may have a structure in which the first metal layer 126a and the second metal layer 126b are provided on the first insulating layer 122, and the first oxide conductive layer 124a and the second oxide conductive layer 124b are disposed on the upper layer side. According to such a structure, the substantially entire upper surface (and the side surface) of the first oxide conductive layer 124a and the second oxide conductive layer 124b contacts the oxide semiconductor layer 128, and the contact resistance can be further reduced. In the transistor 202 shown in FIG. 10, the first metal layer 126a and the second metal layer 126b, and the first oxide conductive layer 124a and the second oxide conductive layer 124b need to be patterned using different photomasks, respectively, so the number of photomasks increases compared to the transistor shown in FIG. 9 (although the number of photolithography steps increases). However, in terms of reliability, the transistor 202 can obtain good characteristics similar to those of the transistor shown in FIG. 9.

[0062] FIG. 11 illustrates a modification of the second structure of the transistor 202. As illustrated in FIG. 11, the oxide semiconductor layer 128 may include a low-resistance region 127. The low-resistance region 127 is a region In other words, even when the oxide semiconductor layer 128 includes the first region 129a and the second region 129b, the transistor 202 in which the source region and the drain region are formed in a self-aligned manner can be formed.

[0063] 9, even if the oxide semiconductor layer 128 has the same composition in the first region 129a and the second region 129b, if the ratio of nanocrystals (crystallization rate) is different between the two regions, the size of the band gap of each region is different. That is, the band gap of the oxide semiconductor layer 128 is smaller in the first region 129a than in the second region 129b. For example, when the composition of the oxide semiconductor layer 128 is the same and the band gap of the first region 129a is in the range of 2.8 eV or more and less than 3.0 eV, the band gap of the second region 129b is in the range of 3.0 eV or more and 3.2 eV or less because the crystallization rate is high. In addition, the work function of the first region 129a is larger than the work function of the second region 129b due to the difference in the crystallization rate. 12(A), when the first region 129a and the second region 129b are joined, the energy (Ec) of the bottom of the conduction band is higher in the second region 129b than in the first region 129a. For example, it is preferable that the energy (Ec) of the bottom of the conduction band in the first region 129a is higher than the energy (Ec) of the bottom of the conduction band in the second region 129b, and the absolute value of the difference is 0.3 eV or more.

[0064] When the oxide semiconductor layer 128 having such a band structure is applied to the transistor 202, it is found that a buried channel is formed as described below. The second region 129b existing between the first insulating layer 122 corresponding to the gate insulating film and the first region 129a forms an energy barrier against electrons in the valence band. Since the oxide semiconductor layer 128 has a higher carrier concentration in the first region 129a than in the second region 129b, the channel region of the transistor 202 is formed in the first region 129a. In other words, the channel region of the transistor 202 is formed at a position (a position separated by the thickness of the second region 129b) away from the interface between the first insulating layer 122 functioning as a gate insulating film and the oxide semiconductor layer 128. That is, by using the oxide semiconductor layer 128 having the first region 129a and the second region 129b, a buried channel is formed in the transistor 202. As a result, the transistor 202 can allow carriers to flow between the source and drain without being affected by the interface between the first insulating layer 122 and the oxide semiconductor layer 128.

[0065] 12B shows an example of a band diagram in the case where oxide materials having different compositions are used for the first region 129a and the second region 129b of the oxide semiconductor layer 128. For example, in the oxide semiconductor layer 128, the first region 129a is formed of an In2O3-Ga2O3-SnO2-ZnO-based oxide material, an In2O3-Ga2O3-SnO2-based oxide material, or an In2O3-Ga2O3-ZnO-based oxide material, and the second region 129b is formed of a Ga2O3-based oxide material, GaSnO x based oxide materials, or GaSiO xThe first region 129a is formed of a gallium oxide material such as an In2O3-Ga2O3-SnO2-based oxide material. Gallium oxide is a wide-gap material and has a band gap of 4 eV or more. By forming the first region 129a and the second region 129b from different materials in this way, the band gap of the first region 129a can be made 3.6 eV or more, and the band gap of the second region 129b can be made 4.1 eV. For example, the band gap of the In2O3-Ga2O3-SnO2-based oxide material forming the first region 129a is 3.6 eV to 3.9 eV, while when the second region 129b is formed of a-Ga2O3, the band gap is 4.3 eV. Also, when the second region 129b is a-GaSnO x When it is formed of a-GaSiO, its band gap is 4.0 eV, and x When the second region 129b is made of gallium oxide, the band gap is 4.5 eV or more. When the second region 129b is made of gallium oxide, the band gap is 1.0 eV or more larger than that of the first region 129a.

[0066] FIG. 12B shows a band diagram when the above-mentioned oxide material is used for the first region 129a and the second region 129b. The band gap of the first region 129a is smaller than that of the second region 129b, and the work function of the first region 129a is larger than that of the second region 129b. As a result, similar to the band diagram shown in FIG. 12A, when the first region 129a and the second region 129b are joined, the bottom energy (Ec) of the conduction band in the second region 129b is higher than that of the first region 129a. Since the oxide semiconductor layer 128 has such a structure, the channel region of the transistor 202 is formed at a position away from the interface between the first insulating layer 122 and the oxide semiconductor layer 128. In other words, the transistor 202 has a structure in which carriers (electrons) are not trapped at the interface between the first insulating layer 122 and the oxide semiconductor layer 128.

[0067] When the second region 129b is made of a gallium-based oxide material, the oxide semiconductor layer 128 can have a band gap that is 1 eV or more larger than that of the first region 129a. For example, when the second region 129b is made of polycrystalline gallium oxide (Ga2O3), the band gap is 4.8 eV to 4.9 eV. When the first region 129a is made of an In2O3-Ga2O3-ZnO-based oxide material, the band gap is 2.8 to 3.0 eV, so that the difference in band gap between the first region 129a and the second region 129b can be 1 eV or more. By forming the first region 129a and the second region 129b of the oxide semiconductor layer 128 from the above-mentioned materials, a buried channel can be reliably formed in the transistor 202.

[0068] The oxide material constituting the first region 129a may further contain silicon (Si) at a ratio of 0.5 atomic % or more and 5 atomic % or less. By including silicon in the oxide material constituting the first region 129a, the carrier concentration of the first region 129a can be increased, the field effect mobility of the transistor 202 can be increased, the heat resistance can be increased, and the threshold voltage can be controlled.

[0069] The oxide semiconductor layer 128 has a structure in which the second region 129b has a lower electrical conductivity and a lower carrier concentration than the first region 129a. The oxide semiconductor layer 128 has a dense structure with a high density surface portion by increasing the crystallization rate of the second region 129b compared to the first region 129a. The oxide semiconductor layer 128 has a structure in which the energy gap of the second region 129b is made wider than that of the first region 129a. The transistor 202 includes the oxide semiconductor layer 128 having such a structure, and thus has a structure in which a channel region is formed inside the oxide semiconductor layer 128.

[0070] When the oxide semiconductor layer is formed by sputtering, the ion sheath disappears when the glow discharge is stopped to finish the film formation, and the sputtered particles remaining in the gas phase are deposited on the surface of the oxide semiconductor layer, forming a low-density surface region. This low-density surface region contains defects, which adversely affects the characteristics of the transistor. In contrast, in this embodiment, the second region 129b is intentionally formed in a region corresponding to the surface region of the oxide semiconductor layer 128, and the channel region is moved away from the interface between the gate insulating film and the oxide semiconductor layer as described above, thereby preventing the characteristics of the transistor 202 from deteriorating.

[0071] In the transistor 202, the oxide semiconductor layer 128 has the first region 129a and the second region 129b, so that the amount of charge trapped at the interface between the first insulating layer 122 and the oxide semiconductor layer 128 is reduced. As a result, the transistor 202 can reduce the amount of shift (fluctuation) in the threshold voltage. Furthermore, the transistor 202 has a buried channel structure, so that leakage current flowing at the interface between the first insulating layer 122 and the oxide semiconductor layer 128 can be suppressed, and the off-current can be reduced. Furthermore, as shown in FIG. 9, Since the oxide conductive layer 124a and the second oxide conductive layer 124b are in contact with the first region 129a having high conductivity, the on-current of the transistor 202 can be increased. 9 From 1×10 12 A ratio of on-current to off-current (on-off ratio) of about 100% can be obtained.

[0072] As shown in FIG. 12C, the first region 129a of the oxide semiconductor layer 128 is made of InGaSnO x , or InGaSmO xIn the case where Ga2O3 having a band gap of 4.7 eV is used in the second region 129b, even if the substrate temperature is raised to 250°C or higher when forming the second insulating layer 130, Ga2O3 is not reduced by hydrogen (H) contained in silane (SiH4) used as the film forming gas, and the oxide semiconductor layer 128 does not become conductive. Therefore, a good quality second insulating layer 130 can be formed.

[0073] Furthermore, by using an oxide semiconductor material having a band gap of 3.6 eV or more for the oxide semiconductor layer 128, light with a wavelength of 450 nm, which is a blue light component of the light irradiated from the backlight, is not absorbed, and the reliability of the liquid crystal display device during actual operation can be significantly improved.

[0074] Although not shown, an intermediate region of an oxide semiconductor in which the carrier concentration changes stepwise or continuously may be present between the first region 129a and the second region 129b. The intermediate region of the oxide semiconductor may be formed together with the first region 129a and the second region 129b in the same oxide semiconductor layer, or may be formed separately as different oxide semiconductor layers. The transistor 202 shown in this embodiment can be used as an element constituting the backplane of not only a liquid crystal display device but also an organic electroluminescence display device (also called an organic EL display device or an organic EL display) and a micro LED display device (also called a micro LED display).

[0075] In the liquid crystal display device according to one embodiment of the present invention, pixels (and driving circuits) are formed by transistors having the structure described above. Next, the liquid crystal display device according to one embodiment of the present invention will be described in detail.

[0076] 3. Liquid crystal display device driving method The liquid crystal display device according to this embodiment will be described in detail. The liquid crystal display device includes the transistor described in the previous section. In this section, the structure of the liquid crystal display device compatible with various types will be described.

[0077] 3-1. FFS type liquid crystal display device As one mode of a liquid crystal display device according to one embodiment of the present invention, a liquid crystal display device having pixels of the FFS system will be exemplified.

[0078] 3-1-1. First embodiment This embodiment describes the structure of a liquid crystal display device 200a having FFS-type pixels in which the transistors shown in FIG. 9 or FIG. 12 are used, and a method for manufacturing the liquid crystal display device 200a.

[0079] 3-1-1-1.Pixel configuration Fig. 13 is a schematic plan view of a pixel 106a in a liquid crystal display device 200a according to this embodiment. Also, Fig. 14(A) shows cross-sectional structures along lines A1-A2 and B1-B2 shown in Fig. 13, and Fig. 14(B) shows a cross-sectional structure along line C1-C2.

[0080] In this embodiment, the element substrate refers to a substrate (also called a backplane) on which transistors for driving liquid crystal and pixel electrodes are formed, while the counter substrate refers to a substrate on which the element The term "substrate" refers to a substrate disposed opposite the substrate and having a color filter appropriately formed thereon. The liquid crystal display device 200a according to this embodiment is assumed to be a transmissive type.

[0081] As shown in FIG. 13, the pixel 106a includes a transistor 202, a pixel electrode 136, and a common electrode 138. The pixel electrode 136 is electrically connected to the transistor 202. The pixel electrode 136 is insulated from the common electrode 138 by an insulating layer (not shown). The scanning signal line 116, the data signal line 118a, the data signal line 118b, and the common wiring 144 are arranged to surround the pixel electrode 136 and the common electrode 138. The scanning signal line 116 and the common wiring 144 are arranged to extend in a first direction, and the data signal lines 118a and 118b are arranged to extend in a second direction intersecting the first direction. The data signal lines 118a and 118b are arranged to intersect with the scanning signal line 116 and the common wiring 144 with an insulating layer (not shown) sandwiched therebetween. The data signal line 118a is electrically connected to the transistor 202, and the data signal line 118b is electrically connected to the transistor of an adjacent pixel.

[0082] The transistor 202 has a dual gate structure in which the oxide semiconductor layer 128 is sandwiched between the first gate electrode 120 and the second gate electrode 132. As shown in FIG. 13, the oxide semiconductor layer 128 is provided so as to overlap the patterns of the data signal line 118a and the pixel electrode 136. The scanning signal line 116 is disposed on the first surface side of the oxide semiconductor layer 128. The scanning signal line 116 has an area overlapping with the oxide semiconductor layer 128, and this overlapping area substantially functions as the first gate electrode 120. The scanning signal line 116 functions both as a wiring for transmitting a scanning signal and as a gate electrode (first gate electrode 120) of the transistor 202. By providing a conductive pattern having such two functions, the aperture ratio of the pixel 106a can be improved. The second gate electrode 132 is disposed so as to overlap at least a part of the first gate electrode 120. The first gate electrode 120 and the second gate electrode 132 are provided with an insulating layer (not shown) sandwiched therebetween, and are electrically connected via a first contact hole 134.

[0083] The first oxide conductive layer 124a has a pattern continuing from the data signal line 118a, and the second oxide conductive layer 124b has a pattern continuing from the pixel electrode 136. In other words, the first oxide conductive layer 124a forms the data signal line 118a, and the second oxide conductive layer 124b forms the pixel electrode 136. In yet another word, the transistor 202 has a structure in which the first oxide conductive layer 124a is electrically connected to the data signal line 118a, and the second oxide conductive layer 124b is electrically connected to the pixel electrode 136.

[0084] 13, the pixel electrode 136 has a solid structure without slits. The pixel electrode 136 is formed of the same oxide conductive material as the second oxide conductive layer 124b. Specifically, the pixel electrode 136 is formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), niobium doped titanium oxide (TiO x :Nb), tantalum-doped titanium oxide (TiO x The insulating film is formed of a conductive film having light transmitting properties, such as Ta.

[0085] The common electrode 138 is disposed so as to overlap the pixel electrode 136. The common electrode 138 has a first slit 139. The first slit 139 is formed by a through hole penetrating the common electrode 138. The common electrode 138 has at least one, preferably a plurality of, first slits 139. The common electrode 138 is formed of an oxide conductive material having the same light-transmitting property as the pixel electrode 136. Furthermore, since the common electrode 138 has the first slit 139, it may be formed of a metal material (non-light-transmitting conductive material) such as aluminum (Al). The common electrode 138 is electrically connected to the common wiring 144. The common electrode 138 is connected to the common wiring 144 via a second contact hole 146 provided in an insulating layer (not shown). are electrically connected.

[0086] The common electrode 138 provided with the first slit 139 is disposed on the upper layer side (liquid crystal layer side) of the solid pixel electrode 136, so that an electric field generated between the pixel electrode 136 and the common electrode 138 acts on the liquid crystal layer. As shown in FIG. 13, the first slit 139 has a structure in which it is elongated in the second direction, which is the same as the direction in which the data signal line 118a extends, and is bent at approximately the center (P1-P2 line) of the pixel 106a. The direction in which the liquid crystal molecules rotate due to the action of the electric field can also be controlled by the structure of the first slit 139. The first slit 139, which is elongated in the second direction, has a structure in which it is bent at approximately the center (P1-P2 line) of the pixel 106a, so that the direction in which the liquid crystal molecules rotate can be made different between the upper half and the lower half of the pixel 106a. That is, a plurality of regions (also called multi-domains) in which the directions of the rotation of the liquid crystal molecules are different can be formed in the liquid crystal layer. With the pixel 106a having such a configuration, the liquid crystal display device 200a can widen the viewing angle.

[0087] 14(A) and 14(B) are schematic cross-sectional views of an element substrate 210. As shown in FIG. 14(A), the element substrate 210 includes a transistor 202, a pixel electrode 136, and a common electrode 138 provided on a first substrate 100. The transistor 202 has a structure similar to that shown in any one of FIG. 7(A), FIG. 7(B), FIG. 8, FIG. 9, FIG. 10, and FIG. 11, and has a structure in which a first gate electrode 120, a first insulating layer 122, a first oxide conductive layer 124a, a second oxide conductive layer 124b, an oxide semiconductor layer 128, a second insulating layer 130, and a second gate electrode 132 are stacked. FIG. 14(A) shows a structure in which the oxide semiconductor layer 128 includes a first region 129a and a second region 129b, but may be substantially formed of one layer (only the first region 129a) as shown in FIG. 7(B).

[0088] Although there is no limitation on the material of the first insulating layer 122 and the second insulating layer 130, it is preferable to form them from an oxide-based insulating material such as silicon oxide, aluminum oxide, etc. Also, they may have a structure in which a silicon nitride film and a silicon oxide film or an aluminum oxide film are stacked.

[0089] The first insulating layer 122 is preferably formed with a thickness of 200 nm to 800 nm, for example, 400 nm. The second insulating layer 130 is preferably formed with a thickness of 100 nm to 400 nm, for example, 200 nm, if the screen size of the liquid crystal display device 200a is about 4 to 6 inches, and with a thickness of 200 nm to 600 nm, for example, 300 nm, if the screen size is about 10 to 27 inches, and with a thickness of 200 nm to 800 nm, for example, 350 nm, if the screen size is 30 inches or more. Different voltages are applied to the pixel electrode 136 and the common electrode 138, and a capacitance is generated by providing the second insulating layer 130 between them. This capacitance has the effect of keeping the potential of the pixel electrode 136 constant. That is, a storage capacitance element is formed by a structure in which the pixel electrode 136, the second insulating layer 130, and the common electrode 138 are stacked. When the screen size of the liquid crystal display device 200a is small, the pixel size is naturally small as well, so it is preferable to reduce the thickness of the second insulating layer 130 to increase the capacitance. On the other hand, when the screen size of the liquid crystal display device 200a is large, such as 30 inches or more, it is preferable to increase the thickness of the second insulating layer 130 in order to reliably insulate the pixel electrodes 136 and the common electrode 138.

[0090] As described above, the first oxide conductive layer 124a extends outward (on the opposite side to the channel region) from the region where the first gate electrode 120 and the second gate electrode 132 overlap, and contacts the data signal line 118a. In other words, the first oxide conductive layer 124a is electrically connected to the data signal line 118a. On the other hand, the second oxide conductive layer 124b is provided so as to extend from the region where the first gate electrode 120 and the second gate electrode 132 overlap to the region of the pixel electrode 136. As described with reference to FIGS. 9(A) and 9(B), the first oxide conductive layer 124a and the second oxide conductive layer 124b extend outward (on the opposite side to the channel region) from the region where the first gate electrode 120 and the second gate electrode 132 overlap, and contacts the data signal line 118a. In other words, the first oxide conductive layer 124a is electrically connected to the data signal line 118a. On the other hand, the second oxide conductive layer 124b is provided so as to extend from the region where the first gate electrode 120 and the second gate electrode 132 overlap to the region of the pixel electrode 136. The oxide conductive layer 124b forms an input / output terminal of the transistor 202. The pixel 106a has a structure in which the transistor 202 is connected to the data signal line 118a by the first oxide conductive layer 124a and to the pixel electrode 136 by the second oxide conductive layer 124b, and thus a contact hole is omitted. With this configuration, the structure of the pixel 106a is simplified and the aperture ratio can be improved. According to one embodiment of the present invention, a structure in which a contact hole is formed to connect the pixel electrode 136 and the transistor 202, as in the conventional liquid crystal display panel, is not applied, so that a contact failure does not occur in principle. Therefore, even if the number of pixels increases with the increase in resolution, defective pixels are unlikely to be formed. As a result, the manufacturing yield of the liquid crystal display device can be improved.

[0091] The structures of the first gate electrode 120 and the second gate electrode 132 are not limited, and may have a structure in which a plurality of conductive layers are laminated as shown in FIG. 14(A). For example, the first gate electrode 120 may have a structure in which a first conductive layer 250 and a second conductive layer 252 are laminated, and the second gate electrode 132 may have a structure in which a fourth conductive layer 256 and a fifth conductive layer 258 are laminated. The first conductive layer 250 is provided in contact with the first substrate 100 (or, in the case where an insulating film is formed on the first substrate 100, the insulating film). The fourth conductive layer 256 is provided in contact with the second insulating layer 130. In order to improve adhesion to the underlying surface, the first conductive layer 250 is preferably made of a high melting point metal such as titanium (Ti), molybdenum (Mo), tantalum (Ta), molybdenum-titanium alloy (Mo-Ti), etc., and the fourth conductive layer 256 is also used as a conductive layer for forming the common electrode 138, so is preferably made of a translucent conductive material such as ITO or IZO.

[0092] The second conductive layer 252 is laminated on the first conductive layer 250, and the fifth conductive layer 258 is laminated on the fourth conductive layer 256. The second conductive layer 252 and the fifth conductive layer 258 are preferably made of a low-resistance metal material such as aluminum (Al) or its alloy, copper (Cu), etc., in order to reduce the resistance of the gate electrode. In liquid crystal display devices with a screen size of 15 inches or less, molybdenum (Mo), a molybdenum-tantalum alloy (MoTa), a molybdenum-tungsten alloy (MoW), etc. may also be used.

[0093] The first conductive layer 250, the second conductive layer 252, the fourth conductive layer 256, and the fifth conductive layer 258 may have any thickness. For example, the first conductive layer 250 and the fourth conductive layer 256 may be formed to a thickness of 20 nm to 200 nm, and the second conductive layer 252 and the fifth conductive layer 258 may be formed to a thickness of 200 nm to 1000 nm. The structure of the first gate electrode 120 is also applied to the scanning signal line 116. By forming the first gate electrode 120 and the scanning signal line 116 in such a laminated structure, it is possible to increase the adhesion with the base surface and reduce the wiring resistance (or electrode resistance).

[0094] The data signal line 118a has a structure in which the third conductive layer 254 is laminated on the first oxide conductive layer 124a. The third conductive layer 254 is formed of copper (Cu), aluminum (Al), or an alloy thereof in order to reduce wiring resistance. For example, molybdenum (Mo) can be applied to a liquid crystal display device having a screen size of 15 inches or less. Although not shown, the third conductive layer 254 may have a laminated structure in which high melting point metal layers such as titanium (Ti) and molybdenum (Mo) are provided on the upper and lower layers of aluminum (Al) in order to improve heat resistance. The data signal line 118a may have a structure covered with the oxide semiconductor layer 128. By having such a layered structure, the data signal line 118a can be prevented from peeling off from the base surface and from becoming oxidized and high-resistance during the manufacturing process. In addition, since the data signal line 118a is not connected to the first oxide conductive layer 124a through a contact hole, but the two layers are directly laminated, the contact area is increased and the contact resistance can be reduced. Such a connection structure between the wiring and the transistor is also effective when miniaturizing pixels.

[0095] As shown in FIG. 14(A) and FIG. 14(B), the common electrode 138 is provided on the second insulating layer 130. The common electrode 138 is formed of the same conductive film as the fourth conductive layer 256 forming the second gate electrode 132. Also, as shown as the section of the line B1-B2 in FIG. 14(A), the common electrode 138 is electrically connected to the common wiring 144 by the second contact hole 146 penetrating the first insulating layer 122 and the second insulating layer 130. The common electrode 138 has a structure in which the fourth conductive layer 256 and the fifth conductive layer 258 are stacked in the region overlapping with the second contact hole 146, thereby preventing an increase in contact resistance. In other words, by providing the fifth conductive layer 258, which is formed of a thicker film than the fourth conductive layer 256, overlapping with the second contact hole 146, it is possible to form a structure in which the step coverage is improved and the contact resistance does not increase. The common wiring 144 is provided between the first substrate 100 and the first insulating layer 122, and is formed with the same layer structure as the scanning signal line 116. Meanwhile, the common electrode 138 is formed only with the fourth conductive layer 256 in the region overlapping with the pixel electrode 136. With this structure, it is possible to prevent a large step from being formed in the region where the liquid crystal is driven by the pixel electrode 136, and it is possible to reduce alignment disturbance (disclination) of the liquid crystal.

[0096] FIG. 14B shows a cross-sectional structure of a portion of the pixel 106a where the transistor 202 is not provided. The pixel electrode 136 is provided between the data signal line 118a and the data signal line 118b of the adjacent pixel. As described above, the pixel electrode 136 is formed of a conductive film having light transmission properties, such as ITO or IZO. As shown in FIG. 14B, the upper surface of the pixel electrode 136 may be covered with an oxide semiconductor layer 128. The oxide semiconductor layer 128 has a band gap similar to that of a transparent conductive film and therefore has light transmission properties. In addition, the oxide semiconductor layer 128 has conductivity as a semiconductor. Therefore, the oxide semiconductor layer overlapping with the pixel electrode 136 can also be regarded as a part of the pixel electrode.

[0097] Fig. 15 shows a cross-sectional structure of the pixel 106a taken along the line C1-C2 shown in Fig. 13. Specifically, a counter substrate 212 and a liquid crystal layer 222 are provided on the element substrate 210 shown in Fig. 14(B).

[0098] On the element substrate 210 side, an alignment film 220a is provided so as to cover the common electrode 138. In addition, the counter substrate 212 has a light-shielding layer 224, a color filter layer 226, an overcoat layer 228, and an alignment film 220b provided on the second substrate 102. The light-shielding layer 224 is provided so as to surround the boundary region of the pixel 106a, and the color filter layer 226 is provided so as to overlap the pixel electrode 136. In this embodiment, since the liquid crystal display device 200a is an FFS type, horizontal alignment films are used for the alignment films 220a and 220b. A liquid crystal layer 222 is provided between the element substrate 210 and the counter substrate 212.

[0099] 14(A), 14(B), and 15, the liquid crystal display device 200a according to this embodiment has a structure in which the transistor 202 is of a dual gate type, but the scanning signal line 116 is not exposed to the liquid crystal layer 222. Also, the data signal line 118 is not exposed to the liquid crystal layer 222. In particular, the pixel 106a has a structure in which the scanning signal line 116 is covered with the first insulating layer 122 and the second insulating layer 130, and therefore the liquid crystal layer 222 is not easily affected by the signal (voltage) applied to the scanning signal line 116.

[0100] The second gate electrode 132 is electrically connected to the first gate electrode 120 and disposed near the liquid crystal layer 222, but is disposed separately and independently for each pixel, reducing the effect on the entire liquid crystal layer 222. Rather, the second gate electrode 132 acts to locally collect impurity ions in the liquid crystal layer 222, thereby suppressing deterioration of the liquid crystal layer 222 and preventing the occurrence of display spots.

[0101] 3-1-1-2.Terminal configuration FIG. 16(A) shows the configuration of the input terminal section 112 of the liquid crystal display device 200a. The input terminal section 112 includes a terminal electrode 114. The terminal electrode 114 is formed of a first conductive layer 250 and a second conductive layer 252. That is, the terminal electrode 114 is formed of the same conductive layer (the first conductive layer 250, the second conductive layer 252) as the first gate electrode 120. The terminal electrode 114 is electrically connected to a wiring 230 extending from a region where pixels are formed toward an end of the first substrate 100 (in other words, the terminal electrode 114 and the wiring 230 have a continuous structure). A first insulating layer 122 and a second insulating layer 130 are provided on the upper layer side of the wiring 230. In the region of the input terminal section 112, an opening 232 is provided by removing the first insulating layer 122 and the second insulating layer 130 so that the terminal electrode 114 is exposed. The terminal electrode 114 may be provided with a metal oxide conductive layer 234 overlapping the opening 232. The metal oxide conductive layer 234 is formed of, for example, ITO or IZO, and is provided to protect the surface of the second conductive layer 252 formed of a relatively soft metal such as aluminum (Al).

[0102] While the liquid crystal layer 222 is provided between the element substrate 210 and the counter substrate 212, the overcoat layer 228 is provided exposed from the counter substrate 212. The element substrate 210 and the counter substrate 212 are fixed by a sealant 236. The sealant 236 is provided in contact with the second insulating layer 130 on the element substrate 210 side and in contact with the overcoat layer 228 on the counter substrate 212 side. The sealant 236 is provided in contact with the second insulating layer 130 formed of an inorganic insulating film, thereby increasing the adhesive strength and preventing peeling. This makes it possible to prevent moisture from entering the liquid crystal layer 222.

[0103] The wiring 230 electrically connected to the terminal electrode 114 is covered with the first insulating layer 122 and the second insulating layer 130 formed of an inorganic insulating film, and is therefore provided at a position that does not directly contact the sealant 236. If the wiring connected to the terminal electrode 114 is formed of the fourth conductive layer 256 and the fifth conductive layer 258 forming the second gate electrode 132, the wiring will be in direct contact with the sealant 236 unless a new inorganic insulating film is added. In this structure, the wiring made of a metal material is a factor that reduces the adhesive force of the sealant 236. In addition, the step (unevenness) formed by the wiring on the second insulating layer 130 may reduce the adhesiveness and cause moisture to penetrate into the liquid crystal layer 222. In order to prevent such a problem, it is effective to form the terminal electrode 114 and the wiring 230 by the first conductive layer 250 and the second conductive layer 252 forming the first gate electrode 120, as shown in FIG. 16(A). According to the liquid crystal display device 200a of this embodiment, the adhesion of the sealant 236 that bonds the element substrate 210 and the counter substrate 212 can be improved, thereby preventing deterioration of the liquid crystal layer 222 and improving reliability.

[0104] 16B shows another example of the terminal electrode 114. The terminal electrode 114 is formed of the first conductive layer 250 and the second conductive layer 252, and has a structure in which a third oxide conductive layer 124c is provided so as to overlap the opening 232. The third oxide conductive layer 124c is a conductive layer formed in the same layer as the first oxide conductive layer 124a and the second oxide conductive layer 124b that form the transistor 202. With this configuration, a process of newly forming a (separate) metal oxide conductive layer for the terminal electrode 114 is not required, and therefore the manufacturing process can be simplified.

[0105] Thus, in the liquid crystal display device 200a according to this embodiment, in a structure in which a dual-gate transistor is provided in a pixel, the wiring (the scanning signal line 116 and the data signal line 118) connected to the transistor can be embedded in an insulating layer, thereby improving the reliability of the liquid crystal display device 200a.

[0106] 3-1-1-3. Manufacturing method A manufacturing process of the liquid crystal display device 200s according to this embodiment will be described in detail with reference to the drawings. As described below, the liquid crystal display device 200a according to this embodiment can be manufactured using five photomasks.

[0107] 17(A) and 17(B) show a step of forming a first gate electrode 120 and a common wiring 144 on a first substrate 100. Although not shown, at this stage, a scanning signal line is also formed simultaneously with the first gate electrode 120.

[0108] A first conductive layer 250 and a second conductive layer 252 are formed on the first substrate 100. The first conductive layer 250 is formed of a metal material such as titanium (Ti), molybdenum (Mo), tantalum (Ta), or a molybdenum-titanium alloy (MoTi), and the second conductive layer 252 is formed of a metal material such as aluminum (Al) or an alloy thereof, or copper (Cu). The first conductive layer 250 and the second conductive layer 252 are formed on substantially the entire surface of the first substrate 100 by, for example, a sputtering method. For example, the first conductive layer 250 is formed to a thickness of 20 nm to 200 nm, and the second conductive layer 252 is formed to a thickness of 200 nm to 1000 nm.

[0109] In a state where the first conductive layer 250 and the second conductive layer 252 are formed on substantially the entire surface of the first substrate 100, a first resist mask 451 is formed on the second conductive layer 252. The first resist mask 451 is formed by a first photomask 401. The first photomask 401 is a binary mask in which a first mask pattern 411 including a pattern of the first gate electrode 120, the common wiring 144, and the scanning signal line (116) (not shown) is formed. FIG. 17(A) shows a case where a positive photoresist is used, and shows an aspect in which the first mask pattern 411 forms a light-shielding portion. On the other hand, FIG. 17(B) shows a cross-sectional view near the center of the pixel 106a, and shows that the first resist mask is not formed in this portion because the gate electrode, the scanning signal line, and the common wiring are not formed.

[0110] 17(A) indicates that the first resist mask 451 is formed of the first photomask 401. The first conductive layer 250 and the second conductive layer 252 are etched using the first resist mask 451, thereby forming the first gate electrode 120, the common wiring 144, the scanning signal line (116), and the like (not shown).

[0111] 18(A) and 18(B) show a stage in which a first insulating layer 122, an oxide conductive layer 124, and a third conductive layer 254 are formed on a first substrate 100 on which a first gate electrode 120, a common wiring 144, and a scanning signal line (116) (not shown) are formed, and a second resist mask 452 is formed thereon.

[0112] The first insulating layer 122 is formed by a plasma CVD (Chemical Vapor Deposition) method or a sputtering method. The first insulating layer 122 is formed by a thin film forming technique such as a ring method, etc. The first insulating layer 122 is an inorganic insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, etc., and is formed to a thickness of 200 nm to 800 nm, for example, 400 nm.

[0113] An oxide conductive layer 124 and a third conductive layer 254 are formed on the first insulating layer 122. The oxide conductive layer 124 is formed by a sputtering method, a vapor deposition method, or a coating method to a thickness of 30 nm to 200 nm. The third conductive layer 254 is a thin film of a metal material such as aluminum (Al) or an alloy thereof, copper (Cu), or the like, formed by a sputtering method to a thickness of 200 nm to 2000 nm.

[0114] A second resist mask 452 is formed on the upper surface of the third conductive layer 254. The second resist mask 452 is formed using a second photomask 402. The second photomask 402 has a light transmitting portion (light-transmitting portion 420) and a light blocking portion (light-shielding portion 424) and a light blocking portion (light-blocking portion 425). 18(A) and 18(B), the second photomask 402 has a second mask pattern 412 including a portion (semi-transmissive portion 422) that transmits light by reducing the amount of light transmitted therethrough. The second photomask 402 is a half-tone mask having a light-shielding portion 424 for forming the data signal lines 118a and 118b and a semi-transmissive portion 422 for forming the first oxide conductive layer 124a and the second oxide conductive layer 124b, unlike a binary mask (a photomask formed by a transmitting portion and a light-shielding portion). The second photomask 402 is exposed to light on a photoresist film to form a second resist mask 452. The circled number "2" shown in FIG. 18(A) and FIG. 18(B) indicates that the second resist mask 452 is formed by the second photomask 402.

[0115] As shown in Figures 18(A) and 18(B), the second resist mask 452 has a pattern corresponding to the first oxide conductive layer 124a and the second oxide conductive layer 124b, and a pattern corresponding to the data signal line 118a is included in a thickened state on top of this pattern.

[0116] With the second resist mask 452 formed, the third conductive layer 254 and the oxide conductive layer 124 are etched. There is no limitation on the etching conditions. For example, the third conductive layer 254 made of a metal material is wet-etched using a mixed acid etching solution, and the oxide conductive layer 124 made of a metal oxide material or the like is dry-etched using a halogen-based gas. At this stage, the first oxide conductive layer 124a and the second oxide conductive layer 124b are formed. After this etching, the thin film region of the second resist mask 452 is removed by an ashing process, and the third conductive layer 254 is further etched while leaving the thick film portion. This etching forms the data signal lines 118a and 118b.

[0117] 19(A) and 19(B) show a stage in which an oxide semiconductor layer 128 is formed on the upper side of the first oxide conductive layer 124a, the second oxide conductive layer 124b, and the data signal lines 118a and 118b, and a third resist mask 453 is formed on the oxide semiconductor layer 128. The oxide semiconductor layer 128 is formed by, for example, a sputtering method. A sintered oxide semiconductor material is used as a sputtering target. The oxide semiconductor layer 128 is formed to a thickness of, for example, 20 nm or more and 100 nm or less, for example, 30 nm or more and 50 nm or less.

[0118] The third resist mask 453 is formed by applying a photoresist onto the oxide semiconductor layer 128 formed on substantially the entire surface of the first substrate 100, and exposing the photoresist using a third photomask 403. The third photomask 403 is a binary mask in which a third mask pattern 413 for forming a pattern of the oxide semiconductor layer 128 is formed. FIG. 19(A) shows an embodiment in which a positive photoresist is used and the third mask pattern 413 is formed in a light-shielding portion. Note that the circled number "3" shown in FIG. 19(A) and FIG. 19(B) indicates that the third resist mask 453 is formed by the third photomask 403. The oxide semiconductor layer 128 is etched using the third resist mask 453, thereby forming a pattern corresponding to the arrangement of the transistors, pixel electrodes, and data signal lines.

[0119] 20A and 20B show a step in which a second insulating layer 130 is formed on the oxide semiconductor layer 128, and a fourth resist mask 454 for forming contact holes is formed.

[0120] The second insulating layer 130 is formed of an oxide-based insulating material such as silicon oxide or aluminum oxide, similar to the first insulating layer 122. Alternatively, the second insulating layer 130 may be formed to have a structure in which a silicon nitride film and a silicon oxide film or an aluminum oxide film are stacked. The second insulating layer 130 is formed to a thickness of, for example, 100 nm or more and 800 nm or less. However, the thickness of the second insulating layer 130 can be appropriately set according to the screen size of the liquid crystal display device 200a.

[0121] The fourth resist mask 454 is formed on the second insulating layer 130 by the fourth photomask 404. The fourth photomask 404 is a binary mask in which a fourth mask pattern 414 corresponding to the first contact hole (134) and the second contact hole 146 (not shown) is formed. FIGS. 20(A) and 20(B) show a form in which the fourth mask pattern 414 is formed in a light-shielding portion, assuming that a positive photoresist is used. The circled number "4" shown in FIG. 20(A) indicates that the fourth resist mask 454 is formed by the fourth photomask 404. The second insulating layer 130 and the first insulating layer 122 are etched using the fourth resist mask 454, thereby forming the first contact hole (134) and the second contact hole 146 (not shown).

[0122] 21(A) and 21(B) show the stage where a first contact hole (134) and a second contact hole 146 are formed in the second insulating layer 130, a fourth conductive layer 256 and a fifth conductive layer 258 are formed thereon, and a fifth resist mask 455 is formed thereon.

[0123] The fourth conductive layer 256 is formed of a transparent conductive material such as ITO or IZO, and has a thickness of 100 nm or more and 400 nm or less by using a sputtering method, etc. The fifth conductive layer 258 is formed in the same manner as the first conductive layer 250.

[0124] The fifth resist mask 455 is formed by using the fifth photomask 405. The fifth photomask 405 is a halftone mask in which a fifth mask pattern 415 including a light-shielding portion 424 and a semi-transmitting portion 422 that reduces the amount of transmitted light and transmits light is formed in a transmitting portion 420. By using the fifth photomask 405, a fifth resist mask 455 is formed in which a portion corresponding to the pattern of the second gate electrode 132 and the common electrode 138 is thickened. The circled number "5" shown in FIG. 21(A) and FIG. 21(B) indicates that the fifth resist mask 455 is formed by the fifth photomask 405.

[0125] As shown in FIG. 21(A) and FIG. 21(B), the fifth resist mask 455 corresponds to the second gate electrode 132 and the common electrode 138, and has a shape in which the portion in which the fifth conductive layer 258 is to be left is thickened. With the fifth resist mask 455 formed, the fifth conductive layer 258 and the fourth conductive layer 256 are etched. There is no limitation on the etching conditions, but for example, the fifth conductive layer 258 formed of a metal material is wet-etched using a mixed acid etching solution, and the fourth conductive layer 256 formed of a metal oxide material or the like is dry-etched using a halogen-based gas. After this etching process, the thin region of the fifth resist mask 455 is removed by an ashing process, and the fifth conductive layer 258 is further etched while leaving the thick portion. The second gate electrode 132 and the common electrode 138 are formed by this etching. The common electrode 138 is connected to the common wiring 144 at the portion in which the second contact hole 146 is formed. Although not shown, the second gate electrode 132 is connected to the first gate electrode 120 through a first contact hole (134).

[0126] By using a halftone mask in this process, the portion of the common electrode 138 that overlaps with the pixel electrode 136 is formed only from the fourth conductive layer 256, and in the portion connecting the common electrode 138 and the common wiring 144, a structure in which the fourth conductive layer 256 and the fifth conductive layer 258 are stacked can be formed.

[0127] Through the above-mentioned steps, the element substrate 210 of the liquid crystal display device 200a having the structure shown in Figures 14(A) and 14(B) can be manufactured using five photomasks. In this manufacturing process, by using a half-tone mask, the structure connecting the data signal line 118a and the transistor 202 can be manufactured using one photomask, and a multi-layered structure of the second gate electrode 132 and the common electrode 138 can be manufactured.

[0128] 3-1-2. Second embodiment In this embodiment, the shape of the pixel electrode is different from that of the pixel 106a shown in the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the description of the same configuration will be omitted as appropriate.

[0129] Fig. 22 is a schematic plan view of a pixel 106b in a liquid crystal display device 200a according to this embodiment. Also, Fig. 23(A) shows cross-sectional structures along lines A3-A4 and B3-B4 shown in Fig. 22, and Fig. 23(B) shows a cross-sectional structure along line C3-C4.

[0130] 22, the pixel 106b has a pixel electrode 136 in which a second slit 137 is provided. The second slit 137 is disposed at a position that does not overlap with a first slit 139 of a common electrode 138. That is, the pixel 106b has a structure in which the first slits 139 and the second slits 137 are disposed alternately.

[0131] 23(A) and 23(B), the pixel electrode 136 has a structure in which the second oxide conductive layer 124b and the oxide semiconductor layer 128 are laminated. The pixel electrode 136 has a structure in which a second slit 137 is provided in a region where the second oxide conductive layer 124b has been removed. The oxide semiconductor layer 128 provided on the second oxide conductive layer 124b may also be removed according to the pattern of the second slit 137. The second slit 137 can also be regarded as a region where the second oxide conductive layer 124b and the oxide semiconductor layer 128 have been removed.

[0132] In the pixel 106b, the area overlapping with the common electrode 138 is reduced by providing the second slit 137 in the pixel electrode 136. As a result, the capacitance formed between the pixel electrode 136 and the common electrode 138 is reduced. This makes it possible to reduce the power consumption of the driver circuit that drives the liquid crystal. Note that the second slit 137 in the pixel electrode 136 can be formed at the same time as patterning the second oxide conductive layer 124b and the oxide semiconductor layer 128, and therefore does not increase the number of steps in the manufacturing process of the liquid crystal display device 200a.

[0133] The pixel 106b according to the present embodiment has the same configuration as the pixel 106a according to the first embodiment, except that the pixel electrode 136 is provided with a second slit 137. Therefore, the liquid crystal display device 200a according to the present embodiment has the same effects as the first embodiment, in addition to the effects achieved by providing the second slit 137.

[0134] Third embodiment This embodiment shows an embodiment in which the shape of the common electrode is different from that of the pixel 106b shown in the second embodiment. In the following, the differences from the second embodiment will be mainly described, and the description of the same configuration will be omitted as appropriate.

[0135] Fig. 24 is a schematic plan view of a pixel 106c in a liquid crystal display device 200a according to this embodiment. Fig. 25(A) shows a cross-sectional structure along line A5-A6 in Fig. 24, and Fig. 25(B) shows a cross-sectional structure along line D1-D2 in Fig. 24.

[0136] 24, the common electrode 138 is electrically connected to the common wiring 144 at two points, the second contact hole 146a and the second contact hole 146b. The second contact hole 146a and the second contact hole 146b are arranged apart from each other, and the pixel electrode 136 has a structure in which it extends to overlap the common electrode 138 in the region between them. Meanwhile, the transistor 202 has a configuration similar to that of the first embodiment. A second metal layer 126b may be provided in a region connecting the input / output terminal of the transistor 202 and the pixel electrode 136 so as to overlap the second oxide conductive layer 124b.

[0137] 25(A) and 25(B) show a structure in which the pixel electrode 136 is provided with the second slit 137 and the common electrode 138 is provided with the first slit 139, but the pixel electrode 136 may be formed of a solid film as in the first embodiment. As shown in FIG. 25(B), the region between the second contact hole 146a and the second contact hole 146b has a region where the pixel electrode 136 and the common electrode 138 overlap with the second insulating layer 130 interposed therebetween. Since this region is a region where electrostatic capacitance is accumulated, the capacitance of the storage capacitor element formed in the region where the pixel electrode 136 and the common electrode 138 overlap can be increased without impairing the aperture ratio of the pixel 106c. Note that, in this embodiment, since only the arrangement of the second contact holes 146a and 146b and the shapes of the pixel electrode 136 and the common electrode 138 are changed, this does not cause an increase in the number of steps in the manufacturing process of the liquid crystal display device.

[0138] The pixel 106c according to this embodiment is suitable for a liquid crystal display device having a relatively small screen size because the capacitance of the capacitance element can be increased without decreasing the aperture ratio. The pixel 106c has the same configuration as the second embodiment except for the arrangement of the second contact holes 146a and 146b and the pixel electrode 136. Therefore, the liquid crystal display device 200a according to this embodiment has the same effect as the second embodiment in addition to the increased capacitance of the capacitance element.

[0139] 3-1-4. Fourth embodiment This embodiment shows an embodiment in which the shape of the common electrode is different from that of the pixel 106a shown in the first embodiment. In the following, the differences from the first embodiment will be mainly described, and the description of the same configuration will be omitted as appropriate.

[0140] Fig. 26 is a schematic plan view of a pixel 106d in a liquid crystal display device 200a according to this embodiment. Fig. 27(A) shows a cross-sectional structure along line A7-A8 in Fig. 26, and Fig. 27(B) shows a cross-sectional structure along line C7-C8 in Fig. 26.

[0141] The pixel 106d shown in FIG. 26 has a structure in which the common electrode 138 is provided so as to be continuous across a plurality of pixels. The common electrode 138 has a stripe pattern so as to be continuous with adjacent pixels (pixels adjacent in the row direction). In addition, the common electrode 138 is provided with a first slit 139 at a position where it overlaps with the pixel electrode 136. Since the pixel 106d has a structure in which the common electrode 138 is continuous across a plurality of pixels, the common wiring is omitted. In comparison with the pixel 106a shown in FIG. 13 in the first embodiment, the pixel 106d shown in FIG. 26 does not have a common wiring, and therefore a contact hole for connecting the common electrode and the common wiring is not required. With such a configuration, the pixel 106d according to this embodiment can increase the aperture ratio.

[0142] As shown in FIG. 27(A), the structure of the portion along the line A7-A6 is the same as that of the pixel 106a in the first embodiment. On the other hand, as shown in FIG. 27(B), the structure along the line C7-C8 is provided so that the common electrode 138 is continuous across adjacent pixels and intersects with the data signal lines 118a and 118b across the second insulating layer 130. As described with reference to FIG. 26, the pixel 106d can omit a contact hole that connects the common electrode 138 and the common wiring within the pixel region. Therefore, the area occupied by the pixel electrode 136 within the pixel 106d region can be increased, and the aperture ratio of the pixel can be increased. Such a structure of the pixel 106d can be said to be suitable for a small display with a screen size of about 4 to 6 inches, for example.

[0143] The pixel 106dd shown in this embodiment has a configuration similar to that of the pixel 106a shown in the first embodiment, except that the common electrode 138 is shared with an adjacent pixel. Therefore, the liquid crystal display device 200a having the pixel 106d has the same effects as those of the first embodiment, Furthermore, the aperture ratio can be improved as described above.

[0144] Fifth embodiment This embodiment shows an aspect in which the transistor structure is different from that of the pixel 106a shown in the first embodiment.

[0145] Fig. 28 is a schematic plan view of a pixel 106e in a liquid crystal display device 200a according to this embodiment. Also, Fig. 29(A) shows cross-sectional structures along lines A9-A10 and B9-B10 shown in Fig. 28, and Fig. 29(B) shows a cross-sectional structure along line C9-C10.

[0146] The pixel 106e includes a transistor 203, a pixel electrode 136, and a common electrode 138. The pixel electrode 136 is electrically connected to the transistor 203. In this embodiment, the transistor 203 is a bottom-gate type transistor. Therefore, the pixel 106e has a structure in which the second gate electrode 132 and the first contact hole 134 shown in the first embodiment are omitted.

[0147] As shown in FIG. 29A, the transistor 203 has a structure in which an oxide semiconductor layer 128 is provided on a first gate electrode 120 via a first insulating layer 122. A first oxide conductive layer 124a and a second oxide conductive layer 124b are provided between the first insulating layer 122 and the oxide semiconductor layer 128. The first oxide conductive layer 124a and the second oxide conductive layer 124b are provided in contact with a surface (first surface) of the oxide semiconductor layer 128 on the first gate electrode 120 side. The oxide semiconductor layer 128 may include a first region 129a and a second region 129b as described above. The first oxide conductive layer 124a and the second oxide conductive layer 124b are in contact with the first surface (first region 129a) of the oxide semiconductor layer 128, thereby reducing contact resistance.

[0148] A second insulating layer 130 is provided on the upper layer side (the second surface side opposite to the first surface) of the oxide semiconductor layer 128. The second region 129b is interposed between the oxide semiconductor layer 128 and the first insulating layer 122, thereby making it possible to reduce defect density at the interface. This makes it possible to prevent fluctuations in the threshold voltage.

[0149] The pixel 106e according to this embodiment has the same configuration as the pixel 106a according to the first embodiment except for the configuration of the transistor 203, and exerts the same effects as those of the first embodiment.

[0150] 3-2-1. Sixth embodiment This embodiment shows a pixel structure of a liquid crystal display device 200a in which a color filter layer is provided below a transistor.

[0151] Fig. 30 is a schematic plan view of a pixel 106f in a liquid crystal display device 200a according to this embodiment. Also, Fig. 31(A) shows cross-sectional structures along lines A11-A12 and B11-B12 shown in Fig. 30, and Fig. 31(B) shows a cross-sectional structure along line C11-C12.

[0152] As shown in FIG. 21, the pixel 106f includes a transistor 208, a pixel electrode 136, and a common electrode 138. The pixel electrode 136 is electrically connected to the transistor 208. The transistor 208 includes an oxide semiconductor layer 128, a second gate electrode 132, a first oxide conductive layer 124a, and a second oxide conductive layer 124b. The second gate electrode 132 also serves as the scanning signal line 116, and is formed in the same layer as the common electrode 138. That is, the transistor 208 has a top-gate structure. The pixel 106f is also provided with a light-shielding layer 178 that overlaps with the scanning signal line 116, the data signal lines 118a and 118b, and the transistor 208. Although not shown, a color filter layer is provided in the area overlapping with the pixel electrode 136.

[0153] 31(A) and 31(B), a light-shielding layer 178 and a color filter layer 180 are provided between the first insulating layer 122 and the first substrate 100. The light-shielding layer 178 is provided in an area overlapping with the transistor 208 and the data signal lines 118a and 118b (and scanning signal lines, not shown). The color filter layer 180 is provided in an area overlapping with the pixel electrode 136.

[0154] An overcoat layer 182 made of a resin material such as polyimide is provided on the light-shielding layer 178 and the color filter layer 180. The overcoat layer 182 fills in the irregularities caused by the patterns of the light-shielding layer 178 and the color filter layer 180, forming a flat surface. Furthermore, by providing a silicon nitride film as a third insulating layer 184 on the overcoat layer 182, the influence of impurities from the color filter layer 180 can be reduced.

[0155] In applications of portable electronic devices such as smartphones and tablet terminals, miniaturizing pixels to improve the resolution of display screens requires that the sizes of transistors, wiring, and contact holes also be miniaturized. For example, in a dual-gate transistor, the diameter of the contact hole that electrically connects the top gate and bottom gate is required to be 2 μm or less. In that case, considering the diameter of the contact hole and the film thickness of the insulating layers that sandwich the oxide semiconductor layer from above and below, it is necessary to form a contact hole with a high aspect ratio on the mother glass, which increases the difficulty of the manufacturing process.

[0156] Therefore, in this embodiment, the light-shielding layer 178 arranged to overlap the transistor 208 is made of a conductive material, and a predetermined bias (for example, ground potential) is applied to stabilize the characteristics of the transistor 208. In other words, the light-shielding layer 178 is arranged on the surface of the oxide semiconductor layer 128 opposite to the second gate electrode 132 to function as a back gate electrode, thereby suppressing characteristic fluctuations (for example, a shift in the threshold voltage) of the transistor 208. The light-shielding layer 178 is made of titanium silicide (TiSi x ), Tantalum silicide (TaSi x ), molybdenum silicide (MoSi x By forming the insulating film 10 from a metal silicide material such as SiO 2 , it is possible to provide the insulating film 10 with electrical conductivity and heat resistance.

[0157] According to this embodiment, by providing a conductive light-shielding layer overlapping a transistor, the characteristics of the transistor can be stabilized and pixels can be miniaturized.

[0158] 3-2.IPS type LCD display As one mode of a liquid crystal display device according to an embodiment of the present invention, a liquid crystal display device having IPS pixels will be exemplified.

[0159] 3-2-1. Seventh embodiment This embodiment shows a structure of a liquid crystal display device 200a having IPS pixels that can use the transistors shown in any one of FIG. 7B, FIG. 8, FIG. 9, FIG. 10, and FIG.

[0160] Fig. 32 shows a schematic plan view of a pixel 106g in a liquid crystal display device 200a according to this embodiment. Fig. 33(A) shows a cross-sectional structure taken along line A13-A14 shown in Fig. 32, and Fig. 33(B) shows a cross-sectional structure taken along line C13-C14 shown in Fig. 32. In the following description, descriptions of parts common to the first embodiment will be omitted, and differences will be mainly described.

[0161] As shown in FIG. 32, the pixel 106g includes a transistor 202, a pixel electrode 150, and a capacitor. The pixel electrode 150 includes a common electrode 152. The pixel electrode 150 has a comb-like (multiple strip-like) pattern and has a shape bent in one direction at the center (L-shaped). The common electrode 152 also has a comb-like (multiple strip-like) pattern and has a shape bent in one direction at the center (L-shaped). The pixel electrode 150 and the common electrode 152 are arranged so that the comb-like portions interdigitate with each other.

[0162] The pixel electrode 150 is electrically connected to the transistor 202 through the third contact hole 148, and the common electrode 152 is electrically connected to the common wiring 144 through the second contact hole 146. As shown in FIG. 32, the common wiring 144 is disposed adjacent to the scanning signal line 116 and extends in the first direction. The second contact hole 146 that electrically connects the common electrode 152 to the common wiring 144 is disposed near the transistor 202. With such a layout, the aperture ratio of the pixel 106g can be improved.

[0163] As shown in FIG. 33(A), the pixel electrode 150 and the common electrode 152 are provided on the second insulating layer 130. The pixel electrode 150 is electrically connected to the transistor 202 through a third contact hole 148 that penetrates the second insulating layer 130 and the oxide semiconductor layer 128. The second metal layer 126b may be provided on the upper surface of the second oxide conductive layer 124b. The third contact hole 148 is preferably provided at a position that overlaps with the second metal layer 126b. The fourth conductive layer 256 has a structure in which it contacts the second metal layer 126b through the third contact hole 148, so that the pixel electrode 150 and the transistor 202 can be reliably electrically connected. Meanwhile, the common electrode 152 is electrically connected to the common wiring 144 through the second contact hole 146, as in the first embodiment.

[0164] 33(B), the pixel electrodes 150 and the common electrodes 152 are arranged alternately with a gap 154 ​​between them on the second insulating layer 130. By arranging them in this manner, the pixel electrodes 150 and the common electrodes 152 can be formed in the same process, and the manufacturing process can be simplified. In addition, the pixel electrodes 150 and the common electrodes 152 can be formed using the conductive layers (fourth conductive layer 256, fifth conductive layer 258) that form the second gate electrode 132 of the transistor 202, and therefore an increase in the number of manufacturing processes can be prevented.

[0165] Fig. 34 shows a cross-sectional structure of a pixel 106g taken along line C9-C10 shown in Fig. 33. Specifically, a counter substrate 212 and a liquid crystal layer 222 are provided on the structure of the element substrate 210 shown in Fig. 33(B).

[0166] An alignment film 220a is provided on the element substrate 210 side so as to cover the pixel electrodes 150 and the common electrode 152. The configuration of the counter substrate 212 is similar to that shown in Fig. 15 in the first embodiment. In this embodiment as well, horizontal alignment films are used for the alignment films 220a and 220b.

[0167] In the liquid crystal display device 200a according to this embodiment, similarly to the first embodiment, the scanning signal lines are embedded in the first insulating layer 122 and the second insulating layer 130, and the data signal lines 118a, 118b are embedded in the second insulating layer 130. This can improve the adhesion of the sealant that bonds the element substrate 210 and the counter substrate 212 together, thereby improving reliability.

[0168] Eighth embodiment In this embodiment, the pixel electrode and the common electrode have different shapes from those of the pixel 106g shown in the seventh embodiment. In the following, the differences from the seventh embodiment will be mainly described, and the description of the same configuration will be omitted as appropriate.

[0169] Fig. 35 is a schematic plan view of a pixel 106h in a liquid crystal display device 200a according to this embodiment. Also, Fig. 36(A) shows cross-sectional structures along lines A15-A16 and B15-B16 shown in Fig. 35, and Fig. 36(B) shows a cross-sectional structure along line C15-C16.

[0170] 35, in the pixel 106h, the connection portion between the common electrode 152 and the common wiring 144 is provided at a position away from the transistor 202. Specifically, the common wiring 144 is disposed adjacent to the scanning signal line of the adjacent pixel. In addition, the common electrode 152 is provided in a layer different from the pixel electrode 150 with an insulating layer interposed therebetween.

[0171] 36(A), the pixel electrode 150 has a structure that continues from the second oxide conductive layer 124b of the transistor 202. In other words, the pixel electrode 150 is electrically connected to the transistor 202 without a contact hole. On the other hand, the common electrode 152 is electrically connected to the common wiring 144 through the second contact hole 146. A second insulating layer 130 is provided between the pixel electrode 150 and the common electrode 152.

[0172] As shown in FIG. 36(B), the pixel electrodes 150 and the common electrodes 152 are arranged so as to be alternately arranged with a gap 154 ​​between them, sandwiching the second insulating layer 130. By providing the second insulating layer 130 between the pixel electrodes 150 and the common electrodes 152, it is possible to prevent a short circuit between the two electrodes even if the width of the gap 154 ​​is narrowed. In addition, by narrowing the gap 154 ​​between the pixel electrodes 150 and the common electrodes 152, it is possible to increase the electric field strength and reduce the driving voltage of the liquid crystal element. In addition, since the pixel electrodes 150 have a structure in which they are electrically connected to the transistors 202 without contact holes, it is possible to increase the effective area of ​​the pixel electrodes by the amount of the omission of the contact holes, and therefore it is possible to increase the aperture ratio.

[0173] The pixel 106h according to the present embodiment has a similar configuration to the pixel 106g according to the seventh embodiment, except for the configuration of the pixel electrode 150 and the common electrode 152. Therefore, the liquid crystal display device 200a according to the present embodiment has the same effects as those of the seventh embodiment, in addition to the effects described above.

[0174] Ninth embodiment In this embodiment, the pixel electrode and the common electrode have different shapes from those of the pixel 106g shown in the seventh embodiment. In the following, the differences from the seventh embodiment will be mainly described, and the description of the same configuration will be omitted as appropriate.

[0175] Fig. 37 is a schematic plan view of a pixel 106j in a liquid crystal display device 200a according to this embodiment. Fig. 38(A) shows a cross-sectional structure along line A17-A18 in Fig. 37, and Fig. 38(B) shows a cross-sectional structure along line B17-B18 in Fig. 37.

[0176] As shown in FIG. 37, the pixel 106j is similar to the seventh embodiment in that the pixel electrode 150 and the common electrode 152 are provided on the same insulating surface. In an IPS type pixel, the pixel electrode and the common electrode are arranged close to each other, and the electrostatic capacitance generated between these two electrodes is used as a storage capacitance. In contrast, the pixel 106j according to this embodiment has a configuration in which an electrode formed of a fourth metal layer 126d (and a fourth oxide conductive layer 124d) is provided so as to overlap with the common wiring 144, and a storage capacitance element 206 is formed within the pixel. The fourth metal layer 126d is electrically connected to the pixel electrode 150 via a fourth contact hole 156.

[0177] 38A, the connection structure between the pixel electrode 150 and the transistor 202 is the same as that in the seventh embodiment. The common wiring 144 is disposed adjacent to the scanning signal line of the adjacent pixel, and is electrically connected to the common electrode 152 via the second contact hole 146. As shown in FIG. 38(B), the storage capacitor element 206 is formed in a region where the fourth metal layer 126d (and the fourth oxide conductive layer 124d) and the common wiring 144 overlap. The storage capacitor element 206 is electrically connected to the pixel electrode 150 via the fourth contact hole 156. The fourth metal layer 126d (and the fourth oxide conductive layer 124d) can be provided on the first insulating layer 122 along the longitudinal direction of the common wiring 144. Therefore, the storage capacitor element 206 can adjust the magnitude of the electrostatic capacitance stored by adjusting the length of the fourth metal layer 126d (and the fourth oxide conductive layer 124d) along the common wiring 144. The pixel 106j can more stably keep the voltage of the pixel electrode 150 constant by providing the storage capacitor element 206.

[0178] The pixel 106j according to the present embodiment has substantially the same configuration as that according to the seventh embodiment, except that the pixel 106j is intentionally provided with the capacitive element 206. Therefore, the liquid crystal display device 200a according to the present embodiment has the same effects as those of the seventh embodiment, in addition to the effects described above.

[0179] 3-3. PVSA type liquid crystal display device As one mode of a liquid crystal display device according to one embodiment of the present invention, a liquid crystal display device having pixels of the PSVA system will be exemplified.

[0180] 3-3-1. Tenth embodiment This embodiment describes the structure of a liquid crystal display device having PSVA type pixels that can use transistors shown in any of Figures 7(A), 7(B), 8, 9, 10, and 11, and a manufacturing method for a liquid crystal display device 200b.

[0181] 3-3-1-1. Pixel configuration (1) Fig. 39 is a schematic plan view of a pixel 106k in a liquid crystal display device 200b according to this embodiment. Fig. 40(A) shows a cross-sectional structure along line A19-A20 shown in Fig. 39, and Fig. 40(B) shows a cross-sectional structure along line C19-C20 shown in Fig. 39.

[0182] As shown in Fig. 39, the pixel 106k includes a transistor 202, a first pixel electrode 158, and a second pixel electrode 160. Although not shown in Fig. 39, a counter electrode (162) is provided on the second substrate 102 on which a color filter layer and the like are provided. The first pixel electrode 158 and the second pixel electrode 160 are arranged to overlap with each other with their centers substantially aligned. The size of the second pixel electrode 160 in a plan view is smaller than the size of the first pixel electrode 158 in a plan view, so the second pixel electrode 160 is arranged inside the first pixel electrode 158.

[0183] The first pixel electrode 158 and the second pixel electrode 160 are provided with slits 161. The slits 161 have a fine structure with a width of about 3 μm and a pitch of about 6 μm. In the first pixel electrode 158 and the second pixel electrode 160, the slits 161 are provided so as to be inclined in four directions. In other words, the first pixel electrode 158 and the second pixel electrode 160 are provided with slits that radiate from the center. When a voltage is applied to the pixel electrode, the liquid crystal molecules have the property of being inclined in a direction parallel to the slits, so that four domains can be formed in the pixel 106k shown in FIG. 39.

[0184] The first pixel electrode 158 and the second pixel electrode 160 are electrically connected to the transistor 202 by a wiring 164. The first pixel electrode 158 and the second pixel electrode 160 are both electrically connected to the wiring 164 through a fifth contact hole 166. That is, the same voltage is applied to the first pixel electrode 158 and the second pixel electrode 160 through the transistor 202.

[0185] As shown in FIG. 40(A) and FIG. 40(B), the first pixel electrode 158 is connected to the first substrate 100. The first pixel electrode 158 is provided between the first insulating layer 122 and the second insulating layer 130, and the second pixel electrode 160 is provided on the second insulating layer 130. The first pixel electrode 158 and the second pixel electrode 160 are electrically connected to each other through a fifth contact hole 166 that penetrates the first insulating layer 122 and the second insulating layer 130 (and further penetrates the second oxide conductive layer 124b and the oxide semiconductor layer 128), but the portions where the slits are provided are provided in different layers.

[0186] The second pixel electrode 160 is provided along the side surface of the fifth contact hole 166, and is in contact with the first pixel electrode 158 exposed at the bottom surface. The wiring 164 is exposed at the side surface of the fifth contact hole 166, and the second pixel electrode 160 is electrically connected to the wiring 164 at the exposed portion. As a result, the first pixel electrode 158 is also electrically connected to the wiring 164.

[0187] The first pixel electrode 158 is formed of the first conductive layer 250, but a conductive pattern by the second conductive layer 252 is provided in the portion where the fifth contact hole 166 is provided. The second pixel electrode 160 is formed of the fourth conductive layer 256, but a conductive pattern by the fifth conductive layer 258 is provided in the portion where the fifth contact hole 166 is provided. The first conductive layer 250 and the fourth conductive layer 256 are transparent conductive films, and the second conductive layer 252 and the fifth conductive layer 258 are metal films. As shown in FIG. 40(A) and FIG. 40(B), by providing the second conductive layer 252 and the fifth conductive layer 258 overlapping the fifth contact hole 166, it is possible to reliably achieve electrical connection between the first pixel electrode 158 and the second pixel electrode 160 and the wiring 164, and to reduce contact resistance.

[0188] Fig. 41 shows a cross-sectional structure of pixel 106k taken along line C15-C16 shown in Fig. 39. Specifically, Fig. 41 shows a structure of pixel 106k in which a counter substrate 212 and a liquid crystal layer 222 are provided on the structure of element substrate 210 shown in Fig. 40(B).

[0189] A first pixel electrode 158 and a second pixel electrode 160 are provided on the element substrate 210 side, and a common electrode 138 is provided on the opposing substrate 212. The first pixel electrode 158 and the second pixel electrode 160 are provided to face the common electrode 138. The first pixel electrode 158 and the second pixel electrode 160 are provided to have different heights from the surface of the first substrate 100, and therefore the distances between the first pixel electrode 158 and the common electrode 138 are also different. In other words, if the distance between the first pixel electrode 158 and the common electrode 138 is d1 and the distance between the second pixel electrode 160 and the common electrode 138 is d2, then there is a relationship of d1>d2.

[0190] In the pixel 106k, a voltage based on a video signal is applied to the first pixel electrode 158 and the second pixel electrode 160, and the common electrode 138 is held at a constant voltage. Since the same voltage is applied to the first pixel electrode 158 and the second pixel electrode 160, the intensity of the electric field E1 in the pixel first region 301 generated between the first pixel electrode 158 and the common electrode 138 is different from the intensity of the electric field E2 in the pixel second region 302 generated between the second pixel electrode 160 and the common electrode 138. In this case, the electric field intensity is E2>E1 due to the relationship of the electrode spacing. As a result, in the liquid crystal layer 222, the liquid crystal molecules in the pixel second region 302 that are subjected to the electric field E2 are subjected to the electric field E2 with respect to the liquid crystal molecules in the pixel first region 301, and the orientation angle is greatly changed.

[0191] Also, the area of ​​the pixel second region 302 is smaller than that of the pixel first region 301. For example, the area ratio between the pixel first region 301 and the pixel second region 302 is 2:1. FIG. 42 is a graph showing a relationship between the applied signal voltage and the luminance characteristics when the area ratio between the pixel first region 301 and the pixel second region 302 in the pixel 106k is in the above-mentioned relationship. Since the area of ​​the pixel first region 301 is relatively large compared to the pixel second region 302, the applied signal voltage is high and the luminance is high in a saturated state in which the liquid crystal molecules are aligned. On the other hand, in the pixel second region 302, the electric field strength generated by the applied signal voltage is high, so that the luminance increases even from a low applied signal voltage.

[0192] In this way, by providing two pixel electrodes (the first pixel electrode 158 and the second pixel electrode 160) with different intervals from the common electrode 138, the dynamic range can be expanded as the image quality of the liquid crystal display device 200b. Moreover, by providing the first pixel electrode 158 and the second pixel electrode 160 with slits inclined in four directions, the pixel 106k can form at least eight domains in the liquid crystal layer 222. By providing such a pixel 106k, the liquid crystal display device 200b according to this embodiment can widen the viewing angle. Moreover, in the pixel of the liquid crystal display device 200b, the portion where the pixel electrode overlaps with the contact hole needs to be shielded from light because it causes the alignment of the liquid crystal to be disturbed. By providing one contact hole connecting two pixel electrodes as shown in this embodiment, the decrease in the aperture ratio can be suppressed.

[0193] In this embodiment as well, the same wiring structure and sealing structure as in the first embodiment can be formed, and the manufacturing process of the liquid crystal display device 200b can be simplified and the reliability can be improved.

[0194] 3-3-1-2. Manufacturing method A manufacturing process of the liquid crystal display device 200b according to this embodiment will be described in detail with reference to the drawings. As described below, the liquid crystal display device 200b according to this embodiment can be manufactured using five photomasks.

[0195] 43(A) and 43(B) show a step of forming a first gate electrode 120 and a first pixel electrode 158 on a first substrate 100. Although not shown, at this stage, a scanning signal line is also formed simultaneously with the first gate electrode 120.

[0196] On the first substrate 100, the first conductive layer 250 and the second conductive layer 252 are formed in the same manner as in the first embodiment. Next, in a state in which the first conductive layer 250 and the second conductive layer 252 are formed on substantially the entire surface of the first substrate 100, a first resist mask 551 is formed on the second conductive layer 252. The first resist mask 551 is formed by a first photomask 501. The first photomask 501 is a halftone mask in which a first mask pattern 511 including a pattern of the first gate electrode 120, the first pixel electrode 158, and a scanning signal line (116) (not shown) is formed. The first photomask 501 includes a light-shielding portion 524 and a semi-transmitting portion 522 that reduces the amount of transmitted light in a transmitting portion 520 of the first mask pattern 511 that forms the first pixel electrode 158. FIG. 43(A) shows a case in which a positive photoresist is used, and shows an aspect in which the first mask pattern 511 forms a light-shielding portion. On the other hand, FIG. 43(B) shows a cross-sectional view near the center of the pixel 106j, illustrating the region where the first pixel electrode 158 is formed.

[0197] 43(A) indicates that the first resist mask 551 is formed by the first photomask 501. The first conductive layer 250 and the second conductive layer 252 are etched using the first resist mask 551 to form the first gate electrode 120, the first pixel electrode 158, the scanning signal line (116) (not shown), and the like. By using a halftone mask as the first photomask 501, the first pixel electrode 158 can be formed into a shape having a portion where the slit 161 formed by the first conductive layer 250 is formed and a portion where the second conductive layer 252 remains in the approximate center.

[0198] Figures 44(A) and 44(B) show the stage in which a first insulating layer 122, an oxide conductive layer 124, and a third conductive layer 254 are formed on a first substrate 100 on which a first gate electrode 120, a first pixel electrode 158, and a scanning signal line (116) (not shown) are formed, and a second resist mask 452 is formed thereon.

[0199] The first insulating layer 122, the oxide conductive layer 124, and the third conductive layer 254 are formed in the same manner as in the first embodiment. A second resist mask 552 is formed on the upper surface of the third conductive layer 254. The second resist mask 552 is formed using a second photomask 502. The second photomask 502 has a second mask pattern 512 including a light-shielding portion 524 and a semi-transmitting portion 522 that reduces the amount of transmitted light in a transmitting portion 520. Unlike a binary mask (a photomask formed by a transmitting portion and a light-shielding portion), the second photomask 502 is a half-tone mask having a light-shielding portion 424 for forming the data signal lines 118a and 118b, and a semi-transmitting portion 422 for forming the first oxide conductive layer 124a and the second oxide conductive layer 124b. The second resist mask 552 is formed by exposing a photoresist film using the second photomask 502. It should be noted that the circled number "2" shown in FIGS. 44(A) and 44(B) indicates that the second resist mask 552 is formed of the second photomask 502.

[0200] As shown in Figures 44(A) and 44(B), the second resist mask 452 has a pattern corresponding to the first oxide conductive layer 124a and the second oxide conductive layer 124b, and a pattern corresponding to the data signal line 118a is included in a thickened state on top of this pattern.

[0201] With the second resist mask 452 formed, the third conductive layer 254 and the oxide conductive layer 124 are etched in the same manner as in the first embodiment. By this etching, the data signal lines 118a and 118b and the wiring 164 are formed.

[0202] 45(A) and 45(B) show a stage in which an oxide semiconductor layer 128 is formed on the upper layer side of the first oxide conductive layer 124a, the second oxide conductive layer 124b, the data signal lines 118a and 118b, and the wiring 164, and a third resist mask 553 is formed on the oxide semiconductor layer 128. The oxide semiconductor layer 128 is formed in the same manner as in the first embodiment. Similarly, a third photomask 503 having a third mask pattern 513 is used to form the third resist mask 553. Note that the circled number "3" shown in FIG. 45(A) and FIG. 45(B) indicates that the third resist mask 553 is formed by the third photomask 503. By etching the oxide semiconductor layer 128 using the third resist mask 553, a pattern corresponding to the arrangement of the transistors, pixel electrodes, and data signal lines is formed.

[0203] 46(A) and 46(B) show a step in which a second insulating layer 130 is formed on the upper side of the oxide semiconductor layer 128, and a fourth resist mask 554 for forming contact holes is formed.

[0204] The second insulating layer 130 is formed in the same manner as in the first embodiment. The fourth resist mask 554 is formed on the second insulating layer 130 by the fourth photomask 504. The fourth photomask 504 is a binary mask in which a fourth mask pattern 514 corresponding to the first contact hole (134) and the fifth contact hole 166 (not shown) is formed. FIG. 46(A) and FIG. 46(B) show a form in which the fourth mask pattern 514 is formed in a light-shielding portion, assuming that a positive photoresist is used. The circled number "4" shown in FIG. 46(A) indicates that the fourth resist mask 554 is formed by the fourth photomask 504. The second insulating layer 130, the oxide semiconductor layer 128, the second oxide conductive layer 124b, and the first insulating layer 122 are etched using the fourth resist mask 554, thereby forming the sixth contact hole 168. It is preferable that the sixth contact hole 168 is formed by taper etching so that the second oxide conductive layer 124b is exposed on the inner wall surface.

[0205] In FIG. 47(A) and FIG. 47(B), after the fifth contact hole 166 is formed, the fourth conductive layer 256 and the fifth conductive layer 258 are formed, and a fifth resist mask 555 is formed thereon. This shows the stages at which

[0206] The fourth conductive layer 256 and the fifth conductive layer 258 are formed in the same manner as in the first embodiment. The fifth resist mask 555 is formed using the fifth photomask 505. The fifth photomask 505 is a halftone mask in which a fifth mask pattern 515 including a light-shielding portion 524 and a semi-transmitting portion 522 that reduces the amount of transmitted light and transmits light is formed in a transmitting portion 520. By using the fifth photomask 505, a fifth resist mask 555 is formed in which a portion corresponding to the pattern of the second gate electrode 132 and the second pixel electrode 160 is thickened. Note that the circled number "5" shown in Figures 47(A) and 47(B) indicates that the fifth resist mask 555 is formed using the fifth photomask 505.

[0207] As shown in FIG. 47(A) and FIG. 47(B), the fifth resist mask 555 corresponds to the second gate electrode 132 and the second pixel electrode 160, and has a shape in which the portion where the fifth conductive layer 258 is to be left is thickened. With the fifth resist mask 555 formed, the fifth conductive layer 258 and the fourth conductive layer 256 are etched in the same manner as in the first embodiment. This etching forms the second gate electrode 132 and the second pixel electrode 160. The second pixel electrode 160 is connected to the wiring 164 at the portion of the fifth contact hole 166, and is also connected to the first pixel electrode 158. Although not shown, the second gate electrode 132 is connected to the first gate electrode 120 through the first contact hole (134).

[0208] By using a half-tone mask in this process, the second pixel electrode 160 can be formed into a shape having a portion where a slit 161 formed by the fourth conductive layer 256 is formed, and a portion where the fifth conductive layer 258 remains in the area overlapping with the fifth contact hole 166.

[0209] Through the above-mentioned steps, the element substrate 210 of the liquid crystal display device 200b having the structure shown in Figures 40(A) and 40(B) can be manufactured using five photomasks. By using a half-tone mask in this manufacturing process, the first pixel electrode 158 and the second pixel electrode 160 can be manufactured using one photomask each, thereby reducing the number of photomasks.

[0210] 3-3-2. Eleventh embodiment This embodiment shows a pixel structure in a PSVA type liquid crystal display device 200b that is different from that of the tenth embodiment. The following description will focus on the differences from the tenth embodiment.

[0211] Fig. 48 is a schematic plan view of a pixel 106m in a liquid crystal display device 200b according to this embodiment. Also, Fig. 40 shows a cross-sectional structure taken along line C21-C22 in Fig. 39.

[0212] In FIG. 48, the second pixel electrode 160 is electrically connected to the wiring 164 extending from the transistor 202 through the sixth contact hole 168. Meanwhile, the first pixel electrode 158 is electrically connected to the second pixel electrode 160 through the seventh contact holes 170a and 170b. The sixth contact hole 168 is provided in the approximate center of the pixel 106m, whereas the seventh contact holes 170a and 170b are provided in the outer (peripheral) region of the sixth contact hole 168. FIG. 48 shows an embodiment in which the seventh contact holes 170a and 170b are provided at two locations outside the sixth contact hole 168. However, this embodiment is merely an example, and the contact hole connecting the first pixel electrode 158 and the second pixel electrode 160 may be provided at at least one location, or may be provided at two or more locations. For example, the contact hole corresponding to the seventh contact hole may be provided at four locations surrounding the sixth contact hole 168.

[0213] As shown in FIG. 49, the second pixel electrode 160 is electrically connected to the wiring 164 through the sixth contact hole 168. The second pixel electrode 160 is also electrically connected to the first pixel electrode 158 through the seventh contact holes 170a and 170b. The first pixel electrode 158 is provided with a metal layer formed of the second conductive layer 252 in an area overlapping with the sixth contact holes 168a and 168b, and the second pixel electrode 160 comes into contact with this portion, thereby ensuring a reliable electrical connection. The first pixel electrode 158 is electrically connected to the wiring 164 through the second pixel electrode 160.

[0214] According to the connection structure between the pixel electrode and the wiring in this embodiment, by providing two types of contact holes, the sixth contact hole 168 and the seventh contact holes 170a and 170b, the depth of each contact hole can be made shallow. For example, in the configuration according to the tenth embodiment, the sixth contact hole 168 penetrates the second insulating layer 130, the oxide semiconductor layer 128, the second oxide conductive layer 124b, and the first insulating layer 122. In contrast, in this embodiment, the sixth contact hole 168 penetrates the second insulating layer 130 and the oxide semiconductor layer 128, and the seventh contact holes 170a and 170b only penetrate the first insulating layer 122 and the second insulating layer 130. In this way, in the pixel 106m, since the contact hole connecting the pixel electrode and the wiring is shallow, disconnection at the contact hole portion can be prevented.

[0215] The pixel 106m has the same configuration as the tenth embodiment, and exerts the same effects as those of the tenth embodiment, except for the shape of the contact holes that electrically connect the first pixel electrode 158 and the second pixel electrode 160 to the wiring.

[0216] 3-3-3. Twelfth embodiment This embodiment shows a pixel structure in a PSVA type liquid crystal display device 200b that is different from that of the tenth embodiment. The following description will focus on the differences from the tenth embodiment.

[0217] Fig. 50 is a schematic plan view of a pixel 106n in a liquid crystal display device 200b according to this embodiment. Fig. 51(A) shows a cross-sectional structure along line A19-A20 shown in Fig. 50, and Fig. 51(B) shows a cross-sectional structure along line C19-C20 shown in Fig. 50.

[0218] 50, the pixel 106n has a structure in which the first pixel electrode 158 and the second pixel electrode 160 are electrically connected to a wiring 164 extending from the transistor 202 through an eighth contact hole 172 and a ninth contact hole 174. The eighth contact hole 172 and the ninth contact hole 174 are provided in the approximate center of the pixel 106n so as to overlap each other.

[0219] As shown in FIG. 51(A) and FIG. 51(B), the eighth contact hole 172 penetrates the first insulating layer 122, and the ninth contact hole 174 penetrates the second insulating layer 130 and the oxide semiconductor layer 128. On the first insulating layer 122, a wiring 164 (second oxide conductive layer 124b) extending from the transistor 202 is provided, and is electrically connected to the first pixel electrode 158 at the site of the eighth contact hole 172. In the first pixel electrode 158, a metal layer formed of the second conductive layer 252 is provided in a region overlapping with the eighth contact hole 172, and the wiring 164 is provided so as to be in contact with this metal layer. In addition, a metal layer 126c is provided on the wiring 164 (second oxide conductive layer 124b) so as to overlap with the eighth contact hole 172. With such a structure, the electrical connection between the first pixel electrode 158 and the wiring 164 can be reliably achieved.

[0220] The second pixel electrode 160 is electrically connected to the wiring 164 by the ninth contact hole 174. The ninth contact hole 174 is provided at a position overlapping the wiring 164. In this configuration, the ninth contact hole 174 is preferably provided at a position overlapping the metal layer 126c. When forming the ninth contact hole 174, the metal layer 126c functions as an etching stopper, making it easy to control the depth of the contact hole. In addition, the upper surface of the metal layer 126c is exposed by the ninth contact hole 174, so that a good electrical connection can be formed with the fourth conductive layer 256 forming the second pixel electrode 160. In this way, in the structure in which the first pixel electrode 158 and the second pixel electrode 160 are connected to the wiring 164, the depth of each contact hole can be made shallow by providing two contact holes overlapping each other, and the electrical connection can be reliably achieved. In the pixel of the liquid crystal display device 200b, the portion where the pixel electrode overlaps the contact hole needs to be shielded from light because it causes the alignment of the liquid crystal to be disturbed. As shown in this embodiment, by providing contact holes connecting two pixel electrodes so as to overlap each other, it is possible to suppress a decrease in the aperture ratio.

[0221] The pixel 106n has the same configuration as the tenth embodiment, except for the shape of the contact holes that electrically connect the first pixel electrode 158 and the second pixel electrode 160 to the wiring, and provides the same effects as those of the tenth embodiment. [Explanation of symbols]

[0222] REFERENCE SIGNS LIST 100 first substrate, 101 FPC substrate, 102 second substrate, 104 display section, 106 pixels, 108 scanning signal line drive circuit, 109 common signal line drive circuit, 110 data signal line drive circuit, 111 driver IC, 112 input terminal section, 114 terminal electrode, 115 output signal line, 116 scanning signal line, 117 common signal line, 118 data signal line, 120 first gate electrode, 122 first insulating layer, 124 Oxide conductive layer, 126...metal layer, 127...low resistance region, 128...oxide semiconductor layer, 129...region, 130...second insulating layer, 132...second gate electrode, 134...first contact hole, 136...pixel electrode, 137...second slit, 138...common electrode, 139...first slit, 144...common wiring, 146...second contact hole, 148...third contact hole, 150...pixel electrode, 152...common electrode, 154...gap, 156...fourth contact hole, 158...first pixel electrode, 160...second pixel electrode, 161...slit, 162...opposite electrode, 164...wiring, 166...fifth contact hole, 168...sixth contact hole, 170...seventh contact hole, 172...eighth contact hole, 174...ninth contact hole, 178...light-shielding layer, 180...color filter a filter layer, 182...overcoat layer, 184...third insulating layer, 200...liquid crystal display device, 202...transistor, 203...transistor, 204...liquid crystal element, 206...storage capacitance element, 208...transistor, 209...demultiplexer, 210...element substrate, 212...opposite substrate, 220...alignment film, 222...liquid crystal layer, 224...light-shielding layer, 226... Color filter layer, 228...overcoat layer, 230...wiring, 232...opening, 234...metal oxide conductive layer, 236...sealing material, 250...first conductive layer, 252...second conductive layer, 254...third conductive layer, 256...fourth conductive layer, 258...fifth conductive layer, 301...pixel first region, 302...pixel second region, 401...first photomask, 402...second photo 403...third photomask, 404...fourth photomask, 405...fifth photomask, 411...first mask pattern, 412...second mask pattern, 413...third mask pattern, 414...fourth mask pattern, 415...fifth mask pattern, 420...transmitting portion, 422...semi-transmitting portion, 424...light-shielding portion, 451...first resist mask, 452 ···second resist mask, 453···third resist mask, 454···fourth resist mask, 455···fifth resist mask, 501···first photomask, 502···second photomask, 503···third photomask, 504···fourth photomask, 505···fifth photomask, 511···first mask pattern, 512···second mask pattern, 513···third mask pattern, 514···fourth mask pattern, 515···fifth mask pattern, 520···transmitting portion, 522···semi-transmitting portion, 524···light-shielding portion, 551···first resist mask, 552···second resist mask, 553···third resist mask, 554···fourth resist mask, 555···fifth resist mask

Claims

1. A first gate electrode; a second gate electrode overlapping the first gate electrode; a semiconductor layer between the first gate electrode and the second gate electrode; a first insulating layer between the first gate electrode and the semiconductor layer; a second insulating layer between the semiconductor layer and the second gate electrode; The first insulating layer and the semiconductor a conductive layer disposed between the layer and the The semiconductor layer is a channel region overlapping the second gate electrode; at least one low resistance region adjacent to the channel region and in contact with the conductive layer; 、 the low resistance region contacts and covers the periphery of the top and side surfaces of the conductive layer; The low resistance region includes a region where the second gate electrode and the semiconductor layer overlap, and a region where the conductive an offset region between the overlapping region of the semiconductor layer and the The length of the second gate electrode in the channel length direction is equal to the length of the first gate electrode in the channel length direction. is greater than the length of The end of the at least one low resistance region on the channel region side is the second gate electrode. overlaps with the edge of The end of the at least one low resistance region on the channel region side is the first gate electrode Outside the edge of A thin film transistor comprising:

2. The width of the offset region is 0.5 μm to 2.0 μm. The thin film transistor of claim 1 .

3. the first gate electrode and the second gate electrode are electrically connected to each other; The thin film transistor of claim 1 .

4. The semiconductor layer is an oxide semiconductor layer. The thin film transistor of claim 1 .

5. The conductive layer includes an oxide conductive layer on the first insulating layer side and a metal layer on the oxide semiconductor layer side. The low resistance region is exposed from the top and side surfaces of the metal layer and from the metal layer. contacting and covering the top and side surfaces of the oxide conductive layer; The thin film transistor according to claim 4 .

6. The oxide semiconductor layer has a first region on the first insulating layer side and a second region on the second insulating layer side. and The first region and the second region have different crystallinity. The thin film transistor according to claim 4 .

7. The first region is amorphous and the second region is crystalline. The thin film transistor of claim 6.

8. The second region has a thickness smaller than that of the first region. The thin film transistor of claim 6.

9. In the channel region, the carrier concentration of the second region is Lower than The thin film transistor of claim 6.

10. The band gap of the second region is wider than the band gap of the first region. The thin film transistor of claim 6.

11. The band gap of the first region is in the range of 2.8 eV to 3.9 eV, The band gap between the two regions is 4.0 eV or more. The thin film transistor of claim 10.

12. The bottom energy level of the conduction band of the second region is lower than the bottom energy level of the conduction band of the first region. Higher than ghee level, The thin film transistor of claim 11.

13. The bottom energy level of the conduction band of the second region is lower than the bottom energy level of the conduction band of the first region. The thin film transistor of claim 12, wherein the gate voltage is at least 0.3 eV higher than the gate voltage level.

14. The first region is In ２ O ３ -Ga ２ O ３ -SnO ２ -ZnO-based oxide material, In ２ O ３ -Ga ２ O ３ -SnO ２ In-based oxide materials, or In ２ O ３ -Ga ２ O ３ -ZnO-based oxide It is made of material, The second region is Ga ２ O ３ based oxide material, GaSnOx based oxide material, or GaSi O ｘ formed of a SiO2-based oxide material, The thin film transistor of claim 6.

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