Modified stack for 3D NAND

Abstract

An exemplary method for forming a semiconductor structure may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The method may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration of about 5 atomic % or greater. The method may also include repeating the formation of a silicon oxide layer and a silicon nitride layer to produce a stack of alternating silicon oxide and silicon nitride layers.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Application No. 62 / 884,034, filed August 7, 2019, the entire contents of which are incorporated herein by reference for all purposes.

[0002] TECHNICAL FIELD The present technology relates to semiconductor processes and materials, and more particularly to forming film stacks of alternating layers. [Background technology]

[0003] Integrated circuits are made possible by processes that fabricate intricately patterned layers of material on a substrate surface. Fabricating patterned materials on a substrate requires controlled methods of formation and removal of exposed material. Stacked memories, such as vertical or 3D NAND, can include the formation of a series of alternating layers of dielectric material that can etch multiple memory holes or apertures. The material properties of the layers of material, as well as the process conditions and materials for etching, can affect the uniformity of the formed structures. Material defects can result in inconsistent patterning that can further affect the uniformity of the formed structures.

[0004] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0005] An exemplary method for forming a semiconductor structure may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The method may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration of about 5 atomic % or more. The method may also include repeating forming a silicon oxide layer and forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

[0006] In some embodiments, the oxygen-containing precursor in forming the silicon oxide layer and the oxygen-containing precursor in forming the silicon nitride layer can be the same or similar precursor. The stack of alternating layers can include a first portion of the stack including a silicon oxide layer and a silicon nitride layer, and a second portion of the stack overlying the first portion of the stack. Producing the second portion of the stack can include forming the silicon nitride layer from a silicon-containing precursor and a nitrogen-containing precursor and an oxygen-containing precursor. The silicon nitride layer can be characterized by an oxygen concentration that is different from the oxygen concentration of the silicon nitride layer in the first portion of the stack. The oxygen concentration of the silicon nitride layer can be between about 10 atomic % and about 30 atomic %, and the atomic percentage of nitrogen can be about 30 atomic % or more.

[0007] Forming the silicon nitride layer may include flowing a silicon-containing precursor and a nitrogen-containing precursor into the substrate processing region. Forming the silicon nitride layer may include forming a quantity of silicon nitride. Forming the silicon nitride layer may include adding an oxygen-containing precursor while continuing to form silicon nitride. The oxygen-containing precursor may be flowed at a constant flow rate, and the formed silicon nitride layer may be or include a bilayer of silicon nitride substantially free of oxygen and silicon nitride characterized by an oxygen concentration of about 5 atomic % or more. The oxygen-containing precursor may be flowed at a variable flow rate, and the formed silicon nitride layer may include a gradient of oxygen concentration through the silicon nitride layer. The flow rate of the oxygen-containing precursor may be increased during the addition of the oxygen-containing precursor. The method may include forming one or more features through a stack of alternating layers of silicon oxide and silicon nitride. The lateral removal of the silicon nitride layer at the interface of the silicon nitride layer and the overlying silicon oxide layer may extend a distance of about 50% or less of a distance corresponding to a thickness of the silicon nitride layer.

[0008] Some embodiments of the present technology may include a semiconductor structure. The structure may include a stack of layers overlying a semiconductor substrate. The stack of layers may include a first portion of layers including alternating layers of silicon oxide and silicon nitride materials. The stack of layers may include a second portion of layers overlying the first portion of layers, the second portion of layers including alternating layers of silicon oxide and silicon nitride materials. The stack of layers may include a third portion of layers overlying the second portion of layers, the third portion of layers including alternating layers of silicon oxide and silicon nitride materials. The structure may include one or more apertures formed in the substrate through the stack of layers. A lateral notch in the individual layer of silicon nitride material at the interface of the individual layer of silicon nitride material with an overlying layer of silicon oxide material may extend a distance of about 100% or less of a distance corresponding to a thickness of the individual layer of silicon nitride material.

[0009] In some embodiments, the silicon nitride material of at least one of the first portion of the layer, the second portion of the layer, or the third portion of the layer may include an oxygen concentration of at least about 5 atomic percent. The oxygen concentration through the silicon nitride material of at least one of the first portion of the layer, the second portion of the layer, or the third portion of the layer may increase through the thickness of each layer of silicon nitride material in a direction toward the interface between the respective layer of silicon nitride material and the overlying silicon oxide material layer. The refractive index of the silicon nitride material of at least one of the first portion of the layer, the second portion of the layer, or the third portion of the layer may be higher than the refractive index of the other two portions of the layer. The refractive index of the silicon nitride of the second portion of the layer may be higher than the refractive index of the silicon nitride of the first portion of the layer and the silicon nitride of the third portion of the layer. The silicon nitride of the first portion of the layer may be characterized by a dopant concentration that is greater than the silicon nitride of the second portion of the layer and the third portion of the layer. The silicon nitride in the second portion of the layer or the silicon nitride in the third portion of the layer may be characterized by a greater carbon concentration than the silicon nitride in the first portion of the layer. The silicon nitride in the first portion of the layer or the silicon nitride in the second portion of the layer may be characterized by a greater nitrogen to silicon ratio than the silicon nitride in the third portion of the layer.

[0010] Some embodiments of the present technology may include a method of forming a semiconductor structure. The method may include forming a first stack of alternating layers of silicon oxide and silicon nitride materials. The method may include annealing the first stack of alternating layers of silicon oxide and silicon nitride materials. The annealing may reduce a hydrogen concentration in the silicon nitride material. The method may include forming a second stack of alternating layers of silicon oxide and silicon nitride materials. The silicon nitride material may be characterized by an oxygen concentration of about 5 atomic % or greater.

[0011] Such techniques can provide many advantages over conventional systems and techniques. For example, processes and structures can be protected from defect formation during etching operations. Additionally, operation of embodiments of the present techniques can improve memory hole formation through stacks. These and other embodiments, along with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique; [Figures 2A-2D] 1 is a schematic cross-sectional view of a substrate material in accordance with some embodiments of the present technique; [Diagram 3] 1 illustrates selected operations of a forming method according to some embodiments of the present technique. [Figure 4A-4B] 1A-1D are schematic cross-sectional views of substrate material performing selected operations in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Some figures are included as schematics. It should be understood that the drawings are for illustrative purposes and should not be taken to scale unless specifically stated to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include unnecessary or exaggerated material for illustrative purposes.

[0015] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same kind may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.

[0016] As 3D NAND structures grow with the number of cells formed, the aspect ratio of memory holes and other structures increases, sometimes dramatically. During 3D NAND processing, a stack of placeholder layers and dielectric materials may form an inter-electrode dielectric or poly-dielectric ("IPD") layer. These placeholder layers may have various operations performed to place structures before the material is completely removed and replaced with metal. IPD layers are often formed over a conductor layer, such as polysilicon. When memory holes are formed, openings may extend through all of the alternating layers of material before accessing the polysilicon or other material substrate. Subsequent processing may form step-like structures for contacts and may also laterally excavate the placeholder material.

[0017] A reactive ion etching ("RIE") operation can be performed to create high aspect ratio memory holes. RIE processes often include a combination of chemical and physical removal of alternating layers, which can form a carbon polymer layer on the sidewalls during etching to protect the layers from further etching. As one non-limiting example, where the alternating layers can include silicon oxide and silicon nitride, the silicon oxide may be removed more by physical bombardment of the layers during RIE, and the silicon nitride may be removed more by chemical reaction of the RIE precursor with the nitride material.

[0018] Prior art techniques can struggle with uniformity and control during memory hole formation due to material differences between the two layer types, as well as RIE processes and materials. The present technique overcomes these issues by tailoring material properties prior to the RIE process, which can accommodate or limit one or more challenges that may otherwise occur. While the remaining disclosure routinely identifies specific materials and semiconductor structures that utilize the disclosed technology, it will be readily understood that the systems, methods, and materials are equally applicable to many other structures that can benefit from aspects of the present technology. Thus, the technique should not be considered limited to use with only 3D NAND processes or materials. Furthermore, while an exemplary chamber is described to provide a foundation for the present technology, it should be understood that the present technology can be applied to any semiconductor processing chamber that can enable the described operations.

[0019] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber system 100 according to some embodiments of the present technique. The chamber 100 can be utilized to form a film layer according to some embodiments of the present technique, but it should be understood that the method can be similarly implemented in any chamber capable of performing film formation. The processing chamber 100 can include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. The substrate 103 can be provided to the processing volume 120 through an opening 126 that can be conventionally sealed for processing using a slit valve or door. The substrate 103 can be seated on a surface 105 of the substrate support during processing. The substrate support 104 can be rotatable along an axis 147, as indicated by arrow 145, along which a shaft 144 of the substrate support 104 can be located. Alternatively, the substrate support 104 can be elevated to rotate as needed during the deposition process.

[0020] The plasma profile modulator 111 may be disposed in the process chamber 100 to control the plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the process chamber 100 surrounding the process volume 120 or may be discontinuous at selected locations as required. The first electrode 108 may also be a porous electrode, such as a porous ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor.

[0021] One or more isolators 110a, 110b, which may be a dielectric material such as a ceramic or metal oxide, e.g., aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing process precursors into the process volume 120. The gas distributor 112 may be coupled to a first power source 142, e.g., an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to a process chamber. In some embodiments, the first power source 142 may be an RF power source.

[0022] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered by, for example, a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be coupled to ground in some embodiments.

[0023] The first electrode 108 can be coupled to a first tuned circuit 128 that can control the ground path of the process chamber 100. The first tuned circuit 128 can include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 can be or include a variable capacitor or other circuit element. The first tuned circuit 128 can be or include one or more inductors 132. The first tuned circuit 128 can be any circuit that allows for a variable or controllable impedance under the plasma conditions present in the process volume 120 during processing. In some illustrated embodiments, the first tuned circuit 128 can include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg can include a first inductor 132A. The second circuit leg can include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage sensor or a current sensor and may be coupled to the first electronic controller 134 to provide some degree of closed loop control of the plasma conditions within the process volume 120.

[0024] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded in the substrate support 104 or may be coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 by a conduit 146 (e.g., a cable having a selected resistance, e.g., 50 ohms, disposed in the shaft 144 of the substrate support 104). The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma conditions in the process volume 120.

[0025] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF power, or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0026] The lid assembly 106 and substrate support 104 of FIG. 1 can be used with any processing chamber for plasma or thermal processing. During operation, the processing chamber 100 can provide real-time control of plasma conditions within the processing volume 120. The substrate 103 can be placed on the substrate support 104, and processing gases can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gases can exit the processing chamber 100 through the outlet 152. Power can be coupled with the gas distributor 112 to establish a plasma within the processing volume 120. The substrate can be subjected to an electrical bias using the third electrode 124 in some embodiments.

[0027] Upon energizing the plasma in the process volume 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. Electronic controllers 134, 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be provided to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and independent control of the center-to-edge plasma density uniformity. In an embodiment where both electronic controllers may be variable capacitors, the electronic sensor may adjust the variable capacitors to maximize the deposition rate and independently minimize the thickness non-uniformity.

[0028] Each of the tuning circuits 128, 136 may have a variable impedance that can be adjusted using the respective electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the capacitance range of each variable capacitor and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide a certain impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with a minimum aerial or lateral coverage on the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma increases to a maximum, and the entire working area of ​​the substrate support 104 may be effectively covered. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and the aerial coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect of increasing or decreasing the aerial coverage of the plasma over the substrate support as the capacitance of the second electronic controller 140 may change.

[0029] The electronic sensors 130, 138 can be used to adjust the respective circuits 128, 136 of the closed loop. Depending on the type of sensor used, a current or voltage set point can be installed in each sensor, which may be equipped with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the plasma shape can be selected and dynamically controlled during processing. Although the above discussion is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic component having adjustable characteristics can be used to provide an adjustable impedance to the tuning circuits 128 and 136.

[0030] As previously mentioned, reactive ion etching ("RIE") processes can produce many structural effects through a stack of semiconductor materials that can produce defective devices if not controlled. Figures 2A-2D show some structural problems that can occur during the formation of memory holes. For example, Figure 2A can show an etching effect known as notching, which can cause graded defects in the silicon nitride layer. This figure includes a structure 200 having a stack 205 that can include multiple portions 210 of alternating layers of materials formed on a substrate 215. Although three portions 210a, 210b, 210c are shown, it is understood that the stack 205 can include any number of portions in embodiments encompassed by the present technology. Each portion 210 can show four layers of alternating silicon oxide material 212 and silicon nitride material 214. Although four layers are shown, it is understood that each portion can include any number of layers, as well as the overall stack. Additionally, although silicon nitride is shown in a particular orientation as the bottom layer, it should be understood that the layers may be in the reverse order, beginning with a silicon oxide layer.

[0031] As described above, etching of silicon oxide materials during the RIE process may occur to a large extent due to ion bombardment, while etching of silicon nitride materials may occur to a large extent due to chemical reactions between the RIE precursors and the nitride materials. Thus, etching of silicon oxide may be controlled by controlling the RIE beam, and oxides located laterally (which may include radially in embodiments) outside the RIE beam may not be etched. However, nitride materials may be etched based on contact and chemical reaction of the precursors or RIE beam with the effluent. Silicon nitride may also be etched more slowly than silicon oxide in some embodiments. Because of hydrogen or other materials associated with silicon nitride, interaction with the RIE effluent, which may include carbon, may generate an amount of polymeric material, which may passivate or protect the sidewalls of the memory holes, limiting lateral etching.

[0032] However, at the interface between the oxide material and the underlying silicon nitride material, the amount of polymerization may be minimized. Additionally, the etch rate of silicon nitride may differ from that of silicon oxide, which may result in exposure or increased residence time of wastewater at the nitride layer. The wastewater may react with the exposed nitride before forming a protective polymeric material, such as at the transition between the oxide and nitride layers, increasing the lateral etching of the material. As polymer buildup occurs, this lateral etching may taper and a notch 220 may form around the leading edge of the silicon nitride material in the direction of the etch. This notching may impede or affect the formation of subsequent layers or materials, and in some embodiments, may increase the diameter or critical dimension of the memory hole.

[0033] FIG. 2B may show examples of striations in both vertical cross section 230 and horizontal cross section 240 that may affect the control of memory hole formation. Striations may occur when a certain amount of lateral etching continues from layer to layer through the structure. For example, in a sense, each layer may act as a kind of mask for the layer below. If lateral defects form in the overlying layer, this may expose and remove portions of the underlying layer that would otherwise be preserved. These defects may continue to form, which may continue to increase the critical dimension and cause the memory hole to flare at one or more locations in the stack structure.

[0034] FIG. 2C may show an example of stress effects that may cause misalignment of memory holes through the stack. For example, this figure may show a detailed view of a single portion 250 of a stack structure prior to forming a subsequent stack structure overlying the illustrated alternating layers. The number of alternating layers shown is for illustrative purposes only and is not intended to limit the number of layers in any particular portion of the stack. Memory holes may be generated through each portion of the stack prior to forming the upper portion of the stack. This process may affect the properties of the pillars and may make them more susceptible to stress. For example, when the pillars are exposed to high temperatures in subsequent processes, a certain amount of outgassing may occur. Continuing with this example, which is not intended to limit the technology, silicon nitride may contain a certain amount of hydrogen depending on the precursors utilized, such as silane in one non-limiting example. When exposed to temperatures in excess of several hundred degrees Celsius, outgassing may occur, which may create stress within each pillar and lead to deformation of the structure as shown. If additional stacks are formed on top of the etched stack, the formation process may be performed at temperatures that cause outgassing, which may create an offset of the underlying memory holes, resulting in misalignment when the overlying memory holes are formed to connect with the underlying memory holes.

[0035] FIG. 2D may show an example of curvature 260, or an enlargement of a critical dimension, in a structure where RIE may be performed to create a memory hole. The curvature may occur anywhere throughout the structure and may be caused by a number of issues. For example, the curvature may be caused by limited passivation or polymerization at the sidewalls, which may result in a certain amount of lateral etching. The curvature may also occur due to changes in the material of the hard mask or other structural features. For example, if the edge of the hard mask 265 may be eroded during the RIE process, ions may be projected into the feature or memory hole at a direction or angle different than normal to the substrate, which may result in additional lateral etching in some areas of the structure until the taper of the hard mask is removed or etched. Thus, many issues may occur during the RIE process, which may affect the memory hole structure in many ways. The present technique may include one or more adjustments to the material properties of the layers of the stack, which may address and offset or prevent one or more of the challenges described.

[0036] The present technology can tailor material properties of one or more layers or materials in an exemplary stack, which can target one or more of the issues discussed above. After generally describing the method of forming one or more portions of a semiconductor material stack of layers, we discuss tailoring that can be combined or implemented in any variation or combination to improve memory hole formation. The chamber 100 described above can be used in performing exemplary methods, including forming methods. Turning to FIG. 3, an exemplary operation in a method 300 for forming a semiconductor structure according to an embodiment of the present technology is shown. Prior to the first operation of the method, a substrate can be processed with one or more methods and then placed in a processing region of a chamber in which the method 300 can be performed. Some or all of the operations can be performed in a chamber or system tool as described above, or can be performed in different chambers on the same system tool, which can include a chamber in which the operations of the method 300 can be performed.

[0037] Method 300 may include several optional operations that may or may not be specifically associated with some embodiments of the method according to the present technology as shown. For example, many of the operations are described to provide a broader range of structure formations, but they are not critical to the technology or may be performed by alternative methodologies discussed further below. Method 300 describes operations shown generally in Figures 4A-4B, examples of which are described in conjunction with the operations of method 300. It should be understood that Figure 4 shows only a partial schematic diagram, and that a substrate may include any number of structural sections having the aspects shown in the figures, as well as alternative structural aspects that may still benefit from the operations of the present technology.

[0038] Structure 400 may show a partial view of a stack of alternating layers of materials that may be used in some embodiments to form a 3D NAND memory. The alternating layers of materials may be fabricated by a number of methods, including plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal chemical vapor deposition, or any other formation technique. In some embodiments, plasma enhanced chemical vapor deposition may be performed in a process chamber, such as process chamber 100 described above. Although the remaining disclosure discusses a stack of alternating layers of silicon oxide and silicon nitride, embodiments of the present technology may use various combinations of materials, such as silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials. Although method 300 discusses the formation of silicon oxide followed by the formation of silicon nitride, the order of formation may be reversed in embodiments also encompassed by the present technology. Additionally, any number of layers of material may be produced in a stack, or in any portion of any stack, and different portions of the stack may include more, fewer, or a similar number of layers than any other portion of the stack, according to embodiments of the present technology.

[0039] The method 300 may include forming a silicon oxide layer on a substrate in operation 305. The formation may be performed using a silicon-containing precursor and an oxygen-containing precursor. The method may also include forming a silicon nitride layer overlying the silicon oxide layer in operation 310. The formation may be performed using a silicon-containing precursor and a nitrogen-containing precursor. These operations may be repeated any number of times until a predetermined number of layer pairs that may constitute a stack of layers can be formed. FIG. 4A shows a structure 400 including a substrate 405 having a stack 410 of alternating layers of silicon oxide and silicon nitride. The illustrated stack 410 may include several portions 415, each of which may include at least one layer of silicon oxide material 417 and at least one layer of silicon nitride material 419. Each portion may also include a plurality of layer pairs, including about 2 pairs or more, about 10 pairs or more, about 50 pairs or more, about 100 pairs or more, or more layer pairs. A particular number of pairs included in any of these described ranges should be understood as if specifically set forth herein. Although three portions 415a, 415b, and 415c are shown, more or fewer portions may be included according to some embodiments of the present technology.

[0040] In some embodiments, multiple portions, including all portions, may be formed during operations 305 and 310, but in some embodiments, portions may be generated in multiple operations. For example, as described further below, one or more optional operations may be performed during the formation of the top portion of the stack, or adjustments as described below may be made between any portions that may be shown as different portions. For example, in optional operation 315, a high temperature anneal may be performed before forming the second portion of the stack. Optional operation 315 may also include forming a first portion of the memory hole, as well as adjustments to the precursors as described below. The second portion of the stack may be formed by forming at least one layer of silicon oxide material in optional operation 320 and at least one layer of silicon nitride material in optional operation 325, which may be repeated to generate any number of pairs of layers similar to the first portion described above.

[0041] Additional optional operation 330 may include additional high temperature annealing or forming a second portion of the memory holes, as well as further conditioning on the precursor. A third portion of the stack may be formed by forming at least one layer of silicon oxide material in optional operation 335 and at least one layer of silicon nitride material in optional operation 340, which may be repeated to produce any number of layer pairs greater or less than the number of pairs in either the first portion or the second portion. Any of the silicon oxide or silicon nitride materials described below may be included in or be any of the layers in any portion of the stack in some embodiments of the present technology.

[0042] The mask material 420 can be formed over any portion of the stack prior to forming a portion of the memory hole or other feature through the structure. While structures according to the present technique can be characterized by any aspect ratio or ratio of the height to width of the structure, in some embodiments, the material can be characterized by a larger aspect ratio, which can have an increased impact on the aspect of the fabricated structure, as described above. For example, in some embodiments, the aspect ratio of an exemplary structure, such as an aperture or memory hole to its cross-sectional diameter, can be about 10:1 or more, about 20:1 or more, about 30:1 or more, about 40:1 or more, about 50:1 or more, or even greater. These high aspect ratios can prevent many conventional etching operations or can cause or exacerbate any of the problems described above.

[0043] The substrate 405 may have a substantially flat or uneven surface in embodiments. The substrate may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 405 may have a variety of dimensions, such as 200 mm or 300 mm diameter wafers, as well as rectangular or square panels. Silicon-containing precursors that can be used during the formation of silicon oxide or silicon nitride can include, but are not limited to, silane (SiH4), disilane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and any other silicon-containing precursor that can be used for silicon-containing film formation. Oxygen-containing precursors used in any operation as described throughout the present technology can include O2, N2O, NO2, O3, H2O, and any other oxygen-containing precursor that can be used for silicon oxide film formation, silicon oxynitride film formation, or other film formation. Nitrogen-containing precursors used in any operation can include N2, N2O, NO2, NH3, N2H2, and any other nitrogen-containing precursor that can be used for silicon nitride film formation. In any of the forming operations, one or more additional precursors can be included, such as inert precursors, which can include Ar, He, Xe, Kr, nitrogen, hydrogen, or other precursors.

[0044] As previously mentioned, notching can occur in the silicon nitride layer during the formation of the memory holes due to reactive species diffusing laterally throughout the structure before sufficient polymerization is formed. However, in some embodiments, the formation of the silicon nitride layer can include the incorporation of an amount of oxygen. As described above, the RIE process can result more from bombardment with oxygen, and by incorporating oxygen in controlled amounts into the nitride layer, notching can be reduced or eliminated in some embodiments. For example, while one or more silicon nitride layers are being formed in any portion of the stack, an oxygen-containing precursor can be flowed along with the nitrogen-containing precursor and / or silicon-containing precursor to produce a film incorporating an amount of oxygen. The oxygen-containing precursor can be any of the oxygen-containing precursors described above, and in some embodiments, can be the same oxygen-containing precursor used to form the silicon oxide material. Using the same precursor in some embodiments can reduce modifications made during the formation of the stack, thereby reducing queue times.

[0045] In some embodiments, one or more layers of silicon nitride material may contain about 5 atomic % or more oxygen, and may include about 10 atomic % or more oxygen, about 15 atomic % or more oxygen, about 20 atomic % or more oxygen, about 25 atomic % or more oxygen, about 30 atomic % or more oxygen, or more. The additional incorporation of oxygen may affect downstream processes, such as exposure of the silicon nitride layer, and therefore, in some embodiments, the amount of oxygen may be maintained at about 30 atomic % or less oxygen, about 25 atomic % or less oxygen, about 20 atomic % or less oxygen, or less, which may facilitate selective removal of the nitride material during subsequent operations without damaging the silicon oxide material. In some embodiments, the layer of silicon nitride material may maintain an amount of nitrogen above a threshold, such as about 20 atomic % or more, which may produce a silicon nitride material characterized by an amount of nitrogen of about 25 atomic % or more, about 30 atomic % or more, about 35 atomic % or more, about 40 atomic % or more, about 45 atomic % or more, or more.

[0046] As mentioned above, notching can occur at the leading edge of the silicon nitride material in the etching direction toward the substrate. In some embodiments, the incorporation of oxygen can be adjusted to accommodate this notching effect. For example, in some embodiments, the formation of the silicon nitride material can include the formation of a bilayer of silicon nitride and silicon oxynitride at each layer of silicon nitride. For example, a silicon-containing precursor and a nitrogen-containing precursor can be flowed to produce a quantity of silicon nitride, and then an oxygen-containing precursor can be added to the flow, which can include maintaining or adjusting the flow rate of the silicon-containing precursor and / or the nitrogen-containing precursor. Each layer of the bilayer can comprise any percentage of the bilayer between about 10% and about 90% of the thickness of the bilayer.

[0047] Whether the oxygen-containing precursor can be added initially during the formation of the silicon nitride material or at some point after the initial formation, the flow rate of the oxygen-containing precursor can be held constant, decreased, or increased during the formation of the layer. For example, a gradient of oxygen concentration can be created in the silicon nitride material, ranging from about 0 atomic % oxygen incorporation to any of the aforementioned incorporations. By starting and then adjusting the flow rate of the oxygen-containing precursor, the silicon nitride material can include a gradient incorporation. For example, the flow rate of the oxygen-containing precursor can be increased during the formation of a layer or bilayer of silicon nitride material, such that the portion of the silicon nitride material at the interface of the overlying silicon oxide material can be characterized by an increased amount of oxygen relative to the underlying portion of the silicon nitride material. Thus, in some embodiments, the notching effect can be reduced where it is most likely to occur, while maintaining more nitride incorporation throughout the film.

[0048] The amount of oxygen incorporated into one or more layers of silicon nitride material can also be tailored between different portions of the stack in some embodiments, and any layer in any portion can be characterized by any amount of oxygen incorporation as described above, or can remain substantially free of oxygen incorporation. For example, some striation effects and / or profile variations can occur in the second portion of the stack, such as portion 415b, which can be between first portion 415a and third portion 415c. Tailoring the oxygen incorporation into the silicon nitride in this portion of the stack can limit or eliminate these issues. For example, some bowing and striations can occur due to the radical effluent of the RIE process that laterally etches the silicon nitride, which can expose additional silicon oxide, increasing the amount of etching of those materials and increasing the striation effects. By limiting this effect on the nitride material, the effect on the oxide material can also be reduced, improving these issues and the uniformity of memory hole formation. Increasing the incorporation of oxygen into the nitride layer in areas where striations and / or bowing may occur can improve resistance to lateral etching and limit the problem of these effects.

[0049] Similarly, memory hole alignment issues can be improved, such as by increasing the oxygen concentration of the nitride material in the lower portion of the stack. Silicon oxide can allow for improved control of stress effects by reducing the amount of hydrogen in the film, or greater control of stress effects that may otherwise limit the aforementioned deformation. Thus, in some embodiments, the first portion of the stack can include an increased oxygen concentration in the nitride layer, which can reduce stress effects due to outgassing. An optional annealing can also be performed as described above, which can increase the temperature of the formed film, with or without an increased oxygen concentration in the nitride material, to increase outgassing prior to the formation of additional portions of the stack. Annealing can include a process of increasing the temperature of the first portion of the stack to about 500° C. or more, which can increase the temperature of the first portion of the stack to about 550° C. or more, about 600° C. or more, about 650° C. or more, about 700° C. or more, about 750° C. or more, about 800° C. or more, about 850° C. or more, about 900° C. or more, or more. For example, temperatures above about 650° C. may cause an amount of outgassing to occur to limit deformation of the structure, allowing for improved alignment between portions of the memory holes.

[0050] In some embodiments of the present technology, notching can be reduced or eliminated by including an amount of oxygen in the nitride material. FIG. 4B shows a close-up view of a portion of an underlying silicon nitride material 425 and an overlying silicon oxide material 427 in which a notch 430 can be formed. The notch can be characterized by a distance A of lateral penetration at the interface between the silicon nitride layer and the overlying silicon oxide material. The layer of silicon nitride material can also be characterized by a thickness B. In some embodiments, any particular layer of silicon nitride material can include a notch having a distance A of penetration that can be about 100% or less of the distance corresponding to the thickness B. In some embodiments, distance A may be about 75% or less of distance B, distance A may be about 50% or less of distance B, distance A may be about 40% or less of distance B, distance A may be about 30% or less of distance B, distance A may be about 20% or less of distance B, distance A may be about 10% or less of distance B, distance A may be about 5% or less of distance B, distance A may be about 1% or less of distance B, or distance A may be zero, and no notches may be formed in the layer.

[0051] Additional adjustments may be made to accommodate or adjust for the aforementioned effects, any of which may be combined together or with any of the other operations or incorporations discussed elsewhere. For example, silicon nitride materials may be characterized by a refractive index that may be adjusted by adjusting the film-forming materials or conditions. For example, in some embodiments, increasing the refractive index of the silicon nitride material may decrease the lateral etch rate or the overall dry etch rate. Thus, in some embodiments, areas where bowing or striation may occur may be modified by forming a silicon nitride layer that is characterized by a higher refractive index than other layers of material. For example, the silicon nitride material may be characterized by a refractive index between about 1.7 and about 2.3. In some embodiments, the silicon nitride material at the bottom of the structure, such as portion 415a, may be characterized by a lower refractive index than the silicon nitride material at the more distal portion of the structure from the substrate. Additionally, the silicon nitride material at the center portion of the structure, such as portion 415b, may be characterized by a higher refractive index than the silicon nitride material above and below. Thus, in one non-limiting example, a stack such as stack 410 can include a portion where the silicon nitride material of the third portion 415c can be characterized by a higher refractive index than the material of the first portion 415a, and the silicon nitride material of the second portion 415b can be characterized by a higher refractive index than the material of either the third portion 415c or the first portion 415a. Any number of other modifications to adjust the refractive index can be similarly implemented to adjust the etch characteristics of various regions of the stack.

[0052] Dopant concentrations may also be tailored in one or more layers of silicon nitride material in some embodiments of the present technology. For example, silicon nitride may be doped with materials including phosphorus, boron, oxygen, or other materials that may increase the etch rate of the silicon nitride material, which may improve etching, such as in the first portion of the stack, which may be tapered or narrow. These dopants may have an affinity for certain materials in the RIE chemistry, which may increase etching through that portion. Thus, incorporating about 0.01% to about 5% or more of these dopants may increase etching of the material. Similarly, silicon nitride may be formed with increased incorporation of carbon, which may decrease etching in some portions. Many RIE etchants may include halocarbons, such as chlorocarbons, fluorocarbons, or chloroflouorcarbons, which may decrease etching of films incorporating higher amounts of carbon compared to films with lower amounts of carbon. Thus, as one non-limiting example, one or more layers or one or more portions of the stack may include an increased carbon concentration, such as between about 1% and about 10%, to control etching. For example, in some embodiments, the layer of silicon nitride material in the second portion 415b may have an increased carbon concentration compared to the first portion 415a.

[0053] The ratio of nitrogen to silicon in a layer of silicon nitride material can also be adjusted in some embodiments to affect the etch rate. For example, increasing the ratio of nitrogen to silicon can increase the etch rate of the material, and decreasing the ratio of nitrogen to silicon can decrease the etch rate of the material. Thus, in some embodiments, one or more layers of silicon nitride material can be characterized by an increased ratio of nitrogen to silicon compared to one or more other layers, such as the first portion, and / or one or more layers of silicon nitride material can be characterized by a decreased ratio of nitrogen to silicon compared to one or more other layers, such as the second portion. The increased ratio of nitrogen to silicon can be about 1.3 or more, and can be about 1.4 or more, about 1.5 or more, about 1.6 or more, or higher. The decreased ratio of nitrogen to silicon can be about 1.3 or less, and can be about 1.2 or less, about 1.1 or less, about 1.0 or less, or lower.

[0054] In some embodiments, adjustments can also be made to the layers of silicon oxide material, which can also affect the etching rate and profile through the stack. For example, in a portion, such as the first portion, where increased etching may be promoted over other layers or portions, the silicon-containing precursor can be adjusted to increase hydrogen bonding with silicon. As one non-limiting example, the second and / or third portions of the layer of silicon oxide material can be formed using TEOS, while the first portion of the layer of silicon oxide material can be formed using, for example, silane or disilane, among other precursors with a larger amount of silicon-hydrogen bonds. For portions where reduced etching may be promoted, the opposite can be done with the precursor, and a precursor with fewer silicon-hydrogen bonds can be used for the second portion of the stack, etc. In addition, for the reasons discussed above with respect to the etchant used in the RIE process, a precursor containing additional carbon can be used, or carbon incorporation in the silicon oxide film can be increased.

[0055] Utilizing one or more of the described processes can enable improved formation of memory holes, thereby limiting effects such as notching and improving profile uniformity through the memory holes. For example, in some embodiments, layers or portions through the stack can be characterized by a diameter variation through the memory holes of the stack of about 200% or less, and can be characterized by a diameter variation through the memory holes of about 150% or less, about 100% or less, about 90% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, or less. As a result, the present techniques can result in improved manufacturing that can produce more uniform stack structures than conventional techniques.

[0056] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0057] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be interpreted as limiting the scope of the present technology. In addition, although a method or process may be described sequentially or stepwise, it should be understood that the operations may be performed simultaneously or in a different order than described.

[0058] Where a range of values ​​is presented, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value in that stated range is also encompassed. The upper and lower limits of these smaller ranges may be independently included or excluded from the range, and each range in which either, neither or both limits are included in the smaller range is also encompassed within the scope of this technology, subject to any specifically excluded limits in the stated range. When one or both limits are included in a stated range, ranges excluding either or both of those included limits are also included.

[0059] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly indicates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0060] Additionally, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and the appended claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A method of forming a semiconductor structure, comprising: forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor; forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor, the silicon nitride layer being characterized by an oxygen concentration of 5 atomic % or greater; and repeating the forming of the silicon oxide layer and the forming of the silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride. Including, forming the silicon nitride layer flowing the silicon-containing precursor and the nitrogen-containing precursor into a substrate processing region; forming a quantity of silicon nitride; and adding said oxygen-containing precursor while continuing to form silicon nitride. A method comprising:

2. 2. The method for forming a semiconductor structure of claim 1, wherein the oxygen-containing precursor in forming the silicon oxide layer and the oxygen-containing precursor in forming the silicon nitride layer are the same precursor.

3. the stack of alternating layers includes a first portion of the stack including the silicon oxide layer and the silicon nitride layer, and a second portion of the stack overlying the first portion of the stack, generating the second portion of the stack; forming a silicon nitride layer from the silicon-containing precursor and the nitrogen-containing precursor, and an oxygen-containing precursor, the silicon nitride layer being characterized by an oxygen concentration different from an oxygen concentration of the silicon nitride layer in the first portion of the stack. A method for forming the semiconductor structure of claim 1.

4. 2. The method for forming a semiconductor structure of claim 1, wherein said oxygen concentration of said silicon nitride layer is between 10 atomic % and 30 atomic %, and the atomic percentage of nitrogen is 30 atomic % or greater.

5. 2. The method for forming a semiconductor structure of claim 1, wherein the oxygen-containing precursor is flowed at a constant flow rate and the silicon nitride layer formed comprises a bilayer of substantially oxygen-free silicon nitride and silicon nitride characterized by an oxygen concentration of 5 atomic % or greater.

6. 2. The method of forming a semiconductor structure of claim 1 , wherein the oxygen-containing precursor is flowed at an increased rate during the addition of the oxygen-containing precursor, and the silicon nitride layer formed comprises a gradient of oxygen concentration through the silicon nitride layer.

7. 2. The method of forming a semiconductor structure of claim 1, further comprising forming one or more features through said stack of alternating layers of silicon oxide and silicon nitride, wherein lateral removal of said silicon nitride layer at an interface of said silicon nitride layer and an overlying silicon oxide layer extends a distance no greater than 50% of a distance corresponding to a thickness of said silicon nitride layer.

8. In a semiconductor structure, A stack of layers overlying a semiconductor substrate, comprising: a first portion of the layer comprising alternating layers of silicon oxide and silicon nitride materials; a second portion of the layer overlying the first portion of the layer, the second portion of the layer including alternating layers of silicon oxide and silicon nitride materials; and a third portion of the layer overlying the second portion of the layer, the third portion of the layer including alternating layers of silicon oxide and silicon nitride materials; A stack of layers, including one or more apertures formed in the semiconductor substrate through the stack of layers, wherein a lateral notch in each layer of silicon nitride material at an interface of the individual layer of silicon nitride material with an overlying layer of silicon oxide material extends a distance that is less than or equal to 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material. Including, 1. A semiconductor structure, wherein the silicon nitride material of at least one of the first portion of the layer, the second portion of the layer, or the third portion of the layer comprises an oxygen concentration of at least 5 atomic %, and wherein the oxygen concentration through the silicon nitride material of at least one of the first portion of the layer, the second portion of the layer, or the third portion of the layer increases through a thickness of each of the layers of silicon nitride material in a direction toward the interface between the respective layer of silicon nitride material and the overlying layer of silicon oxide material.

9. A semiconductor structure comprising: A stack of layers overlying a semiconductor substrate, comprising: a first portion of the layer comprising alternating layers of silicon oxide and silicon nitride materials; a second portion of the layer overlying the first portion of the layer, the second portion of the layer including alternating layers of silicon oxide and silicon nitride materials; and a third portion of the layer overlying the second portion of the layer, the third portion of the layer including alternating layers of silicon oxide and silicon nitride materials; A stack of layers, including one or more apertures formed in the semiconductor substrate through the stack of layers, wherein a lateral notch of an individual layer of silicon nitride material at an interface of the individual layer of silicon nitride material with an overlying layer of silicon oxide material extends a distance that is less than or equal to 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material. Including, A semiconductor structure, wherein the refractive index of the silicon nitride material in the second portion of the layer is higher than the refractive index of the silicon nitride material in the first portion of the layer and the silicon nitride material in a third portion of the layer.

10. 9. The semiconductor structure of claim 8, wherein said silicon nitride material in said first portion of said layer is characterized by a greater dopant concentration than said silicon nitride material in said second portion of said layer and said third portion of said layer.

11. A semiconductor structure comprising: A stack of layers overlying a semiconductor substrate, comprising: a first portion of the layer comprising alternating layers of silicon oxide and silicon nitride materials; a second portion of the layer overlying the first portion of the layer, the second portion of the layer including alternating layers of silicon oxide and silicon nitride materials; and a third portion of the layer overlying the second portion of the layer, the third portion of the layer including alternating layers of silicon oxide and silicon nitride materials; A stack of layers, including one or more apertures formed in the semiconductor substrate through the stack of layers, wherein a lateral notch of an individual layer of silicon nitride material at an interface of the individual layer of silicon nitride material with an overlying layer of silicon oxide material extends a distance that is less than or equal to 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material. Including, A semiconductor structure, wherein the silicon nitride material of the second portion of the layer or the silicon nitride material of the third portion of the layer is characterized by a greater carbon concentration than the silicon nitride material of the first portion of the layer.

12. A semiconductor structure comprising: A stack of layers overlying a semiconductor substrate, comprising: a first portion of the layer comprising alternating layers of silicon oxide and silicon nitride materials; a second portion of the layer overlying the first portion of the layer, the second portion of the layer including alternating layers of silicon oxide and silicon nitride materials; and a third portion of the layer overlying the second portion of the layer, the third portion of the layer including alternating layers of silicon oxide and silicon nitride materials; A stack of layers, including one or more apertures formed in the semiconductor substrate through the stack of layers, wherein a lateral notch of an individual layer of silicon nitride material at an interface of the individual layer of silicon nitride material with an overlying layer of silicon oxide material extends a distance that is less than or equal to 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material. Including, 1. A semiconductor structure comprising: a silicon nitride material in a first portion of said layer or a silicon nitride material in a second portion of said layer characterized by a greater nitrogen to silicon ratio than a silicon nitride material in a third portion of said layer.

13. 1. A method of forming a semiconductor structure, comprising: forming a first stack of alternating layers of silicon oxide and silicon nitride materials; annealing the first stack of alternating layers of the silicon oxide material and the silicon nitride material, the annealing reducing a hydrogen concentration in the silicon nitride material; and forming a second stack of alternating layers of silicon oxide and silicon nitride materials, the silicon nitride materials being characterized by an oxygen concentration of 5 atomic percent or greater; A method comprising:

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