MEMORY DEVICE AND METHODS FOR ERASING AND VERIFYING SAME - Patent application

Abstract

To provide a memory device capable of increasing channel discharge time for avoiding false error verification and a method for erasing and verifying the same.SOLUTION: A memory device includes a plurality of memory blocks and a control circuit. The memory block selected from among the plurality of memory blocks includes an upper selection gate, a lower selection gate, a plurality of word lines, a common source line, and a P well. The control circuit executes an erasure and verification method, and the erasure and verification method includes: a step of erasing the selected memory block during an erasing stage; and a step of performing maintenance in a manner such that the lower selection gate is turned on during a maintenance period before the upper selection gate is turned on during a verifying stage.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a memory device and an erasing and verifying method thereof, and more particularly to a memory device and an erasing and verifying method thereof that can increase the channel discharge time to avoid false error verification. [Background technology]

[0002] Semiconductor memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, and non-mobile computing devices. Non-volatile memory allows information to be stored and retained. Examples of non-volatile memory include flash memory (e.g., NAND and NOR flash memory) and Electrically Erasable Programmable Read-Only Memory (EEPROM).

[0003] Recently, ultra-high density storage devices have been proposed using three-dimensional (3D) stacked memory structures, sometimes referred to as Bit Cost Scalable (BiCS) architectures. For example, a 3D NAND stacked flash memory device can be formed from an array of alternating conductive and dielectric layers. Memory holes are drilled in the layers to simultaneously define multiple memory layers. NAND strings are then formed by filling the memory holes with an appropriate material. The control gates of the memory cells are provided by the conductive layers.

[0004] Each planar NAND memory consists of an array of memory cells connected by multiple word lines and bit lines. Data is programmed into or read from the planar NAND memory in pages, and erased from the planar NAND memory in blocks, i.e., a block is the unit of a conventional erase operation and a page is the unit of a conventional programming operation.

[0005] In existing three-dimensional (3D) NAND flash structures, a verify step is required after the erase step to verify whether the erase is successful. However, in 3D NAND flash, false errors may occur during the verify step. Summary of the Invention [Problem to be solved by the invention]

[0006] It is therefore an object of the present invention to provide a memory device and an erase and verify method thereof that can increase the channel discharge time to avoid false error verification. [Means for solving the problem]

[0007] The present invention discloses a memory device, which includes a plurality of memory blocks and a control circuit, in which a selected one of the plurality of memory blocks includes a top select gate, a bottom select gate, a plurality of word lines, a common source line, and a P-well. The control circuit performs an erase and verify method, which includes erasing the selected memory block during an erase phase and maintaining the bottom select gate turned on during a sustain period before the top select gate is turned on during a verify phase.

[0008] The present invention discloses an erase and verify method for a memory device, in which a selected memory block of a plurality of memory blocks of the memory device comprises an upper select gate, a lower select gate, a plurality of word lines, a common source line and a P-well, the erase and verify method includes the steps of erasing the selected memory block during an erase phase and maintaining the lower select gate turned on during a sustain period before the upper select gate is turned on during a verify phase.

[0009] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 illustrates a top view of one NAND string according to one embodiment of the present invention. [Diagram 2] FIG. 2 illustrates an equivalent circuit of one NAND string according to one embodiment of the present invention. [Diagram 3] FIG. 2 illustrates an exemplary structure of a memory device according to one embodiment of the present invention. [Figure 4] 1 is a timing diagram of a conventional erase and verify process. [Figure 5A] 4 is a timing diagram of an erase and verify process according to one embodiment of the present invention. [Figure 5B] 2A-2C are schematic diagrams of channel potentials for a conventional erase and verify process and an erase and verify process according to an embodiment of the present invention. [Figure 6A] 4 is a timing diagram of an erase and verify process according to another embodiment of the present invention. [Figure 6B] 4 is a timing diagram of an erase and verify process according to another embodiment of the present invention. [Figure 7] FIG. 2 is a schematic diagram of an erase and verify process according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following detailed description, reference is made to the accompanying drawings, which show, by way of example, specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It is to be understood that the various embodiments of the present invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the present invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the present invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined solely by the appended claims, properly interpreted along with the full scope of equivalents to which the claims are entitled. In the drawings, like numbers refer to the same or similar features across the several views.

[0012] In the following description and in the claims, the terms "including" and "comprises" are used without limitation and should therefore be interpreted to mean "including, but not limited to." Also, the term "couple" is intended to mean an indirect or direct electrical connection. Thus, when one device is electrically connected to another device, the connection may be by a direct electrical connection or by an indirect electrical connection through other devices and connections. "Approximately" means that, within an allowable error amount, a person skilled in the art can solve a technical problem within a certain error amount and essentially achieve a technical effect.

[0013] FIG. 1 is a top view of a NAND string according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit thereof. In a flash memory system using a NAND structure, multiple transistors are arranged in series and sandwiched between two select gates, which are called a NAND string. The NAND string shown in FIG. 1 and FIG. 2 includes four transistors 101-104 coupled in series and sandwiched between an upper select gate SG_T, a lower select gate SG_B (source side), and a substrate Sub, which includes a P-well. The upper select gate SG_T is arranged to connect the NAND string to a bit line via a bit line contact, and can be controlled by applying an appropriate voltage to a select gate line SGTL. The lower select gate SG_B is arranged to connect the NAND string to a common source line CSL, and can be controlled by applying an appropriate voltage to a select gate line SGBL. The common source line CSL passes through the stack structure. Each of the transistors 101-104 includes a control gate and a floating gate. For example, transistor 101 includes a control gate CG1 and a floating gate FG1, transistor 102 includes a control gate CG2 and a floating gate FG2, transistor 103 includes a control gate CG3 and a floating gate FG3, and transistor 104 includes a control gate CG4 and a floating gate FG4. The control gate CG1 is connected to a word line WL1, the control gate CG2 is connected to a word line WL2, the control gate CG3 is connected to a word line WL3, and the control gate CG4 is connected to a word line WL4.

[0014] For purposes of illustration, Figures 1 and 2 show four memory cells in a NAND string. In other embodiments, a NAND string may include eight memory cells, sixteen memory cells, thirty-two memory cells, sixty-four memory cells, one hundred and twenty-eight memory cells, etc. However, the number of memory cells in a NAND string does not limit the scope of the present invention.

[0015] A typical architecture of a flash memory system using a NAND structure includes several NAND strings. Each NAND string is connected to a common source line CSL by its lower select gate SG_B controlled by a select line SGBL, and to its associated bit line by its upper select gate SG_T controlled by a select line SGTL. Each bit line and each (one or more) NAND strings connected to the bit line through a bit line contact comprise a column of an array of memory cells. A bit line is shared with multiple NAND strings. Typically, the bit line runs through the top of the NAND string in a direction perpendicular to the word lines and is connected to one or more sense amplifiers.

[0016] 3 is a diagram illustrating an exemplary structure of a memory device 30 according to one embodiment of the present invention. The memory device 30 includes a memory array 302 and a control circuit 304. The control circuit 304 is utilized to perform read, write, erase, and verify operations on the memory array 302 and may include word line drivers, bit line drivers, column decoders, sensing circuits, data buffers, program verify logic, and erase verify circuits. The memory array 302 is divided into BLOCK1 through BLOCK2. I The memory cell is divided into a number of memory blocks of memory cells represented by I, where I is a positive integer, typically equal to a large number. The blocks are connected to bit lines BL1 to BL M , and word lines WL1 to WL N where M and N are integers greater than 1. One terminal of the NAND string is connected to a corresponding bit line through an upper select gate (connected to a select gate line SGTL), and the other terminal is connected to a common source line CSL through a lower select gate (connected to a select gate line SGBL). Each block is generally divided into several pages, shown by dotted lines. In one embodiment, a block is the unit of a conventional erase operation, and a page is the unit of a conventional programming operation. However, other units of erase / program may also be used.

[0017] When the control circuit 304 performs an erase operation in units of blocks, a corresponding verify operation must be performed to ensure that the corresponding memory cells are erased to avoid data remanence or metastability, which can shorten the lifespan of the 3D NAND flash memory.

[0018] More specifically, in the verify phase, the corresponding memory cells are conducted to check whether the corresponding memory cells are "strong" logic 1 or "weak" logic 1 by measuring the threshold voltage of the corresponding memory cells. If the corresponding memory cells are not "strong" enough or the threshold voltage of the corresponding memory cells does not meet the predetermined threshold, the bit cells may change from logic 1 to logic 0 during aging, which reduces the reliability of the 3D NAND flash. Therefore, after the erase phase, it is necessary to check the bit cells to determine whether the threshold voltage of the corresponding memory cells meets the predetermined threshold. However, false errors may occur during the verify phase.

[0019] In particular, conventional erase and verify process Please refer to FIG. 4, which is a timing diagram of the verify phase, where T1 is when the verify phase begins, T2 is when the voltage of the upper select gate SG_T begins to reach the turn-on voltage Von, and T3 is when the verify phase ends. As shown in FIG. 4, memory blocks BLOCK1 to BLOCK IWhen a selected memory block of the NAND string is selected to be erased, taking one NAND string as an example, the upper select gate SG_T, the lower select gate SG_B and the common source line CSL are floating, the word line is grounded, and the P-well is supplied with the erase voltage Ve in the erase phase (i.e., the voltage of the P-well rises and remains as the erase voltage Ve for a period of time, then falls to zero). Thus, the electrons trapped in the floating gate of the corresponding memory cell are attracted by the high erase voltage Ve of the P-well and leave the floating gate, and the corresponding memory cell becomes erased.

[0020] Then, in a verify phase, the word lines are supplied with a verify voltage Vv (e.g., 2.2V), then the top select gate SG_T, the bottom select gate SG_B are supplied with a turn-on voltage Von, and the word lines are finally supplied with the verify voltage Vv again to check whether the threshold voltage of the corresponding memory cell meets the predetermined threshold. If the threshold voltage of the corresponding memory cell does not meet the predetermined threshold, i.e., the verify during the verify phase is unsuccessful, another erase phase and another verify phase are performed until the threshold voltage of the corresponding memory cell meets the predetermined threshold, or an error message is generated if the verify phase with unsuccessful verify has been performed a predetermined number of times.

[0021] However, since the top select gate SG_T and the bottom select gate SG_B are floating in the erase phase, when the voltage of the P-well drops to zero, the voltages of the top select gate SG_T and the bottom select gate SG_B drop accordingly, then become the turn-on voltage Von, and the bottom select gate SG_B is turned off (as shown by the dotted line in FIG. 5B), so that the channel stops discharging and becomes floating. Then, when the voltage of the word line rises to the verify voltage Vv during the verify phase (between T1 and T2), the potential of the channel is coupled with the voltage of the word line and remains at a higher potential. After that, when the top select gate SG_T and the bottom select gate SG_B are turned on in the verify phase (after T2), the channel is connected with the P-well and therefore grounded, the potential of the channel drops rapidly, and therefore the voltage of the word line is coupled and drops accordingly. As a result, a false error occurs in the first verify phase, which requires another erase phase and another verify phase, and therefore the corresponding memory cell is over-erased with a lower threshold voltage than required.

[0022] For example, if the corresponding memory cell is erased to a strong logic 1, but is determined to be a weak logic 1, another erase phase is required to ensure that the erase is successful. However, since the corresponding memory cell is logically strong enough, erasing the corresponding memory cell with a strong logic 1 is a redundant step. As a result, the longer the duration of the erase and verify phases, the more false errors will occur, reducing the reliability and programming performance of the memory device 30.

[0023] In comparison, in the erase and verify process of the present invention, memory blocks BLOCK1 to BLOCK IWhen a selected memory block of is selected to be erased, the control circuit 304 keeps the lower select gate SG_B turned on for the sustain period before the upper select gate SG_T is turned on for the verify phase. As a result, by keeping the lower select gate SG_B turned on for the sustain period before the upper select gate SG_T is turned on for the verify phase, the present invention increases the channel discharge time to avoid word line voltage drop and subsequent false error verification.

[0024] For more details, please refer to Figures 5A and 5B. Figure 5A is a timing chart of an erase and verify process according to an embodiment of the present invention, and Figure 5B is a schematic diagram of channel potentials of a conventional erase and verify process and an erase and verify process according to an embodiment of the present invention. As can be seen from Figure 5A, memory blocks BLOCK1 to BLOCK I When a selected memory block of is selected to be erased, for example one NAND string, the lower select gate SG_B is switched from a floating state to be maintained at the turn-on voltage Von (e.g., 6.5V) for a sustain period Pm before the upper select gate SG_T is changed, where the sustain period Pm is from when the voltage of the lower select gate SG_B drops to the turn-on voltage Von as the voltage of the P-well drops, until the upper select gate SG_T is turned on during the verify phase.

[0025] Under such circumstances, the common source line CSL and the channel may be connected during the sustain period Pm. Thus, compared with the conventional erase and verify process, which has the problems of higher channel potential caused by word line coupling and voltage drop of word line caused by channel discharge coupling as described above, the channel is kept in a discharged state to zero potential in the initial verify stage (after T1) as shown by solid line in FIG. 5B of the present invention, thereby increasing the channel discharge time and avoiding the voltage drop of the word line as shown in FIG. 5A. Other operations of the erase and verify process can be derived by referring to the above description of the conventional erase and verify process, for example, the lower select gate is in a floating state during the erase stage except for the sustain period Pm, which will not be described below for brevity. As a result, the present invention increases the channel discharge time to avoid subsequent false error verification, improving the efficiency of the erase and verify process.

[0026] In particular, the gist of the present invention is to maintain the lower select gate SG_B turned on for a sustain period before the upper select gate SG_T is turned on during the verify phase to increase the channel discharge time to avoid the voltage drop of the word line caused by channel discharge coupling. Those skilled in the art can make changes or modifications, which still fall within the scope of the present invention. For example, the sustain period during which the lower select gate SG_B is turned on is not limited to the sustain period Pm shown in FIG. 5A, and can be other time intervals as long as there is a sustain period before the upper select gate SG_T is turned on during the verify phase.

[0027] For example, see FIG. 6A and FIG. 6B, which are timing charts of the erase and verify process according to another embodiment of the present invention. As shown in FIG. 6A, the sustain period Pm' is in the verify phase, i.e., from about the midpoint between T1 and T2 until the upper select gate SG_T is turned on. Under such circumstances, as shown by the dotted line in FIG. 5B as the conventional erase and verify process, the channel potential may be higher due to the word line coupling, but the channel may still be discharged and reach zero potential quickly, even if starting from the midpoint between T1 and T2 (see the solid line in FIG. 5B, the channel may be discharged quickly). As a result, even if the sustain period Pm' is shorter than the sustain period Pm, the embodiment of FIG. 6A can also increase the channel discharge time to avoid the word line voltage drop caused by the channel discharge coupling.

[0028] On the other hand, the sustain period Pm'' is from the beginning of the erase phase until the top select gate SG_T is turned on, as shown in Figure 6B. Under such circumstances, the channel is made conductive to eject electrons as fast as possible.

[0029] In particular, the default value of the 3D NAND flash is logic 1 in the above embodiment. However, in other embodiments, the default value of the 3D NAND flash may be logic 0, and the erase action is to make the memory cell go from 1 to 0. In one embodiment, a high voltage (e.g., 1.1 volts) represents logic 1, and in one embodiment, logic 1 may be represented by, but is not limited to, a low voltage (e.g., 0 volts). Furthermore, the predetermined threshold between the strong logic 1 and logic 0 may differ between process techniques, for example, the threshold may be 0.7 volts in 22 nm ultra-low power (22ULP) technology. Those skilled in the art may make appropriate changes or modifications and are not limited herein.

[0030] Moreover, the present invention avoids false error verification, however, if the threshold voltage of the corresponding memory cell does not meet the predetermined threshold, i.e., the verification during the verification phase is unsuccessful, another erase phase and another verify phase are performed until the threshold voltage of the corresponding memory cell meets the predetermined threshold, or if the verification phase with verification failure is performed a predetermined number of times, an error message is generated. The criteria for determining the failure of the erase and verify process may be based on, but is not limited to, a threshold time, a threshold number, or a combination thereof for performing the erase and verify process on the 3D NAND flash. In addition, the threshold time or threshold number may be fixed by predetermination or calibration, may be a number mapped in a table, or may be adjusted accordingly to fit the actual scenario. Those skilled in the art may change and modify the decision rule accordingly, and are not limited herein.

[0031] In addition, the erase and verify process may be modified such that a verify phase follows multiple erase phases in sequence. For example, a 3D NAND flash erase and verify process may include a first erase phase, a second erase phase, and a verify phase. In one embodiment, each of the erase and verify processes should include a sustain period during which the lower select gate SG_B is turned on to increase the channel discharge time and thus avoid the word line voltage drop due to channel discharge coupling.

[0032] In particular, the above-mentioned embodiment is used to explain the concept of the present invention. Those skilled in the art may make appropriate changes and modifications, and are not limited herein. Therefore, as long as the lower select gate SG_B is turned on before the upper select gate SG_T is turned on during the verification stage, the requirements of the present application are met and are within the scope of the present application.

[0033] 7 is a schematic diagram of an erase and verify process 70 according to one embodiment of the present invention. As shown in FIG 7, the 3D NAND flash erase and verify process 70 includes the following steps: Step 700: Start. STEP 702: The selected memory block is erased during an erase phase. STEP 704: The lower select gate SG_B is maintained turned on for a sustain period before the upper select gate SG_T is turned on during a verify phase. Step 706: End.

[0034] The detailed operation of the erase and verify process 70 can be derived by reference to the above description and will not be described below for the sake of brevity.

[0035] In summary, by keeping the lower select gate SG_B turned on during the sustain period before the upper select gate SG_T is turned on during the verify phase, the present invention increases the channel discharge time to avoid word line voltage drop and false error verification due to channel discharge coupling.

[0036] Those skilled in the art will readily recognize that numerous modifications and variations of the devices and methods may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. [Explanation of symbols]

[0037] 30 Memory Devices 101 Transistor 102 Transistor 103 Transistor 104 Transistor 302 Memory Array 304 Control circuit

Claims

1. 1. A memory device comprising: a memory block having an upper select gate, a word line, and a lower select gate; coupled to the memory block, in an erase operation erasing said memory block during an erase phase; applying a first voltage to the word line during a first step of a verify step after the erase step; applying a second voltage to the word line during a second phase of the verify phase, the second phase being later than the first phase and the second voltage being lower than the first voltage; applying a first turn-on voltage to the lower select gate from a predetermined time after the start of the erase phase and maintained at least until applying the second voltage to the word line; A control circuit configured to A memory device comprising:

2. The memory device of claim 1 , wherein the predetermined point in time is prior to applying the second voltage to the word line.

3. The control circuit floating the lower select gate prior to applying the first turn-on voltage to the lower select gate; applying the first turn-on voltage to the lower select gate beginning when a floating voltage on the lower select gate drops to the first turn-on voltage; The memory device of claim 1 , further configured to:

4. The memory device of claim 1 , wherein the bottom select gate is turned on by the first turn-on voltage.

5. the memory block further comprises a P-well; 2. The memory device of claim 1, wherein the control circuit is further configured to apply the first turn-on voltage to the lower select gate beginning before the voltage on the P-well drops from an erase voltage to a predetermined voltage.

6. The memory device of claim 1 , wherein the first turn-on voltage is greater than the first voltage.

7. the memory block further comprises a P-well; The memory device of claim 1 , wherein the control circuitry is further configured to ground the word lines when applying an erase voltage to the P-well.

8. 8. The memory device of claim 7, wherein the control circuitry is further configured to apply the first turn-on voltage to the lower select gate beginning when a voltage on the word line drops to a predetermined voltage.

9. 1. A method for operating a memory device comprising a memory block, the memory block comprising an upper select gate, a word line, and a lower select gate, the method comprising: erasing said memory block during an erase phase; applying a first voltage to the word line during a first phase of a verify phase after the erase phase; applying a second voltage to the word line during a second phase of the verify phase, the second phase being later than the first phase and the second voltage being lower than the first voltage; applying a first turn-on voltage to the lower select gate from a predetermined time after the start of the erase phase and maintained at least until applying the second voltage to the word line; A method comprising:

10. 10. The method of claim 9, wherein the predetermined point in time is prior to applying the second voltage to the word line.

11. floating the lower select gate prior to applying the first turn-on voltage to the lower select gate; applying the first turn-on voltage to the lower select gate beginning when a floating voltage on the lower select gate drops to the first turn-on voltage; 10. The method of claim 9, further comprising:

12. The method of claim 9 , wherein the lower select gate is turned on by the first turn-on voltage.

13. the memory block further comprises a P-well; 10. The method of claim 9, further comprising applying the first turn-on voltage to the lower select gate beginning before a voltage on the P-well drops from an erase voltage to a predetermined voltage.

14. The method of claim 9 , wherein the first turn-on voltage is greater than the first voltage.

15. the memory block further comprises a P-well; 10. The method of claim 9, further comprising: grounding the word lines when applying an erase voltage to the P-well.

16. 16. The method of claim 15, further comprising applying the first turn-on voltage to the lower select gate beginning when a voltage on the word line drops to a predetermined voltage.

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