Display device

Abstract

To provide: a display device with suppressed consumption power; a display device of a self-light-emitting type with suppressed consumption power; and a display device of a self-light-emitting type with suppressed consumption power, capable of being usable for a long time even in a dark place.SOLUTION: A circuit is formed using a thin film transistor including a highly purified oxide semiconductor, so that a pixel can be kept in a constant state (state in which a video signal is written). As a result, stable operation is facilitated even in the case of displaying a still image. In addition, since the operation intervals of a driving circuit can be made long, the consumption power of the display device can be reduced. Moreover, when a luminous material is used for a pixel portion of a display device of a self-light-emitting type and light of a light-emitting element is accumulated, the use for a long time becomes possible even in a dark place.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device and an electronic device having the display device. A display device and a display device comprising a field effect transistor and a light emitting element using the same The present invention relates to an electronic device having such a configuration. [Background technology]

[0002] Thin film transistors (TFTs) are fabricated using semiconductor thin films formed on substrates with insulating surfaces. Thin-film transistors are used in displays such as LCD TVs. Silicon-based semiconductors are used as semiconductor thin films that can be applied to thin-film transistors. Although the above-mentioned materials are well known, oxide semiconductors have been attracting attention as other materials.

[0003] Known oxide semiconductor materials include zinc oxide and materials containing zinc oxide as a component. And the electron carrier concentration is 10 18 / cm 3 Amorphous oxide (oxide semiconductor) A thin film transistor formed of the above has been disclosed (Patent Documents 1 to 3).

[0004] A field effect transistor using an oxide semiconductor can be applied to, for example, a display device. The display devices include self-luminous display devices that emit light to display images, and backlight devices that selectively use light from a backlight. A transmissive display device displays an image by partially transmitting external light, and a reflective display device displays an image by reflecting external light. There are display devices of this type.

[0005] The characteristics of self-luminous display devices and transmissive display devices are that they are less susceptible to external light and produce vivid colors. He is highly skilled in expressing himself visually.

[0006] The characteristic of a reflective display device is that it is easy to reduce power consumption because it does not need a built-in light source. Of course, the displayed image can be rewritten, making it an ideal electronic paper alternative to print media. As such, it is attracting attention in a society aiming to conserve resources.

[0007] However, in environments with little external light, the visibility of reflective display devices decreases, and the benefits of using them are Lighting is required for this purpose. When lighting is used, the power consumption is reduced. Therefore, we have developed a system that can reduce power consumption while improving visibility in dark places. To achieve this, materials that store external light, such as phosphorescent fluorescent materials and phosphorescent materials, are applied to reflective display devices. The inventions that achieve this have been disclosed (Patent Documents 4 and 5). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2006-165527 A [Patent Document 2] JP 2006-165528 A [Patent Document 3] JP 2006-165529 A [Patent Document 4] JP 2006-3924 A [Patent Document 5] JP 2008-116855 A Summary of the Invention [Problem to be solved by the invention]

[0009] In the thin film formation process of oxide semiconductors, deviations from the stoichiometric composition occur. For example, The electrical conductivity of the oxide semiconductor changes depending on the amount of oxygen. Hydrogen that is mixed in during the formation of the thin film of the silicon dioxide forms an oxygen (O)-hydrogen (H) bond and becomes an electron donor. This causes a change in electrical conductivity. Furthermore, since OH is a polar molecule, it This is a factor that can affect the characteristics of active devices such as thin film transistors fabricated by do.

[0010] The electron carrier concentration is 10 18 / cm 3 Even if the oxide semiconductor has a The thin film transistor disclosed in the above patent document is an n-type transistor, and the on / off ratio of the thin film transistor is 10 3 Only good The reason for the low on-off ratio of such thin-film transistors is that the off-current is high. This is due to the fact that

[0011] When a thin film transistor with a high off-state current is used in the pixel portion of a display device, In order to hold the voltage, it is necessary to provide an additional capacitance. This causes a problem that the aperture ratio decreases and the power consumption of the display device increases.

[0012] In order to reduce the power consumption of a self-luminous or transmissive display device, the display device has If the energy supplied to the light-emitting element is reduced, the display will become darker or disappear. The impact on display quality is significant.

[0013] In addition, the reflective display device using the phosphorescent material disclosed in the above-mentioned patent document is suitable for use in environments with little external light. Although it is possible to display the image with low power consumption even in the dark, it is necessary to first irradiate the phosphorescent material with external light to make it phosphorescent. The material needs to store light, so it is not suitable for long-term use in dark places.

[0014] The present invention has been made under such technical background. Therefore, the object of the present invention is to provide a method for manufacturing a semiconductor device comprising the steps of: It is an object of the present invention to provide a display device with reduced power consumption. Another object of the present invention is to provide a self-luminous display device that can be used for a long time even in a dark place. It is an object of the present invention to provide a self-luminous display device that can be used in a wide range of applications and has reduced power consumption. . [Means for solving the problem]

[0015] One embodiment of the present invention is a semiconductor device having stable electrical characteristics (e.g., an extremely reduced off-state current). The display device is a self-luminous display device that uses a thin film transistor having an oxide semiconductor. By removing impurities that act as electron donors in the conductor, intrinsic or substantially intrinsic A semiconductor with a larger energy gap than silicon semiconductors. The thin film transistors in which the panel region is formed constitute a driving circuit for the light emitting element. do.

[0016] In other words, in one embodiment of the present invention, the amount of hydrogen contained in the oxide semiconductor is 5×10 19 / cm 3 below , preferably 5 x 10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The following The hydrogen or OH bonds contained in the oxide semiconductor are removed, and the carrier concentration is reduced to 1×10 1 4 / cm 3 Less than 1 x 10 12 / cm 3 The channel of the oxide semiconductor film is The thin film transistors in which the regions are formed constitute a driving circuit for the light emitting element.

[0017] The energy gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As the top, impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration is set to 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Make it as follows.

[0018] Such a highly purified oxide semiconductor is used for the channel formation region of a thin film transistor. By this, even when the channel width is 10 mm, the drain voltage is 1 V and 10 V. In the gate voltage range of -5V to -20V, the drain current is 1×10 - 13 It acts to keep it below A.

[0019] Another embodiment of the present invention focuses on power consumption by a driver circuit included in a self-luminous display device. That is, the frequency with which the driving circuit operates is reduced, thereby reducing the power consumed by the display device. In addition, a light-storing layer is provided in the pixel portion of a self-luminous display device, and a light-emitting element is provided in the light-storing layer. It stores the light emitted and supplies energy to the light emitting element while the light emitted by the phosphorescent layer displays an image. It is only necessary to reduce the energy consumption and the power consumption of the display device.

[0020] That is, one aspect of the present invention is a power supply line for supplying pulsed DC power to a pixel, a first light-emitting element to which power is supplied from a power supply line, and a second light-emitting element for controlling opening and closing of a circuit connecting the light-emitting element to the power supply line; The pixel has a signal line for supplying a video signal, and a thin film transistor and a second thin film transistor that controls opening and closing of a circuit that connects the transistors. The channel formation region of the second thin film transistor has a band gap of 2 eV or more and is water- The elemental concentration is 5×10 19 / cm 3 The channel width is 1 Off-state current per μm is 1×10 -16 The second thin-film transistor with a capacitance of less than A / μm The first thin film transistor is maintained in an on state by the power supply line and the light emitting element. A display device that displays still images.

[0021] In one embodiment of the present invention, the carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 Less than The display device is as described above.

[0022] In addition, one aspect of the present invention is to provide a method for determining a period during which output of a scanning line signal is stopped during a display period of a still image. The display device according to the present invention has the above-mentioned features.

[0023] In another embodiment of the present invention, a light-emitting element includes a pair of electrodes and a light-emitting organic substance between the pair of electrodes. The display device as described above has a layer including:

[0024] Another embodiment of the present invention is the above display device including a luminous layer in a pixel.

[0025] Another embodiment of the present invention is an electronic device including the above-described display device.

[0026] In this specification, the term "luminous material" refers to a material that absorbs external energy such as light and emits light. A material that generates relatively stable and long-lived excitons, and the excitons have a relatively long life span. This refers to materials that emit light and then deactivate over a certain period of time. The material continues to emit light even after the external energy source is discontinued.

[0027] In this specification, a pixel refers to an element, such as a thin film, provided in each pixel of a display device. The display is controlled by electrical signals from transistors, electrodes that function as pixel electrodes, and wiring. A pixel is a group of elements that are made up of elements that control the color of the image. Each pixel may contain one color element whose brightness can be controlled. Therefore, for example, in the case of a color display device consisting of RGB color components, A small unit is composed of three pixels: an R pixel, a G pixel, and a B pixel. The pixels are what allow an image to be obtained.

[0028] In this specification, when it is stated that A and B are connected, it means that A and B are electrically connected. This includes cases where A and B are electrically connected and cases where A and B are directly connected. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers , etc.).

[0029] In this specification, the EL layer refers to a layer provided between a pair of electrodes of a light-emitting element. Therefore, the light-emitting layer containing an organic compound, which is a light-emitting material, sandwiched between the electrodes is one of the EL layers. This is an embodiment.

[0030] In addition, in the present specification, when a substance A is dispersed in a matrix made of another substance B, The substance B that constitutes the trix is ​​called the host material, and the substance A that is dispersed in the matrix is ​​called the guest material. In addition, each of Substance A and Substance B may be a single substance. It may be a mixture of two or more substances.

[0031] In this specification, the term "light-emitting device" refers to an image display device, a light-emitting device, or a light Also, the light emitting device is connected to a connector, such as FPC (Flexib le printed circuit) or TAB (Tape Automate d Bonding) tape or TCP (Tape Carrier Packag e) is attached to the module, the printed wiring board is attached to the end of the TAB tape or TCP. A module with a COG (Chip On Glass) s) All modules in which an IC (integrated circuit) is directly mounted using this method are included in the light-emitting device. Let us assume that. Effect of the Invention

[0032] According to one embodiment of the present invention, a circuit is formed using a thin film transistor including a highly purified oxide semiconductor. By configuring the display device, the operation of the circuitry can be stabilized. The current is 1×10 -13 A or less, the signal applied to the pixel of the display device It is no longer necessary to provide an additional capacitance for holding the voltage. Since the aperture ratio is increased, the light-emitting element can be This suppresses the driving voltage and reduces the power consumption of the display device.

[0033] In addition, a pixel using a thin film transistor according to one embodiment of the present invention is in a constant state (when a video signal is This allows the display to maintain the written state, so it is stable even when displaying still images. In addition, the operation interval of the drive circuit can be extended, so that the power consumption of the display device can be reduced. Power consumption can be reduced.

[0034] According to one embodiment of the present invention, a display device that can be used even in an environment with weak external light can be provided. It is also possible to provide a display device capable of displaying images while suppressing power consumption. [Brief description of the drawings]

[0035] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a pixel according to an embodiment. [Diagram 2] 1A and 1B are diagrams illustrating a structure of a display device according to an embodiment. [Diagram 3] 4A to 4C are diagrams for explaining a writing period and a holding period to a pixel according to an embodiment; [Figure 4] 1A and 1B are a top view and a cross-sectional view of a pixel according to an embodiment. [Diagram 5] 1A and 1B are a top view and a cross-sectional view of a thin film transistor according to an embodiment. [Figure 6] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 7] 1A and 1B are a top view and a cross-sectional view of a thin film transistor according to an embodiment. [Figure 8] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 9] 1 is a cross-sectional view of a thin film transistor according to an embodiment. [Figure 10] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 11] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 12] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 13] 2A to 2C illustrate a manufacturing process of a thin film transistor according to an embodiment; [Figure 14] 1 is a cross-sectional view of a thin film transistor according to an embodiment. [Figure 15] 2A and 2B are diagrams illustrating an equivalent circuit of a pixel according to an embodiment. [Figure 16] FIG. 2 is a cross-sectional view of a pixel according to the embodiment. [Figure 17] 1 is a cross-sectional view of a light emitting device according to an embodiment. [Figure 18]FIG. 2 is a cross-sectional view of a pixel according to the embodiment. [Figure 19] 1A to 1C are diagrams illustrating electronic devices according to an embodiment. [Figure 20] 1A to 1C are diagrams illustrating electronic devices according to an embodiment. [Figure 21] FIG. 1 is a longitudinal sectional view of an inverted staggered thin film transistor including an oxide semiconductor. [Figure 22] FIG. 22 is an energy band diagram (schematic diagram) taken along the line AA′ shown in FIG. 21 . [Diagram 23] (A) shows a state in which a positive potential (+VG) is applied to the gate (G1), and (B) shows a state in which a negative potential (-VG) is applied to the gate (G1). [Figure 24] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Diagram 25] FIG. 1 is a block diagram illustrating a configuration of a display device according to an embodiment. [Figure 26] 2A to 2C illustrate configurations of a driver circuit and a shift register according to an embodiment. [Figure 27] 4 is a timing chart illustrating the operation of a shift register. [Figure 28] 4 is a timing chart illustrating the operation of a shift register. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation will be omitted.

[0037] (Embodiment 1) In this embodiment, a thin film transistor and a pixel electrode using a highly purified oxide semiconductor are An example of the constituent pixels will be described below with reference to FIGS.

[0038] First, a top view of a pixel is shown in FIG. 1(A). The structure of the TFT shown in FIG. 1(A) is as follows: As an example, a bottom gate structure is shown, in which the channel is On the opposite side of the oxide semiconductor layer that will become the gate region, wiring that will become the source and drain electrodes of the TFT is placed. The pixel 10 shown in FIG. 0 is a first wiring 101 functioning as a scanning line, a second wiring 102 functioning as a signal line, A has an oxide semiconductor layer 103, a capacitance line 104, and a pixel electrode 105. The thin film has a third wiring 102B for electrically connecting the thin film layer 103 and the pixel electrode 105. A membrane transistor 106 is constructed.

[0039] The first wiring 101 also functions as a gate of the thin film transistor 106. The wiring 102A is used as one of the source electrode or drain electrode and one electrode of the storage capacitor. The third wiring 102B is a wiring that functions as a source electrode or a drain electrode. The capacitance line 104 is also a wiring that functions as the other electrode of the storage capacitor. The first wiring 101 and the capacitance line 104 are provided in the same layer, and the second wiring 10 The third wiring 102B and the capacitance line 1 04 is provided so as to overlap with the light emitting element, forming a storage capacitor for the light emitting element. The oxide semiconductor layer 103 of the thin film transistor 106 is a wiring that is branched from the first wiring 101. The gate insulating film (not shown) is provided on the wiring.

[0040] FIG. 1B shows a cross-sectional structure between dashed lines A1 and A2 in FIG. In the cross-sectional structure shown in FIG. 1(B), a gate electrode is formed on a substrate 111 via an undercoat film 112. The first wiring 101 and the capacitance line 104 are provided. A gate insulating film 113 is provided so as to cover the line 104. The oxide semiconductor layer 103 is provided on the second wiring 102. The oxide semiconductor layer 103, the second wiring 102A, and the third wiring 102B are provided. An oxide film functioning as a passivation film is provided on the wiring 102A and the third wiring 102B. The oxide insulating layer 114 is provided with an opening. In the opening, the pixel electrode 105 and the third wiring 102B are connected. The wiring 102B and the capacitance line 104 form a capacitance element with the gate insulating film 113 as a dielectric. is.

[0041] FIG. 1C shows a cross-sectional view of the dashed line B1-B2 in FIG. 1A. 1 shows a configuration in which an insulating layer 121 is provided between the capacitance line 104 and the second wiring 102A. .

[0042] When the second wiring 102A is provided on the first wiring 101 and the capacitance line 104, the gate insulating film Depending on the film thickness of 113, the first wiring 101, the second wiring 102A, and the capacitance line 104 may be A parasitic capacitance is generated between the first wiring 102A and the second wiring 102B. Thus, the provision of the insulating layer 121 reduces parasitic capacitance and reduces defects such as malfunctions. can be done.

[0043] The pixels shown in FIGS. 1A to 1C are formed by disposing a plurality of pixels on a substrate 200 as shown in FIG. In FIG. 2, the pixel section 201 is arranged on the substrate 200. 202, a scanning line driver circuit 203, and a signal line driver circuit 204. The pixel 201 is supplied with a first wiring 101 connected to a scanning line driving circuit 203. The scanning signal determines whether each row is selected or not. The pixel 201 selected by the signal is connected to the second wiring 204. 102A, a video voltage (video signal, image signal, video signal) is output from the second wiring 102A. The signal, also called video data, is supplied to the

[0044] In FIG. 2, a scanning line driving circuit 203 and a signal line driving circuit 204 are provided on a substrate 200. However, either the scanning line driver circuit 203 or the signal line driver circuit 204 is The pixel portion 202 may be provided on the substrate 200. Alternatively, only the pixel portion 202 may be provided on the substrate 200. It may also be configured so that

[0045] In FIG. 2, a pixel section 202 has a plurality of pixels 201 arranged in a matrix (striped arrangement). It should be noted that the pixels 201 do not necessarily need to be arranged in a matrix. For example, the pixels 201 may be arranged in a delta arrangement or a Bayer arrangement. The display method in the unit 202 is either the progressive method or the interlace method. In addition, the color elements controlled by pixels when displaying colors are RGB (R The number of colors is not limited to three, i.e. red, green, and blue, but may be more than three. For example, RGBW (W is white), or RGB plus one or more colors such as yellow, cyan, or magenta. The size of the display area may be different for each dot of the color element.

[0046] In FIG. 2, the first wiring 101 and the second wiring 102A are arranged in a number equal to the number of pixels in the row and column directions. In addition, the first wiring 101 and the second wiring 102A are shared between pixels. The pixel 201 may be driven.

[0047] In FIG. 1A, the second wiring 102A of the TFT is shown to have a rectangular shape. However, the shape of the third wiring 102B is made to surround the third wiring 102B (specifically, U-shaped or C-shaped), and the This increases the area of ​​the region through which the carrier moves, decreasing the current (on) that flows when the thin film transistor is turned on. The amount of current (also referred to as electric current) may be increased.

[0048] Note that the on-state current described in this specification refers to a current that flows when a thin film transistor is in an on-state (also called a conductive state). The current that flows between the source and drain when the n-channel thin-film transistor In a transistor, when the voltage applied between the gate and source is greater than the threshold voltage (Vth), This refers to the current that flows between the source and drain.

[0049] The aperture ratio is the ratio of the area through which light passes to a unit area. If the area occupied by the non-transmitting material becomes large, the aperture ratio decreases and the area that transmits light becomes smaller. The larger the area occupied by the material, the higher the aperture ratio. By reducing the area of ​​the wiring to be folded, the area occupied by the capacitance line, and the size of the thin film transistor, This will result in improved oral intake.

[0050] In particular, in the case of a self-luminous display device, the observer observes the display from a position facing the display device. The ratio of the light-emitting area of ​​a possible light-emitting element to the pixel area is called the aperture ratio.

[0051] A thin film transistor has at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain region and the source region. A current can be passed through the drain region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is unclear which is the source and which is the drain. Therefore, it is difficult to determine whether the source or drain is the same. In some cases, the region that functions as a source or drain is not called a source or drain. In some cases, they are referred to as the first terminal and the second terminal. They may be referred to as the first electrode and the second electrode. Or, they may be referred to as the first region and the second region. There is a match.

[0052] Next, the oxide semiconductor layer 103 will be described.

[0053] In the oxide semiconductor used in this embodiment, hydrogen or OH bonds are removed. The body contains 5 x 10 hydrogen 19 / cm 3 Less than or equal to 5×10 18 / cm 3 below, More preferably, 5×10 17 / cm 3 The carrier concentration is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 The oxide semiconductor film having the following channel shape is The hydrogen concentration in the oxide semiconductor layer is measured by applying the method to the oxide semiconductor layer. Secondary ion mass spectrometry (SIMS) This can be done using endoscopic imaging.

[0054] The energy gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, and more preferably or 3 eV or more, and impurities such as hydrogen that form donors are reduced as much as possible, and the carrier concentration 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Make it as follows. That is, the carrier concentration of the oxide semiconductor layer is made as close to zero as possible.

[0055] In this way, hydrogen contained in the oxide semiconductor layer is thoroughly removed, resulting in a highly purified oxide semiconductor layer. By using an oxide semiconductor layer for a channel formation region of a thin film transistor, the off-state current value Extremely small thin film transistors can be provided.

[0056] For example, the channel length of a thin-film transistor using a highly purified oxide semiconductor layer is 3 μm. Even when the channel width is 10 mm, the drain voltage is 1 V and 10 V. When the gate voltage is in the range of -5V to -20V (off state), the drain current is 1× 10 -13 It acts to keep it below A.

[0057] The characteristics of a thin film transistor using a highly purified oxide semiconductor layer are shown in FIGS. FIG. 21 shows an inverted staggered thin film transistor using an oxide semiconductor. The vertical cross-sectional view of the gate electrode (GE1) is shown. An optical waveguide layer (OS) is provided on which a source electrode (S) and a drain electrode (D) are provided. is.

[0058] FIG. 22 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 22(A) shows the case where the voltage between the source and drain is equipotential (VD = 0 V), and Fig. 22(B) shows the case where a positive potential (VD>0V) is applied to the drain relative to the source.

[0059] FIG. 23 is an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. 21. FIG. 23(A) shows a state in which a positive potential (+VG) is applied to the gate (G1), and the source The figure also shows the on-state where carriers (electrons) flow between the gate and drain. is the state in which a negative potential (-VG) is applied to the gate (G1), and the transistor is in the off state (minority capacitance This shows the case where the rear does not flow.

[0060] Figure 24 shows the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). Shows.

[0061] Conventional oxide semiconductors are generally n-type, and the Fermi level (Ef) in this case is It is located away from the intrinsic Fermi level (Ei) in the center of the gap and closer to the conduction band. In addition, some of the hydrogen in an oxide semiconductor acts as a donor, which is one of the reasons for the n-type structure. It is known that this can occur.

[0062] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. By removing impurities other than the main component of the oxide semiconductor, the oxide semiconductor is highly purified to minimize its content. In other words, it is considered to be intrinsic (i type) or intrinsic (i type). By removing as many impurities as possible, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or something close to it. By doing so, the Fermi level (Ef) is the intrinsic Fermi level ( Ei).

[0063] When the band gap (Eg) of an oxide semiconductor is 3.15 eV, the electron affinity (χ) is The specification of titanium (Ti) that constitutes the source and drain electrodes is 4.3 eV. The charge function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, At the interface between the two layers, no Schottky barrier is formed for electrons.

[0064] In other words, when the work function of the metal (φM) and the electron affinity of the oxide semiconductor (χ) are almost equal, When the two come into contact, the energy band diagram (schematic diagram) shown in FIG. 22(A) is displayed. .

[0065] In FIG. 22(B), black circles (●) represent electrons. When a positive potential is applied to the drain, The electrons cross the barrier (h) and are injected into the oxide semiconductor, where they flow toward the drain. In this case, the barrier height (h) changes depending on the gate voltage and the drain voltage. When a gate voltage is applied, the barrier height of FIG. 22(A) without voltage application, i.e., the barrier The barrier height (h) is smaller than half the band gap (Eg).

[0066] At this time, the electrons are transferred to the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable portion on the oxide semiconductor side at the interface with the oxide semiconductor.

[0067] In FIG. 23B, when a negative potential is applied to the gate electrode (G1), the minority capacitance Since the rear hole is essentially zero, the current is very close to zero.

[0068] For example, if the channel width W of a thin-film transistor is 1×10 4 μm and a channel length of 3 μm Even if the off-state current is 10 -13 A or less, and the subthreshold swing value (S value ) of 0.1 V / dec. (gate insulating film thickness 100 nm) can be obtained.

[0069] In this way, it is possible to highly purify the oxide semiconductor so that it contains as few impurities as possible other than the main component. As a result, the thin film transistor can operate satisfactorily.

[0070] In this way, a thin-film transistor with an extremely small current value in the off state (off current value) was When a memory circuit (memory element) is manufactured using this, the off-current value is small and there is almost no leakage current. Since there is no need for a resistor, the time for which an electrical signal such as a video signal is held can be extended.

[0071] Specifically, the thin film transistor having the above-mentioned oxide semiconductor layer has a channel width of 1 μm. The off-state current per -16 A / μm or less, and further 1aA / μm (1× 10 -18 It is possible to keep the loss at 100% (A / μm) or less.

[0072] A transistor with an extremely small current value in the off state (off current value) is used as the switch in the pixel section. It is used as a switching transistor (for example, the switching transistor 6401 in FIG. 15). By doing so, it is possible to extend the retention time of electrical signals such as video signals. Therefore, for example, the writing interval is set to 10 seconds or more, preferably 30 seconds or more. More preferably, the writing interval can be set to 1 minute or more and less than 10 minutes. This can enhance the effect of reducing power consumption.

[0073] The difficulty in passing an off-state current through a transistor can be expressed as an off-state resistivity. Resistivity is the resistivity of the channel formation region when the transistor is off, and off resistivity is It can be calculated from the off-state current.

[0074] Specifically, if the values ​​of the off-state current and drain voltage are known, the transistor can be calculated from Ohm's law. The resistance value when the device is off (off resistance R) can be calculated. The cross-sectional area A and the length of the channel formation region (corresponding to the distance between the source and drain electrodes) L are From this, the off-resistivity ρ can be calculated from the formula ρ=RA / L (R is the off-resistance).

[0075] Here, the cross-sectional area A is expressed as follows, where d is the thickness of the channel forming region and W is the channel width: = dW. The length L of the channel forming region is the channel length L. As described above, the off-state resistivity can be calculated from the off-state current.

[0076] The off-resistance of the transistor including the oxide semiconductor layer of this embodiment is 1×10 9 Ω m More than 1×10 is preferable. 10 Ω·m or more is more preferable.

[0077] The pixel configuration shown in FIG. 15 is one example of this embodiment. For example, It can also be provided between the gate of the transistor 6402 and the power supply line 6407. The capacitance is determined by sandwiching an insulating layer between a pair of electrodes as a dielectric. Considering the off-current of the switching transistor 6401, etc., a charge can be held for a predetermined period. Set it to

[0078] For example, in a thin film transistor using low-temperature polysilicon, the off-current is 1×10 -12 A Therefore, the design and so on are estimated to be equivalent to the oxide semiconductor. In the thin film transistor, the storage capacity is smaller than that of the thin film transistor having low-temperature polysilicon. When the capacitance is the same (about 0.1 pF), the voltage retention period is increased by 10 5 Stretch it out to about twice its size In addition, in the case of a transistor using amorphous silicon, the channel width is 1 μm. The off-state current per m is 1×10 -13 A / μm or more. Therefore, the retention capacity is the same. (about 0.1 pF), a transistor using a high-purity oxide semiconductor has a higher ammonia Compared to transistors using rufus silicon, the voltage retention period is increased by 10 4 More than doubled It can be postponed.

[0079] For example, a pixel having a transistor using low-temperature polysilicon usually displays a 60 This is done at frames per second (16msec per frame). Similarly, if the rate is reduced (the writing interval is extended), the pixel voltage decreases and the display On the other hand, when a transistor including the above-described oxide semiconductor layer is used, In this case, the off-current is small, so the retention period for one signal write is 10 5 Double 160 It can be set to about 0 seconds.

[0080] As described above, the display device of this embodiment can display a still image with a small number of times of writing image signals. Since the hold period can be extended, it is possible to write signals more quickly, especially when displaying still images. This reduces the frequency of writing, which leads to lower power consumption. For example, the number of times that a pixel is written during the display period of one still image can be one or n times. Note that n is 2 to 10. 3 This will reduce the power consumption of the display device. It is possible to achieve this.

[0081] Furthermore, in this embodiment, when a still image is displayed, the signal lines and the scanning lines are supplied with By operating the driver circuit section to stop the output of the signal, not only the pixel section but also the driver The power consumption of the circuit section can also be reduced.

[0082] Figure 3 shows the relationship between the write period and the hold period (also called one frame period). In FIG. 3, periods 251 and 252 correspond to the retention period, and periods 261 and 262 correspond to the write period. The period corresponds to the period during which the highly purified oxide semiconductor layer is Since the retention period (period 251, period 252) can be made long, it is particularly suitable for displaying still images. When displaying, the frequency of writing signals can be significantly reduced. In the case of still image display where the display is not switched often, it is necessary to reduce the number of times signals are written to the pixels. This allows for lower power consumption.

[0083] The voltage applied to the gate of the driving transistor connected to the EL element is Since the voltage applied to the gate of the driving transistor is maintained, the voltage is attenuated while the For example, the driving transistor may be refreshed appropriately, taking into account the ratio of the driving transistors that are being maintained. A specified level is set for the voltage value (initial value) immediately after a signal is written to the gate of the The refresh operation can be performed when the voltage drops to a predetermined level. It is preferable to set the pressure so that flickering is not noticeable compared to the initial value. If the display object is a video, the value should be 1.0% lower than the initial value, preferably 0.3% lower. It is preferable to perform a refresh operation (rewrite) every time the display object If the value is a character, the reset is performed every time the value is 10% lower than the initial value, preferably every time the value is 3% lower. A fresh operation (rewrite) is preferable.

[0084] The top view and cross-sectional view of a pixel without a storage capacitor are shown in FIG. The configurations shown in Figs. 4(A) and (B) are the same as those shown in Figs. 1(A) and (B). This corresponds to a diagram in which the quantity lines are omitted. From the top view shown in FIG. 4(A) and the cross-sectional view shown in FIG. 4(B), As can be seen, by using a thin film transistor having an oxide semiconductor layer, the pixel electrode 10 The area occupied by the 5, that is, the aperture ratio, can be improved. As can be seen from the graph, the use of a thin film transistor having an oxide semiconductor layer reduces the capacitance line and the area occupied by the pixel electrode 105 can be enlarged, i.e., the aperture The rate can be improved.

[0085] In the case of this embodiment, when a highly purified oxide semiconductor layer is used, the off-state current is extremely small. By applying thin-film transistors to the pixel area, the image can be displayed without providing a storage capacitor in the pixel area. It is possible to provide a display device capable of displaying an image (especially a moving image). Even if the voltage is high, the storage capacitor can hold the voltage for a long period, making it possible to display still images, etc. It is possible to provide a display device with reduced power consumption. Thus, a display device having a high-definition display portion can be provided.

[0086] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0087] (Embodiment 2) This embodiment shows an example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 410 described in this embodiment is the same as the thin film transistor 10 described in Embodiment 1. It can be used as 6.

[0088] One embodiment of the thin film transistor and the manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be explained using Figure 6.

[0089] 5(A) and (B) show an example of a top view and a cross-sectional structure of a thin film transistor. The thin film transistor 410 shown in FIG. 1 is one of the thin film transistors having a top gate structure. .

[0090] FIG. 5A is a top view of a thin film transistor 410 having a top gate structure, and FIG. 5(A) is a cross-sectional view taken along line C1-C2 of FIG. 5(A).

[0091] The thin film transistor 410 is formed by forming an insulating layer 407, an oxide semiconductor layer 408, a gate insulating layer 409, a gate insulating layer 410, a gate insulating layer 411, a gate insulating layer 412, a gate insulating layer 413, a gate insulating layer 414, a gate insulating layer 415, a gate insulating layer 416, a gate insulating layer 417, a gate insulating layer 418, a gate insulating layer 419 The conductor layer 412, the source or drain electrode layer 415a, and the source or drain electrode layer The gate electrode layer 415b, the gate insulating layer 402, and the gate electrode layer 411 are The drain electrode layer 415a and the source or drain electrode layer 415b are connected to the wiring layer 4 14a, the wiring layer 414b is provided in contact with and electrically connected to the wiring layer 414b.

[0092] In addition, the thin film transistor 410 is described using a thin film transistor having a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A filter can also be formed.

[0093] Hereinafter, a thin film transistor 410 is fabricated on a substrate 400 using FIGS. 6(A) to 6(E). The process will be explained.

[0094] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0095] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. For the glass substrate, for example, aluminosilicate glass, alumina Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, it is more practical. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0096] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used. Alternatively, crystallized glass may be used. A plastic substrate or the like can also be used as appropriate.

[0097] First, an insulating layer 407 is formed as a base film over a substrate 400 having an insulating surface. The insulating layer 407 in contact with the conductor layer is a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or a silicon nitride layer. It is preferable to use an oxide insulating layer such as an aluminum layer or an aluminum oxynitride layer. The method for forming the film 07 can be a plasma CVD method, a sputtering method, or the like. However, in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, a sputtering method is used. It is preferable to deposit the insulating layer 407 by using a method such as the steps of:

[0098] In this embodiment, a silicon oxide layer is formed as the insulating layer 407 by a sputtering method. The substrate 400 is transferred to a processing chamber and treated with a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A silicon semiconductor target is introduced and an insulating layer 407 is formed on the substrate 400. The silicon oxide layer is formed on the substrate 400. The substrate 400 may be at room temperature or may be heated. .

[0099] For example, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., and the distance between the substrate and the target is 100 nm. The distance between the TS and the oxygen sensor was 60 mm, the pressure was 0.4 Pa, the high-frequency power supply was 1.5 kW, and the oxygen sensor and and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) atmosphere. A silicon oxide film is formed by F sputtering. The film thickness is 100 nm. Instead of quartz (preferably synthetic quartz) as a target for forming a silicon oxide film, A silicon target can be used as the sputtering gas. and argon gas mixture.

[0100] In this case, it is preferable to form the insulating layer 407 while removing residual moisture in the processing chamber. This is to prevent the insulating layer 407 from containing hydrogen, a hydroxyl group, or moisture.

[0101] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as fluorine, the insulating film formed in the processing chamber must be removed. The concentration of impurities contained in the edge layer 407 can be reduced.

[0102] The insulating layer 407 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. Use high-purity gas in which impurities have been removed to a concentration of about ppm, preferably about ppb. It is desirable that

[0103] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and direct sputtering. The DC sputtering method uses a current source, and the pulsed DC sputtering method uses a pulsed bias. There is a sputtering method. The RF sputtering method is mainly used to deposit insulating films. The DC sputtering method is mainly used for forming metal films.

[0104] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0105] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves instead of glow discharge. There is a sputtering device that uses the sputtering method.

[0106] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering gas are interposed during film formation. Reactive sputtering method to form a compound thin film by chemically reacting with the silicon component. There is also a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0107] The insulating layer 407 may have a laminated structure, for example, a silicon nitride layer, a nitride layer, and Nitride insulation such as a silicon oxide layer, an aluminum nitride layer, or an aluminum oxide nitride layer The insulating layer may have a stacked structure of the oxide insulating layer and the oxide insulating layer.

[0108] For example, a spatula containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A target gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is formed while removing the residual moisture in the processing chamber. It is preferable to coat the substrate with a film.

[0109] When forming a silicon nitride layer, the substrate may be heated during film formation.

[0110] When a silicon nitride layer and a silicon oxide layer are laminated as the insulating layer 407, the silicon nitride layer The silicon oxide layer and the silicon oxide layer are formed in the same processing chamber using a common silicon target. First, nitrogen-containing gas is introduced into the processing chamber to heat the silicon target mounted therein. A silicon nitride layer is formed using a gas containing oxygen, and then the same silicon target is grown using a gas containing oxygen. The silicon oxide layer is formed using a vacuum oven. The silicon nitride layer and the silicon oxide layer are exposed to the atmosphere. Since it can be formed continuously without exposure, there is no risk of impurities such as hydrogen or moisture on the silicon nitride layer surface. It is possible to prevent the adsorption of impurities.

[0111] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the insulating layer 407. .

[0112] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor film as much as possible, As a pretreatment for film formation, a substrate on which an insulating layer 407 has been formed in a preheating chamber of a sputtering device. The substrate 400 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 400 are desorbed and exhausted. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. This pre-heating process can be omitted. Also, this pre-heating process is not necessary for the gate to be formed later. This may be performed on the substrate 400 before the insulating layer 402 is formed, or after the source electrode layer or the drain electrode layer is formed later. The substrate 4 is formed with the drain electrode layer 415a and the source or drain electrode layer 415b. You can do the same for 00.

[0113] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the insulating layer 407 is removed. In reverse sputtering, the target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using a high frequency power source under atmospheric pressure to generate plasma near the substrate and to heat the surface. This is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc. can be used instead of the argon atmosphere. Good too.

[0114] The oxide semiconductor film is formed by sputtering. nO-based non-single crystal film, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga- Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, I n-Sn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, Zn In this embodiment, the oxide semiconductor film is an In-Ga-Z The film is formed by a sputtering method using a target for forming an nO-based oxide semiconductor film. The oxide semiconductor film is heated under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. It is formed by sputtering in an atmosphere of nitrogen (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 is preferably 2% by weight or more and 10% by weight or less. The deposition may be performed using a target containing the following:

[0115] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0116] A target mainly composed of zinc oxide was used for forming an oxide semiconductor film by a sputtering method. A metal oxide target having a metal moiety can be used. Another example of the target for forming an oxide semiconductor film includes a target containing In, Ga, and Zn (composition ratio: As the molar ratio, In2O3:Ga2O3:ZnO=1:1:1, In:Ga:Zn =1:1:0.5 [atomic ratio]) can be used. In, Ga, and As a target for forming an oxide semiconductor film containing Zn, In:Ga:Zn=1:1:1[at or In:Ga:Zn=1:1:2 [atomic ratio] A target can also be used. The filling rate of the target for oxide semiconductor film formation is 90% or more. The filling rate is 100% or less, and preferably 95% or more and 99.9% or less. By using a film formation target, the formed oxide semiconductor film becomes a dense film.

[0117] The oxide semiconductor film is formed by holding the substrate in a treatment chamber that is kept in a reduced pressure state and removing residual moisture in the treatment chamber. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the oxygen, and the metal oxide is sputtered onto the target. In order to remove residual moisture in the treatment chamber, an oxide semiconductor film is formed on the substrate 400. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump is used. It is preferable to use a pump or a titanium sublimation pump as the exhaust means. A turbo pump with a cold trap may be used. The evacuated processing chamber contains, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) (preferably In order to exhaust the oxide semiconductor film formed in the processing chamber, the following gases are preferably exhausted: The concentration of impurities contained in the conductive film can be reduced. In addition, the substrate is heated during the formation of the oxide semiconductor film. You may do so.

[0118] An example of the deposition conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, Pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 scc m: Argon flow rate 30sccm) atmosphere is applied. Note that pulse direct current (DC ) power supply reduces the amount of powdery material (also called particles or dust) that is generated during film formation. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be appropriately selected depending on the application.

[0119] Next, the oxide semiconductor film is subjected to a first photolithography process to form an island-shaped oxide semiconductor layer 4 In order to form the island-shaped oxide semiconductor layer 412, The resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the injection method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0120] Note that the etching of the oxide semiconductor film here may be performed by dry etching or wet etching. Alternatively, either one or both may be used.

[0121] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0122] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur, etc. can be used.

[0123] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0124] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0125] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0126] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0127] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 412 by etching.

[0128] In this embodiment, the oxide semiconductor layer 412 is subjected to first heat treatment. The temperature is set to 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment at 450℃ for 1 hour in a nitrogen atmosphere, the material was oxidized without exposure to air. This first heat treatment prevents water and hydrogen from re-mixing into the oxide semiconductor layer, and obtains an oxide semiconductor layer. Thus, the oxide semiconductor layer 412 can be dehydrated or dehydrogenated.

[0129] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gas is used.

[0130] For example, the first heat treatment is performed by subjecting the substrate to a base in an inert gas heated to a high temperature of 650° C. to 700° C. The plate is moved and placed in the oven, heated for a few minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. Using GRTA, high-temperature heat treatment can be performed in a short time. become.

[0131] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0132] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, the crystallization rate is 90% or more. In some cases, the oxide semiconductor film is microcrystalline, or 80% or more of the oxide semiconductor film is microcrystalline. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor layer containing no crystalline components may be obtained. In some cases, it becomes a conductive film. In addition, microcrystals (grain size 1 nm or more) are present in the amorphous oxide semiconductor. In the case where the oxide semiconductor film is a mixture of oxide semiconductor layers having a thickness of 20 nm or less (typically, 2 nm or more and 4 nm or less), There are also cases where this is the case.

[0133] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. The substrate is then taken out and subjected to a photolithography process.

[0134] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer is formed. After the formation of the oxide semiconductor layer, a source electrode and a drain electrode are laminated on the oxide semiconductor layer. After forming a gate insulating layer on the drain electrode, the above-mentioned step may be performed.

[0135] Next, a conductive film is formed over the insulating layer 407 and the oxide semiconductor layer 412. The conductive film can be formed by a metallization method or a vacuum deposition method. , Ta, Ti, Mo, W, or an alloy containing the above elements, or In addition, manganese, magnesium, zinc, etc. The material may be selected from one or more of thorium, beryllium, and arsenic. The conductive film may have a single layer structure or a laminated structure of two or more layers. Single-layer structure of aluminum film containing com, and two-layer structure of titanium film laminated on aluminum film A Ti film is laminated on top of the aluminum film, and a Ti film is formed on top of that. In addition, titanium (Ti), tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scan A film of a single or multiple combinations of elements selected from Sc, alloy film, or nitride A film containing fluorine may also be used.

[0136] A resist mask is formed on the conductive film by a second photolithography process, and selective etching is performed. The source or drain electrode layer 415a is then After the electrode layer 415b is formed, the resist mask is removed (see FIG. 6(B)). When the ends of the formed source electrode layer and drain electrode layer are tapered, the gate electrode layer laminated thereon can be easily formed. This is preferable because it improves the coverage of the insulating layer.

[0137] In this embodiment, the source or drain electrode layer 415a As the electrode layer 415b, a titanium film is formed to a thickness of 150 nm by sputtering.

[0138] Note that the oxide semiconductor layer 412 is removed during etching of the conductive film. The respective materials and etching conditions are set so that the insulating layer 407 underneath is not exposed. Adjust as appropriate.

[0139] In this embodiment, a Ti film is used as the conductive film, and an In-Ga -Zn-O oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as the etchant. The mixture used is a 5:2:2 ratio of hydrogen peroxide to 28% ammonia water.

[0140] Note that in the second photolithography step, the oxide semiconductor layer 412 is only partially etched. In some cases, the oxide semiconductor layer has a groove (a recess). The drain electrode layer 415a and the source or drain electrode layer 415b are formed by The resist mask may be formed by an inkjet method. When the method is used for formation, no photomask is used, and therefore the manufacturing cost can be reduced.

[0141] The exposure to light used to form the resist mask in the second photolithography process is ultraviolet light or KrF laser. The source electrode layers adjacent to each other on the oxide semiconductor layer 412 are exposed to the laser beam or the ArF laser beam. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the thickness of the thin film transistor to be formed later. In addition, when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the second photolithography process. UV exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. This allows for faster operation and, because the off-current is extremely small, it also reduces power consumption. This can be done.

[0142] Next, the insulating layer 407, the oxide semiconductor layer 412, and the source or drain electrode layer 415 a) A gate insulating layer 402 is formed over the source or drain electrode layer 415b (FIG. 6 See (C). ).

[0143] Here, the oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the gate oxide semiconductor (a purified oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the gate insulating film and the highly purified oxide semiconductor is important. The gingival membrane (GI) is required to be of high quality.

[0144] For example, high-density plasma CVD using microwaves (2.45 GHz) produces dense, high-insulation-voltage This is preferable because it allows the formation of a high-quality insulating film with high purity oxide semiconductor and high-quality gate. By closely contacting the insulating film, the interface state density is reduced and the interface characteristics are improved. Because it is possible.

[0145] In addition, the insulating film obtained by the high density plasma CVD device can be formed with a consistent thickness. In addition, the insulating film obtained by the high-density plasma CVD apparatus has excellent step coverage. can precisely control the thickness of thin films.

[0146] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other deposition methods such as the plasma CVD method and the like can be applied. Even if the insulating film has a gate insulating film quality and an interface property with an oxide semiconductor that are modified by In any case, the quality of the gate insulating film is good, and the oxidation Any material may be used as long as it can reduce the interface state density with the solid semiconductor and form a good interface.

[0147] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, The bonds between the main component of are broken by a strong electric field (B: bias) and high temperature (T: temperature), The resulting dangling bonds induce a drift in the threshold voltage (Vth). In the present invention, impurities, particularly hydrogen and water, are removed as much as possible from the oxide semiconductor, and the above-mentioned By improving the interface characteristics with the gate insulating film, a thin film transistor that is stable even in BT tests is obtained. This allows the player to obtain a Jista.

[0148] The gate insulating layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride layer. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or a stacked layer.

[0149] The gate insulating layer is formed using a high-density plasma CVD apparatus. The CVD equipment is 1×10 11 / cm 3 This refers to a device that can achieve a plasma density of 1000 times or more. For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is The film is formed as follows.

[0150] The chamber is filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gas as material gases. A gas is introduced to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the plasma is then applied to insulating materials such as glass. An insulating film is formed on a substrate having a surface. Then, the supply of monosilane gas is stopped and the substrate is exposed to air. Nitrous oxide (N2O) and rare gases are introduced to perform plasma treatment on the insulating film surface without exposing it to heat. It may be performed on the surface of the insulating film by introducing at least nitrous oxide (N2O) and a rare gas. The plasma treatment is performed after the formation of the insulating film. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm. .

[0151] The flow rate ratio of monosilane gas (SiH4) and nitrous oxide (N2O) introduced into the chamber is The ratio of the rare gas introduced into the chamber is in the range of 1:10 to 1:200. Helium, argon, krypton, xenon, etc. can be used, but the cheapest It is preferred to use some argon.

[0152] The insulating film obtained by the above process sequence is different from the insulating film obtained by the conventional parallel plate type PCVD apparatus. The etching rates are significantly different when comparing the etching rates using the same etchant. The insulating film obtained by the parallel plate type PCVD equipment is 10% or more or 20% slower and more efficient. The insulating film obtained using a high-density plasma CVD apparatus can be said to be a dense film.

[0153] In this embodiment, a silicon oxynitride film (SiO The gate insulating layer 402 is also called xNy, where x>y>0. The deposition gases used in the CVD equipment were monosilane (SiH4), nitrous oxide (N2O), and arsenic. Argon (Ar) was used, and the flow rates of each were SiH4 / N2O / Ar=250 / 2500 / 2500 (sccm), deposition pressure 30 Pa, deposition temperature 325°C, 5 kW microphone A microwave power is applied to generate plasma, and a film is formed.

[0154] Alternatively, the gate insulating layer 402 may be formed by a sputtering method. When forming a silicon oxide film, a silicon target or a quartz target is used as the target. The sputtering was performed using oxygen or a mixture of oxygen and argon as the sputtering gas. When the sputtering method is used, the gate insulating layer 402 does not contain a large amount of hydrogen. can.

[0155] The gate insulating layer 402 is a source or drain electrode layer 415a, a source electrode layer Alternatively, a silicon oxide layer and a silicon nitride layer may be stacked on the drain electrode layer 415b side. For example, the first gate insulating layer may be an oxide film having a thickness of 5 nm to 300 nm. Silicon oxide layer (SiO x (x>0) and forming a second gate insulating layer on the first gate insulating layer. A silicon nitride layer with a thickness of 50 nm to 200 nm is deposited by sputtering as an edge layer. SiN y (y>0)) may be laminated. For example, the pressure is 0.4 Pa, and the high frequency power source is 1.5 k W, oxygen and argon (oxygen flow rate 25sccm:argon flow rate 25sccm=1:1) A silicon oxide layer with a thickness of 100 nm can be formed by RF sputtering in an atmosphere.

[0156] Next, a resist mask is formed by a third photolithography process and selectively etched. A part of the gate insulating layer 402 is removed by etching to form the source electrode layer or the drain electrode layer 4 15a, openings 421a and 421b reaching the source electrode layer or drain electrode layer 415b are formed. (See FIG. 6(D)).

[0157] Next, a conductive film is formed over the gate insulating layer 402 and the openings 421a and 421b. A gate electrode layer 411 and wiring layers 414a and 414b are formed by the photolithography process. The resist mask may be formed by an ink-jet method. When the ink jet method is used, no photomask is used, which reduces manufacturing costs.

[0158] The gate electrode layer 411 and the wiring layers 414a and 414b are made of molybdenum, titanium, Metals such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a multilayer structure using a material or an alloy material that has these as its main components. Cut.

[0159] For example, a two-layer laminate structure of a gate electrode layer 411 and wiring layers 414a and 414b may be Two-layer laminate structure with a layer of molybdenum laminated on an aluminum layer, or a layer of molybdenum laminated on a copper layer A two-layer structure with a layer laminated on top of a copper layer, or a titanium nitride layer or tantalum nitride layer laminated on a copper layer A two-layer structure, preferably a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated, is used. The layer stack structure is a tungsten layer or tungsten nitride layer, aluminum and silicon. A layer of titanium nitride or titanium alloy is laminated with a layer of titanium and / or a layer of aluminum and / or titanium. It is preferable that the gate electrode layer is formed using a light-transmitting conductive film. Examples of the conductive film having a light-transmitting property include a light-transmitting conductive oxide. It can be done.

[0160] In this embodiment, the gate electrode layer 411 and the wiring layers 414a and 414b are formed by sputtering. A titanium film with a thickness of 150 nm is formed by this method.

[0161] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, the heating is performed at a temperature of 00° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 410 .

[0162] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to 10 Repeat heating from 0℃ to 200℃ and cooling from the heating temperature to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0163] Through the above steps, the oxide semiconductor layer 41 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is obtained. 2, a thin film transistor 410 can be formed (see FIG. 6(E)). The transistor 410 is used as the thin film transistor 106 in Embodiment 1. can be done.

[0164] In addition, a protective insulating layer and a planarizing insulating layer for planarization are provided over the thin film transistor 410. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like may be used as the protective insulating layer. A silicon nitride oxide layer, a silicon nitride oxide layer, or an aluminum oxide layer may be formed as a single layer or a stacked layer. can.

[0165] The planarizing insulating layer may be made of polyimide, acrylic, benzocyclobutene, or polyamide. In addition to the above organic materials, organic materials having heat resistance such as epoxy can be used. Low-k materials, siloxane resins, PSG (phosphorus glass), BP SG (silicon boron glass) can be used. A planarizing insulating layer may be formed by laminating a plurality of insulating films.

[0166] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0167] The method for forming the flattening insulating layer is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used.

[0168] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0169] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0170] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0171] (Embodiment 3) This embodiment shows an example of a thin film transistor that can be applied to the display device disclosed in this specification. Note that the same parts as those in the second embodiment or parts and steps having similar functions are the same as those in the second embodiment. 2, and the repeated explanation will be omitted. The thin film transistor 460 described in this embodiment is the same as the thin film transistor of Embodiment 1. The sensor 106 can be used as the sensor.

[0172] One embodiment of the thin film transistor and a manufacturing method of the thin film transistor of this embodiment will be described with reference to FIGS. This will be explained using Figure 8.

[0173] 7(A) and (B) show an example of a top view and a cross-sectional structure of a thin film transistor. The thin film transistor 460 shown in FIG. 1 is one of the thin film transistors having a top gate structure. .

[0174] FIG. 7A is a top view of a thin film transistor 460 having a top gate structure, and FIG. 7(A) is a cross-sectional view taken along line D1-D2 of FIG.

[0175] The thin film transistor 460 is formed by forming an insulating layer 457, a source electrode 458, a drain electrode 459, a drain electrode 451, a drain electrode 452, a drain electrode 453, a drain electrode 454, a drain electrode 455, a drain electrode 456, a drain electrode 457, a drain electrode 458, a drain electrode 459 ... a drain electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462, A source or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, and a gate The electrode layer 461 (461a, 461b) includes a source electrode layer or a drain electrode layer 465a (465a1, 465a2) are electrically connected to the wiring layer 464 via the wiring layer 468. Although not shown, the source or drain electrode layer 465b is also formed as a gate insulating layer. An opening 452 is provided to electrically connect to the wiring layer.

[0176] Hereinafter, a thin film transistor 460 is fabricated on a substrate 450 using FIGS. The process will be explained.

[0177] First, an insulating layer 457 serving as a base film is formed over a substrate 450 having an insulating surface.

[0178] In this embodiment, a silicon oxide layer is formed as the insulating layer 457 by a sputtering method. The substrate 450 is transferred to a processing chamber and treated with a spatula containing high-purity oxygen from which hydrogen and moisture have been removed. A target gas is introduced and a silicon target or quartz (preferably synthetic quartz) is used to heat the substrate 45 A silicon oxide layer is formed on the substrate as an insulating layer 457. is carried out using a mixed gas of oxygen and argon.

[0179] For example, the purity is 6N, quartz (preferably synthetic quartz) is used, the substrate temperature is 108° C., and the substrate The distance between the plate and the target (TS distance) was 60 mm, the pressure was 0.4 Pa, and the high-frequency power 1.5kW, oxygen and argon (oxygen flow rate 25sccm: argon flow rate 25sccm = 1 1) A silicon oxide film is formed by RF sputtering in a 100 The target for forming the silicon oxide film is preferably quartz ( A silicon target can be used instead of the target made of synthetic quartz.

[0180] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl, or moisture from being contained in the insulating layer 457. The process chamber is evacuated using an opto-pump, and contains hydrogen atoms, water (H2O), and other hydrogen atoms. Since the compound containing the compound is exhausted, the compound containing the compound formed in the processing chamber and contained in the insulating layer 457 is This can reduce the concentration of impurities.

[0181] The insulating layer 457 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is possible to use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. preferable.

[0182] The insulating layer 457 may have a laminated structure. For example, the insulating layer 457 may have a silicon nitride layer, a nitride layer, and a a nitride insulating layer such as a silicon oxide layer, an aluminum nitride layer, or an aluminum oxide nitride layer; A stacked structure of the insulating layer and the oxide insulating layer may be used.

[0183] For example, a spatula containing high-purity nitrogen from which hydrogen and moisture have been removed is used between the silicon oxide layer and the substrate. A target gas is introduced and a silicon nitride layer is formed using a silicon target. In the same manner as for the silicon oxide layer, the silicon nitride layer is formed while removing the residual moisture in the processing chamber. It is preferable to coat the substrate with a film.

[0184] Next, a conductive film is formed on the insulating layer 457, and a conductive film is formed by a first photolithography process. A resist mask is formed on the film, and selective etching is performed to form a source electrode layer or a drain electrode layer. After the electrode layers 465a1 and 465a2 are formed, the resist mask is removed (see FIG. 8(A)). The source and drain electrode layers 465a1 and 465a2 are divided in the cross-sectional view. Although the source electrode layer and the drain electrode layer are shown as a continuous film, the source electrode layer and the drain electrode layer are shown as a continuous film. The end of the gate insulating layer is preferably tapered to improve coverage with the gate insulating layer to be laminated thereon. stomach.

[0185] Examples of materials for the source electrode layer or the drain electrode layer 465a1 and 465a2 include Al, Cr, An element selected from Cu, Ta, Ti, Mo, and W, or an alloy containing the above elements , and alloy films of the above elements. Using one or more materials selected from zirconium, beryllium, and thorium The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, Single-layer structure of aluminum film containing silicon, and two-layer structure of titanium film laminated on aluminum film Structure: Ti film, aluminum film layered on top of the Ti film, Ti film on top of that In addition, titanium (Ti), tantalum (Ta ), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), A film, alloy film, or a combination of a single or multiple elements selected from candium (Sc) Alternatively, a nitride film may be used.

[0186] In this embodiment, the source and drain electrode layers 465a1 and 465a2 are formed by sputtering. A titanium film having a thickness of 150 nm is formed by a deposition method.

[0187] Next, an oxide semiconductor layer 462 is formed to a thickness of 2 nm to 200 nm.

[0188] The formed oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 4. 62 (see FIG. 8B). In this embodiment, the oxide semiconductor film is A film is formed by sputtering using a Ga-Zn-O oxide semiconductor film formation target. do.

[0189] The oxide semiconductor film is formed by holding the substrate in a treatment chamber that is kept in a reduced pressure state and removing residual moisture in the treatment chamber. The sputtering gas from which hydrogen and moisture have been removed is introduced while removing the oxygen, and the metal oxide is sputtered onto the target. In order to remove residual moisture in the treatment chamber, an oxide semiconductor film is formed over the substrate 450. It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump is used. It is preferable to use a pump or a titanium sublimation pump as the exhaust means. A turbo pump with a cold trap may be used. The evacuated processing chamber contains, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) (preferably In order to exhaust the oxide semiconductor film formed in the processing chamber, the following gases are preferably exhausted: The concentration of impurities contained in the conductive film can be reduced. In addition, the substrate is heated during the formation of the oxide semiconductor film. You may do so.

[0190] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0191] An example of the deposition conditions is as follows: the substrate temperature is room temperature, the distance between the substrate and the target is 110 mm, Pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 scc m: Argon flow rate 30sccm) atmosphere is applied. Note that pulse direct current (DC ) power supply reduces the amount of powdery material (also called particles or dust) that is generated during film formation. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less in thickness. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness can be appropriately selected depending on the application.

[0192] In this embodiment, a wet etching solution is used, which is a mixture of phosphoric acid, acetic acid, and nitric acid. The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 462 by an etching method.

[0193] In this embodiment, the oxide semiconductor layer 462 is subjected to first heat treatment. The temperature is set to 400° C. or higher and 750° C. or lower, preferably 400° C. or higher and lower than the strain point of the substrate. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After heat treatment at 450℃ for 1 hour in a nitrogen atmosphere, the material was oxidized without exposure to air. This first heat treatment prevents water and hydrogen from re-mixing into the oxide semiconductor layer, and obtains an oxide semiconductor layer. Thus, the oxide semiconductor layer 462 can be dehydrated or dehydrogenated.

[0194] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) For example, the first heat treatment may be performed at a temperature of 650° C. to 70° C. The substrate is moved into an inert gas atmosphere heated to 0°C and heated for several minutes. Alternatively, GRTA can be used, in which the sample is moved and released from a heated inert gas atmosphere. This allows high-temperature heat treatment in a short time.

[0195] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0196] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, the film may crystallize to become a microcrystalline or polycrystalline film.

[0197] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. The substrate is then taken out and subjected to a photolithography process.

[0198] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer is formed. After the deposition, a source electrode and a drain electrode are further laminated on the oxide semiconductor layer, and then the source electrode is This may be performed either before or after forming a gate insulating layer on the gate and drain electrodes.

[0199] Next, a conductive film is formed over the insulating layer 457 and the oxide semiconductor layer 462. A resist mask is formed on the conductive film by a lithography process, and selective etching is performed. After forming the source or drain electrode layer 465b and the wiring layer 468, a resist mask The source or drain electrode layer 465b and the wiring layer 4 The source electrode layer 68 is formed by the same material and process as the source electrode layer 465a1 and the drain electrode layer 465a2. It is sufficient to form it.

[0200] In this embodiment, the source or drain electrode layer 465b and the wiring layer 468 are formed by sputtering. A titanium film having a thickness of 150 nm is formed by a deposition method. and the source or drain electrode layer 465a1 and 465a2. In the example in which the same titanium film is used for the source electrode layer 465a1 and the drain electrode layer 46b, The source or drain electrode layer 465b and the source electrode layer 5a2 have a selectivity in etching. Therefore, the source electrode layer or the drain electrode layer 465a1 and 465a2 are not The oxide semiconductor layer 465b is not etched during etching of the drain electrode layer 465b. A wiring layer 468 is formed on the source electrode layer or drain electrode layer 465a2 that is not covered with the dielectric layer 462. The source and drain electrode layers 465a1 and 465a2 are provided. The drain electrode layer 465b is made of a different material having a high selectivity in an etching process. When used, the source or drain electrode layer 465a2 is protected during etching. The wiring layer 468 does not necessarily have to be provided.

[0201] Note that the conductive film was etched so as not to remove the oxide semiconductor layer 462. The material and etching conditions are adjusted appropriately.

[0202] In this embodiment, a Ti film is used as the conductive film, and an In-Ga -Zn-O oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as the etchant. The mixture used is a 5:2:2 ratio of hydrogen peroxide to 28% ammonia water.

[0203] Note that in the third photolithography step, the oxide semiconductor layer 462 is only partially etched. In some cases, the oxide semiconductor layer has a groove (a recess). A resist mask for forming the drain electrode layer 465b and the wiring layer 468 is then formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no additional heat is used, the manufacturing cost can be reduced.

[0204] Next, the insulating layer 457, the oxide semiconductor layer 462, and the source or drain electrode layer 465 The gate insulating layer 452 is formed on the source electrode layer 465a1 or 465a2 or the drain electrode layer 465b. Form.

[0205] The gate insulating layer 452 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. The gate insulating layer 452 can be formed as a single layer or a stacked layer. In order to prevent a large amount of ZnO from being contained, the gate insulating layer 452 is formed by a sputtering method. When the silicon oxide film is formed by sputtering, the target A silicon target or a quartz target is used as the sputtering target, and oxygen or The process is carried out using a mixed gas of oxygen and argon.

[0206] The gate insulating layer 452 is a source or drain electrode layer 465a1, 465a2, A silicon oxide layer and a silicon nitride layer were laminated from the source electrode layer or drain electrode layer 465b side. In this embodiment, the pressure is 0.4 Pa, the high frequency power supply is 1.5 kW, Oxygen and argon (oxygen flow rate 25sccm:argon flow rate 25sccm=1:1) atmosphere A silicon oxide layer with a thickness of 100 nm is formed on the substrate by RF sputtering.

[0207] Next, a resist mask is formed by a fourth photolithography process and selectively etched. A part of the gate insulating layer 452 is removed by etching to form an opening 423 reaching the wiring layer 468. Although not shown, the source electrode layer or the drain electrode layer is formed when the opening 423 is formed (see FIG. 8(D)). An opening may be formed that reaches the source electrode layer 465b. Alternatively, the opening to the drain electrode layer 465b is formed after laminating an interlayer insulating layer. In this example, a wiring layer to be connected to the semiconductor device is formed in the opening.

[0208] Next, a conductive film is formed over the gate insulating layer 452 and the opening 423, and then a fifth photolithography is performed. A gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a lithography process. The resist mask may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0209] The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. , titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium It is formed in a single layer or multilayer using metal materials such as aluminum or alloy materials that contain these as the main components. It is possible.

[0210] In this embodiment, gate electrode layer 461 (461a, 461b) and wiring layer 464 are made of silicon. A titanium film having a thickness of 150 nm is formed by a tarpaulin deposition method.

[0211] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment, the heating is performed at a temperature of 00° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This may be performed after a protective insulating layer or a planarizing insulating layer is formed over the thin film transistor 460 .

[0212] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to 10 Repeat heating from 0℃ to 200℃ and cooling from the heating temperature to room temperature several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. If the heat treatment is carried out under reduced pressure, the heating time can be shortened.

[0213] Through the above steps, the oxide semiconductor layer 46 in which the concentrations of hydrogen, moisture, hydrides, and hydroxides are reduced is formed. 2, a thin film transistor 460 can be formed (see FIG. 8(E)). The transistor 460 is a thin film transistor used in each pixel of the pixel portion 202 in Embodiment 1. can be used.

[0214] In addition, a protective insulating layer and a planarization insulating layer for planarization are provided over the thin film transistor 460. Although not shown, the source insulating layer 452, the protective insulating layer, and the planarizing insulating layer may be formed. An opening reaching the source or drain electrode layer 465b is formed in the opening. A wiring layer is formed which is electrically connected to the drain electrode layer 465b.

[0215] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0216] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0217] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0218] (Embodiment 4) This embodiment describes another example of a thin film transistor that can be applied to the display device disclosed in this specification. Note that the same parts as those in the second embodiment or parts and steps having similar functions are shown in the second embodiment. The same as in the second embodiment may be applied, and the explanation will be omitted. The thin film transistors 425 and 426 described in this embodiment are the same as those in the thin film transistors in Embodiment 1. It can be used as a membrane transistor 106.

[0219] The thin film transistor of this embodiment will be described with reference to FIG.

[0220] An example of a cross-sectional structure of a thin film transistor is shown in FIG. The thin film transistors 425 and 426 each have an oxide semiconductor layer sandwiched between a conductive layer and a gate electrode layer. It is one of the thin film transistors with the same structure.

[0221] In addition, in FIGS. 9(A) and 9(B), a silicon substrate is used, and the silicon substrate 42 Thin film transistors 425 and 426 are provided on an insulating layer 422 provided on the semiconductor substrate 410. is.

[0222] In FIG. 9A, an insulating layer 422 and an insulating layer 407 are provided on a silicon substrate 420. A conductive layer 427 is provided between the oxide semiconductor layer 412 so as to overlap with at least the entire oxide semiconductor layer 412. .

[0223] In FIG. 9B, the conductive layer between the insulating layer 422 and the insulating layer 407 is a conductive layer such as a conductive layer 424. The oxide semiconductor layer 412 is processed by etching as shown in FIG. This is an example where there is some overlap.

[0224] The conductive layers 427 and 424 may be made of any metal material that can withstand the heat treatment temperature in the subsequent process. Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), An element selected from Cr, Nd, and Sc, or any of the above An alloy film containing the above elements as components, an alloy film containing a combination of the above elements, or an alloy film containing the above elements In addition, a single-layer structure or a laminated structure may be used. For example, a single tungsten layer, or a laminated structure of a tungsten nitride layer and a tungsten layer, etc. can be used.

[0225] The conductive layers 427 and 424 are connected to the gate electrode layers of the thin film transistors 425 and 426. It may be the same as or different from 411 and function as a second gate electrode layer. Alternatively, the potentials of the conductive layers 427 and 424 may be fixed potentials of GND and 0V. Good too.

[0226] The conductive layers 427 and 424 control the electrical characteristics of the thin film transistors 425 and 426. It is possible.

[0227] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0228] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0229] (Embodiment 5) This embodiment describes another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 390 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0230] An example of a cross-sectional structure of a thin film transistor of this embodiment is shown in FIGS. The thin film transistor 390 shown in FIG. 10(A) to FIG. 10(E) is one of the bottom gate structures. It is also called an inverted staggered thin film transistor.

[0231] In addition, the thin film transistor 390 is described using a thin film transistor having a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A filter can also be formed.

[0232] 10(A) to (E), a thin film transistor 390 is fabricated on a substrate 394. The process will be explained.

[0233] First, a conductive film is formed on a substrate 394 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 391 is formed by the process. The end of the gate electrode layer is tapered. This is preferable because it improves the coverage of the gate insulating layer to be laminated thereon. The mask may be formed by an inkjet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0234] There is no significant limitation on the substrate that can be used for the substrate 394 having an insulating surface, but at least In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0235] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. For the glass substrate, for example, aluminosilicate glass, alumina Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, it is more practical. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0236] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used. Alternatively, crystallized glass may be used. A plastic substrate or the like can also be used as appropriate.

[0237] An insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391. The silicon nitride film, the silicon oxide film, and the like have a function of preventing the diffusion of impurity elements from the substrate 394. The insulating layer is made of one or more films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film can be formed by a laminate structure.

[0238] The material of the gate electrode layer 391 is molybdenum, titanium, chromium, tantalum, tungsten, or the like. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0239] For example, the gate electrode layer 391 may have a two-layer laminate structure of molybdenum on an aluminum layer. A two-layer structure with a molybdenum layer on a copper layer, a two-layer structure with a nitrogen layer on a copper layer A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated, a titanium nitride layer and a molybdenum layer are laminated, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are laminated. As the three-layer laminate structure, a tungsten layer or a tungsten nitride layer is preferably used. layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and titanium nitride. It is preferable that the conductive film has a light-transmitting property and a titanium layer. The gate electrode layer can also be formed using a light-transmitting conductive film. An example of such a material is a conductive oxide.

[0240] Then, a gate insulating layer 397 is formed over the gate electrode layer 391 .

[0241] The gate insulating layer 397 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. The gate insulating layer 397 may be formed as a single layer or a stacked layer. In order to prevent a large amount of ZnO from being contained, the gate insulating layer 397 is formed by sputtering. When the silicon oxide film is formed by sputtering, the target A silicon target or a quartz target is used as the sputtering target, and oxygen or The process is carried out using a mixed gas of oxygen and argon.

[0242] The gate insulating layer 397 is formed by stacking a silicon nitride layer and a silicon oxide layer from the gate electrode layer 391 side. For example, a structure in which a first gate insulating layer is formed by sputtering may be used. A silicon nitride layer (SiN y (y>0) On the first gate insulating layer, a second gate insulating layer having a thickness of 5 nm to 300 nm is formed. Silicon oxide layer (SiO x (x>0)) is laminated to form a gate insulating layer with a thickness of 100 nm. .

[0243] In addition, the gate insulating layer 397 and the oxide semiconductor film 393 contain hydrogen, a hydroxyl group, and moisture as much as possible. In order to prevent the deposition of the film, the pre-heating chamber of the sputtering equipment is used for pre-treatment. A substrate 394 on which a gate electrode layer 391 is formed, or a substrate on which a gate insulating layer 397 is formed The plate 394 is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate 394 are desorbed and exhausted. The preheating temperature is preferably 100° C. or higher and 400° C. or lower. The temperature is between 150 and 300 degrees Celsius. The exhaust means installed in the preheating chamber is a cryopump. It is preferable that the preheating step is omitted. Before the oxide insulating layer 396 is formed, the source electrode layer 395a and the drain electrode layer 395b are The same may be done with the formed substrate 394 .

[0244] Next, an oxide semiconductor film 39 with a thickness of 2 nm to 200 nm is formed over the gate insulating layer 397. 3 is formed (see FIG. 10(A)).

[0245] Note that before the oxide semiconductor film 393 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the silicon into the gate insulating layer 397 to generate plasma. It is preferable to remove the dust that is generated by the sputtering. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. Either may be used.

[0246] The oxide semiconductor film 393 is formed by a sputtering method. n-Ga-Zn-O non-single crystal film, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-S nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn In this embodiment, the oxide semiconductor film 39 is a Zn-O-based or Zn-O-based oxide semiconductor film. 3 was sputtered using an In-Ga-Zn-O oxide semiconductor film formation target. The oxide semiconductor film 393 is formed in a rare gas (typically, argon) atmosphere. , in an oxygen atmosphere, or in an atmosphere of rare gas (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 The film may be formed using a target containing 2% by weight or more and 10% by weight or less.

[0247] Zinc oxide was used as a target for forming the oxide semiconductor film 393 by a sputtering method. A target made of a metal oxide having a main component of Another example of the target is an oxide semiconductor film formation target containing In, Ga, and Zn ( The composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio], In:Ga Zn=1:1:0.5 [atomic ratio]) can be used. In, Ga As a target for forming an oxide semiconductor film containing Zn, In:Ga:Zn=1:1:1 [atomic ratio], or In:Ga:Zn=1:1:2 [atomic ratio] composition ratio A target having a filling factor of 90% can also be used for forming an oxide semiconductor film. % or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target for semiconductor film formation, the oxide semiconductor film formed becomes a dense film. .

[0248] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate is heated to room temperature or a temperature less than 400°C. Then, the remaining moisture in the processing chamber is removed, and the sputtering gas from which hydrogen and moisture have been removed is heated. A gas is introduced, and an oxide semiconductor film 393 is formed on a substrate 394 using a metal oxide as a target. To remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps are used. As for the exhaust means, it is preferable to use a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be contaminated with, for example, hydrogen atoms, water ( Compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) such as HO are exhausted. Therefore, the concentration of impurities in the oxide semiconductor film formed in the treatment chamber can be reduced. In addition, the sputtering process is performed while removing the moisture remaining in the processing chamber using a cryopump. Thus, the substrate temperature when the oxide semiconductor film 393 is formed is set to room temperature or lower than 400° C. It is possible.

[0249] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particulates) generated during film formation can be easily removed. This is preferable because it can reduce the amount of dirt and dust that accumulates on the surface of the oxide semiconductor layer and also makes the film thickness distribution uniform. The thickness of the film is preferably 5 nm to 30 nm. The appropriate thickness varies and may be selected depending on the material.

[0250] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC DC sputtering using a power supply, and pulsed DC sputtering using a pulsed bias The RF sputtering method is mainly used to deposit insulating films, and the D The C sputtering method is mainly used for forming metal films.

[0251] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0252] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves instead of glow discharge. There is a sputtering device that uses the sputtering method.

[0253] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering gas are interposed during film formation. Reactive sputtering method to form a compound thin film by chemically reacting with the silicon component. There is also a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0254] Next, the oxide semiconductor film is subjected to a second photolithography process to form an island-shaped oxide semiconductor layer 3. 10B. In addition, an island-shaped oxide semiconductor layer 399 is formed. A resist mask for this purpose may be formed by an inkjet method. When the film is formed by the jet method, a photomask is not used, and therefore the manufacturing cost can be reduced.

[0255] In addition, when a contact hole is formed in the gate insulating layer 397, the process is performed using an oxide semiconductor This can be done when layer 399 is formed.

[0256] Note that the etching of the oxide semiconductor film 393 here can be performed by dry etching or wet etching. Alternatively, etching or both may be used.

[0257] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0258] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur, etc. can be used.

[0259] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0260] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0261] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0262] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0263] Note that reverse sputtering is performed before forming a conductive film in the next step, and the oxide semiconductor layer 399 and the gate It is preferable to remove resist residues and the like adhering to the surface of the insulating layer 397.

[0264] Next, a conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive film can be formed by sputtering or vacuum deposition. An element selected from the group consisting of r, Cu, Ta, Ti, Mo, and W, or a composite material containing the above elements. The above-mentioned elements may be combined to form an alloy film. A material selected from one or more of aluminum, zirconium, beryllium, and thorium The conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, or a titanium film laminated on an aluminum film, Two-layer structure: Ti film, aluminum film layered on top of the Ti film, and T In addition, titanium (Ti) and tantalum ( Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd) A film or alloy film made of a single or multiple combinations of elements selected from the group consisting of ZnO (Zn), Zn(Zn), and Zn(Zn). Alternatively, a nitride film may be used.

[0265] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 395a and the drain electrode layer 395b by etching, a resist The mask is removed (see FIG. 10(C)).

[0266] In the third photolithography process, ultraviolet light or KrF laser is used for exposure when forming the resist mask. The source electrode layers adjacent to each other on the oxide semiconductor layer 399 are exposed to the laser beam or the ArF laser beam. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the thickness of the thin film transistor to be formed later. In addition, when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. UV exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. This allows for faster operation and, because the off-current is extremely small, it also reduces power consumption. This can be done.

[0267] Note that the conductive film was etched so as not to remove the oxide semiconductor layer 399. The material and etching conditions are adjusted appropriately.

[0268] In this embodiment, a Ti film is used as the conductive film, and an In-Ga -Zn-O oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as the etchant. The mixture used is a 5:2:2 ratio of hydrogen peroxide to 28% ammonia water.

[0269] Note that in the third photolithography step, the oxide semiconductor layer 399 is only partially etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 95a, a resist mask for forming a drain electrode layer 395b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, the manufacturing cost can be reduced.

[0270] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0271] Plasma treatment with gases such as N2O, N2, or Ar to remove exposed oxide Water adsorbed on the surface of the semiconductor layer may be removed. Alternatively, a plasma treatment may be performed using a gas.

[0272] When plasma treatment is performed, the protective layer in contact with a part of the oxide semiconductor layer is not exposed to the air. An oxide insulating layer 396 is formed as an oxide insulating layer to serve as an insulating film (see FIG. 10D). In this embodiment, the oxide semiconductor layer 399 serves as the source electrode layer 395a and the drain electrode layer 395b. In a region not overlapping with the oxide insulating layer 396, the oxide semiconductor layer 399 is in contact with the oxide insulating layer 396. It is formed so that

[0273] In this embodiment, the oxide insulating layer 396 includes an island-shaped oxide semiconductor layer 399 and a source The substrate 394 on which the electrode layer 395a and the drain electrode layer 395b have been formed is heated at room temperature or below 100° C. The sputtering gas is heated to a temperature of 1000° C. and contains high-purity oxygen from which hydrogen and moisture have been removed. A silicon oxide layer containing defects is deposited using a silicon semiconductor target.

[0274] For example, a silicon target with a purity of 6N and doped with boron (resistance of 0.01 Ωcm), the distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0. 4 Pa, direct current (DC) power supply 6 kW, pulse DC in oxygen (oxygen flow rate 100%) atmosphere A silicon oxide film is formed by sputtering. The film thickness is 300 nm. As a target for forming a silicon oxide film, a quartz target (preferably Preferably, synthetic quartz can be used. In addition, oxygen or oxygen and The process is carried out using a mixture of argon and argon gas.

[0275] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 399 and the oxide insulating layer 396 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed up.

[0276] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The concentration of impurities in the oxide insulating layer 396 can be reduced.

[0277] Note that, as the oxide insulating layer 396, a silicon oxynitride layer or an oxide An aluminum layer, an aluminum oxynitride layer, or the like can also be used.

[0278] Further, the oxide insulating layer 396 and the oxide semiconductor layer 399 are heated at 100° C. to 40° C. in a state where the oxide insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other. Heat treatment may be performed at 0° C. The oxide insulating layer 396 in this embodiment has many defects. Therefore, hydrogen, moisture, and hydroxyl groups contained in the oxide semiconductor layer 399 are removed by this heat treatment. Alternatively, impurities such as hydride are diffused into the oxide insulating layer 396, and then the oxide semiconductor layer 399 is The amount of the impurities contained can be further reduced.

[0279] Through the above steps, the oxide semiconductor layer 39 in which the concentrations of hydrogen, moisture, hydroxyl groups, or hydrides are reduced is formed. 2, a thin film transistor 390 having the same structure as in FIG. 10(E) can be formed.

[0280] When forming the oxide semiconductor film as described above, it is necessary to remove residual moisture in the reaction atmosphere. As a result, the concentrations of hydrogen and hydride in the oxide semiconductor film can be reduced. The oxide semiconductor film can be stabilized.

[0281] A protective insulating layer may be provided over the oxide insulating layer. In this embodiment, the protective insulating layer 398 is The protective insulating layer 398 is formed on a silicon nitride film or a nitride oxide film. A silicon film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used.

[0282] The substrate 394 on which the oxide insulating layer 396 has been formed is heated at 100° C. to 40° C. The sputtering gas is heated to a temperature of 00°C and contains high-purity nitrogen from which hydrogen and moisture have been removed. A silicon nitride film is formed using a silicon semiconductor target. Similarly to the oxide insulating layer 396, a protective insulating layer 398 is formed while removing moisture remaining in the processing chamber. It is preferable to coat the substrate with a film.

[0283] When the protective insulating layer 398 is formed, the protective insulating layer 398 is formed at a temperature of 100° C. to 400° C. By heating the plate 394, hydrogen or moisture contained in the oxide semiconductor layer is converted into an oxide insulating layer. In this case, a heat treatment is performed after the oxide insulating layer 396 is formed. It is not necessary.

[0284] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking silicon layers, the silicon oxide layer and the silicon nitride layer are processed in the same processing chamber using a common sintering process. A film can be formed using a silicon target. A gas containing oxygen is introduced first, and then the process is A silicon oxide layer is formed using a silicon target mounted in the chamber, followed by a nitrogen-containing The gas is switched to the same silicon target and a silicon nitride layer is deposited. The silicon layer and silicon nitride layer can be formed successively without exposure to the atmosphere, so oxidation It is possible to prevent impurities such as hydrogen and moisture from being adsorbed on the surface of the silicon layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396, and a nitride layer is formed as the protective insulating layer 398. After the silicon layer is stacked, hydrogen or moisture contained in the oxide semiconductor layer is removed by an oxide insulating layer. In order to diffuse the impurities, a heat treatment (at a temperature of 100° C. to 400° C.) may be performed.

[0285] After the protective insulation layer is formed, it is further heated in air at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be performed at a constant heating temperature. In addition, the temperature is increased from room temperature to a heating temperature of 100°C to 200°C, and then the temperature is reduced from the heating temperature to room temperature. The temperature lowering may be repeated several times. If the heat treatment is carried out under reduced pressure, the heating time can be shortened. By this heat treatment, a normally-off thin film transistor can be obtained. This makes it possible to improve the reliability of the display device.

[0286] In addition, when an oxide semiconductor layer serving as a channel formation region is formed over a gate insulating layer, By removing residual moisture in the atmosphere, the concentrations of hydrogen and hydride in the oxide semiconductor layer are can be reduced.

[0287] The above process is carried out at temperatures below 400℃, so the thickness is less than 1mm and the length is 1m on each side. It can also be applied to manufacturing processes that use glass substrates at temperatures above 400°C. Since all processes can be performed at the same temperature, a large amount of energy is not required to manufacture a display panel. No need to consume ghee.

[0288] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0289] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0290] (Embodiment 6) This embodiment describes another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 310 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0291] An example of a cross-sectional structure of a thin film transistor of this embodiment is shown in FIGS. The thin film transistor 310 shown in FIG. 11(A) to FIG. 11(E) is one of bottom gate structures. It is also called an inverted staggered thin film transistor.

[0292] In addition, the thin film transistor 310 is described using a thin film transistor having a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A filter can also be formed.

[0293] 11(A) to 11(E), a thin film transistor 310 is fabricated on a substrate 300. In FIG. 11E, a protective insulating layer is formed on the thin film transistor 310. The formed structure is shown below.

[0294] First, a conductive film is formed on a substrate 300 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 311 is formed by a process. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, the manufacturing cost can be reduced.

[0295] There is no significant limitation on the substrate that can be used for the substrate 300 having an insulating surface. In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0296] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. For the glass substrate, for example, aluminosilicate glass, alumina Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, it is more practical. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0297] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used. Alternatively, crystallized glass or the like may be used.

[0298] An insulating film serving as a base film may be provided between the substrate 300 and the gate electrode layer 311. , which has the function of preventing the diffusion of impurity elements from the substrate 300. A laminate structure of one or more films selected from a silicon nitride oxide film or a silicon oxynitride film. It can be formed.

[0299] The material of the gate electrode layer 311 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0300] For example, the gate electrode layer 311 may have a two-layer laminate structure of molybdenum on an aluminum layer. Two-layer laminate structure with a molybdenum layer on a copper layer, two-layer laminate structure with a molybdenum layer on a copper layer, A two-layer laminate structure with a titanium nitride layer or tantalum nitride layer laminated on top, a titanium nitride layer and a molybdenum layer A two-layer structure consisting of a tungsten nitride layer and a tungsten layer, or a two-layer structure consisting of a tungsten nitride layer and a tungsten layer It is preferable to use a three-layer laminate structure. a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, It is preferable to form a laminate including a titanium nitride layer or a titanium layer.

[0301] Next, the gate insulating layer 302 is formed on the gate electrode layer 311 .

[0302] The gate insulating layer 302 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. , a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer, For example, the deposition gas is SiH4, oxygen, and nitrogen. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a multilayer structure, the thickness is, for example, 50 nm to 2 A first gate insulating layer having a thickness of 000 nm or less, and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. The second gate insulating layer has a thickness of 1 m or less.

[0303] In this embodiment, the gate insulating layer 302 is formed by a plasma CVD method to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0304] Next, an oxide semiconductor film 33 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 302. Form 0.

[0305] Before the oxide semiconductor film 330 was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and the dust adhering to the surface of the gate insulating layer 302 is removed. It is preferable to remove the argon atmosphere. It may be used.

[0306] The oxide semiconductor film 330 is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based , In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O system, In-Sn-O system, In-Zn-O system, Sn-Zn-O system, Al-Z In this embodiment, an oxide semiconductor film based on nO, In-O, Sn-O, or Zn-O is used. In this embodiment, the oxide semiconductor film 330 is formed on a target for forming an In-Ga-Zn-O-based oxide semiconductor film. The cross section at this stage corresponds to FIG. 11(A). The oxide semiconductor film 330 is heated in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. Formed by sputtering under an atmosphere of rare gas (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 is preferably 2% by weight or more and 10% by weight or less. % by weight or less.

[0307] As a target for forming the oxide semiconductor film 330 by a sputtering method, zinc oxide A target made of a metal oxide having a main component of Another example of the target is an oxide semiconductor film formation target containing In, Ga, and Zn ( The composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio], In:Ga Zn=1:1:0.5 [atomic ratio]) can be used. In, Ga As a target for forming an oxide semiconductor film containing Zn, In:Ga:Zn=1:1:1 [atomic ratio], or In:Ga:Zn=1:1:2 [atomic ratio] composition ratio A target having a filling factor of 90% can also be used for forming an oxide semiconductor film. % or more and 100% or less, preferably 95% or more and 99.9% or less. By using a target for semiconductor film formation, the oxide semiconductor film formed becomes a dense film. .

[0308] The oxide semiconductor film 330 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or hydrogen. Uses high-purity gas in which impurities such as chlorine and fluorine have been removed to concentrations of ppm or ppb. It is preferable that

[0309] The substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is preferably maintained at 100° C. or more and 600° C. or less. The temperature is preferably 200° C. or higher and 400° C. or lower. In addition, the concentration of impurities in the oxide semiconductor film can be reduced. Damage caused by etching is reduced. In addition, hydrogen and moisture are removed while removing residual moisture in the processing chamber. The removed sputtering gas is introduced, and the metal oxide is used as a target to deposit a layer on the gate insulating layer 302. In order to remove moisture remaining in the treatment chamber, an oxide semiconductor film 330 is formed on the treatment chamber. It is preferable to use a vacuum pump. For example, a cryopump, an ion pump, a titanium sa It is preferable to use a blimpation pump. Also, as the exhaust means, a turbo pump is used. A cold trap may be added to the cryopump. The chamber may be filled with, for example, hydrogen atoms, water (HO) or other compounds containing hydrogen atoms (more preferably carbon Since the exhaust gas contains the oxide semiconductor film formed in the treatment chamber, the This can reduce the concentration of impurities.

[0310] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, when a pulsed direct current (DC) power supply is used, the powdery substances (particulates) generated during film formation can be easily removed. This is preferable because it can reduce the amount of dirt and dust that accumulates on the surface of the oxide semiconductor layer and also makes the film thickness distribution uniform. The thickness of the film is preferably 5 nm to 30 nm. The appropriate thickness varies and may be selected depending on the material.

[0311] Next, the oxide semiconductor film 330 is subjected to a second photolithography process to form an island-shaped oxide semiconductor In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the ink. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0312] Next, the oxide semiconductor layer is subjected to a first heat treatment. The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. The temperature is set to 750° C. or lower, preferably 400° C. or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the processing equipment, and the oxide semiconductor layer was heated to 450 After the heat treatment at 30° C. for 1 hour, the oxide semiconductor layer was cooled to room temperature without being exposed to air. Thus, the oxide semiconductor layer 331 is obtained (see FIG. 11B).

[0313] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gas is used.

[0314] For example, the first heat treatment is performed by subjecting the substrate to a base in an inert gas heated to a high temperature of 650° C. to 700° C. The plate is moved and placed in the oven, heated for a few minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. Using GRTA, high-temperature heat treatment can be performed in a short time. become.

[0315] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0316] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor film In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, the crystallization rate is 90% or more. In some cases, the oxide semiconductor film is microcrystalline, or 80% or more of the oxide semiconductor film is microcrystalline. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor layer containing no crystalline components may be obtained. In some cases, it becomes a conductive film. In addition, microcrystals (grain size 1 nm or more) are present in the amorphous oxide semiconductor. In the case where the oxide semiconductor film is a mixture of oxide semiconductor layers having a thickness of 20 nm or less (typically, 2 nm or more and 4 nm or less), There are also cases where this is the case.

[0317] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 330 may be subjected to the first heat treatment. In that case, the semiconductor film 330 may be heated by the heating device after the first heat treatment. The substrate is taken out and a photolithography process is performed.

[0318] The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer is formed. After the formation of the oxide semiconductor layer, a source electrode and a drain electrode are laminated on the oxide semiconductor layer. After forming a protective insulating film on the drain electrode, the above-mentioned step may be performed.

[0319] In addition, when a contact hole is formed in the gate insulating layer 302, the process is performed using an oxide semiconductor. This may be done before or after membrane 330 is subjected to a dehydration or dehydrogenation treatment.

[0320] Note that the etching of the oxide semiconductor film here is not limited to wet etching and may be dry etching. Etching may also be used.

[0321] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0322] Next, a conductive film is formed over the gate insulating layer 302 and the oxide semiconductor layer 331. The conductive film can be formed by sputtering or vacuum deposition. An element selected from U, Ta, Ti, Mo, and W, or an alloy containing the above elements; In addition, the above-mentioned elements may be combined to form an alloy film. Using one or more materials selected from the group consisting of zinc, beryllium, and thorium The conductive film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of aluminum film containing silicon, and a two-layer structure of titanium film laminated on aluminum film The structure is a Ti film, an aluminum film is layered on top of the Ti film, and a Ti film is layered on top of that. In addition, titanium (Ti), tantalum (Ta) and other , Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium), Sc (Scandium), or a film or alloy film made of a single or multiple combinations of elements selected from the group consisting of A nitride film may also be used.

[0323] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand the heat treatment. is preferred.

[0324] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 315a and the drain electrode layer 315b by etching, a resist The mask is removed (see FIG. 11(C)).

[0325] In the third photolithography process, ultraviolet light or KrF laser is used for exposure when forming the resist mask. The source electrode layers adjacent to each other on the oxide semiconductor layer 331 are exposed to the ion beam. The width of the gap between the end of the drain electrode layer and the lower end of the drain electrode layer determines the thickness of the thin film transistor to be formed later. In addition, when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of 10 nm to several tens of nm. t) is used to perform exposure when forming a resist mask in the third photolithography process. UV exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. This allows for faster operation and, because the off-current is extremely small, it also reduces power consumption. This can be done.

[0326] Note that the conductive film was etched so as not to remove the oxide semiconductor layer 331. The material and etching conditions are adjusted appropriately.

[0327] In this embodiment, a Ti film is used as the conductive film, and an In-Ga -Zn-O oxide semiconductor was used, and ammonia hydrogen peroxide (31 wt.% hydrogen peroxide) was used as the etchant. The mixture used is a 5:2:2 ratio of hydrogen peroxide to 28% ammonia water.

[0328] Note that in the third photolithography step, the oxide semiconductor layer 331 is only partially etched. In some cases, the source electrode layer 3 is formed as an oxide semiconductor layer having a groove (a recess). 15a, a resist mask for forming the drain electrode layer 315b is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, the manufacturing cost can be reduced.

[0329] Further, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer and the metal layer for forming the source and drain electrode layers may be The oxide conductive layer can function as a source region and a drain region.

[0330] The oxide conductive layer is formed as a source region and a drain region, and the oxide semiconductor layer is formed as a source electrode layer and a drain region. By providing the source region and the drain electrode layer, the resistance of the source region and the drain region can be reduced. This allows the transistor to operate at high speed.

[0331] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0332] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0333] After the plasma treatment, the protective insulating film in contact with a part of the oxide semiconductor layer is removed without being exposed to the air. An oxide insulating layer 316 is formed to serve as an insulating film.

[0334] The oxide insulating layer 316 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The layer 316 can be formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed into the layer 316 . When hydrogen is contained in the oxide insulating layer 316, the hydrogen may enter the oxide semiconductor layer or the oxide semiconductor layer may be damaged. The region in which oxygen is extracted from the oxide semiconductor layer and a channel of the oxide semiconductor layer is formed is called a region in which The opposite side (the so-called back channel side) becomes low resistance (N-type), and a parasitic channel Therefore, the oxide insulating layer 316 should be a film that contains as little hydrogen as possible. Therefore, it is important that the deposition process does not involve hydrogen.

[0335] In this embodiment, a 200-nm-thick oxide insulating layer 316 is formed by sputtering. The substrate temperature during the film formation is set to be equal to or higher than room temperature and equal to or lower than 300° C. The temperature is set to 100°C in this embodiment. The deposition of silicon oxide film by sputtering method is performed using rare gas (typically a In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering in air. The oxide insulating layer 316 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any substances and blocks the intrusion of these substances from the outside. silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film A membrane or the like is used.

[0336] In this case, the oxide insulating layer 316 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 331 and the oxide insulating layer 316 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed up.

[0337] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The concentration of impurities in the oxide insulating layer 316 can be reduced.

[0338] The oxide insulating layer 316 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferred.

[0339] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour under atmospheric pressure. A portion of the semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 316 .

[0340] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively As a result, the channel formation region 313 overlapping with the gate electrode layer 311 becomes an i-type. The high-resistance source region 314a overlapping the source electrode layer 315a and the drain electrode layer 315 By the above steps, a thin film is formed in a self-aligned manner. A transistor 310 is formed (see FIG. 11(D)).

[0341] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and thus the reliability of the display device can be improved.

[0342] Note that the oxide semiconductor layer overlapping with the drain electrode layer 315b (and the source electrode layer 315a) forming a high-resistance drain region 314b (or a high-resistance source region 314a) in As a result, the reliability of the thin film transistor can be improved. By forming the drain region 314b, the high-resistance drain region 3 14b, a structure capable of gradually changing the conductivity from the first region to the channel forming region 313. Therefore, a wiring for supplying a high power supply potential Vdd to the drain electrode layer 315b is provided. When the device is connected to a line for operation, a high-temperature is formed between the gate electrode layer 311 and the drain electrode layer 315b. Even when voltage is applied, the high-resistance drain region acts as a buffer, making it difficult for localized electric field concentration to occur. In this case, the withstand voltage of the transistor can be improved.

[0343] The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is preferably an oxide semiconductor. When the thickness of the oxide layer is thin, 15 nm or less, it is formed throughout the thickness direction. When the thickness of the conductor layer is thicker, 30 nm or more and 50 nm or less, a part of the oxide semiconductor layer, The region in contact with the source electrode layer or the drain electrode layer and its vicinity have low resistance, forming a high resistance source region. Alternatively, a high-resistance drain region is formed, and a region of the oxide semiconductor layer close to the gate insulating film is It can also be type i.

[0344] A protective insulating layer may be further formed on the oxide insulating layer 316. For example, the protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. This is a preferred method. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films, An aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like is used. In this embodiment, the protective insulating layer 303 is formed using a silicon nitride film. (See Figure 11(E)).

[0345] In this embodiment, the protective insulating layer 303 is a substrate 3 on which the oxide insulating layer 316 is formed. 00 is heated to a temperature of 100℃ to 400℃, and high-purity nitrogen from which hydrogen and moisture have been removed is obtained. A sputtering gas is introduced and a silicon nitride film is formed using a silicon semiconductor target. In this case, similarly to the oxide insulating layer 316, the remaining moisture in the treatment chamber is removed while the treatment chamber is maintained. A protective insulating layer 303 is preferably deposited.

[0346] A planarization insulating layer for planarization may be provided over the protective insulating layer 303.

[0347] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0348] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0349] (Embodiment 7) This embodiment describes another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 360 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0350] An example of a cross-sectional structure of a thin film transistor of this embodiment is shown in FIGS. The thin film transistor 360 shown in FIG. 12(A) to FIG. 12(D) is a channel protection type (channel strip type). It is one of the bottom-gate structures called inverted staggered thin-film transistors (also called bottom-gate structures). It is also called.

[0351] In addition, the thin film transistor 360 will be described using a thin film transistor with a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A filter can also be formed.

[0352] 12(A) to 12(D), a thin film transistor 360 is fabricated on a substrate 320. The process will be explained.

[0353] First, a conductive film is formed on a substrate 320 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 361 is formed by a process. If the resist mask is formed by the inkjet method, a photomask is not used. Therefore, the manufacturing cost can be reduced.

[0354] The material of the gate electrode layer 361 is molybdenum, titanium, chromium, tantalum, tungsten, or the like. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials that contain these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0355] Next, the gate insulating layer 322 is formed on the gate electrode layer 361 .

[0356] In this embodiment, the gate insulating layer 322 is formed by a plasma CVD method to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0357] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 322. The oxide semiconductor layer is then processed into an island shape by a second photolithography process. In terms of form, it is a target for forming an In-Ga-Zn-O-based oxide semiconductor film as an oxide semiconductor film. The film is formed by sputtering using the above.

[0358] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0359] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The concentration of impurities contained in the oxide semiconductor film can be reduced.

[0360] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0361] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and an oxide semiconductor is The layer was heated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. Therefore, water or hydrogen is prevented from being mixed into the oxide semiconductor layer, and the oxide semiconductor layer 332 is obtained. See Figure 12(A).

[0362] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0363] Next, an oxide insulating layer was formed over the gate insulating layer 322 and the oxide semiconductor layer 332. After that, a resist mask is formed by a third photolithography process, and selective etching is performed. After forming the oxide insulating layer 366, the resist mask is removed.

[0364] In this embodiment, the oxide insulating layer 366 is formed by a sputtering method. The substrate temperature during the film formation is set to be equal to or higher than room temperature and equal to or lower than 300° C. The temperature is set to 100°C in this embodiment. The deposition of silicon oxide film by sputtering method is performed using rare gas (typically a In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering in air. The oxide insulating layer 366 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any substances and blocks the intrusion of these substances from the outside. silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film A membrane or the like is used.

[0365] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 332 and the oxide insulating layer 366 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed up.

[0366] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The impurity concentration in the oxide insulating layer 366 can be reduced.

[0367] The oxide insulating layer 366 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferred.

[0368] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower). For example, A second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. A part of the oxide semiconductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 366. do.

[0369] In this embodiment, an oxide semiconductor layer 366 is further provided and a part of the oxide semiconductor layer 366 is exposed. The oxide insulating layer 332 is subjected to heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed areas of the oxide semiconductor layer 332 that are not covered by 66 are filled with nitrogen, an inert gas, or the like. The resistance can be reduced by performing a heat treatment in a nitrogen atmosphere or under reduced pressure. Heat treatment is carried out in an atmosphere at 250° C. for 1 hour.

[0370] Heat treatment in a nitrogen atmosphere on the oxide semiconductor layer 332 provided with the oxide insulating layer 366 As a result, the exposed region of the oxide semiconductor layer 332 has a low resistance, and the region with a different resistance (FIG. 12( In FIG. 1B, the oxide semiconductor layer 362 has a region indicated by hatched areas and a region indicated by white areas.

[0371] Next, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366. After forming the conductive film, a resist mask is formed by a fourth photolithography process, and a selective After selectively etching the source electrode layer 365a and the drain electrode layer 365b, The resist mask is removed (see FIG. 12(C)).

[0372] The source electrode layer 365a and the drain electrode layer 365b are made of materials such as Al, Cr, Cu, and T. An element selected from a, Ti, Mo, and W, or an alloy containing the above elements, or In addition, conductive films can be made of a single layer or two or more layers. A laminated structure of the above may also be used.

[0373] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively As a result, the channel formation region 363 overlapping with the oxide insulating layer 366 is made to have an i-type The high resistance source region 364a overlaps the source electrode layer 365a, and the drain electrode layer 36 By the above steps, a thin A membrane transistor 360 is formed.

[0374] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and thus the reliability of the display device can be improved.

[0375] Note that the oxide semiconductor layer overlapping with the drain electrode layer 365b (and the source electrode layer 365a) By forming a high resistance drain region 364b (or a high resistance source region 364a) in As a result, the reliability of the thin film transistor can be improved. By forming the drain region 364b, the high resistance drain region 364b and the It is possible to provide a structure in which the conductivity can be changed stepwise over the channel forming region 363. Therefore, the drain electrode layer 365b is connected to a wiring that supplies a high power supply potential Vdd. When the transistor is operated in this manner, a high voltage is applied between the gate electrode layer 361 and the drain electrode layer 365b. Even if the electric field is increased, the high-resistance drain region 364b acts as a buffer to prevent localized electric field concentration. The withstand voltage of the transistor can be improved.

[0376] Next, a protective insulating layer is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See FIG. 12(D)).

[0377] Note that a thin film is further formed over the source electrode layer 365 a, the drain electrode layer 365 b, and the oxide insulating layer 366. An oxide insulating layer may be formed and a protective insulating layer 323 may be stacked over the oxide insulating layer.

[0378] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0379] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0380] (Embodiment 8) This embodiment describes another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 350 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0381] An example of a cross-sectional structure of a thin film transistor of this embodiment mode is shown in FIGS.

[0382] In addition, the thin film transistor 350 is described using a thin film transistor having a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A filter can also be formed.

[0383] Hereinafter, a thin film transistor 350 will be fabricated on a substrate 340 using FIGS. The process will be explained.

[0384] First, a conductive film is formed on a substrate 340 having an insulating surface, and then a first photolithography process is performed. In this embodiment, the gate electrode layer 351 is formed by a process. Then, a tungsten film having a thickness of 150 nm is formed by sputtering.

[0385] Next, a gate insulating layer 342 is formed over the gate electrode layer 351. A silicon oxynitride layer having a thickness of 100 nm or less is formed as the insulating layer 342 by the plasma CVD method. Form.

[0386] Next, a conductive film is formed on the gate insulating layer 342, and a second photolithography process is performed to A resist mask is formed over the conductive film, and selective etching is performed to form a source electrode layer 355a. After the drain electrode layer 355b is formed, the resist mask is removed (see FIG. 13A). .).

[0387] Next, an oxide semiconductor film 345 is formed (see FIG. 13B). As the oxide semiconductor film 345, an In-Ga-Zn-O oxide semiconductor film formation target is used. The oxide semiconductor film 345 is formed by a third photolithography process. The oxide semiconductor layer is then processed into an island shape.

[0388] In this case, the oxide semiconductor film 345 is formed while removing moisture remaining in the treatment chamber. In order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film 345, This is the case.

[0389] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The concentration of impurities in the oxide semiconductor film 345 can be reduced.

[0390] The oxide semiconductor film 345 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or hydrogen. Uses high-purity gas in which impurities such as chlorine and fluorine have been removed to concentrations of ppm or ppb. It is preferable that

[0391] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and an oxide semiconductor is The layer was heated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. Therefore, water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 346 is obtained. See Figure 13(C).

[0392] In the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for a few minutes, the substrate is moved and removed from the inert gas heated to a high temperature. Using GRTA, high-temperature heat treatment can be performed in a short time. do.

[0393] Next, an oxide insulating layer 356 serving as a protective insulating film in contact with the oxide semiconductor layer 346 is formed.

[0394] The oxide insulating layer 356 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The layer 356 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the layer 356 . When hydrogen is contained in the oxide insulating layer 356, the hydrogen may enter the oxide semiconductor layer or the oxide semiconductor layer may be damaged. The region in which oxygen is extracted from the oxide semiconductor layer and a channel of the oxide semiconductor layer is formed is called a region in which The opposite side (the so-called back channel side) becomes low resistance (N-type), and a parasitic channel Therefore, the oxide insulating layer 356 should be a film that contains as little hydrogen as possible. Therefore, it is important that the deposition process does not involve hydrogen.

[0395] In this embodiment, the oxide insulating layer 356 is formed by a sputtering method. The substrate temperature during the film formation is set to be equal to or higher than room temperature and equal to or lower than 300° C. The temperature is set to 100°C in this embodiment. The deposition of silicon oxide film by sputtering method is performed using rare gas (typically a In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering in air. The oxide insulating layer 356 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any substances and blocks the intrusion of these substances from the outside. silicon oxide film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film A membrane or the like is used.

[0396] In this case, the oxide insulating layer 356 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 346 and the oxide insulating layer 356 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed up.

[0397] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The impurity concentration in the oxide insulating layer 356 can be reduced.

[0398] The oxide insulating layer 356 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferred.

[0399] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour under atmospheric pressure. The layer is heated while in contact with oxide insulating layer 356 .

[0400] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for the purpose of reducing the resistance, the oxide semiconductor film is made to have an oxygen excess state. As a result, an i-type oxide semiconductor layer 352 is formed. 0 is formed.

[0401] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and thus the reliability of the display device can be improved.

[0402] A protective insulating layer may be further formed on the oxide insulating layer 356. For example, In this embodiment, a silicon nitride film is formed as a protective insulating layer 3. The film 43 is formed using a silicon nitride film (see FIG. 13(D)).

[0403] Further, a planarization insulating layer for planarization may be provided over the protective insulating layer 343.

[0404] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0405] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0406] (Embodiment 9) This embodiment describes another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor 380 shown in this embodiment is the same as the thin film transistor of Embodiment 1. 106 can be used.

[0407] In this embodiment mode, a manufacturing process of a thin film transistor is partially different from that in Embodiment Mode 6. 4. Figure 14 is the same as Figure 11 except for some differences in the process, so the same parts are The same reference numerals are used and detailed explanations of the same parts are omitted.

[0408] According to the sixth embodiment, a gate electrode layer 381 is formed on a substrate 370, and a first gate insulating film is formed on the substrate 370. A gate insulating layer 372a and a second gate insulating layer 372b are stacked. The first gate insulating layer 372a is a nitride insulating layer, and the second gate insulating layer 372b is a nitride insulating layer. An oxide insulating layer is used for 72b.

[0409] The oxide insulating layer may be a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. As the nitride insulating layer, an aluminum oxynitride layer, or the like can be used. Silicon nitride layer, silicon oxynitride layer, aluminum nitride layer, or aluminum oxynitride layer A layer or the like can be used.

[0410] In this embodiment, a silicon nitride layer and a silicon oxide layer are stacked from the gate electrode layer 381 side. The first gate insulating layer 372a is formed by sputtering to a thickness of 50 nm. A silicon nitride layer (SiN y (y> 0)) and a film as a second gate insulating layer 372b is formed on the first gate insulating layer 372a. A silicon oxide layer (SiO x (x>0) is laminated to form a gate insulating layer with a thickness of 150 nm.

[0411] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is formed into an island shape by a photolithography process. In this embodiment, the oxide semiconductor film is processed into an In-Ga-Z The film is formed by sputtering using a target for forming an nO-based oxide semiconductor film.

[0412] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0413] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The concentration of impurities contained in the oxide semiconductor film can be reduced.

[0414] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. Use high-purity gas in which impurities have been removed to concentrations of ppm or ppb. is preferred.

[0415] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 425° C. or higher. If the temperature is 425°C or higher, the heat treatment time may be 1 hour or less. In this case, the heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is prevented from being exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor layer. After that, high-purity oxygen gas, high-purity NO gas, or ultra-dry gas are used in the same furnace. Dry air (dew point below -40℃, preferably below -60℃) is introduced for cooling. It is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the device is preferably 6N (99.9999%) or more. or 7N (99.99999%) or more (i.e. impurity concentration in oxygen gas or N2O gas) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0416] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) equipment such as LRTA devices can be used with halogen lamps, metal halide lamps, xenon Arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp. Heat is generated by heat conduction or radiation from heating elements such as TA devices, lamps, and resistance heating elements. The GRTA is a heating device that uses high-temperature gas to heat the object to be treated. The gas used is a rare gas such as argon or nitrogen, which is suitable for heating. The RTA method is used to heat the material to 600℃. Heat treatment may be performed at up to 750° C. for several minutes.

[0417] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200℃ and 300℃ in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0418] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. The substrate is then taken out and subjected to a photolithography process.

[0419] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance Thus, the entire oxide semiconductor layer 382 is made i-type.

[0420] Next, a conductive film is formed over the gate insulating layer 372b and the oxide semiconductor layer 382. Further, a resist mask is formed on the conductive film by a photolithography process, and selectively etched. A source electrode layer 385a and a drain electrode layer 385b are formed by etching, and then a sputtering method is performed. An oxide insulating layer 386 is formed.

[0421] In this case, the oxide insulating layer 386 is formed while removing residual moisture in the processing chamber. It is preferable that the oxide semiconductor layer 382 and the oxide insulating layer 386 contain hydrogen, a hydroxyl group, or moisture. This is to prevent it from being swallowed up.

[0422] In order to remove residual moisture from within the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable that the exhaust means is a turbo pump with a cold trap added. The processing chamber evacuated using a cryopump may be filled with hydrogen atoms, water (H2 In order to prevent the exhaust of compounds containing hydrogen atoms such as 1,2-dihydrogen (O), the film formed in the processing chamber is The concentration of impurities in the oxide insulating layer 386 can be reduced.

[0423] The oxide insulating layer 386 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or a hydrogenated Use high-purity gas in which impurities such as ions have been removed to concentrations of about ppm or ppb. It is preferred.

[0424] Through the above steps, a thin film transistor 380 can be formed.

[0425] Next, in order to reduce the variation in the electrical characteristics of the thin-film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is performed under a nitrogen gas atmosphere. For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0426] In addition, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This heat treatment reduces the heating time. A transistor can be obtained, and thus the reliability of the display device can be improved.

[0427] Next, a protective insulating layer 373 is formed over the oxide insulating layer 386. As the edge layer 373, a silicon nitride film is formed to a thickness of 100 nm by sputtering.

[0428] The protective insulating layer 373 and the first gate insulating layer 372a made of a nitride insulating layer are resistant to moisture and water. It does not contain impurities such as hydrogen, hydrides, or hydroxides, and blocks these from entering from the outside. It has the effect of checking.

[0429] Therefore, in the manufacturing process after the protective insulating layer 373 is formed, impurities such as moisture from the outside In addition, even after the device is completed as a display device, It is possible to prevent the intrusion of impurities such as moisture from the outside, improving the long-term reliability of the device. This can be done.

[0430] In addition, between the protective insulating layer 373 made of a nitride insulating layer and the first gate insulating layer 372a The insulating layer is removed, and the protective insulating layer 373 and the first gate insulating layer 372a are in contact with each other. A structure in which

[0431] Therefore, impurities such as moisture, hydrogen, hydrides, and hydroxides in the oxide semiconductor layer can be eliminated as much as possible. and preventing re-mixing of the impurities, thereby maintaining the impurity concentration in the oxide semiconductor layer low. It is possible.

[0432] Note that a planarization insulating layer may be provided over the protective insulating layer 373 for planarization.

[0433] As described above, by applying a highly purified oxide semiconductor layer to a thin film transistor, As a result, a thin film transistor with reduced off-state current can be provided. By applying the thin film transistor with reduced off-state current described above to a pixel of a display device, This allows the period during which the storage capacitor provided in the pixel can store the voltage to be extended. It is possible to provide a display device that consumes less power when displaying.

[0434] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0435] (Embodiment 10) This embodiment describes another example of a thin film transistor that can be applied to the display device disclosed in this specification. The thin film transistor described in this embodiment is the same as any of the thin film transistors described in Embodiments 2 to 8. can be applied to.

[0436] In this embodiment mode, a light-transmitting conductive film is formed in the gate electrode layer, the source electrode layer, and the drain electrode layer. Therefore, the other steps can be carried out in the same manner as in the above embodiment. The description of the same parts as those in the embodiment, parts having similar functions, and steps will be omitted. Further, detailed explanations of the same parts will be omitted.

[0437] For example, the gate electrode layer, the source electrode layer, and the drain electrode layer may be made of a material that is transparent to visible light. Conductive materials with photoresistivity, such as In-Sn-O, In-Sn-Zn-O, In-Al -Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn- O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O The metal oxide of Zn-O system can be applied, and the film thickness is 50 nm to 300 nm. The metal oxide used in the gate electrode layer, the source electrode layer, and the drain electrode layer is appropriately selected within the range. The deposition method of the compound is sputtering, vacuum deposition (electron beam deposition, etc.), arc deposition, etc. Discharge ion plating method, spray method, and sputtering method are used. In this case, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less is used for film formation, and the film is then subjected to a translucent The conductive film has a high crystallization inhibitor SiO x (X>0) and heating in a later process It is preferable to suppress crystallization during processing.

[0438] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be used for the evaluation.

[0439] In addition, the pixel where the thin film transistor is arranged has a pixel electrode layer or other electrode layer (capacitor The wiring layers (such as the capacitance electrode layer) and other wiring layers (such as the capacitance wiring layer) are transparent to visible light. By using a conductive film, a display device having a high aperture ratio can be realized. The gate insulating layer, oxide insulating layer, protective insulating layer, and planarizing insulating layer are also transparent to visible light. It is preferable to use a membrane having the following properties:

[0440] In this specification, a film that is transparent to visible light has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes A conductive film that is semi-transparent to visible light is used as a metal oxide for the wiring layer and other wiring layers. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0441] As described above, by imparting light-transmitting properties to a thin film transistor, the aperture ratio can be improved. In particular, in small display panels of 10 inches or less, the number of gate wirings is increased. In order to achieve high resolution in the displayed image, it is necessary to realize a high aperture ratio even if the pixel size is reduced. In addition, by using a light-transmitting film as a component of a thin-film transistor, high density Even if a group of thin film transistors with a large number of pixels is arranged, the aperture ratio can be made large, and the area of ​​the display area can be increased. In addition, the same materials are used in the same process as the components of thin-film transistors. If a storage capacitor is formed using the same, the storage capacitor can also be made transparent, which further increases the aperture ratio. It can be improved.

[0442] In addition, by applying a highly purified oxide semiconductor layer to a thin film transistor, It is possible to provide a thin film transistor with reduced current. By applying a thin film transistor with reduced off-state current to a pixel of a display device, This allows the storage capacitor in the element to hold the voltage for a longer period. It is possible to provide a display device that consumes less power when displayed on a monitor.

[0443] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0444] (Embodiment 11) In this embodiment, examples of light-emitting elements that can be applied to the display device disclosed in this specification are shown in FIGS. This will be explained below with reference to FIG.

[0445] In this embodiment, an electroluminescent display element is used as a display element of a pixel of a display device. The light-emitting element using electroluminescence is exemplified as follows. They are classified according to whether the material is an organic compound or an inorganic compound. The latter is called an inorganic EL element.

[0446] An organic EL element has an anode, a cathode, and a layer containing an organic compound between them. The potential is then made higher than that of the anode, and holes are injected from the anode and electrons are injected from the cathode into the layer containing the organic compound. When electrons and holes (carriers) recombine in the layer containing the organic compound, energy is generated, The generated energy excites the luminescent organic compound, which then reacts with the substrate. Due to this mechanism, organic EL elements are considered to be current-excited light-emitting devices. This is an example of an optical element.

[0447] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0448] FIG. 15 is an equivalent circuit diagram showing an example of a pixel configuration.

[0449] The structure and operation of a pixel will be described. 1 shows an example in which two n-channel transistors are used in the pixel.

[0450] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, and a light emitting element 6404. The switching transistor 6401 has a gate. The first electrode (one of the source electrode and the drain electrode) is connected to the signal line 64 05, and the second electrode (the other of the source electrode and the drain electrode) of the driving transistor The driving transistor 6402 has a gate connected to a switch A second electrode (the other of the source electrode and the drain electrode) of the switching transistor 6401 is connected to the The first electrode is connected to a power line 6407, and the second electrode is connected to a first electrode (image The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0451] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0452] DC power is supplied to the power line 6407. In particular, pulsed DC power is supplied to the power line 640 7, the light emitting element 6404 can be made to emit light in a pulsed manner. By displaying a loop-like image, a number of still images can be displayed in sequence. Such a display can be used, for example, to display a clock that ticks away seconds. It may also supply DC power that is not

[0453] In this embodiment, a thin film transistor having a highly purified oxide semiconductor layer and a reduced off-state current is Since the transistor is applied to the pixel portion, the switching transistor 6401 is off. During this state, the potential written to the gate of the driving transistor 6402 is held. It is to be noted that even if a capacitor is provided between the gate of the driving transistor 6402 and the power supply line 6407, good.

[0454] As an example of a method for driving the light emitting element 6404, a method for performing analog gray scale driving will be described. The gate of the driving transistor 6402 is connected to the forward voltage of the light emitting element 6404. A voltage equal to or higher than the Vth of the capacitor 6402 is applied. The forward voltage of the light emitting element 6404 is the voltage required for desired brightness. This refers to the voltage when the driving voltage is set to 1 V, and includes at least the forward threshold voltage. A video signal (image signal) that causes the transistor 6402 to operate in the saturation region is input. This allows current to flow through the light emitting element 6404. In order to operate the transistor 6402 in the low-side region, the potential of the power supply line 6407 is By making the video signal analog, the light emitting element 6404 receives the video signal. A current corresponding to the signal flows, enabling analog gray scale driving.

[0455] Note that an oxide semiconductor layer that is not crystallized by laser has little variation in characteristics within the substrate surface. Therefore, the characteristics of a thin film transistor arranged in a display region using the oxide semiconductor layer The driving transistor 6402 has little variation in characteristics, and the light emitting element 640 The current flowing through the gate electrode 4 can be precisely controlled according to the gate voltage written in. A display device according to one embodiment of the present invention is capable of high-quality display with little display unevenness.

[0456] In addition, the voltage input voltage driving method allows for area gradation display using multiple pixels and displays with different luminescent colors. Color representation by combining multiple pixels (e.g. R, G, B) (e.g. R+G, G In the case of voltage input voltage drive method, the driving The gate of the transistor 6402 is connected to the driving transistor 6402 so that the driving transistor 6402 is turned on sufficiently. In other words, the driving transistor 64 is turned on or off. 02 is operated in the linear region. The driving transistor 6402 is operated in the linear region. A voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. In addition, the signal line 6405 is connected to a voltage greater than (power supply line voltage + Vth of the driving transistor 6402). Apply the above voltage.

[0457] In addition, whether the light emitting element 6404 is driven by analog gradation or by voltage input voltage, For example, the off-current per 1 μm of the channel width of the switching transistor 6401 is 1× 10 -16 Since the resistance is suppressed to less than A / μm, the gate voltage of the driving transistor 6402 Therefore, even if the number of image signal writes is small, the still image on the display can be displayed. The frequency of writing signals can be reduced, It is possible to reduce power consumption. In addition, the pixel configuration shown in FIG. 15 is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, or A logic circuit or the like may be added.

[0458] Next, the cross-sectional structure of a pixel will be described with reference to FIG. 16. The driving TFTs 7011, 7021, and 7001 shown in (C) are made of highly purified oxide. A thin film transistor having a nitride semiconductor layer may be applied, for example, as in the second embodiment to the third embodiment. The thin film transistor described in the tenth embodiment can be used.

[0459] The light-emitting element exemplified in this embodiment has a structure in which an EL layer is sandwiched between a first electrode and a second electrode. Yes.

[0460] The first and second electrodes of the light-emitting element are made of a material having a small work function, and the cathode is made of a material having a small work function. Specifically, for example, alkali metals such as Li and Cs, and aluminum metals such as Mg, Ca, and Sr. In addition to potassium earth metals and alloys containing them (Mg:Ag, Al:Li, etc.), Yb and E The anode is preferably made of a material with a large work function, such as rare earth metals such as r. For example, titanium nitride, ZrN, Ti, W, Ni, Pt, Cr, etc., ITO, IZO (Indium Oxide) Transparent conductive materials such as zinc oxide (ZnO) and ZnO are preferred. When the hole injection layer is formed in contact with the anode, or when the hole injection layer is formed in contact with the anode, the work function of the electrode material The electron injection layer and the hole injection layer can be made of, for example, an organic compound and a metal. Composites of oxides, metal oxides, organic compounds and alkali metals, alkaline earth metals, or In addition to composite materials with these compounds, they can also be formed by appropriately combining them.

[0461] The EL layer formed on the first electrode may be composed of a single layer or a laminate of multiple layers. When the EL layer is composed of multiple layers, the layers are an anode, a hole injection layer, A hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and a cathode are laminated in this order in contact with each other. It is not necessary to provide all of these layers. In addition, a plurality of EL layers separated by an intermediate layer functioning as a charge generating layer are disposed between a first electrode and a second electrode. The second electrode may be disposed between the first and second electrodes.

[0462] In order to extract light from the light emitting element, at least one of the first electrode and the second electrode is The light emitting element formed on the substrate is formed of a conductive film having a light transmitting property. When classifying light emitting devices according to the direction, the top surface is taken out from the side where the light emitting device is formed on the substrate. Injection from the bottom, ejection from the side facing the substrate, ejection from the side facing the substrate and the opposite side There are three typical structures of light-emitting devices: dual-side emission, dual-side emission, and dual-side emission. can also be applied to

[0463] In addition, when the EL layer is laminated on the first electrode, the periphery of the first electrode is covered with a partition wall. For example, organic resin films such as polyimide, acrylic, polyamide, and epoxy, inorganic insulating films, The partition wall is formed using organic polysiloxane. Also, the partition wall is formed using a photosensitive resin material. It is preferable that the first electrode is covered with a separator while leaving a separator on the periphery of the first electrode. When an opening is formed in a light-transmitting resin material, the side wall from the partition to the opening has a continuous curvature. This is because it results in a sloping surface having a certain angle, and the step of forming a resist mask can be omitted.

[0464] A color filter may be formed between the substrate and the light emitting element. Droplet ejection methods such as inkjet printing, printing, and etching using photolithography technology The insulating layer 11 may be formed by a bonding method or the like.

[0465] In addition, an overcoat layer is formed on the color filter, and a protective insulating layer is further formed. By providing an overcoat layer, the unevenness caused by the color filter can be smoothed. By forming an insulating film, it is possible to prevent impurities from diffusing from the color filter to the light emitting element. .

[0466] In addition, a light emitting element is formed on the protective insulating layer, the overcoat layer, and the insulating layer on the thin film transistor. When forming the thin film transistor, the insulating layer is formed by penetrating the protective insulating layer, the overcoat layer, and the insulating layer. A contact hole is formed that reaches the source electrode layer or the drain electrode layer. If the contact holes are laid out and formed at positions overlapping the partition walls, the aperture ratio can be reduced. This is preferable because it can be suppressed.

[0467] The structure of a pixel having a light-emitting element with a bottom emission structure will be described. FIG. 16A shows a cross-sectional view of a cut surface including T7011 and the light-emitting element 7012.

[0468] The driving TFT 7011 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. The gate electrode layer, the gate insulating layer, and the gate electrode layer are formed on the source electrode layer and the drain electrode layer. A wiring layer is provided so as to be electrically connected to each other.

[0469] An insulating layer 7031 is formed to cover the driving TFT 7011. A color filter 7033 having an aperture is provided. The overcoat layer 7034 and the insulating layer 7035 are formed to cover the color filter 7033. 035. The drain electrode of the driving TFT 7011 and the conductive film 701 7 is an overcoat layer 7034, an insulating layer 7035, and an opening formed in the insulating layer 7031. The first light-emitting element 7012 is electrically connected to the conductive film 7017 through a hole. An electrode 7013 is provided in contact with the first electrode 7013 .

[0470] The light-emitting element 7012 has an EL layer 7014 between a first electrode 7013 and a second electrode 7015. It is held in a clamped position.

[0471] The light-transmitting conductive film 7017 can be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide (hereinafter referred to as ITO), Conductive materials with optical transparency such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive film can be used.

[0472] Here, the case where the first electrode 7013 of the light-emitting element 7012 is used as a cathode will be described. When the first electrode 7013 is used as a cathode, a metal having a small work function is suitable. In FIG. 16A, the film thickness of the first electrode 7013 is set to a value that allows light to pass through (preferably, 5 For example, an aluminum film or M film having a thickness of 20 nm is used. A g-Ag alloy film is used for the first electrode 7013 .

[0473] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the light-transmitting conductive film 7017 and the first electrode 7013 may be formed. It is preferable that the same mask be used for etching.

[0474] The second electrode 7015 formed on the EL layer 7014 is made of a material having a large work function. It is preferable to provide a shielding film 7016 on the second electrode 7015, for example, a metal that blocks light. A light-reflecting metal or the like is used. In this embodiment, an ITO film is used as the second electrode 7015. A Ti film is used as the shielding film 7016 .

[0475] The color filter 7033 is covered with an overcoat layer 7034, and a protective insulating layer 7035 is formed on the overcoat layer 7034. In FIG. 16A, the overcoat layer 7034 is illustrated as being thin. However, the overcoat layer 7034 flattens the unevenness caused by the color filter 7033. There are.

[0476] In addition, a drain electrode is formed on the overcoat layer 7034 and the protective insulating layer 7035. The contact hole reaching the pole layer 7030 is arranged at a position overlapping with the partition wall 7019. .

[0477] In the case of the pixel structure shown in FIG. 16A, light emitted from the light emitting element 7012 is reflected by the light emitting element 7013 as shown by the arrow. The light is then emitted toward the first electrode 7013, passes through the color filter 7033, and is output to the outside of the display device. do.

[0478] In FIG. 16A, the gate electrode layer, the source electrode layer, and the drain electrode layer are formed of a light-transmitting In this example, the driving TFT 7011 is configured using a conductive film having the following characteristics: A part of the light emitted from the element 7012 is reflected by the color filter 7033 and the driving TFT 701. It passes through 1 and is ejected.

[0479] Next, the configuration of a pixel having a light emitting element with a dual emission structure will be described. FIG. 16B shows a cross-sectional view of a cut surface including the application TFT 7021 and the light-emitting element 7022.

[0480] The driving TFT 7021 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. The gate electrode layer, the gate insulating layer, and the gate electrode layer are formed on the source electrode layer and the drain electrode layer. A wiring layer is provided so as to be electrically connected to each other.

[0481] An insulating layer 7041 is formed to cover the driving TFT 7021. A color filter 7043 having an aperture is provided. The overcoat layer 7044 and the insulating layer 7045 are formed to cover the color filter 7043. 045. The drain electrode of the driving TFT 7021 and the conductive film 702 7 is an overcoat layer 7044, an insulating layer 7045, and an opening formed in the insulating layer 7041. The first light-emitting element 7022 is electrically connected to the conductive film 7027 through a hole. An electrode 7023 is provided in contact with the first electrode 7023 .

[0482] The light-emitting element 7022 has an EL layer 7024 between a first electrode 7023 and a second electrode 7025. It is held in a clamped position.

[0483] Here, the case where the first electrode 7023 of the light-emitting element 7022 is used as a cathode will be described. Note that the light-transmitting conductive film 7027 is the same as the conductive film 7017 shown in FIG. The first electrode 7023 may be formed in the same manner as the first electrode 7013 shown in FIG. The EL layer 7024 may be formed in the same manner as the EL layer 7014 shown in FIG. Since they can be formed in the same manner, detailed explanations will be omitted here.

[0484] The second electrode 7025 formed on the EL layer 7024 functions as an anode here. Materials with a large work function, for example, transparent conductive materials such as ITO, IZO, and ZnO, are preferred. In this embodiment, the second electrode 7025 is formed of ITO.

[0485] The color filter 7043, the overcoat layer 7044, and the protective insulating layer 7045 are The color filter 7033 and the overcoat layer 703 of the pixel shown in FIG. 4 and the protective insulating layer 7035 may be formed in a similar manner.

[0486] In the case of the pixel structure shown in FIG. 16B, light emitted from the light emitting element 7022 is As shown in FIG. 1, the light is emitted toward both the first electrode 7023 side and the second electrode 7025 side. The light on the side 23 passes through the color filter 7043 and exits the display device.

[0487] In FIG. 16B, the gate electrode layer, the source electrode layer, and the drain electrode layer are formed of a light-transmitting In this example, the driving TFT 7021 is configured using a conductive film having the following characteristics: A part of the light emitted from the element 7022 is reflected by the color filter 7043 and the driving TFT 702. It passes through 1 and is ejected.

[0488] In addition, a drain electrode layer is formed on the overcoat layer 7044 and the insulating layer 7045. The contact hole reaching 7040 is arranged at a position overlapping with the partition wall 7029. The layout is such that the contact hole reaching the rain electrode layer and the partition wall 7029 overlap each other. In this way, the aperture ratio on the second electrode 7025 side and the aperture ratio on the first electrode 7023 side are made substantially equal to each other. This can be done.

[0489] However, when both display surfaces of a light-emitting element having a dual emission structure are used for full color display, the second Since the light from the electrode 7025 side does not pass through the color filter 7043, a separate color filter is required. It is preferable that a sealing substrate having a metal layer be provided above the second electrode 7025 .

[0490] Next, the configuration of a pixel having a light emitting element with a top emission structure will be described. FIG. 16C shows a cross-sectional view of a cut surface including the application TFT 7001 and the light-emitting element 7002.

[0491] The driving TFT 7001 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. The gate electrode layer, the gate insulating layer, and the gate electrode layer are formed on the source electrode layer and the drain electrode layer. A wiring layer is provided so as to be electrically connected to each other.

[0492] An insulating layer 7051 is formed to cover the driving TFT 7001. The first electrode 7003 is provided with an insulating layer 7053 having an opening. The driving TFT 7001 is formed on an insulating layer 7055 formed to cover the driving TFT 7001. The drain electrode and the first electrode 7003 are formed on the insulating layer 7055 and the insulating layer 7051. The electrical connection is made through the opening.

[0493] The insulating layer 7053 is made of polyimide, acrylic, benzocyclobutene, polyamide, or ethylene. In addition to the above resin materials, low dielectric constant materials (L ow-k materials), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) In addition, a plurality of insulating films made of these materials can be laminated. The method for forming the insulating layer 7053 is not particularly limited. Depending on the material, sputtering, SOG, spin coating, dip coating, spray coating, Droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife A roll coater, a curtain coater, a knife coater, etc. can be used. By forming 7053, for example, unevenness caused by the driving TFT can be made flat.

[0494] The light-emitting element 7002 has an EL layer 7004 between a first electrode 7003 and a second electrode 7005. In the light-emitting element 7002 illustrated in FIG. The case where 3 is used as a cathode will be described.

[0495] The first electrode 7003 may be made of the same material as the first electrode 7013 shown in FIG. However, in the light emitting element having a top emission structure shown in FIG. 16C, the first electrode 7003 It is preferable that the electrode does not have light transmission and has high reflectance. By using an electrode having such a structure, the light extraction efficiency can be improved.

[0496] The first electrode 7003 is, for example, an aluminum film or a film mainly composed of aluminum. A titanium film is preferably laminated on an aluminum film or an alloy film. The first electrode 7003 is a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. do.

[0497] The EL layer 7004 may be formed in the same manner as the EL layer 7014 shown in FIG. In addition, the second electrode 7005 may be formed in the same manner as the second electrode 7025 shown in FIG. Therefore, a detailed description will be omitted here.

[0498] In the case of the pixel structure shown in FIG. 16C, light emitted from the light emitting element 7002 is indicated by an arrow. As shown in FIG.

[0499] When full color display is performed using the structure of FIG. 16C, for example, the light emitting element 7002 is One adjacent light-emitting element is a red light-emitting element and the other is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is added to make four types of light-emitting elements. A light-emitting display device capable of full color display may be manufactured.

[0500] In addition, all the light emitting elements arranged in the structure of FIG. 16(C) are white light emitting elements. A sealing substrate having a color filter or the like is disposed above each light-emitting element including the element 7002. A full-color light-emitting display device may be fabricated by using a structure in which the light-emitting element is placed on the substrate. By forming elements that emit light of different colors and combining them with color filters and color conversion layers, Color display is possible.

[0501] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0502] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0503] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0504] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the input / output terminals are connected to each other.

[0505] Next, the appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a display device will be described. The surface will be described with reference to FIG. 17. FIG. 17(A) shows a thin film formed on a first substrate. A panel in which the transistor and the light-emitting element are sealed between the second substrate and the transistor and the light-emitting element by a sealant. 17B is a top view, and corresponds to a cross-sectional view taken along line HI in FIG. 17A.

[0506] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0507] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 17B, a thin film transistor 4510 included in a pixel portion 4502 and a signal A thin film transistor 4509 included in the signal line driver circuit 4503a is illustrated. An insulating layer 4542 is provided on the transistors 4509 and 4510. The source electrode of the thin film transistor 4510 is connected to the contact hole 542. The drain electrode layer and the first electrode layer 4517 of the light-emitting element 4511 are electrically connected to each other. is.

[0508] The thin film transistors 4509 and 4510 are the high-performance transistors described in any of Embodiments 1 to 10. A thin film transistor having a purified oxide semiconductor layer is used.

[0509] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is A conductive layer 4540 is provided in a position overlapping with the channel formation region. By providing the transistor at a position overlapping the channel formation region of the nitride semiconductor layer, the BT stress test (Bias-temperature stress test) Threshold voltage of thin-film transistor 4509 before and after In this specification, the BT stress test (bias Temperature stress test is a test in which a high gate voltage is applied to a thin-film transistor in a high-temperature environment. The conductive layer 4540 is connected to the gate of the thin film transistor 4509. The second gate electrode layer may be the same as or different from the first gate electrode layer. In addition, the potential of the conductive layer 4540 can be set to GND, 0 V, or in a floating state. It's fine.

[0510] The light-emitting element 4511 includes a first electrode layer 4517, an electroluminescent layer 4512, a second electrode layer 4513, and a second electrode layer 4514. The laminated structure of the light emitting element 4513 is not limited to the structure shown in FIG. The configuration of the light emitting element 4511 can be changed as appropriate in accordance with the direction of light.

[0511] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0512] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0513] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon oxynitride film, DLC film, etc. can be formed.

[0514] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0515] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer of the second insulating film are formed from the same conductive film as those of the first insulating film and the second insulating film.

[0516] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0517] The substrate located in the direction in which light from the light emitting element 4511 is extracted must be light-transmitting. In this case, a glass plate, a plastic plate, a polyester film or an acrylic film A light-transmitting material such as tungsten is used.

[0518] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0519] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0520] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0521] With the above structure, a thin-film transistor having a highly purified oxide semiconductor layer and a reduced off-current can be obtained. A display device using a thin film transistor with reduced off-current can be provided. Since the pixel is applied to the storage capacitor, the period during which the storage capacitor can store the voltage can be extended. As a result, a display device that operates stably when displaying still images and consumes less power can be provided. .

[0522] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0523] (Embodiment 12) In this embodiment mode, one mode of a display device in which a luminous layer is provided in a pixel portion will be described with reference to FIG. explain.

[0524] FIG. 18 is a cross-sectional view of a pixel part of a bottom emission structure. 7 is a cross-sectional view of a section including a light-emitting element 7212. FIG.

[0525] The driving TFT 7211 has an insulating layer, an oxide semiconductor layer, a source electrode layer, and a drain electrode layer on a substrate. The gate electrode layer, the gate insulating layer, and the gate electrode layer are formed on the source electrode layer and the drain electrode layer. A wiring layer is provided so as to be electrically connected to each other.

[0526] An insulating layer 7231 is formed to cover the driving TFT 7211. The light-transmitting conductive film 7217 is a light-storing layer having an opening. An overcoat layer 7234 formed over the layer 7233 and an insulating layer 7235 are formed on the The drain electrode 7230 and the conductive film 7217 of the driving TFT 7211 are Through the openings formed in the overcoat layer 7234, the insulating layer 7235, and the insulating layer 7231, The first electrode 7212 of the light-emitting element 7212 is formed on the conductive film 7217 and electrically connected to the conductive film 7217. 213 is adjacent to it.

[0527] The driving TFT 7211 and the light emitting element 7212 are manufactured by the method described in the eleventh embodiment. Therefore, detailed description will be omitted here.

[0528] The light-storing layer 7233 contains a light-storing material and stores the light emitted by the adjacent light-emitting element. Even after the light is turned off, the phosphorescent material contained in the phosphorescent layer 7233 continues to emit light. In this study, copper activated zinc sulfide (ZnS:Cu) is used as the phosphorescent material. The phosphors are made of sulfides such as strontium (SrS) and activators added to the host material, and rare earth activated aluminum. Potassium earth aluminates CaAl2O4:Eu, CaAl2O4:Nd, Sr4Al 14 O 25 :Eu, Sr4Al 14 O 25:Dy, SrAl2O4:Eu, and SrAl 2O4:Dy, etc. may also be used.

[0529] The time that the phosphorescent layer 7233 continues to emit light can be changed depending on the type of phosphorescent material used. The amount of time the light continues to emit, or what is called afterglow time, varies depending on the type of phosphorescent material, so it is important to choose the right one for your application. For example, if the display content does not need to be frequently rewritten, For the display device, a phosphorescent material with a long afterglow time can be selected and used. In this case, a phosphorescent material with a short afterglow time should be selected. When the particles are inorganic particles, the particle size is 1 nm to 10 μm, preferably 10 nm to 5 μm. If the particle size is 1 nm or less, the phosphorescence effect is lost, and if the particle size is 10 μm or less, the phosphorescence effect is lost. If the thickness is more than this, the flatness of the phosphorescent layer will be impaired, making it difficult to fabricate the light-emitting element. It is.

[0530] In this embodiment, the luminous layer 7233 contains a binder polymer and has a luminous material dispersed therein. The dispersion liquid is then subjected to a droplet ejection method such as an inkjet method, a printing method, a spin coating method, and a photolithography method. The method is appropriately selected, such as an etching method using lithography technology.

[0531] The phosphorescent layer 7233 is covered with an overcoat layer 7234. It is covered with an insulating layer 7235. In FIG. 18, the overcoat layer 7234 is illustrated as having a thin film thickness. However, the overcoat layer 7234 has the function of flattening the unevenness of the phosphorescent layer 7233. do.

[0532] The position where the phosphorescent layer is provided is not limited to between the user of the display device and the light emitting element. For example, A light-emitting element having a dual emission structure in which an EL layer is sandwiched between a pair of light-transmitting electrodes has light-transmitting properties. In this way, when the light emitting element has a light transmitting property, the phosphorescent layer is not emitting light when viewed from the user of the display device. In other words, it can be placed between the phosphorescent layer and the user of the display device. A light-emitting element can be arranged between the user of the display device and the phosphorescent layer. For example, the phosphorescent layer does not necessarily have to be transparent, which broadens the range of phosphorescent materials that can be selected. Specifically, it will become possible to use phosphorescent materials with particle sizes of 100 μm or less.

[0533] With the above-mentioned configuration, a thin-film transistor having a phosphorescent layer and a highly purified oxide semiconductor layer in a pixel portion is formed. A display device using the thin-film transistor having a reduced off-current can be provided. Since a transistor is applied to the pixel, the period during which the storage capacitor provided in the pixel can store the voltage As a result, the operation when displaying still images etc. is stable and the display consumes less power. The device can be provided.

[0534] In addition, one embodiment of the present invention is a self-luminous display device capable of displaying an image with excellent visibility even in an environment with weak external light. In addition, since the pixel portion has a phosphorescent layer using a phosphorescent material, the display device can be provided with a light-emitting element. It is possible to provide a display device in which flicker is not noticeable even if the light emission interval of the optical element is long. In addition, even in an environment with weak external light, the light-emitting element is driven to provide energy to the phosphorescent material. Therefore, it is possible to provide a display device that can be used continuously for a long period of time.

[0535] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0536] (Embodiment 13) In this embodiment, an electronic device including the display device described in the above embodiment is used as an example. We will explain about this.

[0537] FIG. 19A shows a portable game machine, which includes a housing 9630, a display unit 9631, and a speaker 9633. , operation keys 9635, a connection terminal 9636, a recording medium reading unit 9672, etc. The portable game machine shown in FIG. 19(A) can be used to play a program or data recorded on a recording medium. The function of reading the data and displaying it on the display unit, and the function of sharing information with other portable gaming machines through wireless communication The portable gaming machine shown in FIG. 19(A) has the following functions. The functions are not limited to these, and various functions can be provided.

[0538] FIG. 19B shows a digital camera having a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, connection terminal 9636, shutter button 9676, image receiving unit 9677 , etc. The digital camera with a television receiving function shown in FIG. 19(B) can have the following: Functions for taking still images, shooting videos, and automatically or manually correcting captured images Functions, such as acquiring various information from the antenna, capturing images, or acquiring information from the antenna The function to save the captured information, the function to display the captured image or the information obtained from the antenna on the display. In addition, the digital camera with a television receiving function shown in FIG. The functions of the mobile camera are not limited to those described above, and the mobile camera may have a variety of functions.

[0539] FIG. 19C shows a television receiver, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, etc. A television receiver has two functions: to process television radio waves and convert them into image signals, and to process image signals and It has functions such as converting signals suitable for display and converting the frame frequency of image signals. Note that the functions of the television receiver shown in FIG. 19(C) are not limited to these. It can have a variety of functions.

[0540] FIG. 20A shows a computer, which includes a housing 9630, a display unit 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, pointing devices 9681, external connection points The computer shown in FIG. 20(A) can store various information. The function to display images (still images, videos, text images, etc.) on the display, A function to control processing by a program, a communication function such as wireless communication or wired communication, The ability to connect to various computer networks using the communication function, The function of transmitting or receiving data can be provided. The functions possessed by the computer are not limited to those described above, and the computer may have a variety of functions.

[0541] Next, FIG. 20B shows a mobile phone, which includes a housing 9630, a display portion 9631, and a speaker 963. 3, operation keys 9635, a microphone 9638, etc. FIG. 20(B) The mobile phone shown in has the following functions: A function to display the calendar, date, time, etc. on the display, and to operate or It has the functions of editing, controlling the processing by various software (programs), etc. However, the functions of the mobile phone shown in FIG. 20(B) are not limited to these. It can have a variety of functions.

[0542] Next, FIG. 20C shows an electronic paper (also called an E-book). The electronic pen 9630 may have a display unit 9631, operation keys 9635, etc. The user interface has the functions to display various information (still images, videos, text images, etc.), a calendar, , a function to display the date or time on the display unit, and a function to operate or edit the information displayed on the display unit Functions such as the ability to control processing using various software (programs) Note that the functions of the electronic paper shown in FIG. 20(C) are not limited to these. It can have a variety of functions.

[0543] The electronic device described in this embodiment has a plurality of pixels constituting a display unit, and the pixels are turned off. This reduces the current flow, and therefore the period during which the voltage can be held by the storage capacitor can be extended. The present invention provides a display device capable of reducing power consumption when displaying still images, etc. In addition, by improving the aperture ratio, a high-definition display can be realized. The display device may be a display device that displays the image.

[0544] In addition, one embodiment of the present invention is a self-luminous display device capable of displaying an image with excellent visibility even in an environment with weak external light. In addition, when a phosphorescent layer using a phosphorescent material is applied to the pixel portion, A display device in which flicker is not noticeable even if the light emission interval of a light emitting element is long can be provided. In addition, even in an environment with weak external light, the light-emitting element is driven to provide energy to the phosphorescent material. Therefore, it is possible to provide a display device that can be used continuously for a long period of time.

[0545] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0546] (Embodiment 14) In this embodiment mode, a block diagram of a display device and a procedure for stopping and starting the operation in a driver circuit are shown. First, a block diagram of the display device will be described with reference to FIG.

[0547] The display device 1000 described in this embodiment includes a display panel 1001, a signal generating circuit 1002, The display control circuit 1006 includes a memory circuit 1003, a comparison circuit 1004, a selection circuit 1005, and a display control circuit 1006. do.

[0548] The display panel 1001 includes, for example, a driver circuit portion 1007 and a pixel portion 1008 . The gate line driver circuit 1009A and the signal line driver circuit 1009B are included. 1009A and a signal line driver circuit 1009B drive a pixel portion 1008 having a plurality of pixels. A gate line driver circuit 1009A and a signal line driver circuit 1009B are also provided. The pixel portion 1008 and the pixel portion 1009 are formed of thin film transistors on the same substrate. It may also be something like that.

[0549] The gate line driver circuit 1009A, the signal line driver circuit 1009B, and the pixel portion 1008 are A part or all of the thin film transistors that are made of this material are n-channel transistors with an oxide semiconductor semiconductor layer. The gate line driving circuit 1007 uses a thin film transistor of a gate type. The signal line driver circuit 1009A and the signal line driver circuit 1009B may be formed on the same substrate. Alternatively, the second substrate 11 may be provided on a separate substrate.

[0550] The signal generating circuit 1002 includes a gate line driving circuit 1009A and a signal line driving circuit 1006B. From 09B, a pulse signal for outputting a signal for display in the pixel section 1008 is generated. The signal generating circuit 1002 outputs to the driving circuit section 1007 via wiring. A circuit for converting an image signal (also called a video voltage, a video signal, or video data) into a This is a circuit for outputting the signal to the memory circuit 1003 via a wiring. To generate and output a control signal for driving the 007 and an image signal to be supplied to the pixel unit This is the circuit.

[0551] Specifically, the signal generating circuit 1002 outputs a control signal to a gate line driving circuit 1009A, A high power supply potential Vdd and a low power supply potential Vss are applied to the signal line driver circuit 1009B. Also, a start pulse for the gate line driving circuit is supplied to the gate line driving circuit 1009A. SP, a clock signal CK is generated and output, and the signal line driving circuit 1009B is The signal generating circuit 1 generates and outputs a start pulse SP and a clock signal CK for the line. 002 outputs image signal data for displaying a moving image or a still image to a memory circuit 1003. To exert effort.

[0552] In addition, moving images are generated by switching multiple images at high speed over multiple frame periods. Specifically, it is an image that is recognized as a moving image by the eye 60 times per second (60 By switching images at least one frame, the human eye perceives the image as a moving image with less flicker. A still image is a continuous image signal that is sent over multiple frames. Although it operates by switching multiple images time-divided at high speed during a period, it is difficult to operate the camera during consecutive frame periods. For example, the image signal does not change between the nth frame and the (n+1)th frame. This means.

[0553] The signal generating circuit 1002 is also a circuit for generating other signals such as image signals and latch signals. The signal generating circuit 1002 may also include a gate line driving circuit 1009A and / or a signal The signal line driver circuit 1009B is provided with a reset signal to stop the output of the pulse signal of each driver circuit. Each signal may be a first clock signal, a second clock signal, or a second clock signal. The signal may be a signal composed of multiple signals such as a clock signal.

[0554] The high power supply potential Vdd is a potential higher than the reference potential, and the low power supply potential is a potential higher than the reference potential. Note that both high and low power supply potentials are at the same potential level at which a transistor operates. It is desirable that the potential be as high as possible.

[0555] Voltage refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible.

[0556] The image signal output from the signal generating circuit 1002 to the memory circuit 1003 is an analog signal. In this case, the signal is converted into a digital signal via an A / D converter or the like and stored in the memory circuit 1003. It is sufficient to configure the device to output the signal.

[0557] The memory circuit 1003 includes a plurality of frame memory circuits for storing image signals for a plurality of frame periods. The number of frame memories in the memory circuit 1003 is not particularly limited. Any element capable of storing image signals for multiple frame periods can be used. The frame memory is, for example, a DRAM (Dynamic Random Access Memory). ss Memory), SRAM (Static Random Access Mem The memory element may be configured using a memory device such as a memory cell.

[0558] The frame memory 1010 may be configured to store an image signal for each frame period. The number of frame memories is not particularly limited. The image signal of 0 is selectively read out by the comparison circuit 1004 and the selection circuit 1005. That is why.

[0559] The comparison circuit 1004 compares the image signals of successive frame periods stored in the memory circuit 1003. This is a circuit for selectively reading out the image signals, comparing them, and detecting the difference. When a difference is detected by the comparison of the image signals in the comparison circuit 1004, the difference is detected. In the consecutive frame periods, the image is judged to be a moving image. When no difference is detected by comparing the signals, the consecutive frames in which the difference is not detected are In other words, the comparison circuit 1004 detects the difference between the still image and the still image. whether the image signals for successive frame periods are image signals for displaying a moving image, or It is judged whether the signal is an image signal for displaying a still image. When the difference obtained by the comparison exceeds a certain level, it is determined that a difference has been detected. It may be set as follows.

[0560] The selection circuit 1005 includes a plurality of switches, for example, switches formed of thin film transistors. When an image signal for displaying a moving image is judged by detecting a difference in the comparison circuit, The image signal is selected from the frame memory 1010 in which the image signal is stored, and the display control circuit 1014 controls the image signal to be displayed. The comparison circuit 1004 outputs the inter-frame difference signal to the line 1006. If no difference in the image signal is detected, the image displayed between the frames is a still image. In this case, the image signal for the frame period is not output to the display control circuit 1006. This can be done as follows.

[0561] The display control circuit 1006 receives an image signal, a high power supply potential Vdd, a low power supply potential Vss, a start potential Regarding the control signals of the pulse SP, the clock signal CK, and the reset signal Res, This is a circuit for switching on or off the supply to the comparison circuit 100. 4. When it is determined that the image is a moving image, that is, when the difference between the image signals of consecutive frames is extracted, An image signal is supplied from a selection circuit 1005 to a drive circuit 1006 via a display control circuit 1006. The control signal is supplied to the driving circuit unit 1007 via the display control circuit 1006. On the other hand, the comparator circuit 1004 judges the image to be a still image, i.e., a continuous frame. When the difference between the image signals during the frame period is not extracted, the image signal is supplied from the selection circuit 1005. Therefore, the image signal is not supplied from the display control circuit 1006 to the driver circuit 1007. The display control circuit 1006 stops supplying the control signal to the drive circuit unit 1007 .

[0562] In addition, when it is determined that the image is a still image, if the period during which the image is determined to be a still image is short, the control Of the signals, the high power supply potential Vdd and the low power supply potential Vss may not be stopped. The power consumption caused by frequently stopping and restarting the high power supply potential Vdd and the low power supply potential Vss This is advantageous because it can reduce the increase.

[0563] The image signal and the control signal are stopped when each pixel of the pixel unit 1008 can hold an image signal. It is preferable to supply the image signal again after the retention period of each pixel. In this case, the display control circuit 1005 is caused to re-supply the image signal and control signal that were previously supplied. It is sufficient to adopt such a configuration.

[0564] Note that the supply of a signal means supplying a predetermined potential to a wiring. The supply of a predetermined potential to the wiring to which a predetermined fixed potential is supplied, for example, a low power supply potential Vs The term "stopping a signal" refers to connecting a signal to a wiring that has a specified potential. This refers to cutting off the electrical connection to wiring connected to the board and leaving it in a floating state.

[0565] As described above, a thin film transistor having an oxide semiconductor layer has a channel length of 10 μm. The off-current per 1 μm of channel width is 1 aA (1 × 10 -18 A) Below (this is expressed as 1 aA / μm), the retention period can be made longer. Therefore, in order to reduce power consumption when displaying a still image in this embodiment, A multiplier effect is expected.

[0566] As described above, the video signal is compared to determine whether it is a moving image or a still image, and the clock signal and start pulse are By selectively restarting or stopping the supply of control signals such as pulses to the drive circuit, low power consumption is achieved. It is possible to electrify the system.

[0567] Next, the gate line driver circuit 1009A and the signal line driver circuit 1009B of the driver circuit section 1007 are FIG. 26 shows an example of the configuration of the shift register that constitutes the above.

[0568] The shift register shown in FIG. 26A includes first pulse output circuits 10_1 to N-th pulse The shift register shown in FIG. The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are connected to a first wiring 1 A first clock signal CK1 is output from the first wiring 12, a second clock signal CK2 is output from the second wiring 13, and a third clock signal CK3 is output from the third wiring 14. A third clock signal CK3 is transmitted from the wiring 13, and a fourth clock signal CK 4 is supplied to the first pulse output circuit 10_1. The first start pulse SP1 (first start pulse) is input. In the output circuit 10_n (n is a natural number of 2≦n≦N), A signal (called the previous stage signal OUT(n-1)) (n is a natural number of 2 or more) is input. The pulse output circuit 10_1 receives a signal from a third pulse output circuit 10_3, which is two stages behind. Similarly, in the n-th pulse output circuit 10_n in the second stage or later, the (n The signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2) Therefore, the pulse output circuit of each stage outputs the pulses of the following stage and / or the two stages before it. A first output signal (OUT(1)(SR) to OUT(N)( SR), the second output signal (OUT(1) to OUT(N)) is output, which is input to another circuit, etc. As shown in FIG. 26(A), the last two stages of the shift register are Since the subsequent signal OUT(n+2) is not input, for example, A second start pulse SP2 is output from the first wiring 17, and a third start pulse SP3 is output from the seventh wiring 18. Alternatively, a signal generated inside a separate shift register may be input. For example, the (N+1)th pulse output circuit 10 that does not contribute to the pulse output to the pixel unit may be _(N+1), and a (N+2)-th pulse output circuit 10_(N+2) are provided (also called dummy stages). The second start pulse (SP2) and the third start pulse (SP3) are generated from the dummy stage. P3) may be generated.

[0569] The first clock signal (CK1) to the fourth clock signal (CK4) are generated at regular intervals. The first clock signal (CK1) through the fourth clock signal (CK2) are signals that alternate between H and L. The first clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal CK is used to control the driving of the G It is also called CK or SCK, but here we will explain it as CK.

[0570] In addition, when it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits, etc.). , wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, a given connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may be modified in any way without departing from the spirit or scope of the present invention. This also includes matters other than those involved.

[0571] Each of the first to N-th pulse output circuits 10_N has a first input A first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 26(B)). ).

[0572] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 26(A) and (B) are electrically connected to any one of the first through fourth wirings 14. In the first pulse output circuit 10_1, a first input terminal 21 is electrically connected to a first wiring 11. the second input terminal 22 is electrically connected to the second wiring 12, and the third input The terminal 23 is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10 _2, the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. Connected.

[0573] In addition, in FIG. 26(A) and (B), the first pulse output circuit 10_1 has a fourth input terminal A start pulse is input to the fifth input terminal 24, and a subsequent signal OUT(3) is input to the fifth input terminal 25. The first output terminal 26 outputs a first output signal OUT(1)(SR), and the second output The second output signal OUT( 1 ) is output from the input terminal 27 .

[0574] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0575] In FIG. 26C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39, and a gate electrode The second transistor 32 has a first terminal electrically connected to the fourth input terminal 24. The second terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. and a gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 22. The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is One terminal is electrically connected to the power supply line 52, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 52 and a third terminal electrically connected to the power supply line 52. The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has a first terminal electrically connected to the power supply line 51 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The seventh transistor 3 has a gate electrode electrically connected to the fifth input terminal 25. The seventh transistor has a first terminal electrically connected to the power supply line 51 and a second terminal electrically connected to the eighth transistor 38. The gate electrode is electrically connected to the second terminal and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and The gate electrode of the transistor 34 of the first input terminal 2 is electrically connected to the gate electrode of the transistor 34 of the second input terminal 2. The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. a second terminal of the second transistor 31 and a second terminal of the second transistor 32; The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a current. The gate electrode is electrically connected to the power supply line 51. The first terminal of the stator 40 is electrically connected to the first input terminal 21 and the second terminal of the stator 40 is electrically connected to the second output terminal 22. a gate electrode electrically connected to the second terminal of the ninth transistor 39; The eleventh transistor 41 has a first terminal electrically connected to the power supply line 52. The second terminal is electrically connected to the second output terminal 27, and the gate electrode of the second transistor The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. do.

[0576] In FIG. 26C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is defined as a node NA. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is a node Let's call it NB.

[0577] When the pulse output circuit in FIG. 26(C) is the first pulse output circuit 10_1, the first input A first clock signal CK1 is input to the input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the third input terminal 24. A start pulse SP is input to the fourth input terminal 24, and a The next stage signal OUT(3) is input, and the first output signal OUT(1) is output from the first output terminal 26. )(SR) is output, and the second output terminal 27 outputs the second output signal OUT(1). This will be the case.

[0578] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A timing chart is shown in FIG. 27. In addition, when the shift register is a gate line driving circuit, In FIG. 27, period 61 is a vertical blanking period, and period 62 corresponds to a gate selection period.

[0579] The example shown in Figs. 26 and 27 is fabricated using multiple n-channel transistors. In the driver circuit, the operation of displaying a still image to display a moving image, or the operation of displaying a pixel portion This is the operation of rewriting the light reflected from the EL element to the TFT that drives it (hereinafter referred to as the refresh operation). ) The procedure for supplying or stopping the potential of each wiring to the driver circuit section is shown in Figure 28. FIG. 28 shows the wiring for supplying a high power supply potential (Vdd) to the shift register, A wiring for supplying a power supply potential (Vss), a wiring for supplying a start pulse (SP), and a first A wiring for supplying the fourth clock signal (CK4) through a wiring for supplying the fourth clock signal (CK1). FIG. 13 is a diagram showing changes in potential of a wiring before and after a period (T1).

[0580] In the display device of the present embodiment, the display of moving images, the display of still images, or the refresh operation As a result, still images can be displayed without constantly operating the drive circuit section. As shown in FIG. 28, a high power supply potential (Vdd), a first clock signal, and a second clock signal are applied to the shift register. A fourth clock signal (CK1) to a fourth clock signal (CK4), and control signals such as a start pulse are provided. There is a period during which the control signal is supplied and a period during which the control signal is not supplied. 1 is a period during which a control signal is supplied, i.e., a period during which a moving image is displayed and a period during which a refresh operation is performed. The period T2 shown in FIG. 28 corresponds to a period during which no control signal is supplied. That is, it corresponds to a period during which a still image is displayed.

[0581] In FIG. 28, the period during which the high power supply potential (Vdd) is supplied is not limited to the period T1. The first clock is provided over a period T1 to T2. During the period in which the signal (CK1) to the fourth clock signal (CK4) are supplied, dd) is supplied and before the high power supply potential (Vdd) is stopped. There are.

[0582] As shown in FIG. 28, the first clock signal (CK1) to the fourth clock signal (CK 4) Before the period T1 begins, the signal is set to a high potential and then to a constant cycle of the clock signal. After the period T1 ends, the clock signal starts oscillating as a low potential signal. It is sufficient to configure the process to end.

[0583] As described above, in the display device of the present embodiment, a high power supply voltage is applied to the shift register during the period T2. a first clock signal (CK1) to a fourth clock signal (CK4), The supply of control signals such as a start pulse is stopped. During the period in which the supply of the control signals is stopped, In this case, the transistors are turned on or off to control the output of the shift register. The pulse signal input to the shift register also stops. The power consumed in the pixel unit driven by the shift register can be reduced. It becomes possible.

[0584] Please note that the above refresh operation may cause deterioration of the image quality of the displayed still image. In the display device of the present embodiment, the EL element provided in each pixel The above-mentioned oxide semiconductor is used as a switching element for controlling the voltage applied to the driving TFT. This allows the off-state current to be reduced significantly. This reduces the fluctuation of the voltage applied to the TFT for driving the EL element provided in each pixel. In other words, the operation of the shift register stops when a still image is displayed. Even if the period is long, the deterioration of the image quality can be reduced. It is possible to maintain the quality of the still image displayed even if the duration is 3 minutes. For example, A display device that rewrites 60 times per second and refreshes once every 3 minutes Compared to display devices, it is possible to reduce power consumption to approximately 1 / 10,000.

[0585] The above-mentioned high power supply potential (Vdd) is stopped when the low potential power supply (Vs s), and the high power supply potential (Vdd) is stopped when the high power supply potential is The potential of the wiring to which the potential is supplied may be set in a floating state.

[0586] In addition, the potential of the wiring to which the high power supply potential (Vdd) is supplied is increased, that is, in the period T1, When increasing the power supply potential from a low power supply potential (Vss) to a high power supply potential (Vdd) before It is preferable to control the potential change of the wiring so that the gradient of the potential change of the wiring is If the change in potential is steep, it will become noise and an incorrect pulse will be output from the shift register. The shift register may be a shift register included in the gate line driving circuit. In some cases, the illegal pulse is a signal that turns on a transistor. The pulse changes the voltage applied to the TFT that drives the EL element, causing the image to change. In view of the above, in FIG. 28, the high power supply potential (Vdd) In particular, the rising edge of the signal is more gentle than the falling edge. In the display device of the present embodiment, when a still image is displayed in the pixel section, The supply of high power supply potential (Vdd) to the load register is stopped and re-supplied appropriately. In other words, the change in the potential of the wiring that supplies the high power supply potential (Vdd) is reflected in the pixels as noise. If the noise affects the display area, the noise directly leads to deterioration of the display image. In a display device, a change in the potential of the wiring (especially an increase in the potential) is reflected as noise in the pixel area. It is therefore important to control the intrusion of [Explanation of symbols]

[0587] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 17 Wiring 18 Wiring 51 Power line 52 Power line 61 period 62 period 100 pixels 101 Wiring 102 Wiring 102A Wiring 102B Wiring 103 Oxide semiconductor layer 104 Capacitive Line 105 Pixel electrode 106 Thin Film Transistor 108 Substrate temperature 111 Substrate 112 Base film 113 Gate insulating film 114 Oxide insulating layer 121 Insulating layer 200 boards 201 pixels 202 Pixel section 203 Scanning line driving circuit 204 Signal line driver circuit 251 period 252 period 261 period 300 Substrates 302 Gate insulating layer 303 Protective insulation layer 310 Thin-film transistor 311 Gate electrode layer 313 Channel formation region 314a High resistance source region 314b High-resistance drain region 315a Source electrode layer 315b Drain electrode layer 316 Oxide insulating layer 320 Substrate 322 Gate Insulation Layer 323 Protective Insulation Layer 330 Oxide Semiconductor Film 331 Oxide semiconductor layer 332 Oxide semiconductor layer 340 Substrate 342 Gate Insulation Layer 343 Protective Insulation Layer 345 Oxide Semiconductor Film 346 Oxide Semiconductor Layer 350 Thin Film Transistor 351 Gate electrode layer 352 Oxide semiconductor layer 355a Source electrode layer 355b Drain electrode layer 356 Oxide insulating layer 360 Thin Film Transistor 361 Gate electrode layer 362 Oxide semiconductor layer 363 Channel Formation Region 364a High resistance source region 364b High-resistance drain region 365a Source electrode layer 365b Drain electrode layer 366 Oxide Insulating Layer 370 Substrate 372a Gate insulating layer 372b Gate insulating layer 373 Protective Insulation Layer 380 Thin Film Transistor 381 Gate electrode layer 382 Oxide semiconductor layer 385a Source electrode layer 385b Drain electrode layer 386 Oxide Insulating Layer 390 Thin-film transistor 391 Gate electrode layer 392 Oxide semiconductor layer 393 Oxide Semiconductor Film 394 Substrate 395a Source electrode layer 395b Drain electrode layer 396 Oxide Insulating Layer 397 Gate Insulation Layer 398 Protective Insulation Layer 399 Oxide Semiconductor Layer 400 Substrates 402 Gate insulating layer 407 Insulating Layer 410 Thin Film Transistor 411 Gate electrode layer 412 Oxide semiconductor layer 414a wiring layer 414b wiring layer 415a Drain electrode layer 415b Drain electrode layer 420 Silicon substrate 422 Insulating layer 423 Aperture 424 Conductive layer 425 Thin Film Transistor 427 Conductive Layer 438 Wiring layer 450 Substrate 452 Gate insulation layer 457 Insulating Layer 460 Thin Film Transistor 461 Gate electrode layer 462 Oxide semiconductor layer 464 Wiring layer 465a Drain electrode layer 465a1 Drain electrode layer 465a2 Drain electrode layer 465b Drain electrode layer 468 Wiring layer 472a Gate insulating layer 1008 Pixel section 1009B Signal line driver circuit 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4542 Insulation layer 6400 pixels 6401 Switching transistor 6402 Driving transistor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Driving TFT 7002 Light emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7011 Driving TFT 7012 Light emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7021 Driving TFT 7022 Light emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7026 Electrode 7027 Conductive film 7029 Bulkhead 7030 Drain electrode layer 7031 Insulation layer 7033 Color Filter 7034 Overcoat layer 7035 Insulation layer 7040 Drain electrode layer 7041 Insulation layer 7043 Color Filter 7044 Overcoat layer 7045 Insulation layer 7051 Insulation layer 7053 Insulation layer 7055 Insulation layer 7211 Driving TFT 7212 Light emitting element 7217 Conductive film 7230 Drain electrode 7231 Insulation layer 7233 Luminous layer 7234 Overcoat layer 7235 Insulation layer 9630 Case 9631 Display section 9633 Speaker 9635 Operation Key 9636 Connection terminal 9638 Microphone 9672 Recording medium reading unit 9676 Shutter button 9677 Image receiving unit 9680 External connection port 9681 Pointing Device

Claims

1. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region located on the second insulating layer and functioning as wiring; a fifth conductive layer having a region located on the second insulating layer and functioning as wiring; the second conductive layer and the third conductive layer each have a single-layer structure, the fourth conductive layer is electrically connected to the second conductive layer through a first opening in the second insulating layer; the fifth conductive layer is electrically connected to the third conductive layer through a second opening in the second insulating layer; the first opening of the second insulating layer does not overlap with the oxide semiconductor layer; the second opening of the second insulating layer does not overlap with the oxide semiconductor layer; the first conductive layer has a region overlapping at least the entire oxide semiconductor layer, The first conductive layer has an overlap with the first opening of the second insulating layer.

2. a first conductive layer having a function as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region located on the second insulating layer and functioning as wiring; a fifth conductive layer having a region located on the second insulating layer and functioning as wiring; the second conductive layer and the third conductive layer each have a single-layer structure, the fourth conductive layer is electrically connected to the second conductive layer through a first opening in the second insulating layer; the fifth conductive layer is electrically connected to the third conductive layer through a second opening in the second insulating layer; the first opening of the second insulating layer does not overlap with the oxide semiconductor layer; the second opening of the second insulating layer does not overlap with the oxide semiconductor layer; the first conductive layer has a region overlapping at least the entire oxide semiconductor layer, the first conductive layer has an overlap with the first opening in the second insulating layer; the fourth conductive layer has a region extending in a direction parallel to a channel length direction of the transistor, The fifth conductive layer has a region extending in a direction parallel to a channel length direction of the transistor.

Images