Quantum Data Loader

Abstract

The present disclosure relates generally to the fields of quantum algorithms and quantum data loading, and more specifically to constructing quantum circuits for loading classical data into quantum states, which may reduce the computational resources of the circuit (e.g., the number of qubits, the depth of the quantum circuit, and the types of gates in the circuit).

Description

[Technical field]

[0001] The present disclosure relates generally to the fields of quantum algorithms and quantum data loading, and more specifically to constructing quantum circuits for loading classical data into quantum states, which may reduce the computational resources of the circuit (e.g., the number of qubits, the depth of the quantum circuit, and the types of gates in the circuit). [Background technology]

[0002] Many quantum machine learning and optimization algorithms load classical data into quantum states in order to use quantum procedures for tasks such as classification, clustering, or solving linear systems. This makes these algorithms far from recent because these loaders, also called quantum RAMs (QRAMs, Quantum Random Access Memories), are large and complex circuits, both in terms of the number of qubits and the depth of the quantum circuits. For example, classical QRAM circuits are O(n) deep, where n is the dimension of the vector that represents the classical data points. [Brief description of the drawings]

[0003] Embodiments of the present disclosure have other advantages and features that will become more readily apparent from the following detailed description and the appended claims, when taken in conjunction with the accompanying drawing examples.

[0004] [Figure 1A] FIG. 1 is a schematic diagram illustrating a quantum circuit used to load classical data into a quantum state using a single parameterized two-qubit gate (called BS), according to an embodiment. [Figure 1B] FIG. 1 is a schematic diagram of a quantum circuit used to load classical data into a quantum state using a single parameterized two-qubit gate (called BS) and its controlled version (called c-BS) according to different embodiments. [Diagram 2] FIG. 2 is a schematic diagram illustrating an example of applying a quantum data loader to estimate the distance (or equivalently, the dot product) between two data points, according to an embodiment. [Diagram 3] FIG. 13 is a schematic diagram illustrating an example of applying a quantum data loader to estimate the distance (or equivalently the dot product) between two data points, according to another embodiment. [Figure 4A] FIG. 2 is a schematic diagram illustrating an example of a hardware implementation of a quantum data loader using superconducting qubits, according to some embodiments. [Figure 4B] FIG. 2 is a schematic diagram illustrating an example of a hardware implementation of a quantum data loader using superconducting qubits, according to some embodiments. [Figure 5A] FIG. 1 is a schematic diagram illustrating a hardware implementation of a quantum data loader using linear optics, according to some embodiments. [Figure 5B] FIG. 1 is a schematic diagram illustrating a hardware implementation of a quantum data loader using linear optics, according to some embodiments. [Figure 6] FIG. 1 is a block diagram illustrating components of an exemplary computing system capable of reading instructions from a machine-readable medium and executing them on one or more processors (including quantum processors) according to an embodiment.

[0005] The drawings depict various embodiments for illustrative purposes only, and those skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods shown herein may be employed without departing from the principles described herein, for example, details of the BS gates may be modified. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] The figures and the following description relate to preferred embodiments for purposes of illustration only. It should be noted from the following discussion that alternative embodiments of the structures and methods disclosed herein are readily discernible as viable alternatives that may be employed without departing from the principles of the claims.

[0007] We describe herein novel circuit configurations for loading classical data into a quantum computer that can reduce both the number of qubits and the depth of the quantum circuit.

[0008] Part 1: How to load classical data into a quantum state In one embodiment, the classical data points are represented as n-dimensional vectors (x1, x2, ..., x n ), where x i is real and the Euclidean norm of a vector is 1. To present this aspect with clarity, we assume that n is a power of 2, however, our method can be generalized.

[0009] What we are describing is the classical data points (x1, x2, …, x n ) is a concrete implementation of a circuit that can efficiently create a quantum state that encodes this classical data, specifically involving the creation of the following state:

number

[0010] The first step is to find the classical data points (x1, x2, …, x n ) to a set of angles (θ1, θ2,…, θ n-1 ) classically. In one embodiment, the angle is calculated as follows:

[0011]

number

[0012] The first n / 2-1 values ​​(i.e., r1, r2, …, r n / 2-1 ), where the index j takes values ​​in the interval [1,n / 2] and is defined as follows:

number

number

[0013] The first n / 2-1 values ​​(i.e., θ1, θ2, …, θ n / 2-1 ), where the index j takes values ​​in the interval [1,n / 2] and is defined as follows:

number

[0014] There are similar methods for setting the angle values, which are in the same category as our method.

number

number

[0015] In some cases, a controlled version of the BS(θ) gate is used, called c-BS(θ). Similar to other controlled gates, this gate is defined as:

number

[0016] In other words, this is a three-qubit gate where if the first qubit (the control qubit) is in the |0> state then an identity matrix (Id) is applied to the second and third qubits (the target qubits), and if the first qubit is in |1> then a (BS(θ)) gate is applied to the second and third qubits.

[0017] An exemplary method for constructing the circuit is as follows, which we refer to as a "parallel" loader. Start by initializing all qubits to the 0 state. In the first step, apply an X gate to the first qubit. Then, the circuit is constructed by adding BS gates hierarchically using the previously constructed angle θ. The first layer has one BS gate, the second layer has two BS gates, the third layer has four BS gates, and the lognth layer has n / 2 gates. The total number of BS gates is n-1, which is exactly the same as the number of previously calculated angles θ. The qubits to which gates are added follow a tree structure (e.g., a binary tree structure). For the first layer there is one BS gate between qubit (0,n / 2) with angle θ1, for the second layer there are two BS gates between (0,n / 4) with angle θ2 and (n / 2,3n / 4) with angle θ3, for the third layer there are four BS gates between (0,n / 8) with angle θ4, (n / 4,3n / 8) with angle θ5, (n / 2,5n / 8) with angle θ6 and (3n / 4,7n / 8) with angle θ7, and so on for the other layers.

[0018] FIG. 1A shows one specific implementation of our method for loading 8-dimensional data points (x1, x2, ..., x8). In FIG. 1A, T is the time step, q0-q7 are qubits, X is an X gate, and the vertical lines indicate which qubits the BS gate is applied to. Similar notations are used for FIG. 1B-3. In FIG. 1A, the X gate is applied to the qubit q0 in the first layer, and subsequent layers apply BS gates according to a binary tree pattern, with the root node of the tree being q0. The gate BS in FIG. 1A takes angles (θ1, θ2, ..., θ7) as parameters from left to right and from top to bottom, and can be calculated according to our description or similar. The number of qubits used in the quantum circuit, the depth of the circuit, and the number of gates for 2-qubit and 3-qubit are described below for different dimensions, but in general are as follows:

[0019] For 8 dimensions: number of qubits=8; depth=4; number of 2-qubit gates=7; number of 3-qubit gates=0.

[0020] For 1024 dimensions: number of qubits = 1024; depth = 11; number of 2-qubit gates = 1023; number of 3-qubit gates = 0.

[0021] n-dimension: number of qubits = n; depth = log(n) + 1; number of 2-qubit gates = n-1. Number of 3-qubit gates = 0.

[0022] Since the depth of a circuit may correspond to the execution time or time complexity of the circuit, a vector can be transformed into a quantum state in ∼O(log(n)).

[0023] The following is a description of an exemplary quantum circuit for a parallel loader: A quantum circuit is created for use in encoding an n-dimensional vector representing classical data into a quantum state of n qubits. The quantum circuit includes a first layer with n qubits, an X gate applied to one of the qubits, and multiple subsequent layers that apply BS gates to the qubits according to a binary tree pattern, where each BS gate is a single parameterized two-qubit gate, and the number of subsequent layers is Ceiling Function (log2(n)) Value of In some embodiments, the quantum circuit is part of a larger quantum circuit that includes additional layers.

[0024] JPEG0007649320000009.jpg106166

[0025] JPEG0007649320000010.jpg56166

[0026] The above structure can be made to work even when n is not a power of 4, or when, as mentioned above, the two sets of qubits are not of equal size (for example, when their sizes are t and n / t (note that the product of these still equals n)).

[0027] Figure 1B shows a set of 16-dimensional data points (x1, x2, …, x 16 Here we show one example implementation of our method for loading

[0028] The gates BS and c-BS in FIG. 1B are arranged with the angles (θ1, θ2, …, θ 15 ), which can be calculated according to our explanation or similar explanations. Note that the "@" denotes the control qubit for each c-BS gate.

[0029] Regarding the depth of the circuit of FIG. 1B, this can be improved by noting that many gates apply to different qubits (e.g., gates at times 4 and 8, or 5 and 7, etc.), and thus the total depth of the circuit is It can be relocated to become JPEG0007649320000011.jpg2251.

[0030] The number of qubits used in quantum circuits, the circuit depth, and the number of gates for 2-qubit and 3-qubit circuits are generally as follows:

[0031] JPEG0007649320000012.jpg26166

[0032] JPEG0007649320000013.jpg24166

[0033] JPEG0007649320000014.jpg74167

[0034] Part 2: Application examples of loading classical data into quantum states Below, we show how to use the quantum data loader described in Part 1 to perform several basic procedures that are useful, for example, in machine learning and optimization, among other applications, including: distance estimation, dot product estimation, linear algebra, classification, clustering, neural networks, and many more applications. These are only some of the possible applications, and further applications can be determined based on the methods disclosed herein. The following description uses a parallel loader for convenience. Other quantum data loader embodiments, such as a second loader, can also be used to perform these procedures.

[0035] JPEG0007649320000015.jpg32166

[0036] There are different types of distances between data points that can be defined, and in one embodiment, the distance between these two data points is defined as follows:

number

[0037] Figure 2 shows one concrete implementation of our method for estimating the distance between two 8-dimensional data points x = (x1, x2, ..., x8) and y = (y1, y2, ..., y8). In this implementation, the first gate BS on the left (at T = 1) is

number

[0038] The parameters of gate BS in the top half of the circuit in Figure 2 (related to q0-q7) are given by the vector (x1, x2,…,x n ) corresponds to the quantum data loader's parameters for the vectors (y1, y2, ..., y n), which corresponds to the parameters of the quantum data loader for T = 5. The final set of BS gates in the rightmost portion of Figure 2 (at T = 5) involves θ = π / 4. The final set of BS gates can be executed in parallel during a single time step.

[0039] The result of the circuit illustrated in Figure 2 is the following quantum state:

number

[0040] The number of qubits used in quantum circuits, the depth of the circuits, and the number of 2-qubit and 3-qubit gates are discussed below for different dimensions, but in general are as follows:

[0041] For 8 dimensions: number of qubits=16; depth=6; number of 2-qubit gates=23; number of 3-qubit gates=0.

[0042] For 1024 dimensions: number of qubits = 2048; depth = 13; number of 2-qubit gates = 3071; number of 3-qubit gates = 0.

[0043] n-dimension: number of qubits = 2n; depth = log(n) + 3; number of 2-qubit gates = 3n-1. Number of 3-qubit gates = 0.

[0044] Since the depth of a circuit may correspond to the execution time or time complexity of the circuit, the distance between two vectors can therefore be determined in ∼O(log(n)).

[0045] The following is a description of a quantum circuit according to a first embodiment: A quantum circuit is created for use in encoding a first n-dimensional vector representing classical data into a first quantum state of n qubits, encoding a second n-dimensional vector representing classical data into a second quantum state of n qubits, and determining a distance between the first n-dimensional vector and the second n-dimensional vector. The quantum circuit includes a first layer with 2n qubits and an X gate applied to one of the qubits, a first subsequent group of layers, and an additional layer. The first subsequent group of layers applies BS gates to the qubits according to a binary tree pattern, where each BS gate is a single parameterized two-qubit gate. The additional layer follows the first group and applies BS gates in parallel to pairs of qubits, where the first qubit in the pair is associated with a first quantum state and the second qubit in the pair is associated with a second quantum state. The number of layers in the circuit is: Ceiling Function (log2(n)+3) Value of In some embodiments, the quantum circuit is part of a larger quantum circuit that includes more layers.

[0046] JPEG0007649320000019.jpg43166

[0047] Figure 3 shows one specific implementation of our method for estimating the distance between two 8-dimensional data points x=(x1,x2,...,x8) and y=(y1,y2,...,y8). In this implementation: the first half of the circuit corresponds to a parallel loader for vector x, normalized as in 1A, and the second half of the circuit corresponds to the complex conjugate of the loader for vector y. In other words, the circuit is created by reversing the gate order for the loader for y and conjugating each gate.

[0048] JPEG0007649320000020.jpg59166

[0049] JPEG0007649320000021.jpg42166

[0050] The number of qubits used in quantum circuits, the depth of the circuits, and the number of 2-qubit and 3-qubit gates are discussed below for different dimensions, but in general are as follows:

[0051] For 8 dimensions: number of qubits=8; depth=7; number of 2-qubit gates=14; number of 3-qubit gates=0.

[0052] For 1024 dimensions: number of qubits = 1024; depth = 21; number of 2-qubit gates = 2046; number of 3-qubit gates = 0.

[0053] n-dimension: number of qubits=n; depth=2log(n)+1; number of 2-qubit gates=2n-2; number of 3-qubit gates=0.

[0054] Therefore, the time complexity of this circuit can be kept within .about.O(2log(n)). Although the time complexity is doubled compared to the first embodiment, the number of qubits is halved.

[0055] The following is a description of a quantum circuit according to a second embodiment: A quantum circuit is created for use in encoding a first n-dimensional vector representing classical data into a first quantum state of n qubits, encoding a second n-dimensional vector representing classical data into a second quantum state of n qubits, and determining a distance between the first n-dimensional vector and the second n-dimensional vector. The quantum circuit includes a first layer with n qubits and an X gate applied to one of the qubits, a first group of subsequent layers, and a second group of subsequent layers. The first group of subsequent layers applies BS gates to the qubits according to a binary tree pattern, where each BS gate is a single parameterized two-qubit gate. The second group of subsequent layers applies conjugate BS gates to the same qubits according to the inverse of the binary tree pattern, where each BS gate is a single parameterized two-qubit gate. The number of layers is: Ceiling Function (2log2(n) + 1) Value of In some embodiments, the quantum circuit is part of a larger quantum circuit that includes additional layers.

[0056] 2. Inner product estimation The distance between two data points and their dot product are related by the following mathematical formula:

number

[0057] 3. Matrix-Matrix Multiplication The quantum method for dot product estimation described above can be used to provide applications in linear algebra, specifically matrix multiplication, where we consider the case where we need to compute C=AB for two matrices A and B. In one embodiment, the method can be embodied in a hybrid classical-quantum manner, where each row A of a matrix i and each column of the matrix B j For C, we use a quantum method for estimating the inner product. ij= A i B j We can calculate each element of the matrix C as follows:

[0058] By performing matrix multiplication via the distance estimation method described above, the operation has a time complexity of ∼O(n 2 log(n)) time complexity is ~O(n 3 ), this is a significant improvement over the traditional matrix multiplication algorithm.

[0059] 4. Classification The distance estimation method described above can be readily used to provide classification applications, one example of which among many possible implementations will now be described.

[0060] In one embodiment, a known nearest centroid algorithm may be used, where the data points are classified by calculating the distance of the data point to all centroids and selecting the centroid with the smallest distance. The distance estimation method described above may be used to yield a hybrid classical-quantum classification algorithm, where the data points are classified using the quantum method described in connection with FIG. 2 or FIG. 3.

[0061] 5. Clustering The distance estimation method described above can be readily used to provide clustering applications. One example of many possible implementations will now be described.

[0062] In one embodiment, a hybrid classical-quantum algorithm based on the well-known k-means algorithm may be used, in which case the quantum distance estimation method described above in connection with Figure 2 or Figure 3 may be used both to assign data points to centroids (as in classification) and to update the centroids, in the context of the case where matrix-matrix multiplication is used.

[0063] 6. Training and evaluation of neural networks The dot product estimation method described above can be used to provide an application involving neural networks, one example of which among many possible implementations will now be described.

[0064] In one embodiment, a hybrid classical-quantum algorithm based on well-known feedforward and backpropagation algorithms may be used, in which case the quantum distance estimation method described above in connection with Figures 2 and 3 may be used both to multiply the matrices and weights of the data points during evaluation and during the backpropagation algorithm (and possibly the gradient descent algorithm), again in the context of the case where matrix-matrix multiplication is used.

[0065] It should be noted that alternative embodiments of our methods disclosed herein are readily recognized as viable alternatives that may be employed without departing from the principles of the disclosure.

[0066] Part 3: Hardware implementation example of a quantum data loader Below is described how the quantum data loader can be implemented using different types of current quantum hardware, including superconducting qubits or photonics. These are just some of the possible hardware implementations, and many more could be more easily built based on the same methods described here, or different qubit technologies such as trapped ions or atoms.

[0067] 1. Implementation with superconducting qubits A gate in the family called BS(θ) can be used to couple two superconducting qubits in a manner that makes the following gate directly applicable for any parameter θ:

number

[0068] Thus, the quantum data loader described in Part 1 could be implemented using these gates, but new connectivity would be required in relation to the current connectivity of superconducting qubit machines that are connected as a 2-D grid.

[0069] Our proposal for a quantum data loader may require superconducting qubits connected in a tree structure (rather than a grid) and capable of applying the BS(θ) family of gates mentioned above.

[0070] There are many different alternatives for arranging qubits in a 2-D plane to entail tree-structured connections, and in Figure 4A we disclose an example architecture for a quantum data loader for 32-dimensional vectors using 35 qubits in a grid of dimensions 9x5 (32 corresponds to the number of qubits required for the loader, with an additional 3 qubits to fit the loader into the grid with some qubit repetition). Figure 4B illustrates how the 32 dimensions are mapped onto the qubits of the grid. Many alternative embodiments are possible, all of which follow our method with embedded tree-structured connectivity.

[0071] In Figures 4A and 4B, "O" corresponds to a superconducting qubit, and a horizontal (--) or vertical (|) connection corresponds to the ability to perform a BS(θ) gate between pairs of qubits.

[0072] 2. Example implementation involving linear optics Gates in the family referred to as BS(θ) can also be implemented in a linear optics scheme by implementing a reconfigurable beam splitter, also referred to as an adjustable beam splitter or adjustable Mach-Zender interferometer.

[0073] In FIG. 5A, according to an embodiment, the reconfigurable beam splitter is implemented as a partially reflecting mirror.

[0074] In Figure 5B, such a reconfigurable beam splitter is represented as a gate with two inputs and two outputs performing the BS(θ) family of operations. The reconfigurable beam splitter has a parameter θ (not shown), which corresponds to the ratio of reflectance to transmittance (e.g., it splits the combined light, cos(θ) is reflected and sin(θ) is transmitted). The quantum data loader described in Part 1 can then be implemented using a single photon source, a reconfigurable beam splitter, and a photon detector.

[0075] In some embodiments, the quantum data loader may be implemented in an integrated photonic chip.

[0076] Although there are many different alternative architectures for providing tree-structured connectivity, Figures 5A and 5B disclose an example architecture for a photonic linear optics scheme that may be used as a quantum data loader. Many alternative embodiments of our method with tree-structured connectivity are possible.

[0077] FIG. 6 is a block diagram illustrating components of an exemplary computing system that can read instructions from a machine-readable medium and execute them on one or more processors (or controllers) (including quantum processors) according to some embodiments. In particular, FIG. 6 illustrates a diagrammatic representation of a computer system 600. The computer system 600 can be used to execute instructions 624 (e.g., software) that cause the computing system to perform any one or more of the methodologies (or processes) described herein, such as method 100. In some embodiments, the computing system can operate as a standalone device or as a device connected (e.g., networked) with other machines. In a networked deployment, the computing system can operate in the role of a server machine or a client machine in a server-client network environment, or as a peer machine in a P2P (or distributed) network environment. It is noted that FIG. 6 and its description describe an exemplary device. Other computing systems with quantum processors may behave differently and may have more, fewer, or different components.

[0078] The exemplary computer system 600 includes one or more processing units, such as processors 601, 602. For example, the conventional processor 602 can be a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a controller, a state machine, one or more application specific integrated circuits (ASICs), or any combination thereof.

[0079] Quantum processor 601 may be one or more physical devices that perform operations based on quantum effects, one or more devices with such behavior, or any other device that may be reasonably interpreted as exhibiting quantum processing behavior. Quantum processor 601 exploits the laws of quantum mechanics to perform operations. Quantum processor 601 generally uses qubits (qubits, quantum bits) instead of bits used in classical computers. Classical bits are always either 0 or 1 in value. Roughly speaking, qubits have a nonzero probability of being in a superposition or linear combination of 0 and 1. Because quantum processor 601 can perform operations on qubits, allowing qubits to exist in a superposition of 0 and 1 can result in greatly enhanced performance for certain computational tasks. For example, Shor's algorithm describes how to use a quantum processor to efficiently factor large integers, which has considerable applications and implications in cryptography. Grover's search algorithm describes how to use a quantum processor to efficiently search large sets of information, such as lists and databases.

[0080] Quantum processor 601 may be capable of constructing and executing one or more quantum circuits 626. A quantum circuit is a model of a quantum computation, which is a sequence of quantum gates, which are reversible transformations on one or more qubits.

[0081] The computer system 600 also includes a main memory 604. The computer system may include a storage unit 616. The processors 601, 602, the memory 604, and the storage unit 616 communicate over some communication medium 608. For example, a conventional processor 602, the main memory 604, and the storage unit 616 may communicate over a bus, while the processors 602 and 601 may communicate with each other over separate dedicated communication paths.

[0082] Additionally, computer system 600 may include static memory 606 and a display driver 610 (which may drive a plasma display panel (PDP), liquid crystal display (LCD), or projector that may display UI 105 to a user). Computer system 600 may also include an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse, trackball, joystick, motion sensor, or other pointing device), a signal generating device 618 (e.g., a speaker), and a network interface device 620, which are also configured to communicate over communication medium 608.

[0083] The storage device 616 includes a machine-readable medium 622 having stored thereon instructions 624 (e.g., software) embodying any one or more of the methodologies or functions described herein. The instructions 624 may also reside, completely or at least partially, in the main memory 604 or in the processor 601 (e.g., in a processor's cache memory) during execution by the computer system 600, and the main memory 604 and the processor 601 may involve machine-readable media. The instructions 624 may be executed in part by the quantum circuit 626 using the methods described above. The instructions 624 may be transmitted or received over a network 626 via the network interface device 620.

[0084] While machine-readable medium 622 is shown to be a single medium in the exemplary embodiment, the term "machine-readable medium" should be considered to include a single medium or multiple media capable of storing instructions 624 (e.g., a centralized or distributed database, or associated caches and servers). The term "machine-readable medium" should also be considered to include any medium capable of storing instructions 624 for execution by a machine, causing the machine to perform any one or more of the methodologies disclosed herein. The term "machine-readable medium" includes, but is not limited to, data repositories in the form of solid-state memory, optical media, and magnetic media.

[0085] Although the detailed description includes many specific details, these should not be interpreted as limiting the scope of the present invention, but merely as illustrating different examples. It should be noted that the scope of the present disclosure also includes other embodiments not described in detail above. Various other modifications, changes, and variations that will be apparent to those skilled in the art can be made in the arrangement, operation, and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined in the appended claims. Therefore, the scope of the present invention should be determined by the appended claims and their legal equivalents.

Claims

1. 1. A quantum circuit for use in encoding an n-dimensional vector representing classical data into a quantum state of n qubits, the quantum circuit comprising: n qubits, a first layer comprising an X-gate applied to one of the qubits; A number of subsequent layers of applying BS gates to the qubits according to a binary tree pattern, where each BS gate is a single parameterized two-qubit gate, and the number of subsequent layers is a ceiling function (log 2 (n)) of the number of subsequent layers, A quantum circuit comprising:

2. 2. The quantum circuit of claim 1, wherein n is a power of two.

3. 2. The quantum circuit of claim 1, wherein a root node of the binary tree pattern is a qubit to which an X gate is applied.

4. 10. The quantum circuit of claim 1, wherein a total number of qubits in the quantum circuit does not exceed n.

5. 2. The quantum circuit of claim 1, wherein the total number of BS gates in the quantum circuit does not exceed n-1.

6. 3. The quantum circuit of claim 2, wherein the number of the plurality of subsequent layers is the base 2 logarithm of n.

7. 2. The quantum circuit of claim 1, wherein each BS gate is of the form: [0010] 。

8. 8. The quantum circuit of claim 7, wherein n is a power of 2, and the n-dimensional vector is (x 1 , x 2 , …, x n ) and as j goes from 1 to n / 2-1, [0025] [0030]

9. 10. The quantum circuit of claim 1, wherein the qubit is a superconducting qubit.

10. 10. The quantum circuit of claim 1, wherein the BS gate is implemented as a reconfigurable beam splitter.

11. 1. A quantum circuit for use in encoding an n-dimensional vector representing classical data into a quantum state, the quantum circuit comprising: [0045] The first group of qubits and [0050] A second group of qubits; and a first layer comprising first X-gates applied to qubits in the first group and second X-gates applied to qubits in the second group; a first plurality of subsequent layers applying BS gates to said first group of qubits according to a binary tree pattern, each BS gate being a single parameterized two-qubit gate; a second plurality of subsequent layers applying control BS gates (c-BS gates) to qubits in the first and second groups, each c-BS gate applying a BS gate to a qubit in the second group and controlled by a qubit in the first group; The number of layers is Ceiling Function 【number】 A quantum circuit that does not exceed the value of

12. 12. The quantum circuit of claim 11, wherein the second plurality of subsequent layers includes a group of c-BS gates. [006] wherein each group of c-BS gates applies BS gates to the second group of qubits according to a binary tree pattern.

13. 13. The quantum circuit of claim 12, wherein c-BS gates in the same group are controlled by the same qubit in the first group.

14. 13. The quantum circuit of claim 12, wherein the root node of each binary tree pattern in each group of c-BS gates is a qubit in the second group of qubits to which an X gate is applied.

15. 12. The quantum circuit of claim 11, wherein a root node of the binary tree pattern is a qubit in the first group of qubits to which an X gate is applied.

16. 12. The quantum circuit of claim 11, wherein n is a power of four.

17. 12. The quantum circuit according to claim 11, wherein the number of the BS gates is [0070] Quantum circuits that do not exceed.

18. In the quantum circuit according to claim 11, the number of the c-BS gates is [0080] Quantum circuits that do not exceed.

19. 12. The quantum circuit of claim 11, wherein the qubit is a superconducting qubit.

20. 12. The quantum circuit of claim 11, wherein the BS gate is implemented as a reconfigurable beam splitter.

21. 1. A quantum circuit for use in encoding a first n-dimensional vector representing classical data into a first quantum state of n qubits, encoding a second n-dimensional vector representing classical data into a second quantum state of n qubits, and determining a distance between the first n-dimensional vector and the second n-dimensional vector, the quantum circuit comprising: 2n qubits, a first layer comprising an X-gate applied to one of the qubits; a first subsequent layer group for applying BS gates to the qubits according to a binary tree pattern, each BS gate being a single parameterized two-qubit gate; an additional layer after the first group that applies BS gates to pairs of qubits in parallel, where a first qubit in the pair is associated with a first quantum state and a second qubit in the pair is associated with a second quantum state; A quantum circuit in which the number of layers does not exceed the value of the ceiling function (log2(n) + 3).

22. 22. The quantum circuit of claim 21, wherein n is a power of two.

23. 22. The quantum circuit of claim 21, wherein a root node of the binary tree pattern is a qubit to which an X gate is applied.

24. 22. The quantum circuit of claim 21 , wherein a total number of qubits in the quantum circuit does not exceed 2n.

25. 22. The quantum circuit of claim 21, wherein the total number of BS gates in the quantum circuit does not exceed 3n-1.

26. 23. The quantum circuit of claim 22, wherein the number of the first subsequent layers is the logarithm to the base 2 of n.

27. 22. The quantum circuit of claim 21, wherein each BS gate is of the form: [0090] 。

28. 28. The quantum circuit of claim 27, wherein for a first BS gate of the binary tree: [0010] That is, quantum circuits.

29. 28. The quantum circuit of claim 27, wherein θ=π / 4 for BS gates in the additional layer.

30. 22. The quantum circuit of claim 21 , wherein the probability of observing all zeros on the first n qubits is equal to the distance between the first n-dimensional vector and the second n-dimensional vector divided by four.

31. 1. A quantum circuit for use in encoding a first n-dimensional vector representing classical data into a first quantum state of n qubits, encoding a second n-dimensional vector representing classical data into a second quantum state of n qubits, and determining a distance between the first n-dimensional vector and the second n-dimensional vector, the quantum circuit comprising: n qubits, a first layer comprising an X-gate applied to one of the qubits; a first subsequent layer group for applying BS gates to the qubits according to a binary tree pattern, each BS gate being a single parameterized two-qubit gate; a second subsequent group of layers applying BS gates to the same qubits according to the inverse of the binary tree pattern; A quantum circuit in which the number of layers does not exceed the value of the ceiling function (2log2(n) + 1).

32. 32. The quantum circuit of claim 31 , wherein n is a power of two.

33. 32. The quantum circuit of claim 31 , wherein a root node of the binary tree pattern in the first subsequent layer group is a qubit to which an X gate is applied.

34. 32. The quantum circuit of claim 31 , wherein a root node of the binary tree pattern in the second subsequent layer group is a qubit to which an X gate is applied.

35. 32. The quantum circuit of claim 31 , wherein a total number of qubits in the quantum circuit does not exceed n.

36. 32. The quantum circuit of claim 31 , wherein the total number of BS gates in the quantum circuit does not exceed 2n−2.

37. 32. The quantum circuit of claim 31 , wherein a BS gate in the second subsequent group of layers is a conjugate gate of a BS gate in the first subsequent group of layers.

38. 32. The quantum circuit of claim 31 , wherein each BS gate in the first subsequent group is of the form: ##EQU00011## 。

39. 39. The quantum circuit of claim 38, wherein each BS gate in the second subsequent group of layers is of the form: ##EQU00012## 。

40. 32. The quantum circuit of claim 31 , wherein the number of BS gates in the second subsequent group of layers is equal to the number of BS gates in the first subsequent group of layers.

Images