Clock Distribution Network

Abstract

To provide a clock distribution network and a method of distributing a clock signal, for reducing the power consumption and extending the battery lifetime.SOLUTION: A clock distribution network 10 configured to generate a processor clock signal and a first peripheral clock signal includes: a clock generator 14 including a processor clock output 31, a first peripheral clock output 32 and a first clock request input 42; a processing unit 16 connected to the processor clock output and configured to operate on a rising edge of the processor clock signal receivable via the processor clock output; and a first peripheral unit 22 connected to the first peripheral clock output and to the first clock request input, and configured to operate on a falling edge of the first peripheral clock signal received via the first peripheral clock output. The first peripheral unit via the first clock request input actuates the clock generator to transmit the first peripheral clock signal via the first peripheral clock output.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a clock distribution network and a method for distributing a clock signal in a clock distribution network. [Background technology]

[0002] A digital processing system is typically provided with a frequency generating device, such as a clock source, that provides a master clock signal. The master clock signal is typically provided to clock dividers or clock generators that provide clock signals at different frequencies to peripheral devices of the digital processing system.

[0003] To exchange data between a processing device and an individual or peripheral device or between peripheral devices of a digital processing system, it is necessary that the data exchange devices are part of a common clock tree, e.g. a global clock tree. For the implementation of a global clock tree, it is generally necessary to provide many buffers and inverters. In this case, all flip-flops in such a global clock tree have to toggle simultaneously. This means a relatively high static and dynamic power consumption. In addition, since all logic is part of the same clock tree, the power consumption is also relatively high, which leads to a reduced battery life of the portable electronic device. Summary of the Invention [Problem to be solved by the invention]

[0004] It is therefore an object of the present invention to provide a clock distribution network and a method for distributing a clock signal in a digital processing system that enables reduced power consumption and extended battery life, particularly in portable electronic devices equipped with such a clock distribution network. [Means for solving the problem]

[0005] In one aspect, the present disclosure relates to a clock distribution network. The clock distribution network includes a clock generator configured to generate at least a processor clock signal and at least a first peripheral clock signal. The clock generator further includes at least a processor clock output, a first peripheral clock output, and a first clock request input. A processing device is connected to the processor clock output and configured to operate on a rising edge of the processor clock signal receivable via the processor clock output. In general, the processor clock signal is generated by the clock generator and transmitted through the processing device via the processor clock output.

[0006] The clock distribution network further includes at least a first peripheral device connected to the first peripheral clock output. The first peripheral device is further connected to a first clock request input of the clock generator. The at least first peripheral device is further configured to operate on a falling edge of the first peripheral clock signal received or receivable via the first peripheral clock output. Typically, a clock input of the first peripheral device is connected to the first peripheral clock output of the clock generator.

[0007] It is further provided that in the clock distribution network, at least a first peripheral device is operable to activate the clock generator such that the clock generator transmits the first peripheral clock signal via the first peripheral clock output. This request is generally transmitted via a first clock request input. Thus, the at least a first peripheral device is doubly connected to the clock generator. The clock input of the first peripheral device is connected to the first peripheral clock output of the clock generator to receive the first peripheral clock signal from the clock generator. Also, the first peripheral device is separately connected to the first clock request input of the clock generator. In this way, the first peripheral device is operable to transmit a clock generation request signal to the clock generator, thereby prompting the clock generator to generate the first peripheral clock signal and / or transmit the first peripheral clock signal via the first peripheral clock output to at least a first peripheral device of the clock distribution network.

[0008] Because the at least first peripheral device and the processing device operate on different edges of their respective clock signals, the clock distribution network may not need to establish and / or provide a global clock tree. Rather, in the present clock distribution network, the processing device and the at least first peripheral device or any further peripheral devices are not required to toggle simultaneously and participate in a common global clock tree to enable data transmission therebetween.

[0009] Rather, a data transfer communication link is established to each available peripheral device on or only on demand. In this manner, since the clock distribution network does not require the establishment of a global clock tree, the static and dynamic power consumption of the clock distribution network can be significantly reduced, thereby extending the battery life of portable electronic devices equipped with such a clock distribution network.

[0010] According to a further embodiment, the clock generator is configured to inhibit transmission of a first peripheral clock signal unless such a first peripheral clock signal is requested by at least a first peripheral device via a first clock request input. To that extent, transmission of a particular clock signal to a peripheral device can only be performed at the request of a respective peripheral device of the clock distribution network. If a peripheral device, for example at least a first peripheral device, does not request transmission of a respective clock signal via a respective clock request input of the clock generator, such a peripheral clock signal is not transmitted to the respective peripheral device. In this way, the respective clock distribution traffic and the energy or power for generating and / or transmitting such peripheral clock signals can be effectively saved, thereby reducing the static and / or dynamic energy consumption of the clock distribution network.

[0011] According to a further embodiment, the processing device is directly connected to at least a first peripheral device via a first transmission line. Thus, the processing device may be directly connected to the peripheral devices of the clock distribution network separately via respective transmission lines. By establishing or providing separate transmission lines, a fairly direct and unaltered communication between the processing device and the peripheral device or devices is provided.

[0012] According to a further embodiment, the clock distribution network is coupled to a second peripheral clock output of the clock generator and includes at least a second peripheral device coupled to a second clock request input of the clock generator, the second clock request input of the at least second peripheral device operable to operate the clock generator to transmit a second peripheral clock signal via the second peripheral clock output.

[0013] In some embodiments, the clock generator includes multiple clock outputs, each clock output being connected to at least one peripheral device. The first clock output can be connected to the first peripheral device. The second clock output can be connected to the second peripheral device. In general, the clock generator is operable to generate or derive multiple different clock signals from a master clock signal. Thus, a first peripheral clock signal transmitted to a first peripheral device may include a different frequency compared to a second peripheral clock signal transmitted to a second peripheral device. The frequency of each of the first and second peripheral clock signals depends on the implementation of the respective peripheral device.

[0014] Similar to the first peripheral device, the second peripheral device is also connected to a second clock request input of the clock generator. Similar to the at least first peripheral device, the at least second peripheral device is also operable to activate the clock generator to transmit a second peripheral clock signal. A respective trigger signal or clock generation request signal can be transmitted from the second peripheral device to the clock generator via the second clock request input. In response thereto, and thus upon receiving a respective second clock generation request signal from the at least second peripheral device via the second clock request input, the clock generator generates and / or transmits the requested second peripheral clock signal to the at least second peripheral device via the second clock output.

[0015] The clock distribution network is not limited to only the first and second peripheral devices. The clock distribution network may include n peripheral devices, where n is an integer greater than 2. In some embodiments, for each processing unit, the clock distribution network, and thus the clock generator, includes a plurality of n distinct clock outputs and a corresponding number of n clock request inputs connectable to respective peripheral devices of the clock distribution network.

[0016] In this manner, each peripheral device of the clock distribution network is individually connected to the clock generator and is operable to request generation and / or transmission of a respective clock signal.

[0017] According to a further embodiment, the processing device is directly connected to at least a second peripheral device via a second transmission line, which may be implemented in a similar manner as described above with respect to the first transmission line, by means of which the processing device may be operable to directly communicate and / or exchange data with the second peripheral device.

[0018] The processing device may not be limited to directly communicating only with the first and second peripheral devices. If the clock distribution network is provided with a relatively large number of individual peripheral devices, e.g. a number n of peripheral devices, the processing device may be implemented and configured to directly communicate with each one of the peripheral devices individually, i.e. via a respective transmission line. In this way, it is ensured that the processing device can directly communicate, e.g. exchange data, with any of the available peripheral devices.

[0019] According to a further embodiment, the first peripheral device includes a first local clock tree. The second peripheral device includes a second local clock tree. The first local clock tree operates independently from the second local clock tree. Additionally or alternatively, the second local clock tree operates independently from the first local clock tree.

[0020] Because the peripheral devices can operate on the falling edge of their respective peripheral clock signals received from the clock generator, the peripheral devices can operate completely independently of each other, and therefore there is no need to provide a global clock tree in which peripheral devices and / or their digital components toggle or operate simultaneously with other peripheral devices or their digital components.

[0021] In this way, the power consumption of the clock distribution network can be effectively reduced. In general, the local clock tree of a peripheral device is a clock tree connected to all logic components of the respective peripheral device, and the logic components need to operate on the common local clock tree to provide the desired logic operation.

[0022] By allowing the first peripheral device and the second peripheral device to operate on different local clock trees, it is not necessary to synchronize the clocks of the first and second peripheral devices, respectively. In this way, a means for synchronizing the local clocks of the first and second peripheral devices is no longer necessary. As a result, the respective hardware components, such as buffers, inverters or similar components, that are typically required to synchronize the local clock trees of the first and second peripheral devices are substantially eliminated. This may also lead to a reduction in the size of the clock distribution network.

[0023] According to a further embodiment, the clock distribution network comprises at least delay cells connected to the processor clock outputs and operable to delay the processor clock signal received by the processing unit by a predefined delay offset with respect to the processor clock signal generated and transmitted by the clock generator. By means of the delay cells, the operation of the clock generator is delayed by a fixed time offset and / or an adjustable time offset. Since the processing unit operates on the rising edge of the processor clock signal and the first and / or second peripheral device and any further optional peripheral devices operate on the falling edge of their respective clock signals received from the clock generator, a particularly robust communication and data exchange between the processing unit and each of the first and / or second peripheral devices can be provided even without a global clock tree.

[0024] The predetermined delay is typically provided by the clock generator for any combination of processing unit and available peripheral devices and is selected so as to not introduce spikes into the timing diagram of the clock signal received by either the processing unit and / or the peripheral devices.

[0025] According to a further embodiment, a first logic circuit is provided, connected to the first peripheral clock output and connected to the first peripheral device. The first logic circuit is operable to invert the first peripheral clock signal received from the clock generator and to transmit the inverted first peripheral clock signal to the first peripheral device. The first logic circuit may be provided or implemented only in such clock distribution network embodiments where there are no delay cells between the processor clock output and the processing device. The first logic circuit and the signal inversion optionally provided by the first logic circuit may be beneficial to avoid or suppress spikes in the timing diagram of multiple clock signals generated by the clock generator and transmitted and / or received by individual peripheral or processing devices.

[0026] In general, the first logic circuit is operable to invert the first peripheral clock signal only temporarily. The inversion of the first peripheral clock signal may be controlled and / or regulated by a comparison of the processor clock signal and the first peripheral clock signal. In this case, the first logic circuit actually inverts the first peripheral clock signal only at a predetermined relationship between the first peripheral clock signal and the processor clock signal. In other situations or conditions, the first logic circuit may be operable to simply transmit the first peripheral clock signal received from the clock generator to at least the first peripheral device unchanged.

[0027] According to a further embodiment, the first logic circuit is coupled to the processor clock output and is further operable to invert the first peripheral clock signal and transmit the inverted first peripheral clock signal to the first peripheral device when the processor clock signal is less than the first peripheral clock signal received from the clock generator. This operation of the first logic circuit may help to avoid spikes in the timing diagram or the clock signal received by the first peripheral device.

[0028] According to a further embodiment, the first logic circuit includes a multiplexer having a first multiplexer input, a second multiplexer input, a select line, and a multiplexer output. The first multiplexer input is connected to the first peripheral clock output. The second multiplexer input is connected to the first peripheral clock output via an inverter. The multiplexer output is connected to the first peripheral device and the select line is connected to a comparator. The comparator is operable to compare the processor clock signal to the first peripheral clock signal. Thus, a first input of the comparator is typically connected to the processor clock output of the clock generator and a second input of the comparator is connected to the first peripheral clock output of the clock generator.

[0029] The comparator allows the values ​​of the respective signals, i.e. the peripheral clock signal and the processor clock signal, to be compared with each other. Depending on the comparison, the comparator is connected to a selection line of the multiplexer, so that one of the first and second multiplexer inputs is sent to the multiplexer output. The multiplexer output is connected to an input of the first peripheral device. In practice, the first multiplexer input is connected to the first peripheral clock output of the clock generator and the second input of the multiplexer is connected to the first peripheral clock output via an inverter, so that by comparing the first peripheral clock signal with the processor clock signal, either the first peripheral clock signal or an inverted peripheral clock signal can be sent via the multiplexer to at least the first peripheral clock output.

[0030] The optional inversion of the first peripheral clock output to each first peripheral device can be effectively used to avoid and / or suppress any spikes or unacceptable peaks in the clock signal transmitted or received by at least the first peripheral device.

[0031] According to a further embodiment of the clock distribution network, a second logic circuit is provided, connected to the second peripheral clock output and connected to the second peripheral device. The second logic circuit is operable to invert the second peripheral clock signal received from the clock generator and to transmit the inverted second peripheral clock signal to the second peripheral device. Substantially, the second logic circuit may be implemented in the same or similar manner as the first logic circuit described above. To that extent, all the features, effects and advantages described above in relation to the first logic circuit implemented between the clock generator and the at least first peripheral device may equally apply to the second logic circuit and its interaction with the second peripheral clock output and the at least second peripheral device, respectively.

[0032] In a further aspect, the present disclosure also relates to a method for distributing a clock signal in a clock distribution network, in some embodiments the method for distributing a clock signal in a clock distribution network is implemented by a clock distribution network as described above, to the extent that all the effects, features and advantages described above in relation to the clock distribution network may apply to the method for distributing a clock signal in such a clock distribution network as well.

[0033] Regardless of the particular implementation of the clock distribution network, the method of distributing a clock signal in a clock distribution network can be performed by a clock distribution network including a clock generator, a processing device, and at least a first peripheral device. In this case, the clock generator includes at least a processor clock output, a first peripheral clock output, and a first clock request input. The processing device is connected to the clock generator. The processing device is generally connected to the processor clock output of the clock generator. The first peripheral device is generally connected to the first peripheral clock output of the clock generator and further to the first clock request input of the clock generator. The method of distributing a clock signal includes the steps of generating a processor clock signal and transmitting the processor clock signal to the processing device. The processing device then operates on a rising edge of the processor clock signal.

[0034] The method further includes generating and / or transmitting a first peripheral clock signal to at least the first peripheral device via the first peripheral clock output in response to receiving a first clock request signal from the first peripheral device. In this case, the generation and / or transmission of the first peripheral clock signal is generally triggered by at least the first peripheral device. If not, the generation and / or transmission of the first peripheral clock signal may be suppressed, for example by default. In this way, the energy and / or power consumption of the clock distribution network can be effectively reduced. The distribution of the clock signal further includes operating at least the first peripheral device on a falling edge of the peripheral clock signal.

[0035] By combining the above features with the method of distributing the clock signal, the global clock tree can be eliminated. Instead, the clock distribution network and the method of distributing the clock signal in the clock distribution network can operate with multiple local clock trees, each of which is implemented and / or used locally for a respective peripheral device and / or clock generator. In this case, it is no longer necessary to establish a global clock tree interconnecting a large number of peripheral devices that are permanently synchronized with each other.

[0036] According to a further embodiment, the clock distribution network includes at least a second peripheral device connected to the second peripheral clock output and connected to a second clock request input of the clock generator. The first peripheral device includes a first local clock tree and the second peripheral device includes a second local clock tree. The first and second local clock trees operate independently of each other. Thus, the first local clock tree can operate independently of the second local clock tree and vice versa.

[0037] By abandoning the requirement to synchronize the first and second local clock trees, the respective hardware components that provide such synchronization are effectively unnecessary, thereby saving construction space for such supplemental hardware components, such as buffers or inverters, that would normally be required to synchronize the local clock trees of the individual peripheral devices with each other.

[0038] According to a further embodiment, the method for distributing a clock signal further comprises delaying the processor clock output received by the processing input by a predetermined delay offset with respect to the processor clock signal generated and transmitted by the clock generator. Such a delay is beneficial and particularly useful since the processor operates on the rising edge and the first and / or second peripheral device or any further peripheral device operates on the falling edge of the respective clock signal. Due to the time-delayed operation of the processing device and the first and / or second peripheral device operable to request the generation and / or reception of the respective first and / or second peripheral clock signal, the data exchange between the processing device and the peripheral device is and remains quite robust.

[0039] According to a further embodiment, the method includes the step of inverting the first peripheral clock signal received from the clock generator and sending the inverted first peripheral clock signal to the first peripheral device if the processor clock signal is smaller than the first peripheral clock signal received from the clock generator, in this way occurrence of unacceptable spikes in either the first or second peripheral clock signal or in the processor clock signal can be effectively avoided.

[0040] In general, the above-described clock distribution network and method for distributing clock signals in a clock distribution network are applicable to a clock generator that simultaneously provides a number of different clock signals, each oscillating at a different predetermined frequency. [Brief description of the drawings]

[0041] A number of embodiments of clock distribution networks are described in more detail below with reference to the drawings. [Figure 1] 1 illustrates a schematic diagram of an example clock distribution network according to the present invention; [Diagram 2] 4 illustrates a further embodiment of a clock distribution network. [Diagram 3]1 shows a timing diagram of a first embodiment for operating a clock distribution network. [Figure 4] 4 shows further timing diagrams of the clock distribution network. [Diagram 5] 4 shows further timing diagrams. [Figure 6] 4 shows further timing diagrams. [Figure 7] 4 shows further timing diagrams. [Figure 8] 4 shows further timing diagrams. [Figure 9] 4 shows further timing diagrams. [Figure 10] 4 shows another timing diagram of the clock distribution network. [Figure 11] 1 shows a flowchart of a method for distributing a clock signal in a clock distribution network. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] 1 illustrates a first embodiment of a clock distribution network 10. The clock distribution network 10 includes a clock source 12 that provides a master clock signal. The clock source 12 is connected to a clock generator 14. The clock generator 14 derives and / or generates a number of individual clock signals from a signal obtained from the clock source 12. In general, the clock generator 14 is operable to generate harmonics of the master clock signal and to provide these individual clock signals, for example, as a first peripheral clock signal Clk_periph_1 at a first peripheral clock output 32, as a second peripheral clock signal Clk_periph_2 at a second peripheral clock output 33, and / or as a further peripheral clock signal Clk_periph_n at a further or nth peripheral clock output 34, where n is an integer greater than 2.

[0043] Clock distribution network 10 further includes processing unit 16 and a number of peripheral devices 22, 23, 24. Peripheral device 22 may be a first peripheral device. Peripheral device 23 may represent a second peripheral device. Peripheral device 24 may represent any further peripheral device, for example an nth peripheral device, where n is an integer greater than 2.

[0044] 1, each peripheral device 22, 23, 24 is individually connected to the processing unit 16 via a separate transmission line 52, 53, 54. Thus, a first peripheral device 22 can communicate directly with the processing unit 16 by a first transmission line 52. A second peripheral device 23 can communicate with the processing unit 16 via a second transmission line 53, and a further peripheral device 24 can communicate with the processing unit 16 via a further transmission line 54.

[0045] 1, the clock generator 14 includes a processor clock output 31 connected to the processing unit 16. Via the processor clock output 31, the processing unit 16 can provide a clock signal CPU_clk generated and / or distributed by the clock generator 14. The clock generator 14 further includes a first peripheral clock output 32, a second peripheral clock output 33 and a further peripheral clock output 34.

[0046] The first peripheral clock output 32 is connected to a first peripheral device 22. The second peripheral clock output 33 is connected to a second peripheral device 23 and the further peripheral clock output 34 is connected to a further peripheral device 24. In this case, the first peripheral device 22 may receive a first peripheral clock signal Clk_periph_1 via or from the first peripheral clock output, and the second peripheral device 23 is operable to receive a different second clock signal Clk_periph_2 from and / or via the second peripheral clock output 33.

[0047] The peripherals 22, 23, 24 are further connected to a number of clock request inputs 42, 43, 44 of the clock generator 14. As shown in Figure 1, the first peripheral 22 is connected to the clock generator 14 via a first clock request input 42. The clock generator 14 further includes a second clock request input 43 which is connected to the second peripheral 23. A further clock request input 44 of the clock generator 14 is connected to the further peripheral 24.

[0048] The first peripheral device 22 is operable to generate and / or transmit a first peripheral clock request signal Req_clk_perif_1 to the clock generator 14 via a first clock request input 42. The second peripheral device 23 is operable to generate and / or transmit a second peripheral clock request signal Req_clk_perif_2 to the clock generator 14 via a second clock request input 43, and the further peripheral device 24 is operable to generate and / or transmit a further peripheral clock request signal Req_clk_perif_n to the clock generator 14 via a further clock request input 44.

[0049] 1, the clock input of processing unit 16 is connected to the output of a delay cell 18 arranged between processor clock output 31 and processing unit 16. In this way, the processor clock signal provided and distributed by the clock generator via processor clock output 31 is received at processing unit 16 with a delay.

[0050] The operation of the clock distribution network 10 shown in Figure 1 is further illustrated by the timing diagrams according to Figures 3, 5, 7 and 9. As shown in the timing diagram of Figure 3, the clock generator 14 is operable to generate a number of clock signals, for example, clock signals CLK at 1 MHz, 2 MHz, 4 MHz, 8 MHz and 16 MHz, as shown in the top five diagrams shown at the top of Figure 3.

[0051] 3, the processing unit 16 is driven by an 8 MHz clock signal provided as signal S1 at the processor clock output 31. This signal is subjected to a certain delay so that at the output of the delay cell 18 a further delayed input signal S2 is generated, this signal Clk_CPU_8_MHz being then provided to the processor 16.

[0052] The first peripheral device 22 operates at a clock frequency of 1 MHz, and this clock signal Clk_1_MHz is repeatedly reproduced as signal S3 in the diagram of Fig. 3. The processing device 22, operating on the rising edge of the delayed processor clock signal S2, triggers a data exchange operation with the first peripheral device 22 at time t1. At t1, the processing device 16 generates a start peripheral signal Start_peripheral and transmits it to the first peripheral device 22 via the first transmission line 52.

[0053] The first peripheral device 22 in response generates a first peripheral clock request signal Req_Clock_Perif S5 and transmits this signal S5 to the first clock request input 42. Also at time t1, in response to receiving the peripheral clock request signal S5 from the first peripheral device 22, the clock generator 14 begins transmitting or gating a respective first peripheral clock signal Clk_Perif_1MHz S6 at time t1. As shown in FIG. 3, time t1 precedes the falling edge of the 1MHz clock signal S6 used by the peripheral device 22. Beginning at time t2, and therefore after the falling edge of the 1MHz clock signal, the first peripheral device 22 receives a full period of the clock signal S6, which is then gated from the internal clock signal S3 to the peripheral device 22.

[0054] In the further embodiment of FIG. 5, the processing unit 16 and one of the peripheral devices 22, 23, 24 operate at a common frequency, so that both the processing unit 16 and, for example, the first peripheral device 22 operate at a clock frequency of 8 MHz.

[0055] As described above in connection with Figures 3 and the timing diagrams of Figure 5, clock generator 14 provides a processor clock signal S1 which is delayed by delay cell 18 and provided at the clock input of processing unit 16 as delayed processor clock signal S2. Signal S3 is provided at first peripheral clock output 32. Again, as described above in connection with Figure 3, at time t1 processing unit 16 transmits a start peripheral signal Start_Perif S4 which is transmitted by transmission line 52 to first peripheral device 22.

[0056] In response, the first peripheral device 22 generates and transmits a respective peripheral clock request signal S5 to the first clock request input 42, thereby commencing gating or transmission of the first peripheral clock signal via the first peripheral clock output 32 as signal S6. In this case, the occurrence of a spike at any time t1 or t2 is effectively avoided, since time t1 is delayed relative to the rising edge of signal S3. The commencement of transmission of the first peripheral clock signal at t2 is delayed relative to the rising edge of signal S4 or S5.

[0057] In a further embodiment of the clock distribution network of FIG. 1 shown in FIG. 7, the processing unit 16 again operates from an 8 MHz delayed clock signal Clk_CPU_8_MHz S2, while each peripheral device 22 operates from a 16 MHz peripheral clock signal Clk_Perif_16_MHz S6.

[0058] 7, the clock signal S2 driving the processing unit 16 is delayed compared to the original 8 MHz clock signal S1 provided at the processor output 31 of the clock generator 14. Signal S3 simply reflects the internal 16 MHz clock signal generated or provided by the clock generator 14 and which must be gated to the respective peripheral device 22.

[0059] Again, when the processing unit 16 initiates communication with a peripheral device 22, a start peripheral signal S4 is generated and sent directly to the respective peripheral device 22 via transmission line 52. In response, the peripheral device 22 generates a peripheral clock request signal S5. Due to the time delay of signal S2, the generation of signals S4 and S5 is similarly delayed such that only the first peripheral clock output 32 is active at time t2. The gating or sending of the 16 MHz internal clock signal S3 from the clock generator 14 to the respective peripheral device 22 is active for multiple periods, preferably 16 periods, of the first peripheral clock signal S6.

[0060] In the further timing diagram of Figure 9, the processing unit operates at a frequency of 1 MHz whilst the peripheral device 22 operates at a clock frequency of 8 MHz. Again, in a similar manner as described above in relation to Figures 3, 5 or 7, the processor clock signal S1 provided at the processor clock output 31 is time delayed by a predetermined offset and provided to the processing unit 16 as a time-delayed processor clock signal S2.

[0061] Concurrent with the rising edge of the time-delayed processor clock signal S2, a start peripheral signal Start_Perif S4 and a peripheral clock request signal Req_Clock_Perif S5 are generated. Upon receiving signal S5 at time t2, the clock generator 14 gates signal S3 to the first peripheral clock output 32 as a first peripheral clock signal Clk_Perif_8_MHz S6 and transmits the respective internally generated clock signal S6 to the first peripheral device 22.

[0062] In a further embodiment of the clock distribution network 10 shown in Figure 2, the processing unit 16 is directly connected to the clock generator 14 without the delay cell 18 therebetween. Rather, in the embodiment of Figure 2, in place of the delay cell 18, separate logic circuits 36, 37, 38 are provided between the peripheral devices 22, 23, 24 and the associated peripheral clock outputs 32, 33, 34. Thus, the first peripheral device 22 is connected to the first peripheral clock output 32 via the first logic circuit 36. The second peripheral device 23 is connected to the second peripheral clock output 33 via the second logic circuit 37. The further peripheral device 24 is connected to the further peripheral clock output 34 of the clock generator 14 via the third logic circuit 38.

[0063] Each logic circuit 36, 37, 38 includes a multiplexer 19 having a first multiplexer input directly connected to a corresponding first, second or further peripheral clock output 32, 33, 34. The multiplexer 19 is further provided with a second multiplexer input connected to the corresponding peripheral clock output 32, 33, 34 via an inverter 22.

[0064] Each multiplexer 19 of the multiple logic circuits 36, 37, 38 is further provided with a select line which is connected to and / or driven by a comparator (not shown). In general the comparator is operable to compare, for example, a processor clock signal provided at the processor clock output 31 with a respective peripheral clock signal provided at a respective first, second or further peripheral clock output 32, 33, 34.

[0065] The logic circuits 36, 37, 38 are operable to transmit the corresponding peripheral clock signal directly and unchanged to the corresponding peripheral device 22, 23, 24 when the value of the processor clock signal is greater than the value of the corresponding first, second or third peripheral clock signal, respectively. In other situations, i.e. when the processor clock signal is less than the first, second or third peripheral clock signal, the multiplexer 19 switches to the inverted signal provided by the inverter 20. Indeed, in such situations, the respective peripheral device 22, 23, 24 is supplied with an inverted peripheral clock signal.

[0066] The operation of the embodiment of the clock distribution network shown in FIG. 2 will now be explained in more detail with respect to the timing diagrams shown in FIGS.

[0067] 4, the processing unit 16 operates at a clock frequency of 8 MHz and the first peripheral device 22 operates at a clock frequency of 1 MHz. In this case, the clock signals S1 and S2 are substantially identical because the clock input of the processing unit 16 is connected directly to the processor clock output 31. Signal S3 is simply a reproduction of the internally generated 1 MHz clock signal Clk_1_MHz provided by the clock generator 14.

[0068] At time t1, the processing unit 16 transmits a start peripheral signal Start_Perif S4 to the first peripheral device 22 via the transmission line 52. In response to receiving the signal S4, the first peripheral device 22 generates a respective peripheral clock request signal S5 and transmits this signal to the clock generator 14 via the first peripheral clock input 42. In response to receiving the signal Req_Clock_Perif S5, the clock generator 14 starts operating and gates the signal S3 to the first peripheral device 22 as a peripheral clock signal Clk_Perif_1_MHz S6 via the first peripheral clock output 32. At time t2, the first peripheral device 22 receives a full period of the first peripheral clock signal S6.

[0069] A similar situation and behavior is illustrated in the timing diagram of Figure 6. In this case, both the first peripheral device 22 and the processing unit 16 operate at a common clock frequency of 8 MHz, as already explained in relation to Figure 5. A start peripheral signal S4 and a request clock peripheral signal S5 are generated at time t1, which generate and transmit a period of the first peripheral clock signal S6 starting at time t2.

[0070] 4 and 6, at time t1, processor clock signal S2 is greater than or equal to clock signal S3 intended for peripheral device 22. Thus, signal S3 is not inverted by logic circuits 36, 37 or 38, but rather is gated unchanged to the respective peripheral device.

[0071] In the timing diagram shown in Fig. 8, the situation changes. The processing unit 16 is now driven with a clock frequency of 8 MHz and is supplied with a clock signal S2. The first peripheral device 22 is now driven with a peripheral clock frequency of 16 MHz. In this case, at time t1, the logic value of the processor clock signal S2 is greater than the logic value of the dedicated peripheral clock signal S3. At t1, the rising edge of the processor clock signal S2 coincides with the falling edge of the first peripheral clock signal S3. The first logic circuit 36 ​​is now operable to invert the first peripheral clock signal S3 and generates an inverted first peripheral clock signal S3'.

[0072] This inverted first peripheral clock signal S3' is then sent to the first peripheral device 22, which initiates a request for peripheral clock signal generation at time t1 by generating respective signals S4 and S5 as previously described. Starting at time t2, the clock generator 14 provides multiple periods of the inverted clock signal S3' at the first peripheral clock output 32 to drive or clock one of the peripheral devices 22, 23, 24. Preferably, starting at time t2, the clock generator 14 provides 16 periods of the inverted clock signal S3'.

[0073] In the further timing diagram of Figure 10, a similar inversion as described above in relation to Figure 8 is explained in more detail. In this case, as described above in relation to the timing diagram of Figure 9, the processing unit 16 is clocked at a frequency of 1 MHz, while the peripheral device 22 is clocked at a frequency of 8 MHz.

[0074] Also in this case, at time t1, the processor clock signal S1 or S2 is greater than the peripheral clock signal S3. As a result, the logic circuit 36 ​​inverts the peripheral clock signal S3 to an inverted peripheral clock signal S3' for clocking or driving the respective peripheral device 22, 23, 24. At time t2, triggered by the generation and transmission of signals S4 and S5, each peripheral device 22, 23, 24 obtains and receives the inverted first peripheral clock signal S3', which is gated through to the dedicated peripheral device 22, 23, 24 as the peripheral clock signal S6.

[0075] The timing diagrams of Figures 3-10 above are only illustrative for a limited number of peripheral devices 22, 23, 24. Most of the timing diagrams are described in relation to or with reference to a first peripheral device 22. However, other peripheral devices such as a second peripheral device 23 and a further peripheral device 24 may be driven simultaneously with different clock signals as described above.

[0076] For example, a first peripheral device 22 may be driven by a 1 MHz clock signal, a second peripheral device 23 may be driven by a 4 MHz clock signal, and a second peripheral device 24 may be driven by a 16 MHz clock signal.

[0077] Also, each of the peripheral devices 22, 23, 24 may operate with or include a local clock tree 26, 27, 28, in particular the peripheral device 22 may be provided with a first local clock tree 26. The second peripheral device 23 may be provided with a second local clock tree 27 and the further peripheral device 24 may be provided with a further clock tree 28. The individual clock trees 26, 27, 28 may operate independently of each other and do not need to be synchronized with each other or locked to a global clock tree.

[0078] The flow chart according to Fig. 11 shows diagrammatically a method for distributing a clock signal in such a clock distribution network 10. In this case, in step 100, a processor clock signal is generated and transmitted to the processing device 16. In step 102, the processing device 16 operates on a rising edge of the processor clock signal. In step 104, a first peripheral clock signal is generated and / or transmitted to at least one of the above-mentioned first, second or further peripheral devices 22, 23, 24, and in the following step 106, the respective peripheral device 22, 23 or 24 is driven or operated on a falling edge of the respective peripheral clock signal. [Explanation of symbols]

[0079] 10 Clock Distribution Network 12 Clock Source 14 Clock Generator 16 Processing equipment 18 Delay Cells 19 Multiplexer 20 Inverter 22 Peripheral Devices 23 Peripheral Devices 24 Peripheral Devices 26 Clock Tree 27 Clock Tree 28 Clock Tree 31 Clock Output 32 clock outputs 33 Clock Output 34 Clock Outputs 36 Logic Circuits 37 Logic Circuits 38 Logic Circuits 42 Clock Request Input 43 Clock Request Input 44 Clock Request Input 52 Transmission Line 53 Transmission Line 54 Transmission Line

Claims

1. A clock distribution network (10), comprising: a clock generator (14) configured to generate a processor clock signal and a first peripheral clock signal, the clock generator (14) further comprising a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42); a processing unit (16) connected to said processor clock output (31) and configured to operate on a rising edge of said processor clock signal receivable via said processor clock output (31); a delay cell (18) connected to said processor clock output (31) and operable to delay said processor clock signal received by said processing unit (16) by a predetermined delay offset relative to said processor clock signal and peripheral clock signals generated and transmitted by said clock generator (14); a first peripheral device (22) connected to said first peripheral clock output (32) and to a first clock request input (42) of said clock generator (14), said first peripheral device (22) being configured to operate on a falling edge of said first peripheral clock signal received via said first peripheral clock output (32); Including, - A clock distribution network (10), wherein the first peripheral device (22) via the first clock request input (42) is operable to operate the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).

2. 2. The clock distribution network (10) of claim 1, further comprising means for delaying the processor clock output (31) received by the processing unit (16) by a predetermined delay offset relative to the processor clock signal generated and transmitted by the clock generator (14).

3. 2. The clock distribution network (10) of claim 1, wherein the clock generator (14) is configured to inhibit transmission of the first peripheral clock signal unless requested by the first peripheral device (22) via the first clock request input (42).

4. 2. The clock distribution network (10) of claim 1, wherein said processing device (16) is directly connected to said first peripheral device (22) via a first transmission line (52).

5. 2. The clock distribution network (10) of claim 1, further comprising a second peripheral device (23) connected to a second peripheral clock output (33) and connected to a second clock request input (43) of said clock generator (14), said second peripheral device (23) via said second clock request input (43) operable to operate said clock generator (14) to transmit a second peripheral clock signal via said second peripheral clock output (33).

6. 6. The clock distribution network (10) of claim 5, wherein the processing device (16) is directly connected to the second peripheral device (23) via a second transmission line (53).

7. 6. The clock distribution network (10) of claim 5, wherein the first peripheral device (22) includes a first local clock tree (26) and the second peripheral device (23) includes a second local clock tree (27), the first local clock tree (26) operating independently from the second local clock tree (27) and / or the second local clock tree (27) operating independently from the first local clock tree (26).

8. 2. The clock distribution network of claim 1, further comprising a first logic circuit coupled to said first peripheral clock output and coupled to said first peripheral device, said first logic circuit operable to invert said first peripheral clock signal received from said clock generator and to transmit the inverted first peripheral clock signal to said first peripheral device.

9. 9. The clock distribution network (10) of claim 8, wherein the first logic circuit (36) is connected to the processor clock output (31) and is operable to invert the first peripheral clock signal and transmit the inverted first peripheral clock signal to the first peripheral device (22) when the processor clock signal is less than the first peripheral clock signal received from the clock generator (14).

10. 9. The clock distribution network of claim 8, wherein the first logic circuit includes a multiplexer having a first multiplexer input, a second multiplexer input, a select line, and a multiplexer output, the first multiplexer input being connected to the first peripheral clock output, the second multiplexer input being connected to the first peripheral clock output through an inverter, the multiplexer output being connected to the first peripheral device, and the select line being connected to a comparator operable to compare the processor clock signal and the first peripheral clock signal.

11. 6. The clock distribution network (10) of claim 5, further comprising a second logic circuit (37) connected to the second peripheral clock output (33) and connected to the second peripheral device (23), the second logic circuit (37) operable to invert the second peripheral clock signal received from the clock generator (14) and to transmit the inverted second peripheral clock signal to the second peripheral device (23).

12. A method for distributing a clock signal in a clock distribution network (10), the clock distribution network (10) comprising: a clock generator (14) configured to generate a processor clock signal, the clock generator (14) including a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42); a processing unit (16) connected to said clock generator (14); a delay cell (18) connected to said processor clock output (31) and operable to delay the processor clock signal received by said processing unit (16) by a predetermined delay offset with respect to the processor clock signal generated and transmitted by said clock generator (14); a first peripheral device (22) connected to said first peripheral clock output (32) and to a first clock request input (42) of said clock generator (14); The clock signal distribution method includes: - generating a processor clock signal and transmitting said processor clock signal to said processing unit (16); - operating said processing unit (16) on a rising edge of said processor clock signal; - said clock generator (14) providing a number of periods of an inverted clock signal (S3') at said first peripheral clock output (32) to drive or clock said first peripheral device (22); - in response to receiving a first clock request signal from the first peripheral device (22), generating and / or transmitting a first peripheral clock signal to the first peripheral device (22) via the first peripheral clock output (32); operating said first peripheral device (22) on the falling edge of said first peripheral clock signal; The method includes:

13. 13. The method of claim 12, wherein the clock distribution network (10) includes a second peripheral device (23) connected to a second peripheral clock output (33) and connected to a second clock request input (43) of the clock generator (14), the first peripheral device (22) includes a first local clock tree (26) and the second peripheral device (23) includes a second local clock tree (27), and the first and second local clock trees (26, 27) operate independently of each other.

14. 13. The method of claim 12, further comprising delaying the processor clock output (31) received by the processing unit (16) by a predetermined delay offset relative to the processor clock signal generated and transmitted by the clock generator (14).

15. 13. The method of claim 12, further comprising the step of inverting the first peripheral clock signal received from the clock generator (14) and transmitting the inverted first peripheral clock signal to the first peripheral device (22) if the processor clock signal is less than the first peripheral clock signal received from the clock generator (14).

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