Write driver with magnetic field compensation - Patents.com

Abstract

A method for compensating for an external magnetic field in a memory device includes positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, and positioning a write driver in electrical communication with the at least one external magnetic field sensing element and the at least one array of memory cells. The at least one external magnetic field sensing element is monitored for a signal indicative of the presence of an external magnetic field. The write driver can be adjusted to operate the memory device while compensating for the external magnetic field, thereby adjusting the write current to the at least one array of memory cells.

Description

[Technical field]

[0001] The present invention relates generally to memory devices, and more particularly to magnetic random access memories (MRAMs) and their layout structures including write drivers. [Background technology]

[0002] Magnetic random access memory (MRAM) uses the resistance variations associated with polarity changes in magnetic materials to store digital information. In some cases, sensitivity to external magnetic fields can adversely affect the performance of MRAM, which may result in irreparable failure.

[0003] Costly and complex shielding solutions have been proposed to allow MRAM products to operate in the presence of external magnetic fields. Other solutions have also been proposed to stop the operation of the chip if the presence of an external magnetic field that would alter the data or memory operation is detected. For example, designs including magnetic field sensors have been proposed. In addition, watch cells may be incorporated with the MRAM, where the watch cells are magnetic tunnel junction elements that have a lower switching field than the MRAM bits. In these designs, the system periodically reads the state of the watch cells to determine the presence of an external magnetic field and adjusts the performance of the MRAM accordingly. Such solutions may not be acceptable for high performance applications. Summary of the Invention

[0004] According to one embodiment of the present invention, there is provided a method for compensating for an external magnetic field in a memory device, the method including positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, with a write driver in electrical communication with the at least one external magnetic field sensing element and the at least one array of memory cells. The method then monitors the at least one external magnetic field sensing element for a signal indicative of the presence of an external magnetic field and adjusts a write current to the at least one array of memory cells by adjusting the write driver. By adjusting the write current, the method advantageously enables the memory cells to function in an external magnetic field, whereas previous methods suspended operation of the memory cells when an external magnetic field was present.

[0005] In some embodiments, the array of memory cells includes bit cells having a bit cell magnetic tunnel junction (MTJ). The at least one external magnetic field sensing element can be a magnetic field sensor or a watch cell. In some examples, the watch cells have the advantage of being located in close proximity to the bit cells and can be formed using similar processes. To provide the watch cells, a watch cell magnetic tunnel junction (MTJ) structure can be provided that has a larger diameter than the bit cell magnetic tunnel junction (MTJ). It is noted that this is true for only some embodiments of the methods and structures described herein. In other examples, the watch cells include watch cell magnetic tunnel junctions that have different anisotropy field (Hk) characteristics than the bit cell magnetic tunnel junction (MTJ) characteristics. These examples have the advantage of having a similar geometry to the bit cells, facilitating their integration into designs. In still other embodiments, the watch cells include a watch cell access transistor to the watch cell magnetic tunnel junction that is designed or biased to provide a smaller write current than the bit cell access transistor.

[0006] In some embodiments, monitoring the at least one external magnetic field sensing element for a signal indicative of the presence of an external magnetic field includes measuring programming of the watch cell when the bit cells are not correspondingly programmed substantially simultaneously, while in other embodiments, monitoring the at least one external magnetic field sensing element for a signal indicative of the presence of an external magnetic field includes measuring a change in a write error rate (WER) of the watch cell.

[0007] In another embodiment, a method for compensating for an external magnetic field in a memory device is provided, the method including positioning at least one watch cell adjacent to at least one array of memory cells, where a write driver is in electrical communication with at least one external magnetic field sensing element and the at least one array of memory cells. The method further includes monitoring the at least one watch cell for a variation in write error rate (WER) from a baseline write error rate. In this example, the variation in the write error rate of the watch cell signals the presence of an external magnetic field. The method adjusts a write current to the at least one array of memory cells by adjusting a write driver to compensate for the external magnetic field measured by monitoring the at least one watch cell.

[0008] In another aspect of the disclosure, a memory device is provided that advantageously enables detecting an external magnetic field and adjusting a write current to allow the memory cells to continue to operate while compensating for the external magnetic field. In one embodiment, the memory device includes at least one block of bit cells including a plurality of memory cells and at least one auxiliary column of watch cells. The at least one auxiliary column of watch cells measures the external magnetic field in a vicinity of the plurality of memory cells. The memory device further includes a write driver circuit in electrical communication with at least the plurality of memory cells. The memory device further includes a counter for recording when the at least one auxiliary column of watch cells measures the external magnetic field, the counter in electrical communication with the write driver circuit. A write driver of the write driver circuit adjusts a write current to the plurality of memory cells to compensate for the external magnetic field. By adjusting the write current, the method advantageously enables the memory cells to function in an external magnetic field, whereas previous devices suspended operation of the memory cells when an external magnetic field was present.

[0009] In one embodiment of the memory device, the plurality of memory cells includes a bit cell having a bit cell magnetic tunnel junction (MTJ), and the watch cell includes a watch cell magnetic tunnel junction (MTJ) structure having a diameter larger than the bit cell magnetic tunnel junction (MTJ). In another embodiment, the watch cell has a watch cell magnetic tunnel junction having a magnetic anisotropy field (Hk) characteristic different from the magnetic anisotropy field (Hk) characteristic of the bit cell magnetic tunnel junction (MTJ). In yet another embodiment, the watch cell includes a watch cell access transistor to the watch cell magnetic tunnel junction designed or biased to provide a smaller write current than the bit cell access transistor.

[0010] The watch cells may be located in auxiliary columns of a block of the bit cell array. This advantageously allows the watch cells to be processed simultaneously with the bit cells, which facilitates integration of the watch cells into the memory device. In an example where the watch cells have a different diameter than the bit cells, the bit cells may be arranged in multiple blocks of the array, and the watch cells having a diameter larger than the bit cell magnetic tunnel junctions (MTJs) are located in auxiliary rows with an increasing degree of variation from block to block in the multiple blocks of the array.

[0011] In another aspect, a memory device is provided that includes at least one block of bit cells including a plurality of memory cells and at least one subgroup of watch cells at a periphery of the memory array. The at least one subgroup of watch cells measures an external magnetic field in a vicinity of the plurality of memory cells. The plurality of memory cells includes a bit cell having a bit cell magnetic tunnel junction (MTJ), and the subgroup of watch cells includes a magnetic tunnel junction (MTJ) structure having a diameter larger than the bit cell magnetic tunnel junction (MTJ). The memory device may further include a write driver circuit in electrical communication with at least the plurality of memory cells. A write driver of the write driver circuit adjusts write currents to the plurality of memory cells to compensate for the external magnetic field. In some embodiments, the watch cells are located at the periphery of the block of bit cell array.

[0012] In yet another aspect, a memory device is provided that includes at least one block of bit cells including a plurality of memory cells and at least one auxiliary group of watch cells at a periphery of the memory array. The at least one auxiliary group of watch cells measures an external magnetic field in a vicinity of the plurality of memory cells. The plurality of memory cells includes bit cells having a bit cell magnetic tunnel junction (MTJ), the watch cells including a watch cell magnetic tunnel junction having a magnetic anisotropy field (Hk) characteristic different from a magnetic anisotropy field (Hk) characteristic of the bit cell magnetic tunnel junction (MTJ). In some embodiments, the watch cells are positioned at the periphery of the block of bit cell array.

[0013] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0014] The following description provides details of preferred embodiments with reference to the accompanying drawings. [Brief description of the drawings]

[0015] [Figure 1] 1 is a plot showing the dependence of bit error rate (BER) of an MRAM device in the presence of an external magnetic field. [Diagram 2] FIG. 2 is a schematic diagram illustrating a magnetic field detection circuit coupled to a write driver according to an embodiment of the present disclosure. [Diagram 3] 1 is a plot illustrating how magnetic field compensation can mitigate the bit error rate (BER) of an MRAM device in the presence of an external magnetic field, according to an embodiment of the present disclosure. [Figure 4] 1 is a plot showing a write voltage shmoo without an external magnetic field and with a small applied magnetic field according to one embodiment of the present disclosure. [Diagram 5] FIG. 2 is a block diagram illustrating an embodiment of a magnetic field detection circuit in accordance with an embodiment of the present disclosure. [Figure 6]FIG. 1 is a schematic diagram of an array of memory cells including a magnetic field detection circuit for measuring an external magnetic field including a watch cell having a different diameter than the memory cells, and a write driver controller for controlling write voltages to provide magnetic field compensation, according to one embodiment of the present disclosure. [Figure 7] FIG. 2 is a circuit diagram of an MRAM array according to an embodiment of the present disclosure. [Figure 8] FIG. 13 is a circuit diagram of an MRAM array illustrating biasing for providing a write function that provides a bit data storage value of "0" according to one embodiment of the present disclosure. [Figure 9] FIG. 13 is a circuit diagram of an MRAM array illustrating biasing for providing a write function that provides a bit data storage value of "1" according to one embodiment of the present disclosure. [Figure 10] FIG. 2 is a circuit diagram of an MRAM array showing biasing for read functionality according to one embodiment of the present disclosure. [Figure 11] FIG. 1 is a schematic diagram of an array of memory cells in which an external magnetic field is detected by monitoring changes in write error rate, and a write driver controller for controlling write voltages to provide magnetic field compensation, according to one embodiment of the present disclosure. [Figure 12] FIG. 4 is a block diagram illustrating a processing system that can incorporate the system for application migration shown in FIG. 3 according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] It has been found that magnetic random access memory (MRAM) memories can be sensitive to external magnetic fields, which can adversely affect the performance of the MRAM and, in some cases, can result in irreparable failure.

[0017] FIG. 1 is a plot showing the dependence of the bit error rate (BER) of an MRAM device on the presence of an external magnetic field. The y-axis represents the bit error rate (BER) while the x-axis indicates the strength of the external magnetic field. The plot line identified by reference numeral 10 shows that as the strength of the external magnetic field is increased, the bit error rate (BER) also increases. The data provided in FIG. 1 is generated from a high-speed version of an MRAM architecture including cells having access transistors and MTJs (1T1MTJ) in an array. The MTJ element may be based on the tunneling magneto-resistance (TMR) effect, in which the stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. In an MRAM device, the MTJ element is formed between a bottom electrode, such as a first conductive line, and a top electrode, which is a second conductive line. The MTJ stack, whose layers are later patterned to form the MTJ element, may be formed in a so-called "bottom pinned" configuration by sequentially depositing a seed layer, a ferromagnetic reference (or "pinned") layer, a thin tunnel barrier layer, a ferromagnetic "free" layer, and a capping layer.

[0018] One type of MRAM is spin-transfer torque (STT) MRAM. STT MRAM has the advantages of lower power consumption and better scalability over conventional MRAM that uses a magnetic field to flip the active elements. In STT MRAM, spin-transfer torque is used to flip (switch) the orientation of the magnetic free layer. STT MRAM uses a two-terminal device with a magnetic tunnel junction (MTJ) pillar composed of a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer. The magnetization of the magnetic reference layer is pinned in one direction, and a current applied upwards in the MTJ pillar makes the magnetic free layer antiparallel to the magnetic reference layer, while a current applied downwards in the MTJ pillar makes the magnetic free layer parallel to the magnetic reference layer. Up and down are with respect to the direction of the pinned layer. A smaller current (of either polarity) is used to read the resistance of the device, which depends on the relative orientations of the magnetic reference layer and the magnetic free layer.

[0019] Application of an external magnetic field can affect the energy barrier of the magnetic tunnel junction, changing the switching voltage. As shown in FIG. 1, increasing the switching voltage of the magnetic tunnel junction (MTJ) can result in an increase in the bit error rate (BER) at the array level. In some embodiments, when the number of bit errors, i.e., the bit error rate (BER), increases beyond the capability of the error correction code (ECC), the MRAM elements of the cells start to generate potentially uncorrectable errors that can result in system failure.

[0020] In some embodiments, the disclosed structures and methods overcome the above-mentioned susceptibility of MRAM memory arrays to external magnetic fields by coupling a magnetic field detection circuit to a write driver of the memory array including the MRAM elements. In some embodiments, the magnetic field detection circuit 15 may be used to adjust the write voltage to a driver circuit, i.e., write driver 20, based on a measurement of the external magnetic field recorded by the magnetic field detection circuit 15, as shown in FIG. 2. FIG. 2 is a schematic diagram illustrating one embodiment of the magnetic field detection circuit 15 coupled to a write driver 20. The write driver 20 performs the writing of data to the memory cells 30, e.g., magnetic tunnel junctions (memory elements 35) and access transistors 40. The write driver 20 controls how the write current is provided through the MTJ and how the magnetic state of the MTJ, which stores the data, is written. The write driver 20 may include its own hardware processor and memory for commands configured to control the read and write functions of the memory device, as well as the application of the write current to provide magnetic field compensation.

[0021] 3 and 4 show examples of how magnetic field compensation is accomplished by adjusting the write voltage based on a measurement of an external magnetic field. FIG. 3 is a plot showing how magnetic field compensation can mitigate the bit error rate (BER) of an MRAM device in the presence of an external magnetic field. The y-axis of the plot shown in FIG. 3 represents the bit error rate (BER), while the x-axis represents the strength of the external magnetic field. The plot line identified by reference numeral 10 in FIG. 3 shows that as the strength of the external magnetic field is increased, the bit error rate (BER) also increases. The plot point identified by reference numeral 11 shows a high bit error rate (BER) when a high external magnetic field is applied to the memory cell. This represents the normal operation of the memory cell when an external magnetic field is applied to the memory cell and magnetic field compensation is not invoked. As mentioned above, the methods and structures described herein adjust the write voltage to compensate for an external magnetic field that increases the bit error rate (BER) of the memory cell. The plot point identified by reference number 12 shows a reduction in the bit error rate (BER) in a scenario where the write voltage is increased to compensate for the external magnetic field. By increasing the write voltage through the write driver as shown by the plot point with reference number 12, the bit error rate (BER) of the memory cell in the presence of an external magnetic field can be restored (reduced) to a level of normal operation, i.e., a level substantially equal to the bit error rate (BER) in the absence of an external magnetic field (as shown by plot point 14). Referring to FIG. 3, reference point 12 shows that the bit error rate (BER) for the memory cell has been reduced from a large number of bit errors to a substantially small number of bit errors.

[0022] 4 is a plot showing write voltage shmoos without an external magnetic field and with a small applied magnetic field, according to one embodiment of the present disclosure. Referring to FIG. 4, reference numeral 401 represents data points for the array write characteristics when no magnetic field is applied, and reference numeral 402 represents data points for the array write characteristics when a magnetic field substantially aligned with the direction of the storage layer is applied. The presence of the magnetic field stabilizes the storage layer, increasing its programming current, shifting the write characteristic to the right and increasing the memory error rate under fixed bias conditions.

[0023] Referring to FIG. 2, an external magnetic field is detected by a magnetic field detection circuit 15. FIG. 5 is a block diagram illustrating one embodiment of the magnetic field detection circuit 15. The magnetic field detection circuit 15 may be provided by a magnetic field sensor 17. In other embodiments, the magnetic field detection circuit 15 may include a magnetic position and distance sensor, a magnetic proximity switch, a magnetic force and torque sensor, a magnetic flow meter, and a current sensor. The magnetic field sensor 17 is positioned proximate to the memory cell array. The reader 18, the watch cell 16, and the sensor 17 shown in the magnetic field detection circuit 15 are interconnected by a system bus 102. The system bus 102 may provide interconnectivity with a processing system 400 shown in FIG. 12.

[0024] The magnetic field detection circuitry 15 may also be provided by a watch cell 16. A "watch cell" is a magnetic tunnel junction device used for detection of an external magnetic field. The watch cell 16 is located proximate to a memory cell (also called a bit cell). The watch cell is designed to record changes in electrical programming in response to an external magnetic field. By detecting the changes in the electrical programming of the watch cell 16, the presence of an external magnetic field is detected.

[0025] In some embodiments, the watch cells 16 have a lower switching field than the memory cells, e.g., MRAM bits. In other embodiments, the watch cells can have different anisotropy field (Hk) characteristics than the memory cells to provide watch cells with a lower switching field than the memory cells, e.g., MRAM bits.

[0026] In other embodiments, the watch cells 16 may be configured to have a larger diameter than the memory cells 30 to provide the watch cells 16 for detecting an external magnetic field in the vicinity of the memory cells 30. The watch cells 16 may have a larger diameter that is biased under nominal voltage conditions. In this example, in the absence of a magnetic field, a current applied to the watch cells 16 having a larger diameter geometry when compared to the memory cells 30 is not large enough to program the watch cells 16, but that same level of current would program the memory cells. Furthermore, when exposed to the presence of an external magnetic field, at least some of the watch cells 16 will be programmed at the same current that was previously insufficient to program the watch cells 16. In this example, the percentage of programmed cells is monitored to determine the presence of an external magnetic field. If the percentage of programmed cells for the watch cells 16 reaches a threshold value when exposed to a current known to be insufficient to program the watch cells 16 due to their larger diameter dimension, the condition warrants magnetic field compensation by adjusting the write bias in the array.

[0027] In another embodiment, the watch cell 16 in the magnetic field detection circuit 15 may be driven at a lower voltage than normal, e.g., 1x10 -3In this example, the error rate would be monitored over time to determine the presence of an external magnetic field, and the write bias would be adjusted to keep the write error rate (WER) constant. In some embodiments where the write error rate (WER) is monitored to determine the presence of an external magnetic field, no additional array of bits is needed for the dedicated watch cell 16. By biasing the watch cell at a higher bit error rate (BER) point, it is possible to detect the presence of a magnetic field with fewer writes, improving the response time of the magnetic field detection circuit.

[0028] In each of the above examples, a sensing element, such as a watch cell 16, a magnetic field sensor 17, or an element for measuring a write error rate (WER), or a combination of the above sensing elements, is periodically monitored. Periodic monitoring of the sensing elements of the magnetic field detection circuit 15 may be accomplished using a reader 18, which may include a clock that schedules monitoring cycles. The reader 18 may also include at least one hardware processor and memory, where the memory stores instructions to be executed by the hardware processor of the reader 18 to monitor the watch cell 16 in determining the presence of an external magnetic field. In some embodiments, the magnetic field detection circuit 15 may periodically read the state of the watch cell and look for disturbances indicative of an external magnetic field.

[0029] FIG. 6 illustrates an array of memory cells including a magnetic field detection circuit for measuring an external magnetic field, including a watch cell having a diameter different from the memory cell, and a write driver controller for controlling a write voltage to provide magnetic field compensation. The memory array is constructed as an array of bit cells, each storing one bit of data. The memory cells of the array illustrated in FIG. 6 can be magnetic random access memory cells. In some embodiments, the memory cells include an MRAM architecture including cells having access transistors and MTJs (1T1MTJ) in the array. In the array, each bit cell is connected to a word line and a bit line. For each combination of address bits, the memory asserts a single word line that activates the bit cells in that row.

[0030] Referring to FIG. 6, a number of memory banks 40a, 40b, 40c are shown, with many bit cell (BC) arrays 30' within each memory bank 40a, 40b, 40c. In the embodiment shown in FIG. 6, each array 30' may have auxiliary columns 15' having magnetic tunnel junctions (MTJs) with larger diameters or different anisotropy field (Hk) characteristics than the bit cells providing the memory cells 30. The auxiliary columns 15' provide watch cells 16 for the magnetic field detection circuitry 15. In the embodiment shown in FIG. 6, the watch cells 16 may be biased using the same conditions as the bit cell (BC) array 30'. In some instances, due to the larger diameter of the MTJs for the watch cells 16 in the auxiliary columns 15' relative to the MTJs for the bit cell (BC) array, the watch cells 16 in the auxiliary columns 15' require the presence of an external magnetic field to switch, e.g., be programmed. In a further example, due to different anisotropy field (Hk) characteristics for the watch cells 16 in the auxiliary column 15' relative to the MTJs for the bit cell (BC) array, the watch cells 16 in the auxiliary column 15' require the presence of an external magnetic field to switch, e.g., be programmed.

[0031] It is noted that in the embodiment shown in Figure 6, there are three bit cell (BC) array blocks 30'. It is noted that this example is provided for illustrative purposes only, and the present disclosure is not intended to be limited to only this example. For example, any number of bit cell (BC) array blocks 30' may be employed in the method and structure that provides external magnetic field compensation.

[0032] Referring to FIG. 6, in some embodiments, for further accuracy in determining whether the watch cells 16 in the auxiliary column 15' are switching, i.e., programmed, in response to an external magnetic field, there is a majority voting circuit 45 that detects the percentage of cells that have switched. The majority voting circuit 45 contains a set of combinational logic gates with "n" inputs coming from the watch cell read data of each block (40a, 40b, 40c). It has one output that returns a true "1" if and only if more than 50% of its inputs are true. The use of majority voting circuits increases the accuracy of the external magnetic field detection by accounting for process variations from array to array (30'). Based on the output of the different majority voting circuits 45, the write driver controller 20' derives a shmoo of the write driver voltage, as shown in FIG. 7. The write driver controller 20' consists of a voltage divider that outputs a voltage value specific to its input (the digital data provided by the majority voting circuit).

[0033] To determine the presence of an external magnetic field, the watch cells in the auxiliary column 15' may be monitored. The diameter / Hk of the watch cells may vary between blocks. In the embodiment shown in FIG. 6, each of the bit cell (BC) arrays includes an auxiliary column 15' that includes watch cells 16 having diameters with different deviations from the diameters of the memory cells 30 in the bit cell (BC) array. For example, the memory cells 30 in the bit cell array 30' may include magnetic tunnel junction structures (MTJs) having the same diameter, which may be referred to as a nominal diameter ("nom Dia"). In the embodiment shown in FIG. 6, the watch cells 16 in the auxiliary column 15' of the first block (Block 0) have magnetic tunnel junctions (MTJs) having diameters that are larger than the nominal diameters of the memory cells 30 in the bit cell array 30' by a differential value (Δ). In the adjacent block 40b of the bit cell (BC) array, the watch cells 16 in the auxiliary column 15' have a diameter that is two times the difference value (Δ) larger than the nominal diameter of the memory cells in the bit cell array 30'. That is, the watch cells 16 have a diameter of the nominal diameter plus two times the difference value (nom Dia+2Δ). In the next block 40c of the bit cell (BC) array, the watch cells 16 in the auxiliary column 15' have a diameter that is three times the difference value (Δ) larger than the nominal diameter of the memory cells in the bit cell array 30'. That is, the watch cells 16 have a diameter of the nominal diameter plus three times the difference value (nom Dia+3Δ). In this example, the watch cells of all blocks will detect higher values ​​of the external magnetic field. The larger the diameter difference, the larger the external magnetic field required to program the watch cells 16.

[0034] 6, the write driver control circuit 20' will adjust the write current by dynamically adjusting the write driver 20 based on input from the majority circuit 45 from each block 40a, 40b, 40c. As shown in FIG. 4, for example, when attempting to write a "0", the write current needs to be increased when the magnetic field is applied opposite the direction of the write state, but the magnetic field stabilizes the "1" state. In this case, the majority circuit will detect that the bit is switching to the "1" state.

[0035] 7-10 show several embodiments of memory cells 30 in an MRAM array, e.g., blocks 40a, 40b, 40c, and biases associated with a write driver controller. FIG. 7 is a circuit diagram of one embodiment of an MRAM array as employed in the blocks shown in FIG. 6. The memory cells 30 include a magnetic tunnel junction (MJT) 35 and one or more access transistors 40. Each memory cell 30 is associated with a bit line. The MRAM array and on pitch bit line (BL) / source line (SL) switches correspond to a single bit line (BL) and sense line (SL) combination. A word line (WL) communicates with the access transistors to the magnetic tunnel junction. In the embodiment shown in FIG. 7, the auxiliary column 15′ includes a watch cell having a nominal diameter plus a differential, as described above with the description of block 40a.

[0036] Still referring to FIG. 7, the MRAM array further includes circuits for bit line multiplexing (BL MUXING) 55 and sense line multiplexing (SL MUXING) 60. Multiplexing describes the act of sending one or more signals through a common transmission line at different times or speeds, and therefore a device for doing just that is called a multiplexer. A multiplexer, abbreviated to "MUX," is a combinational logic circuit designed to switch one of several input lines through a single common output line by application of a control signal. In the illustrated embodiment, the MUX includes MOSFETs or relays for switching voltage or current inputs down to a single output.

[0037] The circuitry for bit line multiplexing (BL MUXING) 55 and sense line multiplexing (SL MUXING) 60 is in electrical communication with a write driver controller 20'. The write driver controller 20' receives inputs from majority voting circuits 45 for each of the blocks 40a, 40b, 40c of the array. The write driver controller 20' will regulate the write current by dynamically adjusting the write driver 20 based on the inputs from the majority voting circuits 45 from each block 40a, 40b, 40c.

[0038] 8-10 show how the array shown in FIG. 7 can be biased to provide memory write and read capabilities, and an auxiliary column 15' containing watch cells 16 for monitoring external magnetic currents.

[0039] FIG. 8 is a circuit diagram of an MRAM array showing biasing for providing a write function that provides a bit data storage value of "0". In FIG. 8, a single write line (WL) is selected and the voltage is set equal to the WL activation voltage. The circuit for the bit line multiplexing (BL MUXING) 55 is biased by a thick OX field effect transistor (WR0BIAS) and the select line multiplexing (SL MUXING) is set to force low. The unselected portions of the array are identified by regions 70a, 70b. The write driver controller 20' sets the above-mentioned conditions for writing a "0". As described above, the write driver control circuit 20' will adjust the write current by dynamically adjusting the write driver 20 based on input from the majority circuit 45 from each block 40a, 40b, 40c to compensate for the presence of an external magnetic field.

[0040] FIG. 9 is a circuit diagram of an MRAM array showing biasing for providing a write function that provides a bit data storage value of "1". In FIG. 9, a single write line (WL) is selected and the voltage is set equal to the WL activation voltage. The circuitry for bit line multiplexing (BL MUXING) 55 is set to force low and the select line multiplexing (SL MUXING) is biased by thick OX field effect transistors (WR1BIAS). Unselected portions of the array are identified by regions 70c, 70d. The write driver controller 20' sets the above-mentioned conditions for writing a "1". As described above, the write driver control circuitry 20' will adjust the write current by dynamically adjusting the write driver 20 based on input from the majority circuitry 45 from each block 40a, 40b, 40c to compensate for the presence of an external magnetic field.

[0041] FIG. 10 is a circuit diagram of an MRAM array showing biasing for read function according to one embodiment of the present disclosure. In FIG. 10, a single write line (WL) is selected and the voltage is set equal to the WL activation voltage. The circuit for bit line multiplexing (BL MUXING) 55 is set to force low and the select line multiplexing (SL MUXING) is connected to the sense amplifier. The unselected portions of the array are identified by regions 70e, 70d. The write driver controller 20' sets the above conditions for reading.

[0042] FIG. 11 illustrates another embodiment of the present disclosure in which an external magnetic field is sensed in the presence of a memory cell and the write voltage is adjusted to compensate for the external magnetic field. FIG. 11 is a schematic diagram of an array of memory cells in which an external magnetic field is detected by monitoring changes in the write error rate. As with the embodiment illustrated in FIG. 7, the memory bank illustrated in FIG. 11 includes many BC arrays. All arrays have MTJs of nominal size and auxiliary columns 15' electrically connected to separate write paths. In this embodiment, the watch cells are biased at sub-nominal conditions compared to the bit cells in blocks 40a, 40b, 40c of the array. In some embodiments, a counter 60 is used to monitor the WER error rate of the watch cells and is periodically reset. For example, the counter 60 may monitor the WER error rate every 100-1000 write cycles. In the embodiment illustrated in FIG. 11, when the WER error rate indicates the presence of an external magnetic field, the write driver control circuitry will adjust the write current by dynamically adjusting the write driver based on the output of the counter.

[0043] In yet another embodiment, an alternative embodiment would shrink the access transistor to the watch cell. By shrinking the access transistor, the channel length is reduced and the write bias provided to the MTJ is reduced. Therefore, using the same bias conditions for the BC array and the watch cell array will result in a higher BER for the watch cell array. The operation mode of this embodiment is similar to the previous embodiment, but it brings further simplicity because the bias conditions for the watch cell do not need to be specially adjusted. In response to sensing the programming of the magnetic tunnel junction of the watch cell 16, the write driver control circuitry can adjust the write current by dynamically adjusting the write driver 20 to compensate for the external magnetic field.

[0044] The disclosed method and system advantageously allows for continued operation of the chip even when a magnetic field is detected. A circuit design including a magnetic field detection device coupled to a write driver will adjust the programming voltage to offset the effect of the external magnetic field on the chip error rate.

[0045] In addition, the magnetic field detection circuit 15 and the write driver 20 (collectively identified with reference numeral 300) shown in Figures 2 and 5 may be integrated into a processing system 400 shown in Figure 12. The processing system 400 includes at least one processor (CPU) 104 operatively coupled to other components via a system bus 102. Operatively coupled to the system bus 102 are a cache 106, a read only memory (ROM) 108, a random access memory (RAM) 110, an input / output (I / O) adapter 120, a sound adapter 130, a network adapter 140, a user interface adapter 150, and a display adapter 160. The bus 102 interconnects multiple components to be described herein.

[0046] 12 may further include a first storage device 122 and a second storage device 124, which are operably coupled to the system bus 102 by an I / O adapter 120. The storage devices 122 and 124 can be any of disk storage devices (e.g., magnetic or optical disk storage devices), solid-state magnetic devices, etc. The storage devices 122 and 124 can be the same type of storage device or different types of storage devices.

[0047] Speakers 132 are operably coupled to the system bus 102 by a sound adapter 130. A transceiver 142 is operably coupled to the system bus 102 by a network adapter 140. A display device 162 is operably coupled to the system bus 102 by a display adapter 160.

[0048] A first user input device 152, a second user input device 154, and a third user input device 156 are operatively coupled to the system bus 102 by a user interface adapter 150. The user input devices 152, 154, and 156 can be any of a keyboard, a mouse, a keypad, an image capture device, a motion sensing device, a microphone, a device incorporating the functionality of at least two of the above devices, and the like. Of course, other types of input devices can be used while maintaining the spirit of the invention. The user input devices 152, 154, and 156 can be the same type of user input device or different types of user input devices. The user input devices 152, 154, and 156 are used to input and output information to and from the system 400.

[0049] Of course, processing system 400 may also include other elements (not shown) and omit certain elements, as would be readily contemplated by one of ordinary skill in the art. For example, various other input and / or output devices may be included in processing system 400 depending on its particular implementation, as would be readily understood by one of ordinary skill in the art. For example, various types of wireless and / or wired input and / or output devices may be used. Furthermore, additional processors, controllers, memories, etc., in various configurations, may be utilized, as would be readily understood by one of ordinary skill in the art. These and other variations of processing system 400 are readily contemplated by one of ordinary skill in the art given the teachings of the invention provided herein.

[0050] As used herein, the term "hardware processor subsystem" or "hardware processor" can refer to a processor, memory, software, or combination thereof that work together to perform one or more specific tasks. In useful embodiments, the hardware processor subsystem can include one or more data processing elements (e.g., logic circuits, processing circuits, instruction execution devices, etc.). The one or more data processing elements can be included within a central processing unit, a graphics processing unit, or a separate processor or computing element-based controller (e.g., logic gates, etc.), or a combination thereof. The hardware processor subsystem can include one or more on-board memories (e.g., cache, dedicated memory array, read-only memory, etc.). In some embodiments, the hardware processor subsystem can include one or more memories that can be on or off-board or dedicated for use by the hardware processor subsystem (e.g., ROM, RAM, basic input / output system (BIOS), etc.).

[0051] In some embodiments, the hardware processor subsystem may include and execute one or more software elements, which may include an operating system, or one or more applications, or specific code for achieving a specified result, or any combination thereof.

[0052] In other embodiments, the hardware processor subsystem may include specialized circuitry dedicated to performing one or more electronic processing functions to achieve a specified result, which may include one or more application-specific integrated circuits (ASICs), FPGAs, and / or PLAs.

[0053] These and other variations of hardware processor subsystems are contemplated in accordance with embodiments of the present invention.

[0054] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0055] These computer readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus for producing a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, produce means for performing the functions / acts specified in the blocks or blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored in a computer readable storage medium that can cause a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions that perform aspects of the functions / acts specified in the blocks or blocks of the flowcharts and / or block diagrams.

[0056] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in the blocks or groups of blocks of the flowcharts and / or block diagrams, causing a series of operational steps to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process.

[0057] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for performing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the drawings. For example, two blocks shown in succession may in fact be fulfilled as one step and may be executed simultaneously, substantially simultaneously, partially or completely overlapping in time, or the blocks may sometimes be executed in reverse order depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or acts or executes a combination of dedicated hardware and computer instructions.

[0058] References herein to "one embodiment" of the present invention, or "an embodiment," as well as other variations thereof, mean that the particular features, structures, characteristics, etc. described in connection with the embodiment are included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," or "in an embodiment," as well as any other variations, appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0059] For example, in the cases of "A / B," "A or B or both," and "at least one of A and B," it will be understood that the use of any of the following " / ," "and / or," and "at least one of" is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As a further example, in the cases of "A, B, or C, or combinations thereof," and "at least one of A, B, and C," such language is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A and B), or the selection of only the first and third listed alternatives (A and C), or the selection of only the second and third listed alternatives (B and C), or the selection of all three alternatives (A and B and C). This can be expanded for the number of items listed, as would be readily apparent to one of ordinary skill in this and related arts.

[0060] Having described preferred embodiments of a system and method using a write driver with magnetic field compensation capabilities (intended as examples and not as limitations), it is noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having described above the aspects of the invention with particularity and as particularly required by the patent laws, what is claimed by Letters Patent and desired to be protected is set forth in the appended claims.

Claims

1. 1. A method for compensating for an external magnetic field in a memory device, comprising: positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, a write driver in electrical communication with the at least one external magnetic field sensing element and the at least one array of memory cells, the at least one external magnetic field sensing element being a watch cell including a watch cell access transistor to a watch cell magnetic tunnel junction having a different bias condition than a bit cell access transistor to a bit cell magnetic tunnel junction; monitoring the at least one external magnetic field sensing element for a signal indicative of the presence of an external magnetic field; adjusting a write current to the at least one array of memory cells by adjusting the write driver; A method comprising:

2. 2. The method of claim 1, wherein the array of memory cells includes bit cells having a bit cell magnetic tunnel junction (MTJ).

3. 2. The method of claim 1, wherein the watch cell comprises a watch cell magnetic tunnel junction (MTJ) structure having a larger diameter than the bit cell MTJ.

4. 2. The method of claim 1, wherein the watch cell comprises a watch cell magnetic tunnel junction (MTJ) having a magnetic anisotropy field (Hk) characteristic different from a Hk characteristic of the bit cell MTJ.

5. 2. The method of claim 1, wherein the watch cell includes a watch cell access transistor to a watch cell magnetic tunnel junction having a different dimension than a bit cell access transistor to the bit cell magnetic tunnel junction.

6. 6. The method of claim 1, wherein monitoring the at least one external magnetic field sensing element for a signal indicative of the presence of an external magnetic field comprises measuring programming of a watch cell when a bit cell is not correspondingly programmed substantially simultaneously.

7. 7. The method of claim 1, wherein monitoring the at least one external magnetic field sensing element for a signal indicative of the presence of an external magnetic field comprises measuring a change in a write error rate (WER) of the watch cell.

8. The method according to any one of claims 1 to 7, wherein the external magnetic field sensing element is a magnetic field sensor.

9. The method of any one of claims 1 to 8, wherein the watch cells are positioned on the periphery of a block of a bit cell array.

10. 1. A method for compensating for an external magnetic field in a memory device, comprising: positioning at least one watch cell adjacent to at least one array of memory cells, a write driver in electrical communication with the at least one watch cell and the at least one array of memory cells, the watch cell including a watch cell access transistor to a watch cell magnetic tunnel junction having a different bias condition than a bit cell access transistor to a bit cell magnetic tunnel junction; monitoring the at least one watch cell for a variation in a write error rate (WER) from a baseline write error rate, the variation indicating the presence of an external magnetic field; adjusting a write current to the at least one array of memory cells by adjusting the write driver to compensate for an external magnetic field measured by monitoring the at least one watch cell; A method comprising:

11. 1. A memory device comprising: at least one block of bit cells including a plurality of memory cells and at least one subgroup of watch cells on a periphery of a memory array, the at least one subgroup of watch cells measuring an external magnetic field in a vicinity of the plurality of memory cells; a write driver circuit in electrical communication with at least the plurality of memory cells; a counter for recording when the at least one subgroup of watch cells measures the external magnetic field, the counter being in electrical communication with the write driver circuit, a write driver of the write driver circuit adjusting write currents to the plurality of memory cells to compensate for the external magnetic field; Equipped with A memory device, wherein the watch cell includes a watch cell access transistor to a watch cell magnetic tunnel junction that has a different bias condition than a bit cell access transistor to the bit cell magnetic tunnel junction.

12. The memory device of claim 11 , wherein the plurality of memory cells includes bit cells having a bit cell magnetic tunnel junction (MTJ).

13. 13. The memory device of claim 12, wherein the watch cell comprises a watch cell magnetic tunnel junction (MTJ) structure having a larger diameter than the bit cell MTJ.

14. 13. The memory device of claim 12, wherein the watch cell comprises a watch cell magnetic tunnel junction (MTJ) having a magnetic anisotropy field (Hk) characteristic different from a Hk characteristic of the bit cell MTJ.

15. 15. The memory device of claim 11, wherein monitoring the at least one watch cell for a signal indicative of the presence of an external magnetic field comprises measuring programming of a watch cell when a bit cell is not correspondingly programmed substantially simultaneously.

16. 16. The memory device of claim 11, wherein monitoring the at least one watch cell for a signal indicative of the presence of an external magnetic field comprises measuring a change in a write error rate (WER) of the watch cell.

17. The memory device of any one of claims 11 to 16, wherein the watch cells are positioned on the periphery of a block of a bit cell array.

18. 1. A memory device comprising: at least one block of bit cells including a plurality of memory cells and at least one subgroup of watch cells on a periphery of a memory array, the at least one subgroup of watch cells measuring an external magnetic field in a vicinity of the plurality of memory cells, the plurality of memory cells including bit cells having a bit cell magnetic tunnel junction (MTJ), the subgroup of watch cells including a magnetic tunnel junction (MTJ) structure having a diameter larger than that of the bit cell magnetic tunnel junction (MTJ); a write driver circuit in electrical communication with at least the plurality of memory cells, the write driver of the write driver circuit adjusting write currents to the plurality of memory cells to compensate for the external magnetic field; A memory device comprising:

19. 20. The memory device of claim 18, wherein the watch cells are located on the periphery of a block of a bit cell array.

20. 1. A memory device comprising:

1. A memory device comprising: at least one block of bit cells including a plurality of memory cells and at least one auxiliary group of watch cells on the periphery of a memory array, the at least one auxiliary group of watch cells measuring an external magnetic field in the vicinity of the plurality of memory cells, the plurality of memory cells including bit cells having a bit cell magnetic tunnel junction (MTJ), the watch cell including a watch cell magnetic tunnel junction having a magnetic anisotropy field (Hk) characteristic different from a magnetic anisotropy field (Hk) characteristic of the bit cell magnetic tunnel junction (MTJ), and a watch cell access transistor to the watch cell magnetic tunnel junction having a different bias condition than a bit cell access transistor to the bit cell magnetic tunnel junction.

21. 21. The memory device of claim 20, wherein the watch cells are located on the periphery of a block of a bit cell array.

22. 22. The memory device of claim 21 further comprising a counter for recording when said at least one subgroup of watch cells measures said external magnetic field.

Images