Data transmission and processing method, distributed unit, wireless unit and computer-readable storage medium

Abstract

A data transmission method, which relates to the field of communications technology, includes a step (S110) of reading data to be transmitted from a local on-chip memory device based on a plurality of descriptors and a step (S120) of transmitting the data to be transmitted based on the plurality of descriptors, wherein the plurality of descriptors are for defining a storage form of the data to be transmitted in the on-chip memory device and a form of existence of the data to be transmitted in a transmission link when transmitting the data to be transmitted. A data processing method, a distributed unit, a wireless unit, and a computer-readable storage medium are also provided.

Description

[Technical field]

[0001] This disclosure claims priority to a Chinese patent application bearing application number 202010994936.6, filed with the China Patent Office on September 21, 2020, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The embodiments of the present disclosure relate to the field of communications technology. [Background technology]

[0003] In an Open Radio Access Network (O-RAN), the base station is divided into an O-RAN Distributed Unit (O-DU) and an O-RAN Radio Unit (O-RU). The O-RU is controlled by the O-DU and communicates with the O-DU via optical fiber. Summary of the Invention

[0004] One aspect of an embodiment of the present disclosure provides a data transmission method including the steps of reading data to be transmitted corresponding to a plurality of descriptors from a local on-chip memory device based on the plurality of descriptors, and transmitting the data to be transmitted based on the plurality of descriptors, wherein the plurality of descriptors are for limiting a storage form of the data to be transmitted in the on-chip memory device and a presence form of the data to be transmitted in a transmission link when transmitting the data to be transmitted.

[0005] Another aspect of an embodiment of the present disclosure provides a data processing method including: generating, based on received control data, a plurality of descriptors corresponding to data to be transmitted that corresponds to the control data; and writing the data to be transmitted to a local on-chip memory device based on the plurality of descriptors, wherein the plurality of descriptors are for limiting a storage form of the data to be transmitted in the on-chip memory device and a form in which the data to be transmitted exists in a transmission link when the data to be transmitted is transmitted.

[0006] Yet another aspect of an embodiment of the present disclosure provides a distributed unit including one or more processors and a memory having one or more programs stored therein that, when executed by the one or more processors, cause the one or more processors to implement a data transmission method provided by an embodiment of the present disclosure.

[0007] Yet another aspect of an embodiment of the present disclosure provides a wireless unit including one or more processors and a memory having one or more programs stored therein that, when executed by the one or more processors, cause the one or more processors to implement a data processing method provided by an embodiment of the present disclosure.

[0008] Yet another aspect of an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, realizing at least one of a data transmission method provided by an embodiment of the present disclosure and a data processing method provided by an embodiment of the present disclosure. [Brief description of the drawings]

[0009] [Figure 1a] FIG. 2 is a schematic diagram of the communication process between the O-DU and the O-RU. [Figure 1b] FIG. 2 is a schematic diagram of the communication process between the O-DU and the O-RU. [Diagram 2] 2 is a flowchart of a data transmission method provided by an embodiment of the present disclosure. [Diagram 3] 4 is a flowchart of some steps of a data transmission method provided by an embodiment of the present disclosure. [Figure 4] 4 is a flowchart of some steps of a data transmission method provided by an embodiment of the present disclosure. [Diagram 5] 4 is a flowchart of some steps of a data transmission method provided by an embodiment of the present disclosure. [Figure 6]4 is a flowchart of some steps of a data transmission method provided by an embodiment of the present disclosure. [Figure 7] 4 is a flowchart of some steps of a data transmission method provided by an embodiment of the present disclosure. [Figure 8] 4 is a flowchart of some steps of a data transmission method provided by an embodiment of the present disclosure. [Figure 9] 4 is a flowchart of some steps of a data transmission method provided by an embodiment of the present disclosure. [Figure 10] 1 is a flowchart of a data processing method provided by an embodiment of the present disclosure. [Figure 11] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 12] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 13] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 14] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 15] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 16] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 17] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 18] 4 is a flowchart of some steps of a data processing method provided by an embodiment of the present disclosure. [Figure 19] FIG. 2 is a block diagram of a distributed unit provided by an embodiment of the present disclosure. [Figure 20] FIG. 2 is a configuration block diagram of a wireless unit provided by an embodiment of the present disclosure. [Figure 21] FIG. 2 is a block diagram of a computer-readable storage medium provided by an embodiment of the present disclosure. [Figure 22] FIG. 2 is a schematic diagram showing the correspondence between data segments and descriptors provided by an embodiment of the present disclosure. [Diagram 23] FIG. 2 is a schematic diagram of a storage format of a descriptor provided by an embodiment of the present disclosure. [Figure 24] FIG. 2 is a schematic diagram of another storage format of a descriptor provided by an embodiment of the present disclosure. [Diagram 25] FIG. 2 is a schematic diagram of an O-DU and an O-RU provided by an embodiment of the present disclosure communicating via downlink; [Figure 26] FIG. 2 is a schematic diagram of an O-DU and an O-RU provided by an embodiment of the present disclosure communicating via an uplink; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the following provides a detailed description of the data transmission method, data processing method, distributed unit, wireless unit, and computer-readable storage medium provided in the present disclosure in combination with the drawings.

[0011] Exemplary embodiments are described more fully below with reference to the drawings, which may be embodied in different forms and should not be construed as being limited to the embodiments described herein, but rather are provided so that the disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0012] Unless contradictory, each embodiment and each feature in the embodiments of the present disclosure can be combined with each other.

[0013] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0014] The terms used herein are used only to describe certain embodiments and are not intended to limit the present disclosure. As used herein, the singular terms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. Furthermore, when the terms "comprising" and / or "comprising" are used herein, they refer to the presence of the features, wholes, steps, operations, elements, and / or assemblies, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, assemblies, and / or groups thereof.

[0015] Unless otherwise specified, the meaning of all terms (including technical and scientific terms) used herein is the same as that commonly understood by those skilled in the art. Furthermore, these terms defined in common dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and this disclosure, and should not be interpreted as having an idealized or excessively formal meaning unless expressly specified herein.

[0016] 1a and 1b are signaling diagrams of the communication process between the O-DU and the O-RU. As shown in Fig. 1a, in the downlink, the O-DU transmits control data to the O-RU, and the O-RU receives user data transmitted by the O-DU based on the received control data. As shown in Fig. 1b, in the uplink, the O-DU transmits control data to the O-RU, and the O-RU transmits user data to the O-DU based on the received control data.

[0017] However, in order to improve system throughput and save system cache resources in the communication process between the O-DU and O-RU as shown in Figures 1a and 1b, a general-purpose processor or accelerator, etc., needs to buffer control data to be transmitted or user data such as symbol 0, symbol 1, ..., symbol N in advance in an on-chip memory device on the O-DU or O-RU side. The inventors of the present disclosure have found that, since the general-purpose processor or accelerator frequently accesses the on-chip memory device, the bus is occupied for a long time, resulting in low data read / write efficiency in the communication process between the O-DU and O-RU.

[0018] In view of this, an embodiment of the present disclosure aims to provide an O-RAN fronthaul Direct Memory Access (DMA) method, where DMA is an interface technology that allows an external device to directly exchange data with a system memory without going through a Central Processing Unit (CPU).

[0019] In a first aspect, as shown in FIG. 2, an embodiment of the present disclosure provides a data transmission method, which includes steps S110 and S120.

[0020] In step S110, data to be transmitted corresponding to the plurality of descriptors is read from a local on-chip memory device based on the plurality of descriptors.

[0021] In step S120, the transmission target data is transmitted based on the plurality of descriptors.

[0022] The descriptor is intended to define the storage form of the data to be transmitted in the on-chip memory device and the form in which the data to be transmitted exists in the transmission link when the data to be transmitted is transmitted.

[0023] In the embodiment of the present disclosure, the descriptor is an intermediate parameter for transmitting data in an on-chip memory device in an O-DU. The descriptor corresponds to data to be transmitted, and each descriptor defines the size, content, storage form, etc. of the corresponding data to be transmitted. The hardware logic can identify the storage location of the data to be transmitted corresponding to the descriptor in the on-chip memory device by analyzing the descriptor, thereby reading the user data to be transmitted corresponding to the descriptor from the on-chip memory device to realize DMA. The descriptor further defines the existence form of the data to be transmitted in the link between the O-DU and the O-RU, and the hardware logic can transmit the data to be transmitted through the link by analyzing the descriptor.

[0024] In addition, in the embodiment of the present disclosure, the link between the O-DU and the O-RU is a downlink in the direction from the O-DU to the O-RU, and an uplink in the direction from the O-RU to the O-DU.

[0025] The embodiment of the present disclosure does not particularly limit how the descriptor is constructed, and as an optional embodiment, the descriptor can be designed and constructed by the user based on the actual situation of the system.

[0026] In the embodiment of the present disclosure, the data to be transmitted may be control data for managing and controlling the operation of the O-RU, may be user data, or may be time information (sync message) for system synchronization. The user data to be transmitted may be downlink user data, i.e., user data transmitted by the O-DU to the O-RU, or may be uplink user data, i.e., user data transmitted by the O-RU to the O-DU.

[0027] In addition, when the data to be transmitted is user data, the transmission of the data to be transmitted in step S120 may be to transmit the user data to the O-RU via the downlink, or to receive the user data transmitted by the O-RU via the uplink.

[0028] In the data transmission method provided by the embodiment of the present disclosure, a descriptor is constructed to allow the hardware logic to directly access the on-chip memory device, and the data to be transmitted is read from the on-chip memory device and transmitted, thereby reducing the frequency of direct communication between the general-purpose processor or accelerator and the on-chip memory device during the communication process between the O-DU and the O-RU, thereby reducing the bus occupation time and improving the efficiency of data reading and writing. The descriptor further defines the storage form of the data to be transmitted in the on-chip memory device, thereby improving the utilization rate and flexibility of the on-chip memory device. The descriptor in the embodiment of the present disclosure can also be constructed by the user, thereby further improving the flexibility and extensibility of access to the on-chip memory device during the communication process between the O-DU and the O-RU.

[0029] In the embodiment of the present disclosure, the descriptor is specifically a set of at least one parameter arranged by a software layer, the parameters constituting the descriptor include a parameter defining a storage form of the data to be transmitted in the on-chip memory device, the hardware logic analyzes the parameter defining the storage form of the data to be transmitted in the on-chip memory device in the descriptor to identify the storage location information of the data to be transmitted corresponding to the descriptor in the on-chip memory device, and further reads the data to be transmitted corresponding to the descriptor from the on-chip memory device in step S110.

[0030] In the embodiment of the present disclosure, there is no particular limitation on how the multiple descriptors correspond to the data to be transmitted. As an optional embodiment, the data to be transmitted by the O-DU is segmented to obtain multiple data segments, and each descriptor corresponds to one data segment. Each descriptor defines information such as the storage form of the corresponding data segment in the on-chip memory device and the existence form in the link. By storing the data segment to be transmitted in the on-chip memory device, the flexibility of data storage and access in the on-chip memory device can be further improved. Furthermore, the storage information of the data segment corresponding to the descriptor in the on-chip memory device is placed in the parameter that defines the storage form of the data to be transmitted in the on-chip memory device in the descriptor.

[0031] Accordingly, as an optional embodiment, the data to be transmitted includes multiple data segments, each of which corresponds to one data segment, and the descriptor includes a data address parameter in which data storage information in the on-chip memory device for the data segment to which the descriptor corresponds is located.

[0032] 3, step S110 includes step S111. In step S111, read a data segment corresponding to the descriptor from an on-chip memory device based on data storage information located in a data address parameter in the descriptor.

[0033] In the embodiments of the present disclosure, the specific content of the data storage information is not particularly limited. For example, the data storage information may include a starting address of a storage space in an on-chip memory device for storing a data segment corresponding to a descriptor, a size of the storage space, etc.

[0034] In the embodiment of the present disclosure, there is no particular limitation on how to segment the data to be transmitted to obtain multiple data segments. For example, data that an O-DU needs to transmit within a certain time period can be one data segment, and data that an O-DU needs to transmit within a certain time period can be divided into multiple data segments in units of symbols, for example, one symbol can be one data segment, or multiple symbols can be one data segment.

[0035] In an alternative embodiment, a general purpose processor or accelerator segments the data that the O-DU needs to transmit and stores the segments in an on-chip memory device.

[0036] In an embodiment of the present disclosure, the parameters constituting the descriptor further include a parameter defining the existence form of the data to be transmitted in the link. The hardware logic analyzes the parameter defining the existence form of the data to be transmitted in the link in the descriptor, and transmits the read data to be transmitted in step S120. Furthermore, the existence form information of the data segment in the link corresponding to the descriptor is placed in the parameter defining the existence form of the data to be transmitted in the link in the descriptor. As an optional embodiment, the existence form information of the data segment in the link includes, but is not limited to, frame format information, time domain information, and frequency domain information.

[0037] Accordingly, as an optional embodiment, the descriptor further includes frame format parameters, time domain parameters and frequency domain parameters, in which frame format information of the data segment corresponding to the descriptor is arranged in the frame format parameters, time domain information of the data segment corresponding to the descriptor is arranged in the time domain parameters and frequency domain information of the data segment corresponding to the descriptor is arranged in the frequency domain parameters.

[0038] 4, step S120 includes step S121. In step S121, data to be transmitted is framed and transmitted based on the frame format information allocated to the frame format parameter in each descriptor, the time domain information allocated to the time domain parameter, and the frequency domain information allocated to the frequency domain parameter.

[0039] In the embodiments of the present disclosure, the content of the frame format information is not particularly limited, for example, the frame format information includes a frame type, a frame length, etc. In the embodiments of the present disclosure, the content of the time domain information is not particularly limited, for example, the frequency domain information includes a starting physical resource block (PRB) number. In the embodiments of the present disclosure, the content of the time domain information is not particularly limited, for example, the time domain information includes a 10 ms frame number, a 1 ms subframe number, link delay information, etc.

[0040] In the embodiment of the present disclosure, the descriptor is also stored in the on-chip memory device, and the hardware logic can directly access the on-chip memory device to read the descriptor, and then read and transmit the data to be transmitted stored in the on-chip memory device according to the descriptor from step S110 to step S120.

[0041] Accordingly, as shown in FIG. 5, as an optional embodiment, before step S110, the data transmission method further includes step S130.

[0042] In step S130, a number of descriptors are read from the on-chip memory device.

[0043] The embodiment of the present disclosure does not particularly limit how step S130 is performed. As an optional embodiment, the hardware logic reads the descriptor from the on-chip memory device at a fixed time based on the storage location information of the descriptor in the on-chip memory device.

[0044] Accordingly, as an alternative embodiment, step S130 includes step S131, as shown in Figure 6. In step S131, a number of descriptors are read from an on-chip memory device periodically.

[0045] In the embodiment of the present disclosure, the storage form of the descriptor in the on-chip memory device is not particularly limited. As an optional embodiment, the descriptor can be stored discretely in the on-chip memory device. For example, the storage address of the next descriptor is taken as one of the parameters of the current descriptor to realize the concatenated storage of the descriptor, and the hardware logic obtains the storage location of the next descriptor by analyzing the parameters of the current descriptor, thereby completing the reading and writing of all the descriptors.

[0046] Accordingly, as an optional embodiment, the descriptor further includes a descriptor address parameter, the descriptor storage information is located in the descriptor address parameter of the current descriptor, and the descriptor storage information is used to characterize the storage information in the on-chip memory device of the next descriptor of the current descriptor, and step S130 includes step S132 as shown in FIG. 7.

[0047] In step S132, the next descriptor is read based on the descriptor storage information placed in the descriptor address parameter of the current descriptor.

[0048] It should be noted that in the embodiment of the present disclosure, if the current descriptor is the last descriptor, the descriptor address parameter of the current descriptor may be empty, that is, no descriptor storage information is allocated, and the descriptor storage information of the first descriptor may be allocated to the descriptor address parameter of the current descriptor, thereby realizing circular linked storage, which is not particularly limited in the embodiment of the present disclosure.

[0049] In the embodiment of the present disclosure, the descriptor storage information includes, but is not limited to, information such as the start address of the storage space in the on-chip memory device where the descriptor is stored and the size of the storage space.

[0050] As another alternative embodiment, the descriptors can be stored contiguously in an on-chip memory device, for example, an address space is pre-designated as a dedicated storage space for the descriptors, the addresses of each parameter of the descriptors are fixed and known, and a general-purpose processor, accelerator, hardware logic, etc. cyclically reads and writes the descriptors in the storage space.

[0051] Accordingly, as an optional embodiment, step S130 includes steps S133 and S134, as shown in FIG.

[0052] In step S133, the start addresses of the multiple descriptors in the on-chip memory device are obtained.

[0053] In step S134, a plurality of descriptors are read from a storage space that stores a plurality of descriptors in an on-chip memory device based on the leading address.

[0054] In an embodiment of the present disclosure, the storage space in the on-chip memory device for storing the multiple descriptors is a contiguous address space. As an alternative embodiment, the initial addresses of the multiple descriptors in the on-chip memory device are default. The hardware logic reads the multiple descriptors cyclically starting from the first descriptor based on the default initial address.

[0055] In the embodiment of the present disclosure, the descriptor may be arranged by a general-purpose processor or accelerator, or may be arranged by hardware logic, but the embodiment of the present disclosure is not particularly limited thereto.

[0056] Accordingly, as shown in FIG. 9, as an optional embodiment, before step S110, the data transmission method further includes steps S141 and S142.

[0057] In step S141, a plurality of descriptors are arranged.

[0058] In step S142, the arranged multiple descriptors are stored in an on-chip memory device.

[0059] In addition, in an embodiment of the present disclosure, placing a descriptor means placing data storage information in the on-chip memory device of the data segment corresponding to the descriptor in the data address parameter of the descriptor, placing frame format information of the data segment corresponding to the descriptor in the frame format parameter, placing time domain information of the data segment corresponding to the descriptor in the time domain parameter, placing frequency domain information of the data segment corresponding to the descriptor in the frequency domain parameter, placing descriptor storage information in the on-chip memory device of the next descriptor in the descriptor address parameter, and placing corresponding information in other parameters.

[0060] The embodiment of the present disclosure does not particularly limit how to construct the descriptor. As an optional embodiment, the descriptor can be designed and constructed by a user based on the actual situation of the system, thereby improving the flexibility and extensibility of access to the on-chip memory device in the communication process between the O-DU and the O-RU.

[0061] In the embodiment of the present disclosure, constructing a descriptor means specifying the number, types, etc. of parameters in the descriptor, such as data address parameters, frame format parameters, time domain parameters, frequency domain parameters, and descriptor address parameters.

[0062] In a second aspect, as shown in FIG. 10, an embodiment of the present disclosure provides a data processing method, which includes step S210 and step S220.

[0063] In step S210, a plurality of descriptors corresponding to the transmission target data corresponding to the control data are generated based on the received control data.

[0064] In step S220, data to be transmitted is written to a local on-chip memory device based on the plurality of descriptors.

[0065] The descriptor is intended to define the storage form of the data to be transmitted in the on-chip memory device and the existence form of the data to be transmitted in the transmission link when the data to be transmitted is transmitted.

[0066] In the embodiment of the present disclosure, the descriptor is an intermediate parameter for transmitting data in an on-chip memory device in the O-RU. The descriptor corresponds to data to be transmitted, and each descriptor defines the size, content, storage form, etc. of the corresponding data to be transmitted. The hardware logic can identify the storage location of the data to be transmitted corresponding to the descriptor in the on-chip memory device by analyzing the descriptor, thereby writing the data to be transmitted to the on-chip memory device and reading the user data to be transmitted corresponding to the descriptor from the on-chip memory device to realize DMA. The descriptor further defines the existence form of the data to be transmitted in the link between the O-DU and the O-RU, and the hardware logic can transmit the data to be transmitted through the link by analyzing the descriptor. The O-RU side completes local data caching and framing by analyzing the information sent from the O-DU side, and realizes remote direct memory access (RDMA).

[0067] In addition, in the embodiment of the present disclosure, the link between the O-DU and the O-RU is a downlink in the direction from the O-DU to the O-RU, and an uplink in the direction from the O-RU to the O-DU.

[0068] Control data, user data, time data, etc. are communicated between the O-DU and the O-RU. In the downlink, the O-DU transmits control data to the O-RU via a control channel, and after the O-RU is ready to receive new data, it transmits the corresponding user data again in sequence. In the uplink, the O-DU transmits control data to the O-RU via a control channel, and the O-RU frames the user data based on the received control data and transmits it to the O-DU. The control data defines frame configuration information, frequency domain information, time domain information, etc. of the user data corresponding to the control data, and step S210 is a process in which the hardware logic on the O-RU side receives the control data and then maps the frame configuration information, frequency domain information, time domain information, etc. defined in the control data to a descriptor.

[0069] In the embodiment of the present disclosure, the data to be transmitted may be user data that the O-DU transmits to the O-RU via the downlink, may be user data that the O-RU needs to transmit to the O-DU via the uplink, or may be other data. The embodiment of the present disclosure is not particularly limited thereto.

[0070] In the data processing method provided by the embodiment of the present disclosure, a descriptor is constructed based on the received control data, so that the hardware logic can directly access the on-chip memory device, and the data to be transmitted is written to the on-chip memory device, thereby reducing the frequency of direct communication between the general-purpose processor or accelerator and the on-chip memory device during the communication process between the O-DU and the O-RU, thereby reducing the bus occupation time and improving the efficiency of data reading and writing. The descriptor further defines the storage form of the data to be transmitted in the on-chip memory device, thereby improving the utilization rate and flexibility of the on-chip memory device. The descriptor in the embodiment of the present disclosure can also be constructed by the user, thereby further improving the flexibility and extensibility of access to the on-chip memory device during the communication process between the O-DU and the O-RU.

[0071] In the embodiment of the present disclosure, the descriptor is specifically a set of at least one parameter arranged by a software layer. The parameters constituting the descriptor include a parameter defining a storage format of the data to be transmitted in the on-chip memory device, and in step S210, storage information of the data to be transmitted in the on-chip memory device is arranged in the parameter defining the storage format of the data to be transmitted in the on-chip memory device in the descriptor based on the control data, and further in step S220, the data to be transmitted is written to the on-chip memory device.

[0072] In the embodiment of the present disclosure, there is no particular limitation on how the multiple descriptors correspond to the data to be transmitted. As an optional embodiment, the data to be transmitted is segmented to obtain multiple data segments, and each descriptor corresponds to one data segment. Here, each descriptor defines information such as the storage form of the corresponding data segment in the on-chip memory device and the existence form in the link. By storing the data segment to be transmitted in the on-chip memory device, the flexibility of data storage and access in the on-chip memory device can be further improved. Furthermore, in the process of generating the descriptor in step S210, the storage information of the data segment corresponding to the descriptor in the on-chip memory device is placed in the parameter that defines the storage form of the data to be transmitted in the on-chip memory device in the descriptor.

[0073] Accordingly, as an optional embodiment, the data to be transmitted includes multiple data segments, each of which corresponds to one data segment, and the descriptor includes a data address parameter, and as shown in FIG. 11, step S210 includes step S211.

[0074] In step S211, based on the control data, data storage information for storing the data segment corresponding to the descriptor in the on-chip memory device is configured in the data address parameter.

[0075] In the embodiments of the present disclosure, the specific content of the data storage information is not particularly limited. For example, the data storage information may include a starting address of a storage space in an on-chip memory device for storing a data segment corresponding to a descriptor, a size of the storage space, etc.

[0076] In an embodiment of the present disclosure, when the data to be transmitted is user data, the data to be transmitted may be user data transmitted by an O-DU to an O-RU via a downlink, or may be user data that an O-RU needs to transmit to an O-DU via an uplink.

[0077] In an embodiment of the present disclosure, the parameters constituting the descriptor further include a parameter defining the existence form of the data to be transmitted in the link. The hardware logic analyzes the parameters defining the existence form of the data to be transmitted in the link in the descriptor, and identifies the existence form of the data to be transmitted in the downlink to establish a mapping relationship between the user data to be transmitted by the O-DU to the O-RU and the descriptor, or identifies the existence form of the data to be transmitted in the uplink to establish a mapping relationship between the user data to be transmitted by the O-RU to the O-DU via the uplink and the descriptor. Furthermore, in the process of generating the descriptor in step S210, the existence form information of the data segment in the link corresponding to the descriptor is placed in the parameters defining the existence form of the data to be transmitted in the link in the descriptor. As an optional embodiment, the existence form information of the data segment in the link includes, but is not limited to, frame format information, time domain information, and frequency domain information.

[0078] Accordingly, as an optional embodiment, the descriptor further includes frame format parameters, time domain parameters and frequency domain parameters, and as shown in FIG. 11, step S210 further includes step S212, step S213 and step S214.

[0079] In step S212, frame format information of the data segment corresponding to the descriptor is arranged in the frame format parameter according to the control data.

[0080] In step S213, time domain information of the data segment corresponding to the descriptor is arranged in the time domain parameter according to the control data.

[0081] In step S214, frequency domain information of the data segment corresponding to the descriptor is arranged in the frequency domain parameter according to the control data.

[0082] In an embodiment of the present disclosure, when the data to be transmitted is data to be transmitted upstream, the storage information of the data to be transmitted upstream in the on-chip memory device is arranged in the descriptor generated in step S210, so that the size of each data segment can be determined based on the storage information when storing the data segments to be transmitted upstream in the on-chip memory device. As an optional embodiment, the data to be transmitted upstream is segmented based on the descriptor to obtain the data segments corresponding to the descriptor. Furthermore, each data segment is written to the on-chip memory device in step S220.

[0083] Accordingly, as an optional embodiment, the data to be transmitted includes data to be transmitted upstream, and as shown in FIG. 12, before step S220, the data processing method further includes step S230.

[0084] In step S230, the data to be transmitted upstream is segmented based on the storage address information allocated in the descriptor, and a data segment corresponding to the descriptor is obtained.

[0085] In an embodiment of the present disclosure, when the data to be transmitted is data to be transmitted downstream, information indicating the form in which the data to be transmitted downstream exists in the downlink is placed in the descriptor generated in step S210, and the data segment corresponding to the descriptor can be identified by the information indicating the form in which the data to be transmitted downstream exists in the downlink, which is placed in the descriptor.

[0086] Accordingly, as an optional embodiment, the data to be transmitted includes data to be transmitted downstream, and as shown in FIG. 13, before step S220, the data processing method further includes step S240.

[0087] In step S240, the data to be transmitted downstream is processed based on the frame format information assigned to the frame format parameters, the time domain information assigned to the time domain parameters, and the frequency domain information assigned to the frequency domain parameters, to obtain a plurality of data segments corresponding to a plurality of descriptors.

[0088] In the embodiment of the present disclosure, after receiving the control data sent by the O-DU, the O-RU allocates a storage space to each data segment, and places the address information of the storage space allocated to each data segment in a descriptor corresponding to the data segment in step S210. When writing the data to be transmitted to the on-chip memory device in step S220, the data segment is written to the pre-allocated storage space based on the address information placed in the descriptor corresponding to the data segment.

[0089] Accordingly, as an optional embodiment, step S220 includes step S221, as shown in Fig. 14. In step S221, the data segment is written to the on-chip memory device based on data storage information located in a data address parameter in a descriptor corresponding to the data segment.

[0090] In the embodiment of the present disclosure, the descriptor generated in step S210 is also stored in the on-chip memory device. In the embodiment of the present disclosure, the storage form of the descriptor in the on-chip memory device is not particularly limited. As an optional embodiment, the descriptor can be stored discretely in the on-chip memory device. For example, the storage address of the next descriptor is taken as one of the parameters of the current descriptor to realize the concatenated storage of the descriptor, and the hardware logic obtains the storage location of the next descriptor by analyzing the parameters of the current descriptor, thereby completing the reading and writing of all the descriptors.

[0091] Accordingly, as an alternative embodiment, the descriptor further includes a descriptor address parameter, and as shown in FIG. 15, step S210 further includes step S215 and step S216.

[0092] In step S215, the descriptor storage information in the on-chip memory device of the plurality of descriptors is identified.

[0093] In step S216, the descriptor storage information in the on-chip memory device of the next descriptor is placed in the descriptor address parameter.

[0094] In an embodiment of the present disclosure, after the O-RU writes the data to be transmitted into the on-chip memory device, it further transmits user data transmitted by the O-DU to the O-RU via the downlink to a downstream module, or transmits user data that the O-RU needs to transmit to the O-DU via the uplink to the O-DU.

[0095] Accordingly, as shown in FIG. 16, as an optional embodiment, the data processing method further includes steps S250 and S260.

[0096] In step S250, based on the plurality of descriptors, data to be transmitted that corresponds to the plurality of descriptors and is stored in the on-chip memory device is read.

[0097] In step S260, the transmission target data is transmitted based on the plurality of descriptors.

[0098] In an embodiment of the present disclosure, when the data to be transmitted is data to be transmitted uplink, step S260 includes framing the data to be transmitted and transmitting it to an O-DU based on frame format information assigned to the frame format parameters in each descriptor, time domain information assigned to the time domain parameters, and frequency domain information assigned to the frequency domain parameters.

[0099] If the data to be transmitted is data to be transmitted downstream, step S260 includes sending the data to be transmitted to a subsequent module.

[0100] Accordingly, as an optional embodiment, step S250 includes step S251, as shown in Fig. 17. In step S251, a data segment corresponding to the descriptor is read from an on-chip memory device based on data storage information located in a data address parameter in the descriptor.

[0101] In the embodiment of the present disclosure, the descriptor is also stored in the on-chip memory device, and the hardware logic can directly access the on-chip memory device to read the descriptor, and then read and transmit the data to be transmitted stored in the on-chip memory device according to the descriptor through steps S250 to S260.

[0102] Accordingly, as an optional embodiment, before step S250, the data processing method further includes step S270, as shown in Fig. 16. In step S270, a plurality of descriptors are read from an on-chip memory device.

[0103] The embodiment of the present disclosure does not particularly limit how step S270 is performed. As an optional embodiment, the hardware logic reads the descriptor from the on-chip memory device at a fixed time based on the storage location information of the descriptor in the on-chip memory device.

[0104] Accordingly, as shown in FIG. 18, in an optional embodiment, in step S270, a number of descriptors are periodically read from an on-chip memory device.

[0105] In a third aspect, as shown in FIG. 19, an embodiment of the present disclosure provides a distributed unit including one or more processors 101, a memory 102 in which one or more programs are stored, and which, when executed by the one or more processors 101, causes the one or more processors 101 to realize a data transmission method provided by an embodiment of the present disclosure, and one or more I / O interfaces (read / write interfaces) 103 connected between the processor 101 and the memory 102 and configured to realize information exchange between the processor 101 and the memory 102.

[0106] The processor 101 is a device having a data processing capability, and includes, but is not limited to, a CPU. The memory 102 is a device having a data storage capability, and includes, but is not limited to, a random access memory (RAM, more specifically, a synchronous dynamic random-access memory (SDRAM), a read-only memory (ROM), an electrically erasable programmable read only memory (EEPROM), and a flash memory (FLASH). The I / O interface 103 is connected between the processor 101 and the memory 102, and can realize the exchange of information between the processor 101 and the memory 102, and includes, but is not limited to, a data bus.

[0107] In an alternative embodiment, the processor 101, memory 102 and I / O interface 103 are connected to each other and to other components of the distributed unit by a bus 104.

[0108] In a fourth aspect, as shown in FIG. 20 , an embodiment of the present disclosure provides a wireless unit including one or more processors 201, a memory 202 in which one or more programs are stored, the memory 202 causing the one or more processors 201 to realize a data processing method provided by an embodiment of the present disclosure when the one or more programs are executed by the one or more processors 201, and one or more I / O interfaces 203 connected between the processor 201 and the memory 202 and configured to realize information exchange between the processor 201 and the memory 202.

[0109] Here, the processor 201 is a device having data processing capabilities, including but not limited to a CPU. The memory 202 is a device having data storage capabilities, including but not limited to a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH). The I / O interface 203 is connected between the processor 201 and the memory 202, and can realize information exchange between the processor 201 and the memory 202, including but not limited to a data bus.

[0110] In an alternative embodiment, the processor 201, memory 202 and I / O interface 203 are connected to each other and to other components of the wireless unit by a bus 204.

[0111] In a fifth aspect, as shown in FIG. 21 , an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored therein, the computer-readable storage medium realizing at least one of a data transmission method provided by an embodiment of the present disclosure and a data processing method provided by an embodiment of the present disclosure when the program is executed by a processor.

[0112] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific examples.

[0113] Example 1 22, in the first embodiment, the data to be transmitted includes data segment Frag 0, data segment Frag 1, data segment Frag 2, etc., where data segment Frag 0 corresponds to descriptor dcscriptor 0, data segment Frag 2 corresponds to descriptor dcscriptor 2, etc., and each data segment corresponds to one descriptor. The data to be transmitted may be control data, user data, or time information, and the descriptor includes a frame structure parameter, a frequency domain parameter, a time domain parameter, a data address parameter, and a descriptor address parameter.

[0114] In the first embodiment, the descriptors can be stored discretely in the on-chip memory device. As shown in Fig. 23, the storage address of the next descriptor is taken as one of the parameters of the current descriptor to realize the concatenated storage of the descriptors, and the hardware logic obtains the storage location of the next descriptor by analyzing the parameters in the current descriptor, thereby completing the reading and writing of all the descriptors.

[0115] The descriptors may be stored contiguously in an on-chip memory device. As shown in Fig. 24, a pre-designed address space is a dedicated memory space for the descriptors, and the addresses of each parameter of the descriptors are fixed and known, and a general-purpose processor, accelerator, or hardware logic etc. cyclically reads and writes the descriptors in the memory space.

[0116] In Figures 23 and 24, data_start_addr indicates the start address where the current data segment is stored, length indicates the length of the stored data, frame_id indicates the 10 ms frame number of the stored data segment, start_prb indicates the start number of the PRB, num_prb indicates the number of PRBs used, and next_descriptor_start_addr indicates the start address of the next descriptor.

[0117] Example 2 FIG. 25 is a schematic diagram showing communication between an O-DU and an O-RU via a downlink.

[0118] The communication between the O-DU and the O-RU on the downlink may include the following processes.

[0119] Downstream O-DU side: A general-purpose processor or accelerator segments the current data within a certain period of time, and determines the start position of the descriptor in the on-chip memory device and the descriptor parameters corresponding to each data segment, and then writes the descriptor and data segment to the on-chip memory device. The segment can be a symbol, and each symbol is one segment, and a corresponding storage space is assigned to each data segment. Each data segment corresponds to one descriptor, and the relevant information of the data segment is translated into the parameters of the descriptor and written to the on-chip memory device. The storage form of the data segment is defined by the parameters in the descriptor, such as the data storage start address and the size of the buffer space. The storage form of the descriptor may be defined by the parameters inside the descriptor, or may be designed in advance. The segmented data and the descriptor are stored in the on-chip memory device. The parameters in the descriptor define the address of the descriptor itself and the data segment in the on-chip memory device, so that the general-purpose processor or hardware logic can accurately read the data in the on-chip memory device. The hardware logic reads the descriptor in the on-chip memory device at a fixed time based on the start position of the descriptor located by the general-purpose processor and the position of the next descriptor defined by the parameters in the descriptor, and then reads the corresponding data segment at the specified address based on the read descriptor and sends it to the O-RU.

[0120] Downstream O-RU side: The hardware logic on the O-RU side performs mapping to generate a descriptor based on the received control data, and initializes the start position of the descriptor. The hardware logic processes the received data based on the descriptor, and writes the descriptor and the corresponding data segment to the on-chip memory device. The control data sent from the O-DU defines the format and size of the user data, such as the start position of the resource block, the number of resource blocks, and whether each resource block is used. The hardware logic on the O-RU side needs to extract these parameters from the control data and map them to parameters in the descriptor, such as the data segment number, the start position of the data segment storage space, and the size of the data segment storage space. The descriptor and data are segmented and stored in the on-chip memory device.

[0121] Example 3 FIG. 26 is a schematic diagram showing communication between an O-DU and an O-RU via an uplink.

[0122] The communication between the O-DU and the O-RU via the uplink may include the following processes.

[0123] Upstream O-DU side: The upstream O-DU transmits only control information, and the O-RU transmits user data to the O-DU based on the received control information. A general-purpose processor or accelerator segments data within a certain period of time, and configures the start position of the descriptor in the on-chip memory device and the descriptor parameters corresponding to each data segment, and then writes the descriptor and data segment to the on-chip memory device. The segmented data and the descriptor are stored in the on-chip memory device. The parameters in the descriptor define the address of the descriptor itself and the data segment in the on-chip memory device, so that the general-purpose processor or hardware logic can read the data accurately in the on-chip memory device. The hardware logic reads the descriptor in the on-chip memory device at a fixed time based on the start position of the descriptor configured by the general-purpose processor and the position of the next descriptor defined by the parameters in the descriptor. Then, based on the read descriptor, it reads the corresponding data segment at the specified address and sends it to the O-RU.

[0124] Uplink O-RU side: The hardware logic on the O-RU side performs mapping to generate a descriptor based on the received control data, and initializes the start position of the descriptor. The hardware logic processes the received data based on the descriptor, and writes the descriptor and the corresponding data segment to the on-chip memory device. The control data sent from the O-DU defines the format and size of the user data, such as the start position of the resource block, the number of resource blocks, and whether each resource block is used. The hardware logic on the O-RU side needs to extract these parameters from the control data and map them to parameters in the descriptor, such as the data segment number, the start position of the data segment storage space, and the size of the data segment storage space. The descriptor and data are segmented and stored in the on-chip memory device. The hardware logic reads the descriptor in the on-chip memory device at a fixed time based on the start position of the descriptor and the next descriptor position defined by the parameters in the descriptor. Then, based on the read descriptor, the data is read, framed, and sent to the O-DU or lower module.

[0125] Those skilled in the art will appreciate that all or some of the steps of the methods, systems, and functional modules / units in the devices disclosed herein may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware embodiments, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components, for example, one physical component may have multiple functions, or one function or step may be performed by multiple physical components in cooperation. Some or all of the physical modules may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or may be implemented as hardware or as an integrated circuit, such as a dedicated integrated circuit. Such software may be located on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the technical term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk memory, magnetic boxes, magnetic tapes, magnetic disk memory or other magnetic storage devices, or any other medium that stores the desired information and can be accessed by a computer. Additionally, those skilled in the art will appreciate that communication media typically include computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media.

[0126] Although embodiments are disclosed herein and specific terms are employed, they are used and should be interpreted as merely general illustrative, and not for the purpose of limitation. It is obvious to those skilled in the art that in some embodiments, unless otherwise specified, the features, characteristics and / or elements described in combination with a particular embodiment can be used alone or in combination with the features, characteristics and / or elements described in combination with other embodiments. Thus, those skilled in the art can appreciate that changes in various forms and details can be made without departing from the scope of the present disclosure as described by the appended claims.

Claims

1. A data transmission method implemented by hardware logic of a distributed unit or a radio unit of an open radio access network, comprising: reading data to be transmitted from a local on-chip memory device based on the plurality of descriptors, the data corresponding to the plurality of descriptors; transmitting the data to be transmitted based on the plurality of descriptors; the plurality of descriptors are for limiting a storage form of the data to be transmitted in the on-chip memory device and a form in which the data to be transmitted exists in a transmission link when the data to be transmitted is transmitted; the data to be transmitted includes a plurality of data segments, each of the plurality of descriptors corresponds to one of the plurality of data segments, the descriptor includes a data address parameter, and data storage information in the on-chip memory device of the data segment corresponding to the descriptor is arranged in the data address parameter; reading the data to be transmitted from the local on-chip memory device based on the plurality of descriptors, the data corresponding to the plurality of descriptors comprising: reading the data segment corresponding to the descriptor from the on-chip memory device based on the data storage information located in the data address parameter in the descriptor. Data transmission method.

2. The descriptor further includes a frame format parameter, a time domain parameter, and a frequency domain parameter, in which frame format information of the data segment corresponding to the descriptor is arranged in the frame format parameter, time domain information of the data segment corresponding to the descriptor is arranged in the time domain parameter, and frequency domain information of the data segment corresponding to the descriptor is arranged in the frequency domain parameter; The step of transmitting the data to be transmitted based on the plurality of descriptors includes: The method includes a step of framing the data to be transmitted based on the frame format information arranged in the frame format parameter in the descriptor among the plurality of descriptors, the time domain information arranged in the time domain parameter, and the frequency domain information arranged in the frequency domain parameter in the descriptor, and transmitting the data to be transmitted.

2. The data transmission method according to claim 1.

3. prior to the step of reading the data to be transmitted from the on-chip memory device based on the plurality of descriptors, The data transmission method according to claim 1 or 2, further comprising the step of reading the plurality of descriptors from the on-chip memory device.

4. The step of reading the plurality of descriptors from the on-chip memory device comprises: periodically reading the plurality of descriptors from the on-chip memory device.

4. The data transmission method according to claim 3.

5. the descriptor further includes a descriptor address parameter in which descriptor storage information is located, the descriptor storage information being for characterizing storage information in the on-chip memory device of a descriptor subsequent to the descriptor; The step of reading the plurality of descriptors from the on-chip memory device comprises: reading the next descriptor based on the descriptor storage information located in the descriptor address parameter of the descriptor.

4. The data transmission method according to claim 3.

6. the plurality of descriptors are contiguous with respect to storage address in the on-chip memory device; The step of reading the plurality of descriptors from the on-chip memory device comprises: reading the plurality of descriptors from a storage space in the on-chip memory device in which the plurality of descriptors are stored, based on a leading address in the on-chip memory device of the plurality of descriptors; 4. The data transmission method according to claim 3.

7. prior to the step of reading the data to be transmitted from the on-chip memory device based on the plurality of descriptors, locating the plurality of descriptors; storing the arranged plurality of descriptors in the on-chip memory device.

3. A data transmission method according to claim 1 or 2.

8. 1. A data processing method executed by hardware logic in a distributed unit or a radio unit of an open radio access network, comprising: generating, based on the received control data, a plurality of descriptors corresponding to data to be transmitted that corresponds to the control data; writing the data to be transmitted to a local on-chip memory device based on the plurality of descriptors; the plurality of descriptors are for defining a storage form of the data to be transmitted in the on-chip memory device and a form in which the data to be transmitted exists in a transmission link when the data to be transmitted is transmitted; the data to be transmitted includes a plurality of data segments, each of the plurality of descriptors corresponds to one of the plurality of data segments, and the descriptors include data address parameters; Generating the plurality of descriptors based on the received control data includes: populating the data address parameters with data storage information for storing the data segment corresponding to the descriptor in the on-chip memory device based on the control data; The method further includes reading, based on the plurality of descriptors, the data to be transmitted that corresponds to the plurality of descriptors and is stored in the on-chip memory device; The step of reading the data to be transmitted, which corresponds to the plurality of descriptors and is stored in the on-chip memory device, based on the plurality of descriptors includes: reading the data segment corresponding to the descriptor from the on-chip memory device based on the data storage information located in the data address parameter in the descriptor. Data processing methods.

9. the descriptor further comprises frame format parameters, time domain parameters, and frequency domain parameters; Generating the plurality of descriptors based on the received control data includes: generating the descriptor corresponding to the data segment based on the control data; generating the descriptor corresponding to the data segment based on the control data, arranging frame format information of the data segment corresponding to the descriptor in the frame format parameter based on the control data; arranging time domain information of the data segment corresponding to the descriptor in the time domain parameters based on the control data; and arranging, based on the control data, frequency domain information of the data segment corresponding to the descriptor into the frequency domain parameters. The data processing method according to claim 8.

10. The data to be transmitted includes data to be transmitted upstream, Prior to the step of writing the data to be transmitted to the local on-chip memory device based on the plurality of descriptors, the data processing method further comprises: The method further includes a step of segmenting the data to be transmitted upstream based on storage address information arranged in the descriptor, and acquiring the data segment corresponding to the descriptor.

10. The data processing method according to claim 9.

11. the data to be transmitted includes downstream data to be transmitted, Prior to the step of writing the data to be transmitted to the local on-chip memory device based on the plurality of descriptors, the data processing method further comprises: The method further includes a step of processing the data to be transmitted downlink based on the frame format information arranged in the frame format parameter of the descriptors in the plurality of descriptors, the time domain information arranged in the time domain parameter, and the frequency domain information arranged in the frequency domain parameter of the descriptors in the plurality of descriptors, and acquiring a plurality of data segments corresponding to the plurality of descriptors.

10. The data processing method according to claim 9.

12. writing the data to be transmitted to the local on-chip memory device based on the plurality of descriptors, writing the data segment to the on-chip memory device based on the data storage information located in the data address parameters in the descriptor corresponding to the data segment. A data processing method according to any one of claims 8 to 11.

13. the descriptor further includes a descriptor address parameter; Generating the plurality of descriptors based on the received control data includes: identifying storage information of the plurality of descriptors in the on-chip memory device for the plurality of descriptors; and locating in the descriptor address parameter a descriptor storage information in the on-chip memory device of a next descriptor. A data processing method according to any one of claims 8 to 11.

14. A data processing method as described in any one of claims 8 to 11, further comprising a step of transmitting the data to be transmitted based on the plurality of descriptors.

15. prior to the step of reading the data to be transmitted, which corresponds to the plurality of descriptors and is stored in the on-chip memory device, based on the plurality of descriptors; The data processing method of claim 14 , further comprising the step of reading the plurality of descriptors from the on-chip memory device.

16. The step of reading the plurality of descriptors from the on-chip memory device comprises: periodically reading the plurality of descriptors from the on-chip memory device.

16. The data processing method according to claim 15.

17. one or more processors; a memory in which one or more programs are stored, the one or more programs causing the one or more processors to implement the data transmission method according to any one of claims 1 to 7 when the one or more programs are executed by the one or more processors. Distributed units.

18. one or more processors; a memory in which one or more programs are stored, the one or more programs, when executed by the one or more processors, causing the one or more processors to implement the data processing method according to any one of claims 8 to 16. Wireless unit.

19. When a computer program is stored and executed by a processor, A data transmission method according to any one of claims 1 to 7, and a data processing method according to any one of claims 8 to 16. A computer-readable storage medium.

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