Quantum state preparation circuit generation method, quantum state preparation method, and quantum device

Abstract

The present application relates to a quantum state preparation circuit generating method, a quantum state preparation method, and a quantum device. The quantum state preparation circuit generating method includes the steps of: setting an input register in the quantum state preparation circuit based on a circuit preparation parameter of the quantum state preparation circuit and determining the number of auxiliary quantum bits (302); setting a duplicate register and a target register in the quantum state preparation circuit based on the number of auxiliary quantum bits (304); constructing a circuit using the input register, the duplicate register, and the target register based on a quantum bit duplication scheme to obtain a diagonal unitary matrix quantum circuit, the quantum bit duplication scheme being obtained based on a grid restriction condition (306); combining the diagonal unitary matrix quantum circuit and a one-bit quantum gate to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit (308); and generating a quantum state preparation circuit based on at least one uniform control gate circuit (310). The method can be used to reduce decoherence effects.

Description

[Technical field]

[0001] The present application relates to the technical field of quantum computing, and in particular to a quantum state preparation circuit generation method, a quantum state preparation method, and a quantum device.

[0002] This application claims priority to a Chinese patent application filed on May 30, 2022, bearing application number 202210602826X and entitled "Quantum state preparation circuit generation method, quantum state preparation method, and quantum equipment," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] With the development of quantum computing technology, quantum state preparation technology has emerged, and quantum state preparation refers to loading data that meets given conditions into a quantum state to obtain quantum state data.

[0004] In the prior art, when there are no constraints, a quantum state preparation circuit is designed based on the number of input quantum bits, a quantum state preparation circuit is obtained, and quantum state preparation is then performed based on the quantum state preparation circuit.

[0005] However, in the physical realization of conventional quantum devices, there is decoherence, that is, with the increase of time, the coherence of the quantum system gradually disappears and degenerates into a classical system. In contrast to the case where the connectivity of quantum bits in a quantum device is limited by the grid structure, the depth of the quantum state preparation circuit obtained by adopting conventional technology is large, which causes the appearance of the decoherence phenomenon and affects the preparation of the quantum state. Summary of the Invention [Problem to be solved by the invention]

[0006] According to various embodiments provided by the present application, a quantum state preparation circuit generation method, an apparatus, a computer device, a computer-readable storage medium, and a computer program product are provided, and a quantum state preparation method, an apparatus, a computer device, a computer-readable storage medium, a computer program product, and a quantum device are provided. [Means for solving the problem]

[0007] In a first aspect, the present application provides a method for generating a quantum state preparation circuit, the method being executed by a computing device and comprising the steps of: setting an input register in the quantum state preparation circuit based on a circuit preparation parameter of the quantum state preparation circuit; and determining a number of auxiliary qubits; Setting a replica register and a target register in a quantum state preparation circuit based on the number of auxiliary quantum bits; A step of constructing a circuit by an input register, a duplicated register, and a target register based on a qubit duplication scheme to obtain a diagonal unitary matrix quantum circuit, the qubit duplication scheme being obtained based on a grid restriction condition; combining the diagonal unitary matrix quantum circuit and the one-bit quantum gate to obtain a diagonal unitary matrix quantum circuit and a corresponding uniform control gate circuit; and generating a quantum state preparation circuit based on the at least one uniform control gate circuit.

[0008] In a second aspect, the present application further provides a quantum state preparation circuit generation device, the device comprising: A first setting module is used for setting an input register in the quantum state preparation circuit according to a circuit preparation parameter of the quantum state preparation circuit and determining a number of auxiliary quantum bits; A second setting module is used for setting a replica register and a target register in the quantum state preparation circuit according to the number of auxiliary quantum bits; A circuit construction module used to construct a circuit using an input register, a copy register, and a target register based on a quantum bit duplication scheme to obtain a diagonal unitary matrix quantum circuit, the quantum bit duplication scheme being obtained based on a grid restriction condition; a circuit combination module used for combining the diagonal unitary matrix quantum circuit and the 1-bit quantum gate to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit; and a processing module used to generate the quantum state preparation circuit based on the at least one uniform control gate circuit.

[0009] In a third aspect, the present application further provides a computing device, the computing device including a memory and a processor, the memory having computer readable instructions stored therein, the processor performing steps of the quantum state preparation circuit generation method when executing the computer readable instructions.

[0010] In a fourth aspect, the present application further provides a computer-readable storage medium having computer-readable instructions stored thereon that, when executed by a processor, implement the steps of the quantum state preparation circuit generation method.

[0011] In a fifth aspect, the present application further provides a computer program product, the computer program product including computer readable instructions that, when executed by a processor, implement the steps of the quantum state preparation circuit generation method.

[0012] In a sixth aspect, the present application provides a method for preparing a quantum state, the method being performed by a quantum computer, the method comprising: The method includes a step of performing quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, the quantum state preparation circuit being realized by the quantum state preparation circuit generation method.

[0013] In a seventh aspect, the present application provides a quantum state preparation device, the device comprising: A preparation module used for performing quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, the quantum state preparation circuit including a preparation module realized by the quantum state preparation circuit generation method.

[0014] In an eighth aspect, the present application further provides a quantum computer, the quantum computer including a memory and a processor, the memory having computer-readable instructions stored therein, the processor performing steps of the quantum state preparation method when executing the computer-readable instructions.

[0015] In a ninth aspect, the present application further provides a computer-readable storage medium having computer-readable instructions stored thereon that, when executed by a processor, implement the steps of the quantum state preparation method.

[0016] In a tenth aspect, the present application further provides a computer program product, the computer program product comprising computer readable instructions that, when executed by a processor, implement the steps of the quantum state preparation method.

[0017] In an eleventh aspect, the present application further provides a quantum device, the quantum device realizing a quantum state preparation circuit by the quantum state preparation circuit generation method.

[0018] The details of one or more embodiments of the present application are set forth in the drawings and description that follow. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims.

[0019] In order to more clearly describe the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces drawings that need to be used in the description of the embodiments or the prior art. It is obvious that the drawings in the following description are only embodiments of the present application, and those skilled in the art can further obtain other drawings based on the disclosed drawings without creative labor. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a diagram illustrating an application environment of a quantum state preparation circuit generation method in one embodiment. [Diagram 2] FIG. 2 is a schematic diagram of a quantum circuit restricted by grid constraints in one embodiment. [Diagram 3] FIG. 1 is a process diagram of a quantum state preparation circuit generation method in one embodiment. [Figure 4] FIG. 2 is a schematic diagram of an n1×n2-grid restriction for an n1n2-qubit circuit in one embodiment. [Diagram 5] FIG. 2 is a schematic diagram of route restriction in one embodiment. [Figure 6] FIG. 2 is a schematic diagram of a quantum circuit of any n-qubits in one embodiment. [Figure 7] FIG. 2 is a schematic diagram of a replica circuit under column constraints in one embodiment. [Figure 8] FIG. 2 is a schematic diagram of a controlled NOT gate circuit in one embodiment. [Figure 9] FIG. 1 is a schematic diagram showing steps for designing a quantum state preparation circuit in one embodiment. [Figure 10] FIG. 2 is a structural block diagram of a quantum state preparation circuit generation device in one embodiment. [Figure 11] 1 is a diagram showing the internal structure of a computer device according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The following clearly and completely describes the technical solutions in the embodiments of the present application, in conjunction with the drawings in the embodiments of the present application. It is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can obtain without creative labor, all belong to the protection scope of the present application.

[0022] The quantum state preparation circuit generation method provided by the embodiment of the present application can be applied in the application environment shown in FIG. 1. The application environment includes a classical computer 102 and a quantum computer 104. Here, the quantum computer 104 can communicate with the classical computer 102 through a network, and the quantum computer is a kind of physical device that performs high-speed mathematical and logical operations, storage, and processing of quantum information in accordance with the laws of quantum mechanics. A classical computer is a name for a quantum computer, which may also be called an ordinary computer, and is a computational device that has matured in development. The qubits in a quantum computer may be partially connected, and the connectivity of the qubits in a quantum computer is limited, i.e., only some of the qubits can be connected. A quantum computer can only perform quantum operations between qubit pairs that have a connection relationship or on a single qubit, i.e., the qubit that acts as a two-bit quantum gate is graphically limited. To explain by way of example, as shown in FIG. 2, in a quantum computer, a quantum circuit is often limited by grid constraints, and only two qubits connected by a tunable coupler can act as one two-bit quantum gate. The design of a conventional quantum state preparation circuit does not take into account that in an actual quantum computer, the connectivity of qubits is limited by the grid structure, and the depth of the quantum state preparation circuit designed becomes large, which causes the appearance of the decoherence phenomenon and affects the quantum state preparation. Therefore, by utilizing the combination skill with the auxiliary qubit, it is possible to realize the parallelization of the quantum state preparation circuit constrained by the grid limit condition, and obtain a quantum state preparation circuit with an effectively compressed circuit depth, thereby realizing the reduction of the decoherence effect. In conjunction with the application scenario shown in FIG. 1, the quantum state preparation circuit generation method may be executed by the classical computer in FIG. 1.

[0023] In one embodiment, the classical computer is in communication with the quantum computer, and the classical computer sets an input register in the quantum state preparation circuit according to a circuit preparation parameter of the quantum state preparation circuit, and determines the number of auxiliary quantum bits, sets a copy register and a target register in the quantum state preparation circuit according to the number of auxiliary quantum bits, and constructs a circuit using the input register, the copy register and the target register according to a quantum bit duplication scheme to obtain a diagonal unitary matrix quantum circuit. The quantum bit duplication scheme is obtained according to a grid restriction condition, combines the diagonal unitary matrix quantum circuit with a 1-bit quantum gate to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit, generates a quantum state preparation circuit based on the at least one uniform control gate circuit, and sends the quantum program configured by the quantum state preparation circuit to the quantum computer for execution.

[0024] Here, the classical computer 102 may be, but is not limited to, various personal computers, notebook computers, smartphones, tablet computers, ubiquitous network devices, and portable wearable devices, and the ubiquitous network devices may be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. The portable wearable devices may be smart watches, smart bracelets, headset devices, etc. The quantum computer 104 is a kind of physical device that performs high-speed mathematical and logical operations, storage, and processing of quantum information in accordance with the laws of quantum mechanics.

[0025] In one embodiment, as shown in FIG. 3, a quantum state preparation circuit generation method is provided, and the method is taken as an example for application to the classical computer 102 in FIG. 1, and includes the following steps:

[0026] Step 302: Set an input register in the quantum state preparation circuit according to the circuit preparation parameters of the quantum state preparation circuit, and determine the number of auxiliary quantum bits.

[0027] Here, quantum state preparation refers to loading data that satisfies a given condition into a quantum state to obtain quantum state data. Quantum state preparation circuit refers to a circuit used to prepare a quantum state. It is necessary to explain that the quantum state preparation circuit in this embodiment is a kind of quantum computing model, also called a quantum circuit model, which is composed of a series of quantum bit gate sequences, and the calculation is completed by the quantum bit gate. The quantum state preparation circuit in this embodiment can be realized by real quantum components, and each quantum bit gate in the quantum state preparation circuit corresponds to one operation of the real quantum components. In a specific application, the mathematical description of the quantum state preparation problem is as follows. Given classical data (complex vector) [Number 1], and the classical data satisfies ||v||2=1 (the modulus length is 1), a (n+m)-quantum state preparation circuit QSP is designed, which is: [Number 2] is satisfied, Here, n is the number of input quantum bits, [Equation 3] is the given initial state, [Equation 4], and {k>: k=0,1,…,2 n −1} is a set of computational cardinals of the quantum system, and [Number 5] is m ancillary qubits, where m is the number of ancillary qubits.

[0028]

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[0029] The quantum state preparation problem is widely present in various quantum machine learning algorithms, so the efficient realization of the quantum state preparation circuit QSP contributes to improving the efficiency of quantum machine learning algorithms. And the physical realization of conventional quantum devices has decoherence, that is, with the increase in time, the coherence of the quantum system gradually disappears and eventually degenerates into a classical system. Therefore, in order to reduce the effect of decoherence as much as possible, the quantum circuit must be parallelized to reduce its circuit depth.

[0030] Here, a quantum bit is a basic unit for storing data, and a specific function can be realized by performing a corresponding operation on the quantum bit. In this embodiment, the quantum state preparation is realized by mainly performing a corresponding operation on the quantum bit. A quantum gate can change the state of the quantum bit it acts on, thereby realizing a specific quantum operation. According to the number of quantum bits it acts on, a quantum gate can be divided into a 1-bit quantum gate and a 2-bit quantum gate. A 1-bit quantum gate can only act on one specific quantum bit and only change the state of the quantum bit, and a 2-bit quantum gate can act on two quantum bits and change the states of two quantum bits, such as a controlled NOT gate.

[0031] Here, the circuit preparation parameters refer to parameters used in designing the quantum state preparation circuit. For example, the circuit preparation parameters may specifically include the preparation target of the quantum state preparation circuit and the quantum bit parameters of the quantum computer, where the preparation target is the target quantum state that needs to be prepared based on the quantum state preparation circuit, and the quantum bit parameters include the total number of quantum bits and the communication relationship of the quantum bits. The input register refers to the input quantum bit, that is, a set of quantum bits that stores the input initial state, and the input initial state refers to the data to be prepared that is input to the quantum state preparation circuit. For example, the input initial state may specifically be a quantum bit string consisting of any n-qubits, where n is the number of quantum bits to be input. The number of auxiliary quantum bits refers to the quantity of auxiliary quantum bits in the quantum state preparation circuit, and the quantum state preparation circuit includes an input register and an auxiliary quantum bit.

[0032] Specifically, the classical computer can determine the number of input quantum bits based on the circuit preparation parameters of the quantum state preparation circuit, and can set an input register in the quantum state preparation circuit based on the number of input quantum bits and the communication relationship of the quantum bits, and the number of quantum bits in the input register is the same as the number of input quantum bits. After determining the number of input quantum bits, the classical computer can determine the number of auxiliary quantum bits based on the number of input quantum bits and the total number of quantum bits. In one specific application, the classical computer can take the difference between the total number of quantum bits and the number of input quantum bits as the number of auxiliary quantum bits.

[0033] Step 304: Set a replica register and a target register in the quantum state preparation circuit based on the number of auxiliary quantum bits.

[0034] Here, the replica register refers to a set of quantum bits that stores the replicated data, and the target register refers to a set of quantum bits that stores the objective function that needs to be realized in the quantum state preparation process.

[0035] Specifically, the classical computer sets a replica register and a target register in the quantum state preparation circuit according to the number of auxiliary quantum bits, that is, divides the auxiliary quantum bits into a replica register and a target register. In one specific application, when the number of auxiliary quantum bits is m, the number of quantum bits in the replica register is m / 2, and the number of quantum bits in the target register is m / 2. In another specific application, when the number of auxiliary quantum bits is m, the number of quantum bits in the replica register is m / 3, and the number of quantum bits in the target register is m / 3, and the remaining m / 3 quantum bits of the auxiliary quantum bits are divided as auxiliary registers, which are used to assist in quantum state preparation and further compress the circuit depth.

[0036] Step 306: Based on the qubit duplication scheme, a circuit is constructed by the input register, the duplication register, and the target register to obtain a diagonal unitary matrix quantum circuit, where the qubit duplication scheme is obtained based on the grid restriction condition.

[0037] Here, the qubit duplication scheme refers to a scheme for duplication of qubits designed based on the grid restriction condition. Under the grid restriction condition, the controlled NOT gate can only act on two connected qubits, so that the duplication using the conventional duplication scheme will cause the depth of the duplication circuit used to realize the duplication to be large, and therefore the duplication circuit needs to be designed based on the grid restriction condition. For example, the qubit duplication scheme may specifically first perform column duplication on the qubits, and then perform row duplication based on the column duplication result. The conventional duplication scheme first performs one duplication to obtain a first duplication result, then performs two duplications based on the first duplication result to obtain a second duplication result, and then performs four duplications based on the second duplication result to obtain a third duplication result, thereby realizing the duplication of qubits by such an iterative duplication scheme.

[0038] Here, the grid restriction condition refers to the fact that in quantum devices, quantum circuits are often restricted by grid constraints. To illustrate, FIG. 4 shows the n1×n2-grid restriction of an n1n2-qubit circuit, where n1 refers to the number of qubits in a single column in the grid, n2 is the number of qubits in a single row in the grid, and each vertex [6] represents n1×n2 qubits. If two qubits are connected by one edge in the grid, a controlled NOT gate can act on these two qubits. When n1 or n2 is 1, the grid restriction degenerates to a path restriction (shown in FIG. 5). In this application, we assume n1≧n2 without loss of generality. A diagonal unitary matrix quantum circuit refers to a quantum circuit that can be expressed by a diagonal unitary matrix. To explain with an example, the definition of an n-qubit diagonal unitary matrix is ​​[Mathematical formula 7], where diag refers to a diagonal matrix, and the matrix elements such as [Mathematical formula 8] can be determined by decomposing the quantum state preparation circuit based on the preparation target.

[0039]

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[0040] Specifically, a classical computer can construct a circuit using an input register, a duplicate register, and a target register based on the qubit duplication scheme to obtain a diagonal unitary matrix quantum circuit. In a specific application, the function of the diagonal unitary matrix quantum circuit is to realize the following transformation on each vector |x> in a set of computational bases of the quantum system: |x>→e iθ(x) |x>,∀x∈{0,1} n That is, for each vector |x> in a set of computational bases, there is a corresponding vector with topology e iθ(x)|x>, where e iθ(x) are the matrix elements of the diagonal unitary matrix in the diagonal unitary matrix quantum circuit.

[0041] Based on this, we set the parameter {α s :s∈{0,1} n -{0 n}} is Σ s <s,x> α s =θ(x),∀x∈{0,1} n -{0 n}, where s and x are qubit strings, n is the number of qubits input, and α s is the phase,<s,x> represents the dot product of the quantum bit string s and the quantum bit string x, so that 2 n All phases α corresponding to the quantum bit string s s By generating the diagonal unitary matrix quantum circuit, n Each of the quantum bit strings s has a corresponding phase α s where the inner product has the sign<x,y> It can be expressed as [9], where x=(x1,…,x n ) T ,y=(y1,…,y n ) T ∈{0,1} n where addition and multiplication are operations on binary fields.

[0042]

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[0043] In one specific application, a classical computer is based on a qubit duplication scheme, and uses an input register, a duplication register, and a target register to perform two n All phases α corresponding to the quantum bit string s sA circuit can be constructed with the goal of generating a diagonal unitary matrix quantum circuit. Furthermore, a classical computer can generate a qubit by using the input register, the duplicate register, and the target register. n Each quantum bit string s among the quantum bit strings s is gradually generated, and a corresponding phase α s The phase α s are all Σ s <s,x> α s =θ(x), where x can be any quantum bit string other than 0, there is one corresponding equation for each quantum bit string x, and by solving all the equations simultaneously, the phase α s can be obtained.

[0044] To illustrate, in the case of two qubits, qubit string s can be 01, 10, or 11, and qubit string x can also be 01, 10, or 11. For qubit string x being 01, the corresponding equation is <01,01>α s(01) +<10,01>α s(10) +<11,01>α s(11) =θ(01), where <01,01>, <10,01>, and <11,01> are the inner products of qubit string s and qubit string x when they are 01, respectively, and α s(01) , α s(10) , and α s(11) are the phases α s Represents.

[0045] Step 308: Combine the diagonal unitary matrix quantum circuit and the 1-bit quantum gate to obtain a diagonal unitary matrix quantum circuit and a corresponding uniform control gate circuit.

[0046] Here, a 1-bit quantum gate acts only on one specific quantum bit and can change only the state of that quantum bit. A uniformly controlled gate circuit refers to a quantum circuit that can be represented by a uniformly controlled gate. To explain this by way of example, an n-qubit uniformly controlled gate (UCG) V n teeth, [Number 10] It is defined as Here, for any k∈[2 n-1 ], U k ∈C 2×2 is a unitary matrix. Any n-qubit quantum circuit can be decomposed into a combination of n uniform control gates of different sizes, i.e., [Equation 11], where I n-k represents the identity operator of nk qubits. Based on the principle of circuit decomposition, when one global phase is ignored, the uniform control gate can be decomposed into a diagonal unitary matrix and a 1-bit quantum gate, that is, the uniform control gate circuit includes a diagonal unitary matrix quantum circuit and a 1-bit quantum gate. To explain by way of example, the uniform control gate can be decomposed into a combination of three diagonal unitary matrices and four 1-bit quantum gates.

[0047]

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[0048] Specifically, any n-qubit quantum circuit can be decomposed into a combination of n uniform control gates with different scales, and the uniform control gate can be decomposed into a combination of a diagonal unitary matrix and a 1-bit quantum gate.Therefore, when designing a quantum state preparation circuit, in a classical computer, it is necessary to first decompose the quantum state preparation circuit according to the circuit preparation parameters of the quantum state preparation circuit, decompose the quantum state preparation circuit into a combination of uniform control gates, and then decompose the uniform control gate, and decompose the uniform control gate into a combination of a diagonal unitary matrix and a 1-bit quantum gate, so that it is necessary to first construct a circuit to obtain a diagonal unitary matrix quantum circuit, and then obtain the uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit by combining the diagonal unitary matrix quantum circuit and the 1-bit quantum gate.

[0049] Step 310: Generate a quantum state preparation circuit based on the at least one uniform control gate circuit.

[0050] Specifically, any n-qubit quantum circuit can be decomposed into a combination of n uniform control gates of different scales, so that the classical computer can decompose the quantum state preparation circuit, decompose the quantum state preparation circuit into a combination of uniform control gates, and then generate the quantum state preparation circuit based on at least one uniform control gate circuit after obtaining the uniform control gate circuit. To explain by example, assuming that the initial state of the circuit is [Mathematical formula 12], the schematic diagram of any n-qubit quantum circuit may be decomposed into a combination of n uniform control gates of different scales, as shown in FIG. 6.

[0051]

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[0052] The above quantum state preparation circuit generation method can set an input register in the quantum state preparation circuit according to the circuit preparation parameters, and determine the number of auxiliary quantum bits, thereby realizing the setting of the copy register and the target register according to the number of auxiliary quantum bits. Based on the quantum bit duplication method, the circuit is constructed by the input register, the copy register, and the target register, and when the constraint of the grid limiting condition is taken into consideration, a diagonal unitary matrix quantum circuit can be constructed by using combination skills. Furthermore, a uniform control gate circuit can be obtained by combining the diagonal unitary matrix quantum circuit and the 1-bit quantum gate, and a quantum state preparation circuit can be generated based on the uniform control gate circuit. In the whole process, the auxiliary quantum bits and combination skills can be used to realize the parallelization of the quantum state preparation circuit under the constraint of the grid limiting condition, and a quantum state preparation circuit with an effectively compressed circuit depth can be obtained, thereby realizing the reduction of the decoherence effect.

[0053] In one embodiment, the qubit duplication scheme includes performing column duplication on the qubits under a grid-constrained condition, obtaining a column duplication result, and performing row duplication based on the column duplication result.

[0054] Here, column duplication refers to duplication of quantum bits in the column direction, and row duplication refers to duplication of quantum bits in the row direction.

[0055] Specifically, the qubit duplication scheme includes performing column duplication on qubits under grid restriction conditions, obtaining column duplication results, and performing parallel row duplication based on the column duplication results. In one specific application, performing column duplication refers to single-column duplication, which duplicates qubits in the first column. Parallel row duplication refers to duplicating qubits in the first column row by row through the action of a controlled NOT gate. Based on the grid restriction conditions and the qubit duplication scheme, the circuit depth for realizing the qubit duplication circuit can be determined. To explain by taking an example, under the n1×n2 grid restriction, for any x=x1x2…x n ∈{0,1} nIn contrast, the duplication of the transformation [Eq. 13] has depth O(n 2 This can be realized by a CNOT (controlled-NOT) circuit (n1 + n2).

[0056]

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[0057] In one specific application, the quantum bit duplication scheme under the n1×n2 grid restriction may include the following two steps.

[0058] Step 1: Replication under the first column restriction (n1-path restriction n) is to realize the following transformation [Equation 14].

[0059]

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[0060] That is, |x> is replicated and replicated on [Equation 15] quantum bits. The replication of the above transformation can be realized by a replication circuit under column restriction shown in FIG. 7. In the replication circuit under column restriction, the action of a controlled NOT gate is used to replicate x1...x n Each of these is replicated (n1-n) times, with each controlled NOT gate implementing one replication. Here, the first controlled NOT gate operates on positions (n,1) to (2n,1) and x n Furthermore, as can be seen from the fact that the controlled NOT gates are realized by circuits under the path restriction, each controlled NOT gate in the replicated circuit under the column restriction can be realized by a controlled NOT gate circuit with a depth of O(n) under the (n+1)-path restriction. Therefore, under the n1-path restriction n, the circuit depth of the above transformation is [Equation 16].

[0061]

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[0062] Here, the circuit realization under the path restriction of the controlled NOT gate refers to that under the path restriction, [Equation 17] can be realized by a CNOT circuit with a depth and size of O(|ij|) (as shown in FIG. 8, where the small black dots represent the control bits and the large circles represent the target bits), where i is the control bit of the controlled NOT gate and j is the target bit of the controlled NOT gate. To explain by way of example, in the replica circuit under the column restriction shown in FIG. 7, the first controlled NOT gate operates on positions (n,1) to (2n,1), where (n,1) is the control bit and (2n,1) is the target bit.

[0063]

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[0064] Step 2: Duplicate each qubit (i,1) n2-1 times under the constraint of n2-paths (i,1)-(i,2)-...-(i,n2) (row i of the grid). For any i∈[n1], this step can be realized by a quantum circuit of depth O(n2) [Equation 18]. The n1 path constraints are disjoint and can therefore be realized in parallel.

[0065]

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[0066] In this embodiment, a quantum bit duplication method is designed in which column duplication is first performed based on the grid restriction conditions, and then row duplication is performed based on the column duplication results. This reduces the circuit depth of the quantum bit duplication circuit, effectively compresses the circuit depth of the quantum state preparation circuit, and reduces the decoherence effect.

[0067] In one embodiment, the input register includes a prefix partial qubit and a suffix partial qubit, and the step of constructing a circuit using the input register, the duplicated register, and the target register based on the qubit duplication scheme to obtain a diagonal unitary matrix quantum circuit includes: According to a qubit duplication scheme, duplicate the suffix partial qubit in the input register, and duplicate the suffix partial qubit into the duplicate register to obtain a suffix duplication stage circuit; performing a Gray initialization process using the suffix partial qubits in the replica register and the target register to obtain a Gray initialization stage circuit; According to a qubit duplication scheme, duplicate the prefix partial qubit in the input register, and duplicate the prefix partial qubit into the duplicate register to obtain a prefix duplication stage circuit; performing a Gray path process using the prefix partial qubit in the replica register and the target register to obtain a Gray path stage circuit; performing an inversion process based on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, and the Gray path stage circuit to obtain an inversion process stage circuit; and obtaining a diagonal unitary matrix quantum circuit based on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, the Gray path stage circuit, and the inversion processing stage circuit.

[0068] Here, the input register includes a prefix partial qubit and a suffix partial qubit. For example, when the input register is n-qubit, the prefix partial qubit refers to the first np qubits in the input register, and the suffix partial qubit refers to the last p qubits in the input register, where np can be set based on the actual application scenario. In one specific application, the number of qubits in the prefix partial qubit and the suffix partial qubit may be the same or close. For example, when the input register is 4-qubit, the prefix partial qubit may refer to the first two qubits in the input register, and the suffix partial qubit refers to the last two qubits in the input register.

[0069] Here, the Gray initialization process is mainly used to realize an objective function matching the Gray initialization stage on each quantum bit of the target register and a phase rotation. The objective function matching the Gray initialization stage realized on each quantum bit is a linear function configured based on the suffix partial quantum bit. To explain by way of example, the objective function may specifically be a function determined based on a pre-constructed quantum bit string set. The pre-constructed quantum bit string set is constructed based on the conditions that the quantum bit string set needs to satisfy and a Gray code cycle.

[0070] In a concrete application, a preconstructed set of qubit strings {0,1} corresponding to n qubits is n is a two-dimensional array of n-bit strings, {s(j,k):j∈[2 n-p ],k∈[2 p ]}, where p=log2(m / 3), m being the number of ancillary qubits. In this case, the objective function for matching the Gray initialization stage is specifically f 1,k(x)=<s(1,k),x> where s(1,k) is the bit string in the first row of the two-dimensional array and x is the input register. Phase rotation is used to change the phase of the objective function being realized, and the phase changed on each qubit may be determined based on the objective function matching to the qubit.

[0071] Here, the Gray code cycle is {0,1} n A Gray code cycle is a sequence of all n-bit strings in the sequence, where two adjacent bit strings in the sequence differ in exactly one bit, and the first bit string and the last bit string in the sequence also differ in exactly one bit. The Gray code cycle is structured as follows: x 1 =0 n Define i=1,2,…,2 n For -1, x i by flipping the t-th bit of x i+1 where t is the time it takes for x to reach a 1-Gray code cycle. i and x i+1 represents the number of different bits, and t is 2 t-1 |i and satisfies

[19] . For any k ∈ [n], the construction method of the k-Gray code cycle is y 1 =0 n Define i=1,2,…,2 n -1, if t+k-1≦n, then y i By inverting the t+k-1-th bit of y i+1 If t+k-1>n, then y i by inverting the t+k-1-nth bit of y i+1 where t is the time it takes for x to reach a 1-Gray code cycle. i and x i+1 represents the number of different bits. To further illustrate, a 1-Gray code cycle for a 2-bit string may be 00, 01, 11, 10.

[0072]

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[0073] In one specific application, the conditions that the qubit string set must satisfy may include some of the following: 1. The first row of the array {s(1,k):k∈[2 p ]}, the leading (np) bits of the bit string are all 0, and each column of the array {s(j,k):j∈[2 n-p ]} have the same last p bits. 2.∀k∈[2 p ], ∀j∈[2 n-p -1], and s(j,k) and s(j+1,k) differ in exactly one bit. 3. [Number 20], and the prefix partial bits of s(1+(l-1)(np),k), s(2+(l-1)(np),k), ..., s(l(np),k) are 1-Gray code, 2-Gray code, ..., np Gray code, respectively.

[0074]

number

[0075] Here, the gray path processing is mainly used to realize, in each processing step, an objective function transformation and a phase rotation on each quantum bit of the target register that matches the current processing step. For example, in the first processing step of the gray path processing step, the objective function realized by the gray initialization processing is mainly transformed. Also, for example, in the second processing step of the gray path processing step, the transformed objective function obtained in the first processing step is mainly transformed. The objective function transformation here mainly refers to realizing a new objective function. For example, the objective function transformation may specifically be realizing a linear function configured based on the prefix partial quantum bit. In a specific application, for a two-dimensional array obtained by dividing a pre-constructed quantum bit string set, the objective function transformation in each processing step is to respectively realize the inner product of the bit strings of different rows and the input register. For example, the objective function transformation realized in the first processing step is f 2,k (x)=<s(2,k),x> where s(2,k) is the bit string in the second row of the two-dimensional array, and x is the input register.

[0076] Specifically, the classical computer divides the input register, divides the input register into a prefix partial qubit and a suffix partial qubit, and based on the qubit duplication method, duplicates the suffix partial qubit in the input register, and duplicates the suffix partial qubit to the duplicate register based on the suffix duplication stage condition, thereby obtaining a suffix duplication stage circuit. Furthermore, by performing Gray initialization processing using the suffix partial qubit in the duplicate register and the target register, an objective function matching the Gray initialization stage and a phase rotation on each qubit of the target register can be realized, and a Gray initialization stage circuit can be obtained. Furthermore, based on the qubit duplication method, the prefix partial qubit in the input register can be duplicated, and based on the prefix duplication stage condition, the prefix duplication stage circuit can be obtained. Furthermore, by performing Gray path processing using the prefix partial qubit in the duplicate register and the target register, an objective function transformation matching the current processing stage and a phase rotation on each qubit of the target register can be realized at each processing stage of the Gray path processing, thereby obtaining a Gray path stage circuit.

[0077] Here, the suffix duplication stage condition refers to the number of suffix partial qubits that need to be duplicated in the suffix duplication stage, and can be set based on the actual application scenario. For example, the number of suffix partial qubits that need to be duplicated can be np, where n is the number of input qubits, p=log2(m / 3), and m is the number of auxiliary qubits. The prefix duplication stage condition refers to the number of prefix partial qubits that need to be duplicated in the prefix duplication stage, and can be set based on the actual application scenario. For example, the number of prefix partial qubits that need to be duplicated can be np, where n is the number of input qubits, p=log2(m / 3), and m is the number of auxiliary qubits.

[0078] Specifically, the function of the diagonal unitary matrix quantum circuit is to output one corresponding phase-attached vector for each vector of a set of calculation cardinals. Therefore, after obtaining the Gray path stage circuit, the classical computer performs inversion processing based on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, and the Gray path stage circuit to restore the duplication register and the target register, and obtains an inversion processing stage circuit, and further obtains a diagonal unitary matrix quantum circuit based on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, the Gray path stage circuit, and the inversion processing stage circuit.

[0079] In a specific application, the step of performing inversion processing based on the suffix duplication stage circuit, the gray initialization stage circuit, the prefix duplication stage circuit, and the gray path stage circuit includes the steps of respectively performing inversion processing on the suffix duplication stage circuit, the gray initialization stage circuit, the prefix duplication stage circuit, and the gray path stage circuit to obtain corresponding inversion circuits of each stage, and combining the corresponding inversion circuits of each stage to obtain an inversion processing stage circuit.

[0080] For example, the inversion processing stage circuit may be expressed as [Equation 21], where [Equation 22] represents the corresponding inversion circuit of the gray path stage circuit, [Equation 23] represents the corresponding inversion circuit of the prefix duplication stage circuit, [Equation 24] represents the corresponding inversion circuit of the gray initialization stage circuit, and [Equation 25] represents the corresponding inversion circuit of the suffix duplication stage circuit. Here, [Equation 26] indicates that the corresponding inversion circuit of the gray path stage circuit can be obtained by inverting each processing stage of the gray path processing.

[0081]

number

number

number

number

number

number

[0082] Also, by way of example, the inversion processing stage circuit can be expressed as [Number 27], where [Number 28] represents the corresponding inversion circuit of the gray path stage circuit, [Number 29] represents the corresponding inversion circuit of the prefix duplication stage circuit, [Number 30] represents the corresponding inversion circuit of the gray initialization stage circuit, and [Number 31] represents the corresponding inversion circuit of the suffix duplication stage circuit. Here, [Number 32] refers to the corresponding inversion circuit of the gray path stage circuit can be obtained by re-transforming the objective function obtained in the last processing stage of the gray path processing. In a specific application, for a two-dimensional array obtained by dividing a set of pre-constructed quantum bit strings, the objective function transformation in each processing stage is to respectively realize the inner product between different rows of bit strings and input registers. In this case, the objective function transformation in the last processing step is to realize the dot product of the bit string in the last row of the array and the input register, while re-transforming the objective function obtained in the last processing step is to realize the dot product of the bit string in the first row of the array and the input register.

[0083]

number

number

number

number

number

number

[0084] In this embodiment, based on the quantum bit duplication method, a suffix duplication process, a Gray initialization process, a prefix duplication process, a Gray path process, and an inversion process are performed, so that a diagonal unitary matrix quantum circuit can be constructed based on combination skills by utilizing the properties of the Gray code cycle, the duplication register, and the target register, thereby realizing the compression of the circuit depth of the diagonal unitary matrix quantum circuit under the grid restriction condition.

[0085] In one embodiment, the step of duplicating the suffix partial qubits in the input register based on the qubit duplication scheme and duplicating the suffix partial qubits into the duplication register to obtain a suffix duplication stage circuit includes: performing column duplication for the suffix partial qubits in the input register based on a qubit duplication scheme, and duplicating them onto different qubits in the duplication register to obtain a first controlled NOT gate circuit; Repeatedly duplicating the suffix partial qubits replicated on different qubits in the replica register in a row direction until the number of suffix partial qubits in the replica register satisfies a suffix replication phase condition to obtain a second controlled NOT gate circuit; and obtaining a suffix duplication stage circuit based on the first controlled NOT gate circuit and the second controlled NOT gate circuit.

[0086] Specifically, the suffix duplication stage is used to duplicate the suffix partial qubits in the input register to the duplicate register under grid restriction conditions, in which the classical computer performs column duplication on the suffix partial qubits in the input register once based on the qubit duplication method, duplicates the suffix partial qubits onto different qubits in a single column in the duplicate register respectively, to obtain a first controlled NOT gate circuit, and then performs repeated row duplication on the suffix partial qubits duplicated onto the different qubits in a single column in the duplicate register until the number of suffix partial qubits in the duplicate register satisfies the suffix duplication stage condition, to obtain a second controlled NOT gate circuit, and combines the first controlled NOT gate circuit and the second controlled NOT gate circuit to obtain a suffix duplication stage circuit.

[0087] In one specific application, when repeatedly replicating suffix partial qubits replicated on different qubits in a single column in the replica register in the row direction, the classical computer determines the number of rows that need to be replicated in the row direction based on the number of suffix partial qubits that need to be replicated in the suffix replication stage condition, and the number of rows that need to be replicated is the number of suffix partial qubits that need to be replicated in the suffix replication stage condition minus 1.

[0088] In this embodiment, based on the quantum bit duplication method, the suffix partial quantum bits are first subjected to column duplication, and then repeatedly duplicated in the row direction, thereby reducing the circuit depth of the suffix duplication stage circuit under grid restriction conditions, effectively compressing the circuit depth of the quantum state preparation circuit and realizing a reduction in the decoherence effect.

[0089] In one embodiment, the step of performing a Gray initialization process using the suffix partial qubits in the replica register and the target register to obtain a Gray initialization stage circuit includes: implementing a matching objective function on each qubit of the target register with a suffix partial qubit in the replica register to obtain a third controlled NOT gate circuit; determining a first phase to match each quantum bit of the target register based on an objective function to match each quantum bit; implementing a matching first phase rotation on each quantum bit of the target register to obtain a first phase rotation circuit; and obtaining a Gray initialization stage circuit based on the third controlled NOT gate circuit and the first phase rotation circuit.

[0090] Here, the matching objective function refers to a linear function constructed based on the suffix partial qubits, that is, when performing the Gray initialization process, it is first necessary to convert the state of the qubit in the target register to [Mathematical Formula 33].

[0091]

number

[0092] where x n-p+1 ,x n-p+2 ,…,x n is the suffix partial qubit, and the process converts the kth qubit in the target register into |f 1,k (x)>, where f 1,k (x)=<s(1,k),x> where s(1,k) is a two-dimensional array {s(j,k):j∈[2 n-p ],k∈[2 p ]}, x is the input register, where p=log2(m / 3) and m is the number of ancillary qubits.

[0093] Here, the first matching phase refers to the phase that corresponds to the bit string in the objective function, and the classical computern All phases α corresponding to the quantum bit string s s Therefore, for each bit string in the objective function, there is a corresponding phase α s There exists a phase α s are all Σ s <s,x> α s =θ(x), where x can be any quantum bit string other than 0, there is one corresponding equation for each quantum bit string x, and by solving all the equations simultaneously, the phase α s In one specific application, the objective function is f 1,k (x)=<s(1,k),x> In this case, the bit string in the objective function refers to s(1,k), where k∈[2 p ].

[0094] Specifically, the classical computer determines a matching objective function that needs to be realized on each quantum bit of the target register, then realizes the matching objective function on each quantum bit of the target register by a suffix partial quantum bit in the replica register to obtain a third controlled NOT gate circuit, then determines a first phase that matches each quantum bit of the target register based on a phase corresponding to the bit string in the objective function matching each quantum bit, respectively, realizes a phase rotation of the first phase that matches on each quantum bit of the target register, to obtain a first phase rotation circuit, and combines the third controlled NOT gate circuit and the first phase rotation circuit to obtain a Gray initialization stage circuit.

[0095] In one specific application, the classical computer determines the matching objective function that needs to be realized on each quantum bit of the target register, and then determines the target quantum bit that acts on each quantum bit of the target register respectively. The target quantum bit may be at least one quantum bit in the suffix partial quantum bit, or may be empty, and further, based on the action relationship between the target quantum bit and each quantum bit of the target register, the suffix partial quantum bit that is duplicated from the duplicate register can be selected to act on each quantum bit of the target register, thereby realizing the matching objective function on each quantum bit of the target register. It is necessary to explain that if the target quantum bit that acts on the quantum bit of the target register is empty, it is not necessary to select the suffix partial quantum bit that is duplicated from the duplicate register to act on the quantum bit.

[0096] To illustrate, let us denote by f the matching objective function that needs to be realized on one qubit in the target register. 1,k (x)=<s(1,k),x> =<0000,x>=<0000,x1x2x3x4>, where s(1,k)=0000, x=x1x2x3x4, and as a classical computer can see based on the dot product result (0*x1+0*x2+0*x3+0*x4=0), the target qubit to operate on that qubit is empty, thereby eliminating the need to select a qubit from the replica register to operate on that qubit in the target register.

[0097] To illustrate this further, let us denote by f the matching objective function that needs to be realized on one qubit in the target register. 1,k(x)=<s(1,k),x> Assume that s(1,k)=<0010,x>=<0010,x1x2x3x4>, where s(1,k)=0010, x=x1x2x3x4, and as a classical computer can understand based on the inner product result (0*x1+0*x2+1*x3+0*x4=x3), the target qubit acting on the qubit is x3, and one x3 can be further selected from the replica register to act on the qubit in the target register. Here, since x1x2x3x4 is a 4-qubit, the suffix partial qubit may be x3x4, and if the number of suffix partial qubits that need to be replicated as a suffix-stage replication condition is 2, then it may be x3x4x3x4 in the replica register.

[0098] In one specific application, achieving a matching first phase rotation on each qubit of the target register can be achieved by a rotation gate, i.e., by applying a rotation gate

[34] to the kth qubit of the target register. That is, if<s(1,k),x> If = 1, then the phase of the kth qubit in the target register is α s(1,k) otherwise the phase remains unchanged, where α s(1,k) refers to the phase corresponding to the bit string s(1,k).

[0099]

number

[0100] In this embodiment, when the suffix partial qubits in the replica register are used to realize the objective function matching on each qubit of the target register, the suffix partial qubits in the replica register can act on different qubits of the target register. Therefore, the circuits at the time of action can be realized in parallel, thereby obtaining a third controlled NOT gate circuit with a reduced circuit depth, and when the phase rotation of the first phase matching on each qubit of the target register is realized, all the phase rotations do not act on the same qubit. Therefore, all the phase rotations can be arranged in the same layer of the circuit, and the reduced circuit depth can be realized.

[0101] In one embodiment, the step of determining a first phase to match each quantum bit of the target register based on an objective function to match each quantum bit includes: determining a qubit string corresponding to each qubit in the target register based on an objective function matching each qubit; determining a phase corresponding to the quantum bit string; determining a phase corresponding to the quantum bit string as a first phase that matches a quantum bit corresponding to the quantum bit string.

[0102] Here, a quantum bit string refers to a bit string that performs an inner product with an input register in an objective function. For example, if the objective function is f 1,k (x)=<s(1,k),x> Then, the quantum bit string refers to s(1, k) that performs an inner product with the input register x. s(1, k) is a quantum bit string that is a two-dimensional array {s(j, k): j ∈ [2 n-p ],k∈[2 p ]}, and the two-dimensional array is obtained by dividing a pre-constructed set of quantum bit strings.

[0103] Specifically, since the objective function matching each quantum bit is to perform an inner product between the bit string and the input register, the classical computer can determine the quantum bit string corresponding to each quantum bit in the target register based on the objective function matching each quantum bit, and thereby calculate the phase α s A phase corresponding to the quantum bit string can be determined based on the first phase, and the phase corresponding to the quantum bit string can be a first phase that matches a quantum bit corresponding to the quantum bit string.

[0104] In this embodiment, a quantum bit and a corresponding quantum bit string can be determined based on the objective function, and a first phase matching the quantum bit can be determined based on the quantum bit string, and a corresponding phase rotation can be realized based on the first phase.

[0105] In one embodiment, the step of replicating the prefix partial qubit in the input register based on the qubit duplication scheme and replicating the prefix partial qubit to the replica register to obtain a prefix duplication stage circuit includes: performing a restoration process on the qubits that have undergone the suffix processing stage in the replica register; performing column duplication on the prefix partial qubits in the input register according to a qubit duplication scheme, and duplicating them onto different qubits in the duplication register to obtain a fourth controlled NOT gate circuit; Repeatedly duplicating the duplicated prefix partial qubits on different qubits in the duplicate register in a row direction until the number of prefix partial qubits in the duplicate register satisfies a prefix duplication stage condition to obtain a fifth controlled NOT gate circuit; and obtaining a prefix duplication stage circuit based on the fourth controlled NOT gate circuit and the fifth controlled NOT gate circuit.

[0106] Here, the restoration process refers to restoring the quantum state obtained in the suffix duplication step to the state before the suffix duplication step.

[0107] Specifically, the prefix duplication step is used to duplicate the prefix partial qubits in the input register to the duplicate register under the grid restriction condition, and since the qubits in the duplicate register are suffix processing steps, the classical computer must first perform a restoration process on the qubits in the duplicate register that have undergone the suffix processing step, and restore the duplicate register to a state before the suffix duplication step. Furthermore, based on the qubit duplication method, a column duplication is performed once on the prefix partial qubits in the input register, and the prefix partial qubits are respectively duplicated on different qubits in a single column in the duplicate register to obtain a fourth controlled NOT gate, and further, until the number of prefix partial qubits in the duplicate register satisfies the prefix duplication step condition, the prefix partial qubits duplicated on the different qubits in a single column in the duplicate register are repeatedly duplicated in the row direction to obtain a fifth controlled NOT gate circuit, and the fourth controlled NOT gate circuit and the fifth controlled NOT gate circuit are combined to obtain a prefix duplication step circuit.

[0108] In one specific application, when performing repeated row-wise duplication of prefix partial qubits duplicated onto different qubits in a single column in the duplication register, the classical computer determines the number of rows that need to be duplicated in the row direction based on the number of prefix partial qubits that need to be duplicated onto the duplication register under the prefix duplication stage condition, and the number of rows that need to be duplicated is the number of prefix partial qubits that need to be duplicated onto the duplication register under the prefix duplication stage condition minus one.

[0109] In this embodiment, based on the quantum bit duplication method, the prefix partial quantum bits are first subjected to column duplication and then repeatedly duplicated in the row direction, thereby reducing the circuit depth of the prefix duplication stage circuit under grid restriction conditions, effectively compressing the circuit depth of the quantum state preparation circuit and realizing a reduction in the decoherence effect.

[0110] In one embodiment, the step of performing a Gray path process using the prefix partial qubits in the replica register and the target register to obtain a Gray path stage circuit includes: In each processing stage of the gray path processing, realizing an objective function transformation matching the current processing stage on each quantum bit of the target register by the prefix partial quantum bit in the replica register to obtain a processing circuit of the current processing stage; and obtaining a gray path stage circuit based on the processing circuit of each processing stage in the gray path processing.

[0111] Here, the gray path processing steps are 2 n-p The objective function transformation for matching the current processing step refers to transforming the objective function obtained in the previous processing step to realize a new objective function. For example, the objective function transformation may specifically be to realize a linear function constructed based on the prefix partial qubits. For the first processing step, the previous processing step refers to the Gray initialization step, that is, in the first processing step of the Gray path processing step, the objective function realized mainly in the Gray initialization process is transformed. In a specific application, for a two-dimensional array obtained by dividing a pre-constructed set of quantum bit strings, the objective function transformation in each processing step is to respectively realize the inner product of different rows of bit strings and input registers. For example, the objective function transformation realized in the first processing step is f 2,k(x)=<s(2,k),x> where s(2,k) is the bit string in the second row of the two-dimensional array, and x is the input register.

[0112] Specifically, at each processing stage of the gray path processing, the classical computer transforms the objective function obtained in the previous processing stage by the prefix partial quantum bit in the replica register, realizes an objective function transformation matching the current processing stage on each quantum bit of the target register, obtains a processing circuit for the current processing stage, and combines the processing circuits of each processing stage in the gray path processing to obtain a gray path stage circuit.

[0113] In this embodiment, the prefix partial quantum bit in the replica register can be used to realize an objective function transformation matching the current processing stage on each quantum bit of the target register, thereby obtaining a processing circuit for the current processing stage, and further obtaining a gray path stage circuit based on the processing circuits of each processing stage in the gray path processing.

[0114] In one embodiment, the step of implementing an objective function transformation matching the current processing stage on each qubit of the target register by the prefix partial qubit in the replica register to obtain a processing circuit of the current processing stage includes: determining a qubit control bit to operate on each qubit of the target register based on an objective function transformation matching the current processing step, and a second phase matching each qubit, respectively; According to the qubit control bit, an objective function transformation control is realized by a prefix partial qubit in the replica register to obtain an objective function transformation circuit; implementing a matching second phase rotation on each quantum bit of the target register to obtain a second phase rotation circuit; and obtaining a processing circuit of the current processing stage based on the objective function transformation circuit and the second phase rotation circuit.

[0115] Here, the matching objective function transformation refers to a transformation to the objective function of the previous processing stage that is realized based on the prefix partial qubit. The qubit control bit refers to a qubit that controls the modification of the qubit. For example, the qubit control bit may specifically refer to a qubit in an input register that controls the modification of the qubit. Controlling the modification of the qubit can be realized by a controlled NOT gate, where the qubit control bit is the control bit in the controlled NOT gate, and the qubit that needs to be modified is the target bit.

[0116] Here, the matching second phase refers to the phase that corresponds to the bit string in the transformed objective function of the current processing stage. n All phases α corresponding to the quantum bit string s s Therefore, for each bit string in the transformed objective function, the corresponding phase α s The phase α corresponding to each quantum bit string s also exists. s are all Σ s <s,x> α s =θ(x), and if x can be a quantum bit string other than 0, then there is one corresponding equation for each quantum bit string x. By solving all the equations simultaneously, the phase α s In one specific application, the transformed objective function is f 2,k (x)=<s(2,k),x> In this case, the bit string in the transformed objective function refers to s(2,k), where k∈[2 p ].

[0117] Specifically, the classical computer can determine a matching objective function transformation that needs to be realized on each quantum bit of the current processing stage, and determine a quantum bit control bit that acts on each quantum bit of the target register and a second phase that matches each quantum bit based on the objective function transformation that matches the current processing stage. The quantum bit control bit is at least one quantum bit in the prefix partial quantum bit, and further, based on the action relationship between the quantum bit control bit and each quantum bit of the target register, a duplicated prefix partial quantum bit from the duplicate register can be selected to act on each quantum bit of the target register, thereby realizing an objective function transformation on each quantum bit of the target register by the prefix partial quantum bit in the duplicate register, and an objective function transformation circuit can be obtained.

[0118] Here, after determining the objective function transformation matching the current processing stage, the classical computer can determine a second phase matching each quantum bit based on the phase corresponding to the bit string in the transformed objective function matching the current processing stage. In a specific application, since the transformed objective function performs an inner product between the bit string and the input register, the classical computer can respectively determine the quantum bit string corresponding to each quantum bit in the target register at the current processing stage based on the transformed objective function, and the phase α corresponding to each quantum bit string s obtained by the calculation is s A phase corresponding to the quantum bit string may be determined based on the first phase, and the phase corresponding to the quantum bit string may be a second phase that matches the quantum bit corresponding to the quantum bit string.

[0119] To illustrate this with an example, let us assume that the objective function transformation that needs to be realized on one qubit in the target register is f 1,k (x)=<s(1,k),x> =<0000,x>=<0000,x1x2x3x4> to f 2k(x)=<s(2,k),x> =<1000,x>=<1000,x1x2x3x4>, the classical computer can understand based on the inner product result (0*x1+0*x2+0*x3+0*x4=0,1*x1+0*x2+0*x3+0*x4=x1) that the qubit control bit acting on the qubit is x1, and can further select one x1 from the replica register to act on the qubit in the target register. Here, since x1x2x3x4 is a 4-qubit, its prefix partial qubit is x1x2, and if the number of suffix partial qubits that need to be replicated as a suffix stage replication condition is 2, then it may be x1x2x1x2 in the replication register.

[0120] Specifically, after obtaining the objective function transformation circuit, the classical computer realizes a matching second-phase phase rotation on each quantum bit of the target register, obtains a second phase rotation circuit, and obtains a processing circuit for the current processing stage based on the objective function transformation circuit and the second phase rotation circuit. In one specific application, achieving a matching second-phase phase rotation on each quantum bit of the target register can be realized by a rotation gate, that is, by applying a rotation gate

[35] to the k-th quantum bit of the target register. That is, if<s(j,k),x> If = 1, then the phase of the kth qubit in the target register is α s(j,k) otherwise, the phase remains unchanged. s(j,k) refers to the phase corresponding to the bit string s(j,k), where j is used to represent the current processing stage. The Gray path processing is n-p -1 processing step, where n is the number of input qubits, p = log2(m / 3), m is the number of ancillary qubits, and j = 2, 3, ..., 2 n-p is used to represent each processing step, respectively, where the Gray initialization step can be considered as the processing step with j=1.

[0121]

number

[0122] In this embodiment, the qubit control bits acting on each qubit of the target register and the second phases matching each qubit can be determined based on the objective function transformation matching the current processing step, and when the objective function transformation control is realized by the prefix partial qubits in the duplicated register based on the qubit control bits, the prefix partial qubits in the duplicated register can act on different qubits of the target register respectively. Therefore, the circuits at the time of action can be realized in parallel, thereby obtaining an objective function transformation circuit with a reduced circuit depth, and when realizing the phase rotation of the second phase matching on each qubit of the target register, all phase rotations do not act on the same qubit, and therefore all phase rotations can be arranged in the same layer of the circuit to realize the reduced circuit depth.

[0123] In one embodiment, a method for generating a quantum state preparation circuit includes: Further comprising the step of setting an auxiliary register in the quantum state preparation circuit based on the number of auxiliary quantum bits; According to the qubit duplication scheme, the step of duplicating the prefix partial qubit in the input register and duplicating the prefix partial qubit into the duplication register to obtain a prefix duplication stage circuit includes: According to a qubit duplication scheme, duplicating a prefix partial qubit in an input register, duplicating the prefix partial qubit into a duplication register, and duplicating the prefix partial qubit into an auxiliary register to obtain a prefix duplication stage circuit; The step of performing a gray path process using the prefix partial qubit in the replica register and the target register to obtain a gray path stage circuit includes: The method includes performing a Gray path process using the prefix partial qubit in the replica register, the prefix partial qubit in the auxiliary register, and the target register to obtain a Gray path stage circuit.

[0124] Here, the auxiliary register refers to a set of quantum bits that store auxiliary data, and in this embodiment, the auxiliary data mainly refers to the prefix partial quantum bits. The auxiliary register is used to assist in quantum state preparation and further compress the circuit depth.

[0125] Specifically, the classical computer sets a duplicate register and a target register in the quantum state preparation circuit according to the number of auxiliary quantum bits, and further sets an auxiliary register. In one specific application, when the number of auxiliary quantum bits is m, the number of quantum bits in the duplicate register is m / 3, the number of quantum bits in the target register is m / 3, and the remaining m / 3 quantum bits of the auxiliary quantum bits are divided as the auxiliary register. When duplicating the prefix partial quantum bits in the input register, the classical computer performs a restoration process on the quantum bits that have undergone the suffix processing stage in the duplicate register, and performs column duplication on the prefix partial quantum bits in the input register according to the quantum bit duplication method, and duplicates them on different quantum bits in the duplicate register to obtain a fourth controlled NOT gate circuit, and performs repeated duplication in the row direction on the prefix partial quantum bits duplicated on different quantum bits in the duplicate register until the number of prefix partial quantum bits in the duplicate register meets the prefix duplication stage condition, to obtain a fifth controlled NOT gate circuit.

[0126] At the same time, the classical computer can duplicate the prefix partial quantum bit into the auxiliary register based on the quantum bit duplication method to obtain a sixth controlled NOT gate circuit, and further combine the fourth controlled NOT gate circuit, the fifth controlled NOT gate circuit, and the sixth controlled NOT gate circuit to obtain a prefix duplication stage circuit.

[0127] In a specific application, when the classical computer copies the prefix partial qubits to the auxiliary register according to the qubit duplication method, it first performs column duplication on the prefix partial qubits in the input register once, respectively copies the prefix partial qubits onto different qubits in a single column in the auxiliary register, and then performs repeated duplication in the row direction on the prefix partial qubits copied onto different qubits in a single column in the auxiliary register until the number of prefix partial qubits in the auxiliary register meets the prefix duplication stage condition, to obtain a sixth controlled NOT gate circuit. In a specific application, when performing repeated duplication in the row direction on the prefix partial qubits copied onto different qubits in a single column in the auxiliary register, the classical computer determines the number of rows that need to be copied in the row direction based on the number of prefix partial qubits that need to be copied onto the auxiliary register under the prefix duplication stage condition, and the number of rows that need to be copied is the number of prefix partial qubits that need to be copied onto the auxiliary register under the prefix duplication stage condition minus 1.

[0128] Specifically, at each processing stage of the gray path processing, the classical computer realizes an objective function transformation matching the current processing stage on each quantum bit of the target register by the prefix partial quantum bit in the replica register and the prefix partial quantum bit in the auxiliary register, thereby obtaining a processing circuit of the current processing stage. A gray path stage circuit is obtained based on the processing circuits of each processing stage in the gray path processing. In a specific application, when the prefix partial quantum bit in the replica register and the prefix partial quantum bit in the auxiliary register are used to realize an objective function transformation on each quantum bit of the target register that matches the current processing stage, the classical computer determines the quantum bit control bits acting on each quantum bit of the target register and the second phase matching each quantum bit based on the objective function transformation that matches the current processing stage, respectively, realizes the objective function transformation control using the prefix partial quantum bit in the replica register and the prefix partial quantum bit in the auxiliary register based on the quantum bit control bits, obtains an objective function transformation circuit, realizes phase rotation of the second phase matching on each quantum bit of the target register, obtains a second phase rotation circuit, and obtains a processing circuit for the current processing stage based on the objective function transformation circuit and the second phase rotation circuit.

[0129] In one specific application, the qubit control bit is at least one qubit in the prefix partial qubit. The classical computer can select the duplicated prefix partial qubit from the replica register or the auxiliary register according to the action relationship between the qubit control bit and each qubit of the target register, and operate on each qubit of the target register, thereby realizing the objective function transformation on each qubit of the target register by the prefix partial qubit in the replica register and the qubit in the auxiliary register, and obtain the objective function transformation circuit.

[0130] In this embodiment, by introducing auxiliary registers to perform gray path processing, the auxiliary registers can be used to assist the duplicate registers, and the circuit depth of the gray path stage circuit can be effectively compressed.

[0131] In one embodiment, a quantum state preparation method is provided, and taking the method as applied to the quantum computer 104 in FIG. 1 as an example, the method includes the following steps.

[0132] Quantum state preparation is performed on the circuit initial state data based on the quantum state preparation circuit to obtain quantum state data, and the quantum state preparation circuit is realized by the above quantum state preparation circuit generation method.

[0133] Here, the circuit initial state data refers to the initial data required to prepare the quantum state data. For example, the circuit initial state data may be [Number 36], where n is the number of quantum bits to be input. Also, for example, the circuit initial state data may be any set of computational cardinals of the quantum system.

[0134]

number

[0135] Specifically, the classical computer transmits a quantum program configured by the quantum state preparation circuit to the quantum computer, and the quantum computer executes the quantum program to perform quantum state preparation for the circuit initial state data based on the quantum state preparation circuit, thereby obtaining quantum state data.

[0136] The above quantum state preparation method can reduce the decoherence effect by using a quantum state preparation circuit that effectively compresses the circuit depth to perform quantum state preparation on circuit initial state data and obtain quantum state data.

[0137] This application further provides an application scenario, in which the quantum state preparation circuit generation method according to the above embodiment can be used to realize any n-qubit quantum circuit. In the following, the design of any n-qubit quantum circuit is described, that is, the above quantum state preparation circuit generation method is described. First, the symbols used in this application scenario are defined. The main symbols used in this application scenario are shown in the following [Table 1].

[0138] [Table 1]

[0139] Specifically, as shown in Figure 9, in this application scenario, the design of the quantum state preparation circuit can be divided into three steps. Step 1: Construct a circuit framework and design the quantum state preparation circuit as a set of uniform control gates V1, V2, …, V n Step 2: Decompose each uniform control gate in the quantum state preparation circuit into three diagonal unitary matrices and four 1-bit quantum gates. Step 3: Realize a diagonal unitary matrix quantum circuit with an auxiliary qubit under the grid restriction condition. Here, step 3 is specifically n All phases α corresponding to the quantum bit string s s This can be realized by generating the above, which includes steps 3.1 to 3.5. Steps 3.1 to 3.5 are: step 3.1: suffix duplication step; step 3.2: Gray initialization step; step 3.3: prefix duplication step; step 3.4: Gray cycle step; step 3.5: inversion step. As can be seen from this, as long as a diagonal unitary matrix quantum circuit with an auxiliary quantum bit can be realized under the grid restriction condition, a uniform control gate circuit can be obtained by combining the diagonal unitary matrix quantum circuit and the 1-bit quantum gate, and a quantum state preparation circuit can be generated by combining the uniform control gate circuit. Each step will be described in detail below.

[0140] Step 1: Construct a circuit framework and define the quantum state preparation circuit as a set of uniform control gates V1, V2, …, V n Decompose into:

[0141] First, we define a uniform control gate and define an n-qubit uniform control gate V n teeth, It is defined as [Equation 37], Here, for any k∈[2 n-1 ], U k ∈C 2×2 is a unitary matrix. Any n-qubit quantum circuit can be decomposed into a combination of n uniform control gates of different sizes, i.e., [Equation 38], where I n-k represents the unitary operator of nk qubits. Based on the principle of circuit decomposition, when one global phase is ignored, the uniform control gate can be decomposed into a diagonal unitary matrix and a 1-bit quantum gate, that is, the uniform control gate circuit includes a diagonal unitary matrix quantum circuit and a 1-bit quantum gate. In this application scenario, the uniform control gate is decomposed into a combination of three diagonal unitary matrices and four 1-bit quantum gates.

[0142] Step 2: Decompose each uniform control gate in the quantum state preparation circuit into three diagonal unitary matrices and four 1-bit quantum gates.

[0143]

number

number

[0144] First, we define an n-qubit diagonal unitary matrix

[39] . As can be seen from the principle of circuit decomposition, when one global phase is ignored, the uniform control gate can be decomposed into the following form

[40] : where

[41] is an n-qubit diagonal unitary matrix, that is, each uniform control gate in the quantum state preparation circuit can be decomposed into three diagonal unitary matrices and four 1-bit quantum gates.

[0145]

number

number

number

[0146] Step 3: Realize a diagonal unitary matrix quantum circuit with ancillary qubits under grid restriction conditions.

[0147] After steps 1 and 2, the quantum state preparation circuit has been decomposed into a series of diagonal unitary matrices and some 1-bit quantum gates. Therefore, the quantum state preparation circuit can be obtained by simply realizing the quantum circuit of any diagonal unitary matrix. Therefore, in step 3, under the grid restriction condition, this application scenario utilizes auxiliary qubits to realize the parallelism of the diagonal unitary matrix quantum circuit, thereby achieving the purpose of reducing the circuit depth.

[0148] Here, the action of the diagonal unitary matrix quantum circuit is to realize the following transformation on each vector |x> in a set of computational cardinalities of the quantum system, |x>→e iθ(x) |x>,∀x∈{0,1} n Based on this, the inventors determine the parameter {α s :s∈{0,1} n -{0 n}} is Σ s <s,x> α s =θ(x),∀x∈{0,1} n -{0 n}, where s and x are quantum bit strings, n is the number of input quantum bits, and α s is the phase,<s,x> represents the dot product of the quantum bit string s and the quantum bit string x, so that 2 n All phases α corresponding to the quantum bit string s sBy generating n Each of the quantum bit strings s has a corresponding phase α s exists.

[0149] First, the inventors introduce three circuit structures under grid-constrained conditions, and the following three circuits are used to realize step 3. 1. The controlled NOT gate [Equation 42] is realized by a circuit under path constraint. Under path constraint, [Equation 43] can be realized by a CNOT circuit with depth and size both O(|ij|) (as shown in Figure 8). 2. A reversible linear transformation of n-qubits is realized by a circuit under path constraint. Assume that U is a reversible linear transformation of n qubits. Under the n-path constraint, U has a circuit depth of O(n 2 3. Transformation duplication can be realized by a circuit under the grid restriction. Under the n1×n2 grid restriction, for any x=x1x2…x n ∈{0,1} n In contrast, the duplication of the transformation

[44] has depth O(n 2 This can be realized by a CNOT circuit (n1+n2).

[0150]

number

number

number

[0151] Here, the realization of transformation replication under the n1 × n2 grid restriction is divided into two steps. Step 1: Replication under the first column restriction (n1-path restriction n) is to realize the following transformation:

[0152] [Number 45] That is, |x> is replicated and replicated on [Numerical formula 46] quantum bits. The replication of the above transformation can be realized by a replication circuit under column restriction shown in Fig. 7. As can be seen from the fact that the controlled NOT gates in the replication circuit under column restriction are realized by circuits under path restriction, each controlled NOT gate can be realized by a CNOT circuit with a depth of O(n) under (n+1)-path restriction. Therefore, under the n1-path restriction, the circuit depth of the above transformation is [Numerical formula 47].

[0153]

number

number

number

[0154] Step 2: Duplicate each qubit (i,1) n2-1 times under the constraint of n2-paths (i,1)-(i,2)-...-(i,n2) (row i of the grid). For any i ∈ [n1], this step can be realized by a quantum circuit of depth O(n2) [Equation 48]. The n1 path constraints are disjoint and can therefore be realized in parallel.

[0155]

number

[0156] Furthermore, in order to more clearly describe the quantum circuit structure of each step, this application scenario first introduces some symbols: p = log(m / 3), x = x pre x suf ∈{0,1} n , x pre =x1x2…x n-p , and x suf =x n-p+1 …x n where m is the number of ancillary qubits, x is the qubit in the input register, and x preis the prefix partial qubit in the input register, and x suf is the suffix partial qubit in the input register, n is the number of qubits to be input, and without loss of generality, n1 ≥ n2. Before designing the quantum state preparation circuit under the grid limit, this application scenario first introduces the circuit realization of the unitary transformation that needs to be used subsequently. Without loss of generality, n2 ≤ 2 n / 3 , and [Equation 49]. n2 is 2 n / 3 If the width is larger than 2, the application scene n / 3 If we use only a grid of I = {ι1,ι2,…,ι}, then we use only ancillary qubits not exceeding I = {ι1,ι2,…,ι}. The input qubits are called the input register and are written as I = {ι1,ι2,…,ι}. n The ancillary qubits are split into three registers, and the replica register C:C={c1, c2, …, c m / 3}, target register T: T={t1, t2, …, t m / 3}, auxiliary register A: A={a1, a2, …, a m / 3}.

[0157]

number

number

number

[0158] In the n1×n2-grid, there is one path of length n+m=n1×n2. The arrangement of the qubits in these three registers under the n+m-path restriction is as follows, where c i , t i , and a i (i∈[1,m / 3]) is the name of each qubit in the n1×n2-grid, and R i ([Number 52]) is the group name after the named quantum bits are grouped.

[0159]

number

[0160] R1: c1, t1, c2, t2, …, c n-p ,t n-p ,a1,a2,…,a n-p R2:c n-p+1 ,t n-p+1 ,c n-p+2 ,t n-p+2 ,…,c 2(n-p) ,t 2(n-p) ,a n-p+1 ,a n-p+2 ,…,a 2(n-p) R k :c (k-1)(n-p)+1 ,t (k-1)(n-p)+1 ,c (k-1)(n-p)+2 ,t (k-1)(n-p)+2 ,…,c k(n-p) ,t k(n-p) ,a (k-1)(n-p)+1 ,a (k-1)(n-p)+2 ,…,a k(n-p) [Number 53] [Number 54]

[0161]

number

number

[0162] Below, we will explain each of the subdivided steps included in step 3.

[0163] Step 3.1: Suffix duplication phase.

[0164] In the suffix duplication stage, under the grid constraint, the remaining p qubits in the input register x n-p+1 ,x n-p+2 ,…,x nWe need to realize a system where we replicate the input register and the replicated register C with

[55] copies of the input register and the replicated register C. That is, under the grid constraint, we can realize a diagonal unitary matrix U copy,1 To achieve this.

[0165]

number

[0166] [Number 56] Where: [Number 57]

[0167]

number

number

[0168] As can be seen from the grid-restricted circuit realization of the transformation replication, under the grid restriction, U copy,1 is a depth of O(p 2 +n1+n2)=O(log 2 This can be realized by a CNOT circuit (m+n1+n2).

[0169] Step 3.2: Gray initialization stage.

[0170] In the Gray initialization stage, the circuit realization is divided into two steps. The first step U1 is to realize m / 3 linear functions f 1,k (x)=<s(1,k),x> where s(1,k) is an n-bit string and the subscript j indicates that the linear function is realized in the k-th bit of the target register. The second step realizes phase rotation in the target register. To clearly describe the linear function realized in the first step, the following bit string set is constructed in this application scenario:

[0171] Here, p = log(m / 3). Set {0,1} nis a two-dimensional array of n-bit strings, {s(j,k):j∈[2 n-p ],k∈[2 p ]}, and the two-dimensional array satisfies the following three conditions: 1. The first row of the array {s(1,k):k∈[2 p ]}, the leading (np) bits of the bit string are all 0, and each column of the array {s(j,k):j∈[2 n-p ]} have the same last p bits. 2.∀k∈[2 p ], ∀j∈[2 n-p -1], and s(j,k) and s(j+1,k) differ in exactly one bit. 3. [Number 58], and the prefix partial bits of s(1+(l-1)(np),k), s(2+(l-1)(np),k), ..., s(l(np),k) are 1-Gray code, 2-Gray code, ..., np Gray code, respectively.

[0172]

number

[0173] Here, the target of the first step U1, after completing the step, stores the quantum state |f 1,k (x)>, where f 1,k (x)=<s(1,k),x> The second step is used to apply a rotation gate

[59] to the kth qubit of the target register. That is, if<s(1,k),x> If = 1, then the phase of the kth qubit is α s(1,k) If it rotates, the phase remains unchanged. R1 = R(α s(1,k) )

[0174]

number

[0175] In the following, we describe the transformations implemented in the Gray initialization stage and the circuit depths that implement these transformations.

[0176] The gray initialization stage is usually GrayInit , which can complete the following operations:

[0177] [Number 60] where

[61] . Under the path (grid) constraint, the Gray initialization stage has depth O(log 2 This can be realized by a quantum circuit (m).

[0178]

number

number

[0179] First, in the first step U1, the suffix variable x n-p+1 ,x n-p+2 ,…,x n After the first step U1, the 2 in the target register is p The state of the qubits is transformed to [Equation 62], i.e., the process converts the kth qubit in the target register to |f 1,k (x)>. In the second step, the base |x> I |x SufCopy > C |0 m / 3 > T Phase f 1,k (x)·α s(1,k) Add. Therefore, [Number 63] can be obtained.

[0180]

number

number

[0181] After step 3.1, for the qubits in the replica register C and the target register T, we have the form

[0182]

number

[0183] where c 1+(l-1)p , c 2+(l-1)p , …c lp respectively represent qubits in the replica register C, and t 1+(l-1)p , t 2+(l-1)p , …t lp respectively represent qubits in the target register T, i.e., the suffix partial qubit has already been replicated in the replicate register and is still 0 in the target register.

[0184] Therefore, the transformation of U1 can be written in the following form: [Number 65] [Number 66]

[0185]

number

number

[0186] For each [number 67], transform [Number 68] is a reversible linear transformation of p-qubits, so in the path (grid) restriction, the above process has depth O(p 2 ) CNOT circuit. Since the circuit constraint diagrams of the above transformations do not intersect with each other, all transformations can be realized in parallel. Therefore, transformation U1 can be realized with a depth of O(p 2 ) can be realized using the CNOT circuit.

[0187]

number

number

[0188] For operator R1, all rotation gates do not operate on the same quantum bit, so they can be placed in the same layer of the circuit, i.e., the circuit depth is 1. As described above, the circuit depth in the Gray initialization phase is O(p 2 )=O(log 2 m).

[0189] Step 3.3: Prefix duplication phase.

[0190] In the prefix duplication step, we first restore the quantum state obtained in the suffix duplication step, and then recalculate the prefix variables x1, x2, …, x in the duplicate register and the auxiliary register, respectively. n-p The prefix duplication stage is similar to the suffix duplication stage, and a duplicated description of the circuit structure is omitted here.

[0191]

number

[0192] The prefix duplication stage usually begins with U copy,2 and the variables x1,…,x in the input registers. n-p Each of the 70 copies of each of the 80 is replicated in the replica register and the auxiliary register, so that the depth is at most O(n 2 It is necessary to realize a CNOT circuit of n1 + n2).

[0193]

number

[0194] U copy,2 The effect achieved by [Number 71], where |0m / 3 > C represents the duplicate register, and |0 m / 3 > A represents the auxiliary register and is given by [number 72].

[0195]

number

number

[0196] The operator of the prefix duplication stage is

[73] , and the depth is at most O(p 2 +n1+n2)+2·O((np) 2 +n1+n2)=O(n 2 +n1+n2), where [Equation 74] represents the restoration of the quantum state obtained in the suffix duplication step. Therefore, the effect of the operator [Equation 75] in this step is [Number 76] [Number 77]

[0197]

number

number

number

number

number

[0198] Step 3.4: Gray cycle stage (i.e., gray pathway processing stage).

[0199] The grey cycle phase is 2 n-p -1 processing step, j=2,3,…,2 n-pWe use , to subscript these processing steps. The Gray initialization step can be considered as the processing step with j=1. At each processing step j, the circuit C realizes the following two steps. Step 1 is a quantum circuit U consisting of CNOT gates. j The CNOT gate is controlled by

[78] , the target bit is the kth bit of the target register, where t jk represents the subscript of the distinct bits of s(j,k) and s(j+1,k) in the two-dimensional array. Step 2 operates on the kth qubit of the target register to find R(α s(j,k) ) rotate. Let us use [Number 79].

[0200]

number

number

[0201] Thus, in the Gray cycle stages, the jth stage actually realizes the following transformation:

[0202] [Number 80] where f j,k (x)=<s(j,k),x> , and [Equation 81]. The circuit depth of the Gray cycle stage is at most O(2 n-p ).

[0203]

number

number

[0204] Below, we provide a proof of the structure of the circuit in the Gray cycle stage. The Gray cycle stage consists of two steps, namely, two steps realized in each processing stage. n-p -Repeat 1 time.

[0205] For step 1, for convenience of description, we use U j Write the transformation in the following equivalent form: [Number 82]

[0206]

number

[0207] In register R1 we implement the following transformation:

[0208] [Number 83] [Number 84] where f j,1 (x)=<s(j,1),x> , f j+1,1 (x)=<s(j+1,1),x> That is, what is realized in the register R1 is the conversion from the bit string in the jth row to the bit string in the j+1th row of the structured two-dimensional array.

[0209]

number

number

[0210] Without loss of generality, assume that s(j,1) and s(j+1,1) differ in the γth bit. By the properties of the Gray code cycle, s(j,1), …, s(j,np) and s(j+1,1), …, s(j+1,np) differ in the γ, γ+1, γ+2, …, np, 1, 2, …, γ-1th bits, respectively.

[0211] If γ=1, the conversion can be realized by the following CNOT circuit. [Number 85]

[0212]

number

[0213] The control bits and target bits of each CNOT gate in the circuit are adjacent, and the control bits and target bits of any two CNOT gates are different, so the circuit depth is 1. If γ is strictly greater than 1, the conversion can be realized by the CNOT circuit shown below in [Equation 86].

[0214]

number

[0215] Here, the circuit represents the ability to operate on the target register with the qubits in the auxiliary register, i.e., γ-1 using the qubits in the auxiliary register and the rest using the qubits in the replica register. k All CNOT gates in are bounded by non-intersecting paths, and these CNOT gates can be realized in parallel, i.e., auxiliary registers can be used to further compress the circuit depth. Also, the distance between the control bit and the target bit of a CNOT gate is O(γ). Therefore, under the grid (path) constraint, C k can be realized by a circuit of depth O(γ). Therefore, under the grid constraint,

[87] can be realized by a circuit of depth O(γ)·(γ-1). For every register R l The conversion in R1 is the same as in R2, and the diagram restrictions in these registers do not cross, so U j The circuit depth is O(γ 2 ).

[0216]

number

[0217] For step 2, it only involves 1-bit quantum gates operating on different qubits, and therefore the step can be realized in one layer of circuits in parallel.

[0218] However, as can be understood based on the nature of the Gray code, n-p In the -1 processing step, s(j,1) and s(j+1,1) are the γth bit of n-p-γ Therefore, under the path (grid) constraint, the Grey cycle stage can be realized by a circuit with a depth of

[88] .

[0219]

number

[0220] Step 3.5: Inversion stage.

[0221] The quantum circuit for the inversion stage is given by [Number 89].

[0222]

number

[0223] It achieves the following transformations: [Number 90]

[0224]

number

[0225] That is, the duplicate registers, the target registers, and the auxiliary registers are restored.

[0226] It is necessary to explain that the quantum circuit in the inversion stage is the inverse circuit of all the CNOT circuits in steps 3.1 to 3.4, and has a depth of [Mathematical Formula 91].

[0227]

number

[0228] Combining the above five steps, we can get to step 3 (diagonal unitary matrix Λ n ) we can obtain a diagonal unitary matrix quantum circuit corresponding to

[0229] By adding up the depths of the five quantum circuits above, we can obtain the full circuit depth

[92] .

[0230]

number

[0231] The five steps in step 3 above are the diagonal unitary matrix Λ n The process of achieving this can be expressed by the following equation [Equation 93].

[0232]

number

[0233] Here, U copy,1 refers to the suffix duplication stage, and U GrayInit refers to the Gray initialization stage, [Equation 94] refers to the prefix duplication stage, R2U2 refers to the first processing stage of the Gray cycle stage, [Equation 95] refers to the last processing stage of the Gray cycle stage, and U Inverse refers to the inversion stage. θ(x) refers to the phase rotation that a diagonal unitary matrix needs to achieve.

[0234]

number

number

[0235] From the above analysis, we can conclude that if the number of ancillary qubits is m≧3n and m+n=n1n2, then under the n1×n2-grid restriction, any n-qubit diagonal unitary matrix

[96] can be realized by a quantum circuit with a circuit depth of

[97] .

[0236]

number

number

[0237] By further reasoning, we can obtain the following, and set m+n=n1n2. Given m (m ≥ 3n) ancillary qubits and the constraint of an n1 × n2-2-dimensional grid, any n-qubit quantum state |ψ v > can be prepared by a quantum circuit of depth [number 98].

[0238]

number

[0239] It should be understood that although the steps in the flowcharts according to the above embodiments are displayed in order according to the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this specification, the execution of these steps is not limited to a strict order, and these steps may be executed in other orders. Furthermore, at least some of the steps in the flowcharts according to the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily performed in order, but may be performed alternately or with other steps, or at least some of the steps or stages of other steps.

[0240] Based on the same inventive idea, the embodiments of the present application further provide a quantum state preparation circuit generation device used to realize the above-mentioned quantum state preparation circuit generation method. The means for solving the problem provided by the device are similar to the means described in the above-mentioned method, therefore, for the specific limitations in one or more embodiments of the quantum state preparation circuit generation device provided below, the limitations of the above-mentioned quantum state preparation circuit generation method can be referred to, and the duplicated description will be omitted here.

[0241] In one embodiment, as shown in FIG. 10, a quantum state preparation circuit generation device is provided, which includes a first setting module 1002, a second setting module 1004, a circuit construction module 1006, a circuit combination module 1008, and a processing module 1010, wherein: The first setting module 1002 is used for setting an input register in the quantum state preparation circuit according to a circuit preparation parameter of the quantum state preparation circuit, and determining the number of auxiliary quantum bits; The second setting module 1004 is used for setting the replica register and the target register in the quantum state preparation circuit according to the number of auxiliary quantum bits; The circuit construction module 1006 is used to construct a circuit by using an input register, a copy register, and a target register according to a qubit duplication scheme to obtain a diagonal unitary matrix quantum circuit, the qubit duplication scheme being obtained according to a grid restriction condition; the circuit combination module 1008 is used for combining the diagonal unitary matrix quantum circuit and the one-bit quantum gate to obtain the diagonal unitary matrix quantum circuit and the corresponding uniform control gate circuit; The processing module 1010 is used to generate a quantum state preparation circuit based on at least one uniform control gate circuit.

[0242] The quantum state preparation circuit generation device can set an input register in the quantum state preparation circuit according to the circuit preparation parameters, and determine the number of auxiliary quantum bits, thereby realizing the setting of the copy register and the target register according to the number of auxiliary quantum bits. Based on the quantum bit duplication method, the circuit is constructed by the input register, the copy register, and the target register, and when the constraint of the grid limiting condition is taken into consideration, a diagonal unitary matrix quantum circuit can be constructed by using combination skills. Furthermore, a uniform control gate circuit can be obtained by combining the diagonal unitary matrix quantum circuit and the 1-bit quantum gate, and a quantum state preparation circuit can be generated based on the uniform control gate circuit. In the whole process, the auxiliary quantum bits and combination skills can be used to realize the parallelization of the quantum state preparation circuit under the constraint of the grid limiting condition, and a quantum state preparation circuit with an effectively compressed circuit depth can be obtained, thereby realizing the reduction of the decoherence effect.

[0243] In one embodiment, the qubit duplication scheme includes performing column duplication on the qubits under a grid-constrained condition, obtaining a column duplication result, and performing row duplication based on the column duplication result.

[0244] In one embodiment, the input register includes a prefix partial qubit and a suffix partial qubit. The circuit construction module is further used for: duplicating the suffix partial qubit in the input register according to a qubit duplication scheme, duplicating the suffix partial qubit into a duplication register, obtaining a suffix duplication stage circuit, performing a Gray initialization process by the suffix partial qubit in the duplication register and a target register, obtaining a Gray initialization stage circuit, duplicating the prefix partial qubit in the input register according to a qubit duplication scheme, duplicating the prefix partial qubit into a duplication register, obtaining a prefix duplication stage circuit, performing a Gray path process by the prefix partial qubit in the duplication register and a target register, obtaining a Gray path stage circuit, performing an inversion process according to the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, and the Gray path stage circuit, obtaining an inversion process stage circuit, and obtaining a diagonal unitary matrix quantum circuit according to the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, the Gray path stage circuit, and the inversion process stage circuit.

[0245] In one embodiment, the circuit construction module is further used to perform column duplication on the suffix partial qubits in the input register based on a qubit duplication scheme, duplication onto different qubits in the duplication register to obtain a first controlled NOT gate circuit, and iteratively perform row-wise duplication on the suffix partial qubits duplicated onto different qubits in the duplication register until the number of suffix partial qubits in the duplication register satisfies a suffix duplication stage condition to obtain a second controlled NOT gate circuit, and obtain a suffix duplication stage circuit based on the first controlled NOT gate circuit and the second controlled NOT gate circuit.

[0246] In one embodiment, the circuit construction module is further used to realize an objective function matching on each quantum bit of the target register by the suffix partial quantum bit in the replica register, obtain a third controlled NOT gate circuit, respectively determine a first phase matching each quantum bit of the target register based on the objective function matching each quantum bit, realize a phase rotation of the first phase matching on each quantum bit of the target register, obtain a first phase rotation circuit, and obtain a Gray initialization stage circuit based on the third controlled NOT gate circuit and the first phase rotation circuit.

[0247] In one embodiment, the circuit construction module is further used for respectively determining a quantum bit string corresponding to each quantum bit in the target register based on an objective function matching each quantum bit, determining a phase corresponding to the quantum bit string, and setting the phase corresponding to the quantum bit string as a first phase matching the quantum bit corresponding to the quantum bit string.

[0248] In one embodiment, the circuit construction module is further used to perform a restoration process on the quantum bits that have undergone the suffix processing stage in the replica register, perform column duplication on the prefix partial quantum bits in the input register based on a quantum bit duplication scheme, duplicate them onto different quantum bits in the replica register, obtain a fourth controlled NOT gate circuit, perform repeated row duplication on the prefix partial quantum bits duplicated onto different quantum bits in the replica register until the number of prefix partial quantum bits in the replica register satisfies the prefix duplication stage condition, obtain a fifth controlled NOT gate circuit, and obtain a prefix duplication stage circuit based on the fourth controlled NOT gate circuit and the fifth controlled NOT gate circuit.

[0249] In one embodiment, the circuit construction module is further used to realize, at each processing stage of the gray path processing, an objective function transformation matching the current processing stage on each quantum bit of the target register by a prefix partial quantum bit in the replica register, to obtain a processing circuit of the current processing stage, and obtain a gray path stage circuit based on the processing circuit of each processing stage in the gray path processing.

[0250] In one embodiment, the circuit construction module is further used for respectively determining, based on the objective function transformation matching the current processing stage, a quantum bit control bit acting on each quantum bit of the target register and a second phase matching each quantum bit, and realizing the objective function transformation control by a prefix partial quantum bit in the replica register based on the quantum bit control bit, obtaining an objective function transformation circuit, realizing a phase rotation of the second phase matching on each quantum bit of the target register, obtaining a second phase rotation circuit, and obtaining a processing circuit of the current processing stage based on the objective function transformation circuit and the second phase rotation circuit.

[0251] In one embodiment, the second setting module is further used for setting an auxiliary register in the quantum state preparation circuit based on the number of auxiliary quantum bits, and the circuit construction module is further used for duplicating the prefix partial quantum bits in the input register based on a quantum bit duplication scheme, duplicating the prefix partial quantum bits to a duplicate register, and duplicating the prefix partial quantum bits to the auxiliary register to obtain a prefix duplication stage circuit, and performing Gray path processing by the prefix partial quantum bits in the duplicate register, the prefix partial quantum bits in the auxiliary register, and the target register to obtain a Gray path stage circuit.

[0252] Based on the same inventive idea, the embodiments of the present application further provide a quantum state preparation device used to realize the above quantum state preparation method. The means for solving the problem provided by the device are similar to the means described in the above method. Therefore, for the specific limitations of one or more embodiments of the quantum state preparation device provided below, the limitations of the above quantum state preparation method can be referred to, and the duplicated description will be omitted here.

[0253] In one embodiment, a quantum state preparation device is provided, which includes a preparation module used to perform quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, wherein the quantum state preparation circuit is realized by the above-mentioned quantum state preparation circuit generation method.

[0254] The above-mentioned quantum state preparation device can reduce the decoherence effect by using a quantum state preparation circuit that effectively compresses the circuit depth to perform quantum state preparation on circuit initial state data and obtain quantum state data.

[0255] The quantum state preparation circuit generation device and each module in the quantum state preparation device can be realized in whole or in part by software, hardware, or a combination thereof. Each module may be built into a processor in a computer device in the form of hardware, or may be independent, or may be stored in a memory in a computer device in the form of software, so that the processor calls and executes the operations corresponding to each module.

[0256] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram is shown in FIG. 11. The computer device includes a processor, a memory, an input / output interface (abbreviated as Input / Output, I / O), and a communication interface. Here, the processor, the memory, and the input / output interface are connected by a system bus, and the communication interface is connected to the system bus by the input / output interface. Here, the processor of the computer device is used to provide calculation and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer-readable instructions, and a database. The internal memory provides an environment for the operation of the operating system and the computer-readable instructions in the non-volatile storage medium. The database of the computer device is used to store data such as circuit preparation parameters. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to connect and communicate with an external terminal through a network. The computer readable instructions, when executed by a processor, implement a quantum state preparation circuit generation method.

[0257] As will be understood by those skilled in the art, the structure shown in FIG. 11 is merely a block diagram of a partial structure related to the means of the present application, and does not constitute a limitation on a computer device to which the means of the present application is applied; a specific computer device may include more or fewer components than those shown, or may combine some components, or may have a different component arrangement.

[0258] In one embodiment, a computer device is further provided, comprising a memory and a processor, wherein computer-readable instructions are stored in the memory, and the processor, when executing the computer-readable instructions, realizes the steps in each of the embodiments of the quantum state preparation circuit generation method described above.

[0259] In one embodiment, a quantum computer is provided, comprising a memory and a processor, the memory having computer-readable instructions stored therein, the processor performing steps in the embodiment of the quantum state preparation method described above when executing the computer-readable instructions.

[0260] In one embodiment, a computer readable storage medium is provided having computer readable instructions stored thereon which, when executed by a processor, implement the steps in each of the method embodiments described above.

[0261] In one embodiment, a computer program product is provided, the computer program product including computer readable instructions, the computer readable instructions being stored in a computer readable storage medium, a processor of a computing device reads the computer readable instructions from the computer readable storage medium, and the processor executes the computer readable instructions, thereby causing the computing device to perform the steps in each of the method embodiments described above.

[0262] In one embodiment, a quantum device is provided, which realizes a quantum state preparation circuit by the above quantum state preparation circuit generation method.

[0263] Here, the quantum device refers to a device that uses the principle of quantum mechanics to perform calculations. Based on the superposition principle of quantum mechanics and quantum entanglement, the quantum device has a relatively strong parallel processing ability and can solve problems that are difficult to calculate with some classical computers. For example, the quantum device may specifically refer to a quantum computer. Also, for example, the quantum device may specifically refer to a quantum chip. The quantum chip is the central processor of a quantum computer.

[0264] Specifically, the quantum device can realize the quantum state preparation circuit by executing the corresponding quantum program based on the above quantum state preparation circuit generation method. It is necessary to explain that the circuit for realizing the quantum state preparation in this embodiment refers to realizing the quantum state preparation circuit on the actual quantum components, that is, the realized quantum state preparation circuit is a physical circuit.

[0265] The quantum device can obtain a quantum state preparation circuit with an effectively compressed circuit depth, thereby realizing a reduction in the effect of decoherence.

[0266] It is necessary to explain that all data related to this application (including but not limited to data used for analysis, data stored, data displayed, etc.) is data authorized by the user or fully authorized by each party, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0267] As can be understood by those skilled in the art, the realization of all or part of the process in the above embodiment method may be completed by issuing instructions to relevant hardware by computer readable instructions, and the above computer readable instructions may be stored in a non-volatile computer readable storage medium, and when the computer readable instructions are executed, the process of each embodiment of the above method may be included. Here, any examples of memory, database, or other medium used in each embodiment provided in the present application may include at least one of non-volatile and volatile memory. The non-volatile memory may include a read-only memory (ROM), a tape, a floppy disk, a flash memory, an optical memory, a high-density embedded non-volatile memory, a resistive memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM (registered trademark)), a phase change memory (PCM), and a graphene memory, etc. The volatile memory may include a random access memory (RAM), an external high-speed cache memory, etc. By way of illustration and not limitation, the RAM may be in a variety of forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The database according to the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a distributed database based on a blockchain. The processor according to the embodiments provided herein may be, but is not limited to, a general-purpose processor, a central processor, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, and the like.

[0268] Each technical feature of the above embodiments can be combined in any combination, and for the sake of brevity, not all possible combinations of each technical feature in the above embodiments are described. However, as long as these combinations of technical features are not mutually inconsistent, they should be considered to be within the scope described herein.

[0269] It should be understood that the above examples merely show some embodiments of the present application, and the description is relatively specific and detailed, but does not limit the patent scope of the application. It should be noted that a person skilled in the art can make various modifications and improvements without departing from the idea of ​​the present application, all of which are within the scope of protection of the present application. Therefore, the scope of protection of the present application should be in accordance with the scope of the attached claims. [Explanation of symbols]

[0270] 102 Classical Computers 104 Quantum Computer 1002 First setting module 1004 Second Setting Module 1006 Circuit Construction Module 1008 Circuit Combination Module 1010 Processing Module

Claims

1. 1. A quantum state preparation circuit generation method executed by a computing device, the quantum state preparation circuit generation method comprising: setting an input register in the quantum state preparation circuit based on a circuit preparation parameter of the quantum state preparation circuit and determining a number of auxiliary quantum bits; setting a replica register and a target register in the quantum state preparation circuit based on the number of auxiliary quantum bits; A step of constructing a circuit by the input register, the duplicated register, and the target register based on a quantum bit duplication scheme to obtain a diagonal unitary matrix quantum circuit, the quantum bit duplication scheme being obtained based on a grid restriction condition; combining the diagonal unitary matrix quantum circuit with a one-bit quantum gate to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit; generating the quantum state preparation circuit based on at least one of the uniform control gate circuits; The quantum state preparation circuit generating method includes performing column duplication on quantum bits under a grid limiting condition, obtaining column duplication results, and performing row duplication based on the column duplication results.

2. the input register includes a prefix partial qubit and a suffix partial qubit; The step of constructing a circuit using the input register, the duplicated register, and the target register based on a quantum bit duplication scheme to obtain a diagonal unitary matrix quantum circuit includes: Duplicating the suffix partial qubits in the input register according to a qubit duplication scheme, and duplicating the suffix partial qubits into the duplication register to obtain a suffix duplication stage circuit; performing a Gray initialization process using the suffix partial qubits in the replica register and the target register to obtain a Gray initialization stage circuit; Duplicating the prefix partial qubit in the input register according to the qubit duplication scheme, and duplicating the prefix partial qubit into the duplication register to obtain a prefix duplication stage circuit; performing a Gray path process using the prefix partial qubit in the replica register and the target register to obtain a Gray path stage circuit; performing an inversion process based on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, and the Gray path stage circuit to obtain an inversion process stage circuit; and obtaining a diagonal unitary matrix quantum circuit based on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, the Gray path stage circuit, and the inversion processing stage circuit.

3. The step of duplicating the suffix partial qubits in the input register based on a qubit duplication scheme and duplicating the suffix partial qubits to the duplication register to obtain a suffix duplication stage circuit includes: performing column duplication for suffix partial qubits in the input register based on a qubit duplication scheme, and duplicating them onto different qubits in the duplication register to obtain a first controlled NOT gate circuit; Repeatedly duplicating the suffix partial qubits replicated on different qubits in the replica register in a row direction until a quantity of suffix partial qubits in the replica register satisfies a suffix duplication stage condition to obtain a second controlled NOT gate circuit; and deriving a suffix duplication stage circuit based on said first controlled NOT gate circuit and said second controlled NOT gate circuit.

4. The step of performing a Gray initialization process using the suffix partial qubits in the replica register and the target register to obtain a Gray initialization stage circuit includes: implementing a matching objective function on each qubit of the target register with a suffix partial qubit in the replica register to obtain a third controlled NOT gate circuit; determining a first phase that matches each quantum bit of the target register based on an objective function that matches each quantum bit; implementing a phase rotation of the matching first phase on each quantum bit of the target register to obtain a first phase rotation circuit; and obtaining a Gray initialization stage circuit based on said third controlled NOT gate circuit and said first phase rotation circuit.

5. The step of determining a first phase to match each quantum bit of the target register based on an objective function to match each quantum bit, respectively, comprises: determining a qubit string corresponding to each qubit in the target register based on an objective function matching each qubit; determining a phase corresponding to the quantum bit string; and determining a phase corresponding to the quantum bit string as a first phase that matches a quantum bit corresponding to the quantum bit string.

6. The step of duplicating the prefix partial qubit in the input register based on the qubit duplication scheme and duplicating the prefix partial qubit to the duplication register to obtain a prefix duplication stage circuit includes: performing a restoration process on the quantum bits that have undergone the suffix processing step in the replica register; performing column duplication on the prefix partial qubits in the input register according to the qubit duplication scheme, and duplicating them onto different qubits in the duplication register to obtain a fourth controlled NOT gate circuit; repeating duplication in a row direction of the duplicated prefix partial qubits on different qubits in the duplicate register until the number of prefix partial qubits in the duplicate register satisfies a prefix duplication stage condition to obtain a fifth controlled NOT gate circuit; and obtaining a prefix duplication stage circuit based on the fourth controlled NOT gate circuit and the fifth controlled NOT gate circuit.

7. The step of performing a Gray path process using the prefix partial qubit in the replica register and the target register to obtain a Gray path stage circuit includes: At each processing stage of the Gray path processing, implementing an objective function transformation on each qubit of the target register by a prefix partial qubit in the replica register that matches the current processing stage to obtain a processing circuit of the current processing stage; and deriving a gray path stage circuit based on the processing circuitry of each processing stage in the gray path processing.

8. The step of implementing an objective function transformation on each qubit of the target register by a prefix partial qubit in the replica register that matches a current processing stage to obtain a processing circuit of the current processing stage includes: determining a qubit control bit to operate on each qubit in the target register based on an objective function transformation matching a current processing step, and a second phase matching each qubit; According to the quantum bit control bit, an objective function conversion control is realized by a prefix partial quantum bit in the replica register to obtain an objective function conversion circuit; implementing a phase rotation of the matching second phase on each quantum bit of the target register to obtain a second phase rotation circuit; and obtaining a processing circuit of a current processing stage based on the objective function transformation circuit and the second phase rotation circuit.

9. the qubit control bit is at least one qubit in the prefix portion qubits; The step of realizing objective function conversion control by a prefix partial quantum bit in the replica register based on the quantum bit control bit to obtain an objective function conversion circuit includes:

9. The method of claim 8, comprising, for each qubit in the target register, selecting at least one replicated prefix portion qubit from the replicated register to operate on the qubit of interest based on a qubit control bit that operates on the qubit of interest.

10. The step of performing inversion processing based on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, and the Gray path stage circuit to obtain an inversion processing stage circuit includes: performing an inversion process on the suffix duplication stage circuit, the Gray initialization stage circuit, the prefix duplication stage circuit, and the Gray path stage circuit respectively to obtain a corresponding inversion circuit of the suffix duplication stage circuit, a corresponding inversion circuit of the Gray initialization stage circuit, a corresponding inversion circuit of the prefix duplication stage circuit, and a corresponding inversion circuit of the Gray path stage circuit; and combining a corresponding inversion circuit of the suffix duplication stage circuit, a corresponding inversion circuit of the Gray initialization stage circuit, a corresponding inversion circuit of the prefix duplication stage circuit, and a corresponding inversion circuit of the Gray path stage circuit to obtain an inversion processing stage circuit.

11. The method comprises: The method further includes setting an auxiliary register in the quantum state preparation circuit based on the number of auxiliary quantum bits; The step of duplicating the prefix partial qubit in the input register based on the qubit duplication scheme and duplicating the prefix partial qubit to the duplication register to obtain a prefix duplication stage circuit includes: According to the qubit duplication scheme, duplicating a prefix partial qubit in the input register, duplicating the prefix partial qubit to the duplication register, and duplicating the prefix partial qubit to the auxiliary register to obtain a prefix duplication stage circuit; The step of performing a Gray path process using the prefix partial qubit in the replica register and the target register to obtain a Gray path stage circuit includes:

3. The method of claim 2, comprising performing a Gray path operation with a prefix partial qubit in the replica register, a prefix partial qubit in the auxiliary register, and the target register to obtain a Gray path stage circuit.

12. The step of performing a Gray path process using the prefix partial qubit in the replica register, the prefix partial qubit in the auxiliary register, and the target register to obtain a Gray path stage circuit includes: At each processing stage of the Gray path processing, realizing an objective function transformation matching the current processing stage on each quantum bit of the target register by the prefix partial quantum bit in the replica register and the prefix partial quantum bit in the auxiliary register to obtain a processing circuit of the current processing stage; and deriving a gray path stage circuit based on the processing circuitry of each processing stage in the gray path processing.

13. A quantum state preparation method executed by a quantum computer, the quantum state preparation method comprising: A quantum state preparation method comprising the steps of: performing quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, the quantum state preparation circuit being realized by a quantum state preparation circuit generation method according to any one of claims 1 to 12.

14. A quantum state preparation circuit generation device, the device comprising: A first setting module is used for setting an input register in the quantum state preparation circuit according to a circuit preparation parameter of the quantum state preparation circuit and determining a number of auxiliary quantum bits; a second setting module for setting a replica register and a target register in the quantum state preparation circuit according to the number of auxiliary quantum bits; A circuit construction module used to construct a circuit using the input register, the copy register, and the target register based on a quantum bit duplication scheme to obtain a diagonal unitary matrix quantum circuit, the quantum bit duplication scheme being obtained based on a grid restriction condition; a circuit combination module used for combining the diagonal unitary matrix quantum circuit and a one-bit quantum gate to obtain a uniform control gate circuit corresponding to the diagonal unitary matrix quantum circuit; a processing module adapted to generate the quantum state preparation circuit based on at least one of the uniform control gate circuits; The quantum state preparation circuit generation device, characterized in that the quantum bit duplication method includes performing column duplication on quantum bits under a grid restriction condition, obtaining a column duplication result, and performing row duplication based on the column duplication result.

15. 1. A quantum state preparation device, comprising: A quantum state preparation device including a preparation module used to perform quantum state preparation on circuit initial state data based on a quantum state preparation circuit to obtain quantum state data, wherein the quantum state preparation circuit is realized by a quantum state preparation circuit generation method described in any one of claims 1 to 12.

16. 14. A computing device comprising a memory and a processor, the memory having computer readable instructions stored therein, the processor implementing the method of any one of claims 1 to 13 when executing the computer readable instructions.

17. A computer program which, when executed by a processor, implements the method according to any one of claims 1 to 13.

18. A quantum device, the quantum device realizing a quantum state preparation circuit by the quantum state preparation circuit generation method according to any one of claims 1 to 12.

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