Semiconductor Device

Abstract

Provided is a semiconductor device that has a novel configuration. The semiconductor device comprises a plurality of arithmetic operation blocks each comprising an arithmetic operation circuit unit and a storage circuit unit. The arithmetic operation circuit unit and the storage circuit unit are electrically connected. The arithmetic operation circuit unit and the storage circuit unit have mutually overlapping regions. The arithmetic operation circuit unit includes a Si transistor, for example, and the storage circuit unit includes an OS transistor, for example. The arithmetic operation circuit unit has the function of performing a product-sum operation. The storage circuit unit has the function of holding weighting data. A first drive circuit has the function of writing the weighting data to the storage circuit unit. The first drive circuit is used to write weighting data to all storage circuit units included in the same row.

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in the present specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0004] Electronic devices having semiconductor devices including a CPU (Central Processing Unit) and the like are in widespread use. In order to process a large amount of data at high speed in such electronic devices, there has been active technological development to improve the performance of the semiconductor devices. One technology that achieves high performance is, for example, the application of the so-called SoC (System on Chip) technology, which tightly couples an accelerator such as a GPU (Graphics Processing Unit) with a CPU. In semiconductor devices that have high performance due to SoC, heat generation and increased power consumption become problems.

[0005] In AI (Artificial Intelligence) technology, the amount of calculations and the number of parameters become enormous, so the amount of calculations increases. Since the increase in the amount of calculations leads to an increase in heat generation and power consumption, architectures for reducing the amount of calculations have been actively proposed. Representative architectures include the Binary Neural Network (BNN) and the Ternary Neural Network (TNN), which are particularly effective in reducing circuit scale and power consumption (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2019 / 078924 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with a reduced occupation area.An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with improved arithmetic processing speed.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0008] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0009] (1) One embodiment of the present invention is a semiconductor device including a plurality of calculation blocks, each of which has an arithmetic circuit unit and a memory circuit unit, the arithmetic circuit unit having a first transistor, the memory circuit unit having a second transistor, the arithmetic circuit unit being electrically connected to the memory circuit unit, and the arithmetic circuit unit and the memory circuit unit having overlapping regions.

[0010] In (1), the arithmetic block may have a first drive circuit, a second drive circuit, and a third drive circuit. The first drive circuit, the second drive circuit, and the third drive circuit are electrically connected to the memory circuit section, and the arithmetic circuit section, the first drive circuit, the second drive circuit, and the third drive circuit are provided in a first layer. The memory circuit section is provided in a second layer. The first layer and the second layer have an overlapping area.

[0011] For example, the first driver circuit may have a function of supplying data to the memory circuit unit. The second driver circuit may have a function of controlling an operation of writing data to the memory circuit unit. The third driver circuit may have a function of controlling an operation of reading data from the memory circuit unit. The arithmetic circuit unit has a function of performing product-sum operations, and the memory circuit unit has a function of holding data. The data held by the memory circuit unit is, for example, weight data.

[0012] The first transistor is preferably a transistor including silicon as a semiconductor in which a channel is formed, and the second transistor is preferably a transistor including an oxide semiconductor as a semiconductor in which a channel is formed.

[0013] (2) Another aspect of the present invention is a semiconductor device having a plurality of calculation blocks arranged in a matrix of M rows and N columns (M and N are each natural numbers greater than or equal to 2) and N first drive circuits, wherein the N first drive circuits are arranged in each column, each of the plurality of calculation blocks has an arithmetic circuit unit and a memory circuit unit, the arithmetic circuit unit is electrically connected to the memory circuit unit, the arithmetic circuit unit and the memory circuit unit have overlapping areas, and the memory circuit unit arranged in the e-th column (e is a natural number greater than or equal to 1 and less than or equal to N) is electrically connected to the first drive circuit arranged in the e-th column.

[0014] In the above-mentioned configuration, the second driving circuit may be provided extending in the column direction. In the above-mentioned configuration, it is preferable that each of the plurality of arithmetic blocks has a third driving circuit.

[0015] The memory circuit portion preferably includes a plurality of memory cells, and each memory cell preferably includes a transistor including an oxide semiconductor as a semiconductor in which a channel is formed. Effect of the Invention

[0016] According to one embodiment of the present invention, a semiconductor device with a reduced occupation area, reduced power consumption, improved processing speed, or a novel semiconductor device can be provided.

[0017] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description of the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above. [Brief description of the drawings]

[0018] FIG. 1 is a top view showing the configuration of a semiconductor device. 2A and 2B are perspective views showing a configuration of a semiconductor device. FIG. 3 is a perspective view showing a configuration of the semiconductor device. Fig. 4A is a diagram for explaining the configuration of a processing block, and Fig. 4B and Fig. 4C are diagrams showing an example of the circuit configuration of a memory cell. 5A to 5C are diagrams showing examples of circuit configurations of memory cells. 6A and 6B are diagrams showing examples of circuit configurations of arithmetic circuits. FIG. 7 is a block diagram showing an example of the configuration of a computation system. Fig. 8A is a block diagram for explaining the sequence of the arithmetic processing, and Fig. 8B is a diagram for explaining the data flow in the arithmetic processing. Fig. 9A is a block diagram for explaining the sequence of the arithmetic processing, and Fig. 9B is a diagram for explaining the data flow in the arithmetic processing. Fig. 10A is a block diagram for explaining the sequence of the arithmetic processing, and Fig. 10B is a diagram for explaining the data flow in the arithmetic processing. FIG. 11 is a diagram showing a modified example of the semiconductor device. FIG. 12 is a diagram showing a modified example of the semiconductor device. FIG. 13 is a diagram showing a modified example of the semiconductor device. FIG. 14 is a diagram showing a modified example of the semiconductor device. FIG. 15 is a diagram showing a modified example of the semiconductor device. FIG. 16 is a diagram showing a modified example of the semiconductor device. FIG. 17 is a diagram showing a modified example of the semiconductor device. FIG. 18 is a diagram illustrating an example of the operation of the arithmetic processing system. FIG. 19 is a diagram illustrating an example of the configuration of a CPU. 20A and 20B are diagrams showing examples of circuit configurations of flip-flop circuits. FIG. 21 is a timing chart illustrating an example of the operation of the CPU. FIG. 22 is a diagram showing an example of the structure of a semiconductor device. 23A and 23B are diagrams showing configuration examples of transistors. 24A and 24B are diagrams showing configuration examples of an integrated circuit. 25A and 25B are diagrams showing an example of an application of an integrated circuit. 26A and 26B are diagrams showing an example of an application of an integrated circuit. 27A to 27C are diagrams for explaining an application example of an integrated circuit. FIG. 28 is a diagram showing an application example of an integrated circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the embodiment and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0020] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may have semiconductor devices.

[0021] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in the figure or text. X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0022] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The on and off states of the switch are controlled. In other words, the switch has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.

[0023] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0024] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0025] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished to determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0026] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0027] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be rephrased as "resistance", "load", "region having a resistance value", and the like, and conversely, the terms "resistance", "load", and "region having a resistance value" can be rephrased as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0028] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" refers not only to a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also to a parasitic capacitance occurring between wirings, a gate capacitance occurring between one of the source or drain of a transistor and the gate, and the like. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like can be rephrased as "capacitance", and conversely, the term "capacitance" can be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0029] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain can be used interchangeably. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode, or the first terminal) and "the other of the source or drain" (or the second electrode, or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0030] In this specification, the term "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as a "conductive state"), and the term "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as a "non-conductive state").

[0031] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0032] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on a circuit configuration, a device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0033] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0034] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is described as a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0035] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0036] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0037] In addition, the positional relationship of the components changes appropriately depending on the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, etc., and can be appropriately rephrased depending on the situation. For example, in this specification, etc., words and phrases indicating the arrangement, such as "above" and "below," may be used for convenience in order to explain the positional relationship of the components with reference to the drawings. Therefore, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing by 180 degrees. Also, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the left surface (or right surface) of the conductor" by rotating the orientation of the drawing by 90 degrees.

[0038] Similarly, in this specification and the like, the term "overlap" does not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state where "electrode B is formed on insulating layer A", but does not exclude the state where "electrode B is formed under insulating layer A" or "electrode B is formed on the right (or left) side of insulating layer A", etc.

[0039] In addition, in this specification, the terms "adjacent" and "close to" do not limit the components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0040] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0041] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wirings" are formed integrally. Furthermore, for example, "terminal" may be used as a part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wiring", "terminals", and the like are formed integrally. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0042] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0043] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of an impurity may cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and transition metals other than the main component, and in particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is silicon, the impurity that changes the characteristics of the semiconductor may be, for example, oxygen, and Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements, and the like.

[0044] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0045] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0046] An example of a mechanical switch is a switch that uses MEMS (Microelectromechanical Systems) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0047] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0048] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0049] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0050] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0051] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0052] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0053] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0054] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will easily understand that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in order to make the drawings easier to understand, the description of some components may be omitted in perspective views or top views.

[0055] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0056] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size and aspect ratio are not necessarily limited. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0057] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, "[m,n]”, etc. may be added to the symbol.

[0058] (Embodiment 1) A semiconductor device 100 according to an embodiment of the present invention will be described with reference to the drawings. In the drawings, arrows indicating the X, Y, and Z directions may be added. The X, Y, and Z directions are directions that intersect with each other. More specifically, the X, Y, and Z directions are directions that are perpendicular to each other. In this specification and the like, one of the X, Y, and Z directions may be called the "first direction" or "first direction". The other may be called the "second direction" or "second direction". The remaining one may be called the "third direction" or "third direction".

[0059] <Semiconductor device 100> Fig. 1 shows a top view of the semiconductor device 100. Fig. 2A shows a perspective view of the semiconductor device 100. The semiconductor device 100 has a function as an accelerator. Specifically, it has a function of executing a program (also called a kernel or a kernel program) called from a host program. The semiconductor device 100 can perform, for example, parallel processing of matrix operations in graphic processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations.

[0060] <Calculation block> The semiconductor device 100 has a plurality of operation blocks 200 arranged in a matrix of M rows and N columns (M and N are each natural numbers equal to or greater than 2). In Fig. 1, the operation block 200 in the first row and second column is indicated as operation block 200[1,2], and the operation block 200 in the Mth row and Nth column is indicated as operation block 200[M,N].

[0061] 2B shows a perspective view of the operation block 200. The operation block 200 has an operation circuit section 210, a write bit line drive circuit 220, a write word line drive circuit 240, a read word line drive circuit 230, and a memory circuit section 310.

[0062] The operation block 200 is configured using a plurality of transistors. As the semiconductors of the transistors included in the operation block 200, single crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used. Furthermore, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used.

[0063] Further, a high electron mobility transistor (HEMT) can be used as the transistor included in the operational block 200, and the HEMT may be made of gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like.

[0064] The semiconductor used in the transistor may be a stack of semiconductors. When the semiconductors are stacked, semiconductors having different crystal states may be stacked, or different semiconductor materials may be stacked.

[0065] The semiconductor device 100 also has a layer 110 and a layer 120. Fig. 3 shows a perspective view illustrating the configuration of the semiconductor device 100. The layer 110 and the layer 120 are provided to overlap in the Z direction. Although the present embodiment shows an example in which the layer 120 is provided on the layer 110, the layer 110 may be provided on the layer 120.

[0066] Since an oxide semiconductor has a band gap of 2 eV or more, a transistor including an oxide semiconductor in a semiconductor in which a channel is formed (also referred to as an "OS transistor") has an extremely low off-state current. For example, a transistor including silicon in a semiconductor in which a channel is formed (also referred to as an "Si transistor"), particularly a Si transistor including crystalline silicon in the semiconductor (also referred to as a "crystalline Si transistor"), can easily achieve a relatively high mobility compared to an OS transistor. On the other hand, it is difficult for a crystalline Si transistor to achieve an extremely low off-state current like an OS transistor.

[0067] Therefore, it is important to appropriately select a semiconductor material for use in a semiconductor in which a transistor channel is formed, depending on the purpose and / or application. For example, it is preferable to use an OS transistor in combination with a Si transistor or other transistors depending on the purpose and / or application.

[0068] In a semiconductor device 100 according to an embodiment of the present invention, the layer 110 includes, for example, Si transistors, and the layer 120 includes, for example, OS transistors. An arithmetic circuit unit 210, a write bit line driver circuit 220, a write word line driver circuit 240, and a read word line driver circuit 230, which are required to operate at a higher speed than a memory circuit, are provided in the layer 110. In addition, a memory circuit unit 310, which is required to have a smaller off-current rather than an operating speed, is provided in the layer 120.

[0069] By changing the semiconductor material used in a transistor depending on the purpose and / or application, it is possible to improve the operating speed (calculation processing speed) and reduce power consumption.

[0070] The layer 110 includes an arithmetic circuit section 210 with M rows and N columns. Therefore, the layer 110 may be called an "arithmetic circuit array." The layer 120 includes a memory circuit section 310 with M rows and N columns. Therefore, the layer 120 may be called a "memory array." The memory circuit section 310 may be called a "memory sub-array." By stacking the arithmetic circuit array and the memory array, the semiconductor device 100 can be made smaller. That is, by having an area where the arithmetic circuit section 210 and the memory circuit section 310 overlap each other, the semiconductor device 100 can be made smaller. Also, the area occupied by the semiconductor device 100 can be reduced.

[0071] 4A is a diagram for explaining the configuration of the operation block 200. The memory circuit section 310 has a plurality of memory cells 320 arranged in a matrix of P rows and Q columns (P and Q are each a natural number of 2 or more). Therefore, the memory array includes M×N×P×Q memory cells 320. Here, if R=M×P and S=N×Q, it can be said that the memory array has a plurality of memory cells 320 arranged in a matrix of R rows and S columns.

[0072] In FIG. 4A, the memory cell 320 in the first row and second column is indicated as memory cell 320[1,2], and the memory cell 320 in the Pth row and Qth column is indicated as memory cell 320[P,Q].

[0073] Moreover, the operation block 200 shown in FIG. 4A has P wires WWL and P wires RWL extending in the row direction, and Q wires WBL and Q wires RBL extending in the column direction.

[0074] The i-th (i is a natural number from 1 to P) wiring WWL and the i-th wiring RWL are electrically connected to the Q memory cells 320 arranged in the i-th row. The j-th (j is a natural number from 1 to Q) wiring WBL and the j-th wiring RBL are electrically connected to the P memory cells 320 arranged in the j-th column.

[0075] The memory cell 320 is electrically connected to the arithmetic circuit unit 210 via a wiring RBL. The memory cell 320 is also electrically connected to the write bit line driving circuit 220 via a wiring WBL. The memory cell 320 is also electrically connected to the read word line driving circuit 230 via a wiring RWL. The memory cell 320 is also electrically connected to the write word line driving circuit 240 via a wiring WWL.

[0076] It is not necessary to provide the arithmetic circuit unit 210 and the memory circuit unit 310 overlapping each other in all of the arithmetic blocks 200 included in the semiconductor device 100. Some of the arithmetic blocks 200 included in the semiconductor device 100 may include arithmetic blocks 200 in which the arithmetic circuit unit 210 and the memory circuit unit 310 do not overlap each other.

[0077] [Memory Cell] FIG. 4B shows an example of a circuit configuration that can be used for the memory cell 320. The memory cell 320 shown in FIG. 4B includes a transistor 321, a transistor 322, and a transistor 323. The gate of the transistor 321 is electrically connected to a wiring WWL. One of the source or drain of the transistor 321 is electrically connected to a wiring WBL, and the other is electrically connected to a gate of the transistor 322. One of the source or drain of the transistor 322 is electrically connected to a wiring that applies a fixed potential, such as a ground potential, and the other is electrically connected to one of the source or drain of the transistor 323. The other of the source or drain of the transistor 323 is electrically connected to a wiring RBL. The gate of the transistor 323 is electrically connected to a wiring RWL. A node where the other of the source or drain of the transistor 321 and the gate of the transistor 322 are electrically connected to each other functions as a node SN.

[0078] 4C, a capacitor 324 may be provided at the node SN. One electrode of the capacitor 324 is electrically connected to the gate (node ​​SN) of the transistor 322, and the other electrode is electrically connected to a wiring that applies a fixed potential, such as a ground potential.

[0079] It is preferable to use an OS transistor as the transistor 321. Since an oxide semiconductor has a band gap of 2 eV or more, the off-state current of an OS transistor is extremely small. Thus, charge supplied to the node SN can be held for a long period of time. In addition, the capacitance 324 can be reduced or omitted. Furthermore, the power consumption of the semiconductor device 100 can be reduced.

[0080] In addition, when an OS transistor is used as the transistor 321 and transistors other than OS transistors are used as the transistors 322 and 323 , the transistor 321 may be provided in the layer 120 , and the transistors 322 and 323 may be provided in the layer 110 .

[0081] Alternatively, OS transistors may be used as the transistors 321, 322, and 323. The off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range from room temperature to 200° C. or lower. The OS transistor has a high withstand voltage between the source and drain. By using an OS transistor, a semiconductor device with stable operation and high reliability even in a high-temperature environment can be realized. A memory including an OS transistor is also referred to as an "OS memory."

[0082] By using OS transistors for the transistors 321 , 322 , and 323 , the memory circuit portion 310 can be stacked directly over the arithmetic circuit portion 210 .

[0083] The circuit configuration examples shown in Figures 4B and 4C are circuit configurations of NOSRAM (registered trademark). "NOSRAM" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM." NOSRAM refers to a memory element in which the memory cell is a two-transistor type (2T) or three-transistor type (3T) gain cell, and the access transistor is an OS transistor. Therefore, NOSRAM is a type of OS memory.

[0084] NOSRAM can function as a non-volatile memory by using the extremely small off-current characteristic of OS transistors to hold a charge corresponding to data in the memory circuit (node ​​SN).In addition, since NOSRAM can read the held data without destroying it (non-destructive read), it is suitable for parallel processing of product-sum operations in neural networks that repeat data read operations many times, for example.

[0085] The data that can be held in the memory cell 320 is not limited to 1-bit data. The memory cell 320 can hold multiple-bit data (multi-level data) or analog data.

[0086] The circuit configuration that can be used for the memory cell 320 is not limited to the circuit configuration shown in Figures 4B and 4C. For example, a circuit equivalent to the DOSRAM shown in Figure 5A may be used. "DOSRAM" is a RAM having 1T1C type memory cells including OS transistors, and is an abbreviation for "Dynamic Oxide Semiconductor RAM." Therefore, DOSRAM is a type of OS memory.

[0087] Furthermore, the memory cells 320 may be flash memories, magnetoresistive RAMs (MRAMs), phase change RAMs (PRAMs), resistive RAMs (ReRAMs), ferroelectric RAMs (FeRAMs), or the like.

[0088] The memory cell 320A illustrated in FIG. 5A includes a transistor 321 and a capacitor 324. The transistor 321 illustrated in FIG. 5A is an OS transistor having a backgate. The memory cell 320A is electrically connected to a wiring BL, a wiring WWL, and a wiring BGL. The wiring BGL is electrically connected to the backgate of the transistor 321. The wiring BL may function as a wiring WBL or as a wiring RBL.

[0089] A circuit configuration that can be used for the memory cell 320 may be a circuit corresponding to a 2T-type NOSRAM shown in Fig. 5B. Fig. 5B illustrates a memory cell 320B having a transistor 321, a transistor 322, and a capacitor 324. The transistors 321 and 322 shown in Fig. 5B are OS transistors. The transistors 321 and 322 may be OS transistors in which their semiconductor layers are arranged in different layers, or may be OS transistors in which their semiconductor layers are arranged in the same layer.

[0090] The memory cell 320B is electrically connected to the wiring WBL, the wiring RBL, the wiring WWL, the wiring RWL, the wiring SL, and the wiring BGL. The wiring BGL is electrically connected to the backgate of the transistor 321. In the memory cell 320B, one electrode of the capacitor 324 is electrically connected to the gate of the transistor 322, and the other electrode is electrically connected to the wiring RWL. One of the source and drain of the transistor 322 is electrically connected to the wiring RBL, and the other electrode is electrically connected to the wiring SL.

[0091] A circuit configuration applicable to the memory cell 320 may be a circuit combining 3T-type NOSRAMs as shown in Fig. 5C. Fig. 5C illustrates a memory cell 320C having a memory cell 320P and a memory cell 320N that can hold data of different logic. Each transistor in the memory cell 320C is an OS transistor.

[0092] The memory cell 320P is electrically connected to the wiring WBL_P, the wiring RBL_P, the wiring WWL, and the wiring RWL. The memory cell 320N is electrically connected to the wiring WBL_N, the wiring RBL_N, the wiring WWL, and the wiring RWL. The memory cell 320P includes a transistor 321P, a transistor 322P, a transistor 323P, and a capacitor 324P, and can hold data (charge) supplied to the node SNP for a long period of time. The memory cell 320N includes a transistor 321N, a transistor 322N, a transistor 323N, and a capacitor 324N, and can hold data (charge) supplied to the node SNN for a long period of time.

[0093] The semiconductor layers of the transistors in the memory cell 320C may be arranged in different layers, or may all be arranged in the same layer. Also, multiple semiconductor layers may be arranged in the same layer.

[0094] Moreover, the memory cell 320C can hold data of different logic in the nodes SNP and SNN, and can read out the held data via the wirings RBL_P and RBL_N.

[0095] In the configuration of FIG. 5C, an exclusive OR circuit (XOR circuit) may be provided so that data equivalent to the multiplication of data held in the memory cell 320P and the memory cell 320N is output to the wiring RBL (not shown in FIG. 5C). With this configuration, it is possible to omit an operation equivalent to the multiplication in the arithmetic circuit unit 210. As a result, the power consumption of the semiconductor device can be reduced.

[0096] [Arithmetic circuit] An arithmetic circuit for performing various arithmetic processes such as a product-sum operation, a pooling operation, a normalization operation, and an activation operation can be applied to the arithmetic circuit unit 210. A plurality of arithmetic circuits can be provided in the arithmetic circuit unit 210. Also, a plurality of types of arithmetic circuits can be provided in the arithmetic circuit unit 210. Fig. 6A shows an example of a circuit configuration of an arithmetic circuit 211 that can be applied to the arithmetic circuit unit 210. Fig. 6A shows an example of a circuit configuration that can perform a product-sum operation of 8-bit weight data W and 8-bit input data A.

[0097] The arithmetic circuit 211 shown in FIG. 6A includes a multiplication circuit 24, an addition circuit 25, and a register 26. Among the multiple weight data W, the selected weight data W SEL and input data A IN is multiplied by the multiplication circuit 24 to produce 16-bit data D M and input to the adder circuit 25. In the adder circuit 25, the data D M The data D held in the register 26 is R is added, and new data D R At this time, the new data D R The number of digits in the data may be 17 bits. Each time the above multiplication and addition are repeated, new data D R The number of digits of the weight data W may increase. Therefore, in FIG. 6A, "17+α" is written on the output of the adder circuit 25 to indicate the number of digits of the data. "α" indicates a carry that occurs when the multiplied data is added. In this way, the weight data W SEL and input data A IN Output data D corresponding to the multiplication and accumulation operation MAC The register 26 is controlled by a clock signal CLK and a reset signal reset_B.

[0098] In FIG. 6A, a circuit configuration for performing arithmetic processing using 8-bit data has been described. The arithmetic circuit 211 shown in FIG. 6A can also be applied to arithmetic processing using 1-bit data. The circuit configuration is illustrated in FIG. 6B in the same manner as in FIG. 6A. SEL and input data AIN When is 1-bit data, the data D generated by the multiplication circuit 24 is M becomes 1-bit data. The other calculation processes are the same as those described above, so further explanation will be omitted.

[0099] In addition, in the semiconductor device 100 according to one embodiment of the present invention, the weight data W used in the product-sum calculation process is held in the memory circuit unit 310 provided to overlap the arithmetic circuit unit 210. Therefore, the wiring RBL used to read the weight data W can be shortened, and therefore the wiring resistance and parasitic capacitance are reduced, enabling high-speed reading of the weight data W. In addition, the power consumption required to read the weight data W can be reduced.

[0100] Furthermore, the semiconductor device 100 according to an aspect of the present invention has the read word line driving circuit 230 for each operation block 200, and therefore the weight data W can be read at even higher speed.

[0101] Furthermore, the semiconductor device 100 according to one aspect of the present invention has the write bit line drive circuit 220 and the write word line drive circuit 240 for each operation block 200, and therefore, high speed writing of the weight data W can be realized.

[0102] <Calculation processing system> FIG. 7 shows a block diagram of a processing system 1000 including a semiconductor device 100 that functions as an AI accelerator.

[0103] 7 includes the semiconductor device 100, a CPU 400, a bus 410, a control device 150, and a storage device 160. The system may also include a main storage device 420, an auxiliary storage device 430, an input / output device 440, and the like. The control device 150, the main storage device 420, the auxiliary storage device 430, the input / output device 440, and the like are electrically connected to the CPU 400 via the bus 410.

[0104] The CPU 400 has a CPU core 401 and a backup circuit 402. As described above, the semiconductor device 100 has a plurality of operation blocks 200, but one operation block 200 is shown in FIG.

[0105] CPU 400 has the function of performing general-purpose processing such as running an operating system, controlling data, performing various calculations, and running programs. CPU 400 has CPU core 401. CPU core 401 corresponds to one or more CPU cores. CPU 400 also has backup circuit 402 that can retain data in CPU core 401 even if the supply of power supply voltage is stopped. The supply of power supply voltage can be controlled by electrically disconnecting it from the power supply domain using a power switch or the like. The power supply voltage is sometimes called a drive voltage.

[0106] As the backup circuit 402, for example, an OS memory having OS transistors is preferably used. The backup circuit 402 made up of OS transistors can be stacked with the CPU core 401 which can be made up of Si transistors. Since the area of ​​the backup circuit 402 is smaller than the area of ​​the CPU core 401, the backup circuit 402 can be arranged on the CPU core 401 without increasing the circuit area. The backup circuit 402 has a function of holding data in a register of the CPU core 401. The backup circuit 402 is also called a data holding circuit. Details of the configuration of the CPU 400 including the backup circuit 402 having OS transistors will be described in the third embodiment.

[0107] The control device 150 has a function of controlling the operation of the semiconductor device 100 functioning as an AI accelerator. For example, the control device 150 has a function of supplying the semiconductor device 100 with a signal that controls the writing and reading of weight data W. The control device 150 also has a function of providing the semiconductor device 100 with input data A and causing the semiconductor device 100 to execute a product-sum operation of a neural network or the like. The control device 150 is electrically connected to the CPU 400 via a bus 410. Thus, the semiconductor device 100 is electrically connected to the CPU 400 via the bus 410.

[0108] The storage device 160 also has a function of holding output data obtained by the semiconductor device 100, such as the product-sum operation results of the neural network. As the storage device 160, a dynamic random access memory (DRAM), a static random access memory (SRAM), an OS memory, or the like can be used.

[0109] The main memory 420 has a function of storing programs and parameters related to the operation of the arithmetic processing system 1000, and is preferably at least partially rewritable memory. For example, the main memory 420 can include a volatile memory such as a random access memory (RAM) and a non-volatile memory such as a read only memory (ROM). The main memory 420 may be an OS memory.

[0110] The auxiliary storage device 430 is a storage device for storing an operating system, application programs, various data, etc. In addition, various parameters used by the CPU 400 and the semiconductor device 100 may also be stored therein.

[0111] The auxiliary storage device 430 may be, for example, a storage device using a non-volatile storage element such as a flash memory, MRAM, PRAM, ReRAM, or FeRAM, or a storage device using a volatile storage element such as a DRAM and / or SRAM. Also, a recording media drive such as a hard disk drive (HDD) and / or a solid state drive (SSD) may be used.

[0112] Also, for example, the auxiliary storage device 430 may be a storage device such as an HDD or SSD that is removable via the input / output device 440. Also, a media drive for a recording medium such as a flash memory, a Blu-ray disc, or a DVD may be used as the auxiliary storage device 430.

[0113] The input / output device 440 has a function of controlling input / output of signals between an external device and the arithmetic processing system 1000. Furthermore, an HDMI (registered trademark) terminal, a USB terminal, a terminal for connecting to a LAN (Local Area Network), or the like may be used as an external port of the input / output device 440. Furthermore, the input / output device 440 may have a transmission / reception function for optical communication using infrared rays, visible light, ultraviolet rays, or the like.

[0114] [Example of arithmetic processing] An example of the computation process of the convolutional neural network is shown using Figures 8A and 8B. Figure 8A is a block diagram explaining the sequence of the computation process. Figure 8B is a diagram explaining the data flow (flow of input data A and weight data W) of the sequence shown in Figure 8A. Figure 8B shows the data flow between the memory circuit unit 310, the computation circuit unit 210, and the storage device 160.

[0115] 8A shows an input layer 90A, an intermediate layer (also called a hidden layer) 90B, and an output layer 90C. The input layer 90A shows an input data input process 92 (illustrated as "Input"). The intermediate layer 90B shows a convolution operation process 93, a convolution operation process 94, a convolution operation process 96 (illustrated as "Conv.1", "Conv.2", "Conv.3"), a pooling operation process 95, and a pooling operation process 97 (illustrated as "Pool.1", "Pool.2"). The output layer 90C shows a full connection operation process 98 (illustrated as "Full").

[0116] First, a weight data initialization process 91 (indicated as "W-Ini." in the figure) is performed. In the weight data initialization process 91, the weight data W1 to W4 held in the main storage device 420 or the auxiliary storage device 430 are written to the memory circuit unit 310 of the calculation block 200 via the control device 150.

[0117] Next, input processing 92 is performed. In the input processing 92, data A0 held in the main storage device 420 or the auxiliary storage device 430 is processed to generate data A1 for performing the convolution operation processing 93. The data A1 is held in the storage device 160. Note that data held in the storage device 160 may be used as the data A0.

[0118] Next, convolution calculation processing 93 is performed. In the convolution calculation processing 93, a multiply-accumulate process (MAC) is performed using the weight data W1 and the data A1 to generate data A2. Specifically, the data A1 is read from the storage device 160, and input to the calculation block 200 in which the weight data W1 is written, and the multiply-accumulate process is performed in the calculation block 200. The obtained data A2 is held in the storage device 160.

[0119] Next, a convolution operation 94 is performed. In the convolution operation 94, a multiply-and-accumulate operation is performed using the weight data W2 and the data A2 to generate data A3. As in the convolution operation 93, the data A2 is read from the storage device 160, and input to the operation block 200 in which the weight data W2 has been written, and the multiply-and-accumulate operation is performed in the operation block 200. The obtained data A3 is stored in the storage device 160.

[0120] Next, a pooling operation process 95 is performed. When the pooling operation process 95 is performed, the data A3 obtained by the convolution operation process 94 may be directly subjected to the pooling operation process without going through the storage device 160. In the pooling operation process 95, the data A3 obtained by the convolution process is compressed and transformed into data that is easier to handle (down sampling). The pooling operation process may be performed by maximum pooling. Alternatively, average pooling, Lp pooling, or the like may be used as the pooling operation process. Data A4 is generated by the pooling operation process 95. The obtained data A4 is stored in the storage device 160.

[0121] Next, a convolution operation 96 is performed. In the convolution operation 96, a multiply-and-accumulate operation is performed using the weight data W3 and the data A4 to generate data A5. As in the convolution operation 94, the data A4 is read from the storage device 160 and input to the operation block 200 in which the weight data W3 has been written, and the multiply-and-accumulate operation is performed in the operation block 200. The obtained data A5 is stored in the storage device 160.

[0122] Next, a pooling operation process 97 is performed. When the pooling operation process 97 is performed, the data A5 obtained in the convolution operation process 96 may be directly subjected to the pooling operation process without going through the storage device 160. In the pooling operation process 97, a pooling operation process is performed on the data A5 to generate data A6. The obtained data A6 is held in the storage device 160. The generated data A6 is data from which the feature amount of the data A0 is extracted.

[0123] Next, a full connection calculation process 98 is performed. Data A6 is data from which the features of data A0 have been extracted, and therefore cannot be classified or identified as is. In the full connection calculation process 98, a product-sum calculation process is performed using weight data W4 and data A6 to generate data A7. For example, by using a softmax function, data A7 can be converted into the probability of being correctly classified into each category.

[0124] The flow of the calculation process in the input layer 90A, the intermediate layer 90B, and the output layer 90C is an example, and in the actual calculation process of a convolutional neural network, other calculation processes may be performed.

[0125] Furthermore, in the arithmetic processing system 1000 including the semiconductor device 100, when performing arithmetic processing of the convolutional neural network for the second or subsequent time, it is not necessary to perform the weight data initialization process 91 again. Therefore, the power consumption and processing time required for the weight data initialization process 91 can be reduced.

[0126] The semiconductor device 100 according to an embodiment of the present invention can write and hold all weight data W used in the arithmetic processing of the convolutional neural network in the memory array (the memory circuit unit 310). The semiconductor device 100 according to an embodiment of the present invention can realize high-speed arithmetic processing because it is not necessary to write the weight data W every time a product-sum arithmetic processing (such as a convolution arithmetic processing) is performed.

[0127] When large weight data is supplied to the arithmetic circuit array (arithmetic circuit unit 210) via the bus 410, it is necessary to widen the bandwidth of the bus 410. If the connection via the bus 410 is considered to be a one-dimensional connection, the semiconductor device 100 according to an embodiment of the present invention can realize a two-dimensional connection because the arithmetic circuit unit 21 and the memory circuit unit 310 are provided overlapping each other. That is, the semiconductor device 100 according to an embodiment of the present invention can easily widen the bandwidth. Furthermore, the semiconductor device 100 according to an embodiment of the present invention can easily increase the number of parallel arithmetic circuits.

[0128] 9A and 9B, a weight data initialization process 99 may be performed during the convolution calculation process 96 to rewrite the contents of the memory circuit unit 310 to which the data W1 has been written, with the data W4. As described above, the weight data W is written at a high speed in the semiconductor device 100 according to one embodiment of the present invention. Therefore, even in the calculation process shown in FIG. 9A and FIG. 9B, high-speed calculation can be achieved.

[0129] Moreover, since the data W4 is used in the full connection calculation process 98, the weight data initialization process 99 only needs to be completed before the start of the full connection calculation process 98. Figures 10A and 10B show a sequence and data flow when the weight data initialization process 99 is performed during the execution of the pooling calculation process 97.

[0130] The sequences shown in FIGS. 9 and 10 are effective when the total capacity of the weight data W (in this embodiment, the total of the weight data W1 to W4) is larger than the storage capacity of the memory array.

[0131] The semiconductor device 100 according to one embodiment of the present invention is not limited to the arithmetic processing of a convolutional neural network, but can also perform various other arithmetic processing.

[0132] <Modification 1 of the semiconductor device> 11 shows a top view of the semiconductor device 100A. The semiconductor device 100A is a modified example of the semiconductor device 100. In order to reduce repetition of explanation, differences between the semiconductor device 100A and the semiconductor device 100 will be mainly described.

[0133] The semiconductor device 100A has a plurality of operation blocks 200A arranged in a matrix of M rows and N columns (M and N are each a natural number of 2 or more). As in the operation block 200A shown in FIG. 11, the write word line drive circuit 240 and the read word line drive circuit 230 may be arranged to face each other with a memory circuit unit 310 in between.

[0134] <Modification 2 of Semiconductor Device> 12 shows a top view of the semiconductor device 100B. The semiconductor device 100B is a modified example of the semiconductor device 100. In order to reduce repetition of explanation, differences between the semiconductor device 100B and the semiconductor device 100 will be mainly described.

[0135] The semiconductor device 100B has an operation block array 290 including a plurality of operation blocks 200B arranged in a matrix of M rows and N columns (M and N are each natural numbers greater than or equal to 2), a write word line driving circuit 240A, and N write bit line driving circuits 220A.

[0136] The operation block 200B has an operation circuit section 210, a read word line drive circuit 230, and a memory circuit section 310. The operation block 200B has a configuration in which the write bit line drive circuit 220A and the write word line drive circuit 240 are excluded from the operation block 200.

[0137] Similarly to the semiconductor device 100, the memory circuit unit 310 has memory cells 320 arranged in P rows and Q columns. Thus, the memory array of the semiconductor device 100B includes memory cells 320 arranged in R rows and S columns. In Fig. 12, the memory cell 320 arranged in the Rth row and Sth column is indicated as memory cell 320[R,S]. Note that memory cell 320[R,S] corresponds to memory cell [P,Q] in the operation block 200B[M,N].

[0138] The write word line driving circuit 240A is provided outside the operation block array 290. The write word line driving circuit 240A extends in the column direction and is electrically connected to R wirings WWL extending in the row direction (Y direction). The gth wiring WWL (g is a natural number between 1 and R) is electrically connected to S memory cells 320 arranged in the gth row.

[0139] The write word line driving circuit 240A has a function of controlling the write operation of all the operation blocks 200B included in the semiconductor device 100B. For example, it has a function of controlling the operation of writing weight data W to the memory circuit unit 310 in the operation block 200B. By providing the write word line driving circuit 240A, it is possible to reduce the number of M×N write word line driving circuits 240 included in the semiconductor device 100. The semiconductor device 100B can occupy an even smaller area than the semiconductor device 100.

[0140] 12, N write bit line driving circuits 220A are provided outside the operation block array 290. Each of the write bit line driving circuits 220A extends in the row direction (X direction). The N write bit line driving circuits 220A are arranged in series in the row direction. Each of the write bit line driving circuits 220A is arranged in each column of the operation block 200B.

[0141] 12, the write bit line driving circuit 220A arranged in the first position (first column) is indicated as "write bit line driving circuit 220A[1]," the write bit line driving circuit 220A arranged in the Nth position (Nth column) is indicated as "write bit line driving circuit 220A[N]," and the write bit line driving circuit 220A arranged in the eth position (eth column) (e is a natural number between 1 and N) is indicated as "write bit line driving circuit 220A[e]."

[0142] In FIG. 12, the processing block 200B in the 1st row, eth column is indicated as "processing block 200B[1,e]", and the processing block 200B in the Mth row, eth column is indicated as "processing block 200B[M,e]".

[0143] The write bit line driving circuit 220A[e] is electrically connected to the operation block 200B arranged in the e-th column through Q wirings WBL extending in the column direction (Y direction). In other words, the write bit line driving circuit 220A[e] is electrically connected to the memory circuit unit 310 of each of the operation blocks 200B arranged in the e-th column. More precisely, the j-th wiring WBL among the Q wirings WBL electrically connected to the write bit line driving circuit 220A[e] is electrically connected to the j-th memory cell 320 included in the memory circuit unit 310 of each of the operation blocks 200B arranged in the e-th column. That is, the j-th wiring WBL electrically connected to the write bit line driving circuit 220A[e] is electrically connected to the memory cell 320[1,j] to the memory cell 320[P,j] included in each of the operation blocks 200B[1,e] to 200B[M,e].

[0144] The write bit line driving circuit 220A[e] has a function of supplying data to all the operation blocks 200B arranged in the e-th column. For example, it has a function of supplying weight data W to all the memory circuit units 310 arranged in the e-th column. By providing the write bit line driving circuit 220A, it is possible to reduce the number of M×N write bit line driving circuits 220 included in the semiconductor device 100. The semiconductor device 100B can occupy an even smaller area than the semiconductor device 100.

[0145] The semiconductor device 100B can occupy a smaller area than the semiconductor device 100. On the other hand, the time required to write the weight data W is longer than that of the semiconductor device 100. However, as described with reference to FIG. 8, when the weight data W is written only once at the beginning of the arithmetic processing, even if the time required to write the weight data W is somewhat long, the proportion of the total arithmetic processing time taken by the weight data W may be small. In such a case, it is preferable to use the configuration of the semiconductor device 100B.

[0146] <Modification 3 of the semiconductor device> 13 shows a top view of the semiconductor device 100C. The semiconductor device 100C is a modification of the semiconductor device 100B. The write word line driver circuit 240A may be provided inside the operation block array 290, as in the semiconductor device 100C.

[0147] When the write word line driving circuit 240A is provided inside the operation block array 290, it is preferable to provide it at or near the center of the N columns of operation blocks 200B. For example, when N is an even number, it is preferable to provide it between the N / 2th column operation block 200B and the (N / 2)+1th column operation block 200B. When N is an odd number, it is preferable to provide it between the (N / 2)-0.5th column operation block 200B and the (N / 2)+0.5th column operation block 200B. Alternatively, it is preferable to provide the write word line driving circuit 240A adjacent to the operation block 200B in the range of the N×0.4th column or more and the N×0.6th column or less.

[0148] By providing the write word line driving circuit 240A at or near the center of the operation block array 290, the maximum connection distance between the write word line driving circuit 240A and the operation block 200B is shortened. Therefore, the maximum connection distance between the write word line driving circuit 240A and the memory cell 320 is shortened. By shortening the maximum connection distance, effects such as reduced power consumption, improved operating speed, reduced variation, and improved reliability can be obtained.

[0149] <Modification 4 of the semiconductor device> 14 shows a top view of the semiconductor device 100D. The semiconductor device 100D is a modification of the semiconductor device 100B. The write bit line driver circuit 220A may be provided inside the operation block array 290, as in the semiconductor device 100D.

[0150] When the write bit line driving circuit 220A is provided inside the operation block array 290, it is preferable to provide it in the center or near the center of the M rows of operation blocks 200B. For example, when M is an even number, it is preferable to provide it between the operation block 200B in the M / 2th row and the operation block 200B in the (M / 2)+1th row. When M is an odd number, it is preferable to provide it between the operation block 200B in the (M / 2)-0.5th row and the operation block 200B in the (M / 2)+0.5th row. Alternatively, it is preferable to provide the write bit line driving circuit 220A adjacent to the operation block 200B in the range of the M×0.4th row or more and the M×0.6th row or less.

[0151] By providing the write bit line driving circuit 220A at or near the center of the operation block array 290, the maximum connection distance between the write bit line driving circuit 220A and the operation block 200B is shortened. Therefore, the maximum connection distance between the write bit line driving circuit 220A and the memory cell 320 is shortened. By shortening the maximum connection distance, effects such as reduced power consumption, improved operating speed, reduced variation, and improved reliability can be obtained.

[0152] <Modification 5 of the semiconductor device> 15 shows a top view of the semiconductor device 100E. The semiconductor device 100E is a modified example of the semiconductor device 100B. In order to reduce repetition of explanation, the following mainly describes the differences between the semiconductor device 100E and the semiconductor device 100B.

[0153] The semiconductor device 100E has an operation block array 290 including a plurality of operation blocks 200C arranged in a matrix of M rows and N columns (M and N are each a natural number of 2 or more), a write word line drive circuit 240A, a read word line drive circuit 230A, and N write bit line drive circuits 220A. Similarly to the semiconductor device 100B, the memory array in the semiconductor device 100E also includes memory cells 320 arranged in a matrix of R rows and S columns.

[0154] The operation block 200C includes an operation circuit section 210 and a memory circuit section 310. The operation block 200C has a configuration in which the read word line driving circuit 230 is removed from the operation block 200B.

[0155] The read word line driving circuit 230A, like the write word line driving circuit 240A, is provided outside the operation block array 290. The read word line driving circuit 230A extends in the column direction and is electrically connected to R wirings RWL extending in the row direction. The gth wiring RWL is electrically connected to S memory cells 320 arranged in the gth row.

[0156] The read word line driving circuit 230A has a function of controlling the read operation of all the operation blocks 200C included in the semiconductor device 100E. For example, it has a function of controlling the operation of reading the weight data W from the memory circuit unit 310 in the operation block 200C. By providing the read word line driving circuit 230A, it is possible to reduce the M×N read word line driving circuits 230 included in the semiconductor device 100B. The semiconductor device 100E can occupy an even smaller area than the semiconductor device 100B.

[0157] <Semiconductor Device Modification 6> Fig. 16 shows a top view of a semiconductor device 100F. The semiconductor device 100F is a modified example of the semiconductor device 100E. As in the semiconductor device 100F shown in Fig. 16, the write word line drive circuit 240A and the read word line drive circuit 230A may be provided facing each other with the operation block array 290 in between.

[0158] <Seventh Modification of Semiconductor Device> 17 shows a top view of a semiconductor device 100G. The semiconductor device 100G is a modification of the semiconductor device 100E. As in the semiconductor device 100G, the write word line drive circuit 240A and the read word line drive circuit 230A may be provided inside the operation block array 290.

[0159] When the write word line driving circuit 240A and the read word line driving circuit 230A are provided inside the operation block array 290, it is preferable to provide them at or near the center of the N columns of operation blocks 200C. For example, when N is an even number, it is preferable to provide them between the N / 2th column operation block 200C and the (N / 2)+1th column operation block 200C. When N is an odd number, it is preferable to provide them between the (N / 2)-0.5th column operation block 200C and the (N / 2)+0.5th column operation block 200C. Alternatively, it is preferable to provide the write word line driving circuit 240A adjacent to the operation block 200C in the range of the N×0.4th column or more and the N×0.6th column or less.

[0160] By providing the write word line driving circuit 240A and the read word line driving circuit 230A at or near the center of the operation block array 290, the maximum connection distance between the write word line driving circuit 240A and the read word line driving circuit 230A and the operation block 200C is shortened. Therefore, the maximum connection distance between the write word line driving circuit 240A and the read word line driving circuit 230A and the memory cells 320 is shortened. By shortening the maximum connection distance, effects such as reduced power consumption, improved operating speed, reduced variation, and improved reliability can be obtained.

[0161] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0162] (Embodiment 2) In this embodiment, an example of an operation will be described in the case where a part of the calculations of a program executed by the CPU 400 described in the above embodiment is executed by the semiconductor device 100 functioning as an accelerator.

[0163] FIG. 18 is a diagram for explaining an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator (semiconductor device 100).

[0164] First, the host program is executed by the CPU (host program execution: step S1).

[0165] When the CPU confirms an instruction to reserve an area for data required for performing calculations using the accelerator in the memory circuit unit (memory circuit unit 310) (memory reservation instruction: step S2), the CPU reserves the area for data in the memory circuit unit (memory reservation: step S3).

[0166] Next, the CPU transmits weight data, which is input data, from the main memory or an external storage device to the memory circuit unit (data transmission: step S4). The memory circuit unit receives the weight data and stores the weight data in the area secured in step S2 (data reception: step S5).

[0167] When the CPU confirms an instruction to start the kernel program (start of kernel program: step S6), the accelerator starts executing the kernel program (start of operation: step S7).

[0168] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state performing calculations to a PG (power gating) state (PG state transition: step S8). In this case, the CPU is switched from the PG state to a state performing calculations immediately before the accelerator finishes executing the kernel program (PG state stop: step S9). By putting the CPU into the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the entire calculation processing system.

[0169] When the accelerator finishes the execution of the kernel program, the output data is stored in a storage unit that holds the calculation results in the accelerator (end of calculation: step S10).

[0170] After the execution of the kernel program is completed, if the CPU confirms an instruction to transmit the output data stored in the memory unit to the main memory or an external storage device (data transmission request: step S11), the output data is transmitted to the main memory or the external storage device and stored in the main memory or the external storage device (data transmission: step S12).

[0171] By repeating the above operations from step S1 to step S14, it is possible to suppress the power consumption and heat generation of the CPU and the accelerator, while allowing the accelerator to execute part of the calculations executed by the CPU. The semiconductor device according to one embodiment of the present invention has a non-von Neumann architecture, and can perform calculation processing with extremely low power consumption compared to a von Neumann architecture in which power consumption increases as the processing speed increases.

[0172] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0173] (Embodiment 3) In this embodiment, an example of a CPU having a CPU core capable of power gating will be described.

[0174] 19 shows an example of the configuration of a CPU 400. The CPU 400 includes a CPU core 401, an L1 (level 1) cache memory device (L1 Cache) 403, an L2 cache memory device (L2 Cache) 404, a bus interface unit (Bus I / F) 405, power switches 491 to 493, and a level shifter (LS) 494. The CPU core 401 includes a flip-flop 480.

[0175] The CPU core 401, the L1 cache memory device 403, and the L2 cache memory device 404 are interconnected via a bus interface unit 405.

[0176] The PMU 193 generates a clock signal GCLK1 and various PG (power gating) control signals in response to interrupt signals (Interrupts) input from outside and signals such as a signal SLEEP1 issued by the CPU 400. The clock signal GCLK1 and the PG control signals are input to the CPU 400. The PG control signals control the power switches 491 to 493 and the flip-flop 480.

[0177] Power switches 491 and 492 respectively control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line). A power switch 493 controls the supply of a voltage VDDH to a level shifter 494. A voltage VSSS is input to the CPU 400 and the PMU 193 without passing through a power switch. A voltage VDDD is input to the PMU 193 without passing through a power switch.

[0178] The voltages VDDD and VDD1 are drive voltages for the CMOS circuits. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is a drive voltage for the OS transistors and is higher than the voltage VDDD.

[0179] Each of the L1 cache memory device 403, the L2 cache memory device 404, and the bus interface unit 405 has at least one power domain that can be power-gated. The power domain that can be power-gated is provided with one or more power switches. These power switches are controlled by a PG control signal.

[0180] The flip-flop 480 is used as a register. A backup circuit is provided in the flip-flop 480. The flip-flop 480 will be described below.

[0181] 20A shows an example of the circuit configuration of a flip-flop 480. The flip-flop 480 has a scan flip-flop 481 and a backup circuit 402. FIG 20B is a perspective view showing an example of the circuit configuration of the flip-flop 480.

[0182] The scan flip-flop 481 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 481A.

[0183] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 481A. Analog switches of scan flip-flop 481 are connected to nodes CK1 and CKB1 of clock buffer circuit 481A. Node RT is an input node for a reset signal.

[0184] A signal SCE is a scan enable signal, and is generated by the PMU 193. The PMU 193 generates signals BK and RC. A level shifter 494 level-shifts the signals BK and RC to generate signals BKH and RCH. The signal BK is a backup signal, and the signal RC is a recovery signal.

[0185] The circuit configuration of the scan flip-flop 481 is not limited to that shown in Fig. 20. Flip-flops available in a standard circuit library can be applied.

[0186] The backup circuit 402 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitive element C11.

[0187] The node SD_IN is an input node for scan test data, and is connected to the node Q1 of the scan flip-flop 481. The node SN11 is a storage node of the backup circuit 402. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0188] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0189] The transistors M11 to M13 are OS transistors, similar to the transistors 321 to 323 included in the memory cell 320 described above. The transistors M11 to M13 each have a back gate. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0190] At least the transistors M11 and M12 are preferably OS transistors. The characteristic of OS transistors is that the off-state current is extremely small, which can suppress a drop in the voltage of the node SN11 and consumes almost no power to retain data, so that the backup circuit 402 has nonvolatile characteristics. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 402 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and data can be written and read with low energy.

[0191] It is highly preferable that all the transistors in the backup circuit 402 are OS transistors. As shown in Fig. 20B, the backup circuit 402 can be stacked on a scan flip-flop 481 that is configured with a silicon CMOS circuit.

[0192] Since the backup circuit 402 has a very small number of elements compared to the scan flip-flop 481, there is no need to change the circuit configuration and layout of the scan flip-flop 481 in order to stack the backup circuit 402. In other words, the backup circuit 402 is a highly versatile backup circuit. In addition, since the backup circuit 402 can be provided in the region in which the scan flip-flop 481 is formed, the area overhead of the flip-flop 480 can be reduced to zero even if the backup circuit 402 is incorporated. Therefore, by providing the backup circuit 402 in the flip-flop 480, power gating of the CPU core 401 becomes possible. Since little energy is required for power gating, the CPU core 401 can be power gated with high efficiency.

[0193] By providing backup circuit 402, a parasitic capacitance due to transistor M11 is added to node Q1, but since it is small compared with the parasitic capacitance due to the logic circuit connected to node Q1, it does not affect the operation of scan flip-flop 481. In other words, even if backup circuit 402 is provided, the performance of flip-flop 480 does not substantially deteriorate.

[0194] For example, a clock gating state, a power gating state, or a pause state can be set as the low power consumption state of the CPU core 401. The PMU 193 selects the low power consumption mode of the CPU core 401 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operation state to a clock gating state, the PMU 193 stops generation of the clock signal GCLK1.

[0195] For example, when transitioning from a normal operation state to a hibernation state, the PMU 193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 193 turns off the power switch 491 and turns on the power switch 492 to input the voltage VDD1 to the CPU core 401. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 481. When performing frequency scaling, the PMU 193 reduces the frequency of the clock signal GCLK1.

[0196] When the CPU core 401 is transitioned from a normal operation state to a power gating state, an operation is performed to back up the data of the scan flip-flop 481 in the backup circuit 402. When the CPU core 401 is returned from the power gating state to the normal operation state, an operation is performed to recover the data of the backup circuit 402 to the scan flip-flop 481.

[0197] Fig. 21 is a timing chart for explaining an example of a power gating sequence of the CPU core 401. In Fig. 21, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 491 to 493, and are generated by the PMU 193. When the signal PSE0 is "H" / "L", the power switch 491 is on / off. The same applies to the signals PSE1 and PSE2.

[0198] Before time t1, the state is normal operation. The power switch 491 is on, and the voltage VDDD is input to the CPU core 401. The scan flip-flop 481 performs normal operation. At this time, since the level shifter 494 does not need to operate, the power switch 493 is off, and the signals SCE, BK, and RC are "L". Since the node SE is "L", the scan flip-flop 481 stores the data of the node D1. Note that in the example of FIG. 21, at time t1, the node SN11 of the backup circuit 402 is "L".

[0199] The operation during backup will be described. At operation time t1, the PMU 193 stops the clock signal GCLK1 and sets the signals PSE2 and BK to “H.” The level shifter 494 becomes active and outputs the signal BKH at “H” to the backup circuit 402.

[0200] The transistor M11 of the backup circuit 402 turns on, and the data of the node Q1 of the scan flip-flop 481 is written to the node SN11 of the backup circuit 402. If the node Q1 of the scan flip-flop 481 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0201] The PMU 193 sets signals PSE2 and BK to "L" at time t2, and sets signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 401 transitions to the power gating state. Note that signal PSE0 may also fall at the same timing as signal BK falls.

[0202] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at the node Q1 is lost. The node SN11 continues to hold the data at the node Q1 at time t3.

[0203] The operation during recovery will be explained below. At time t4, the PMU 193 changes the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage of the V_VDD line reaches VDDD (time t5), the PMU 193 changes the signals PSE2, RC, and SCE to "H".

[0204] The transistor M12 turns on, and the charge of the capacitive element C11 is distributed to the nodes SN11 and SD. If the node SN11 is "H", the voltage of the node SD rises. Since the node SE is "H", the data of the node SD is written to the input side latch circuit of the scan flip-flop 481. When the clock signal GCLK1 is input to the node CK at time t6, the data of the input side latch circuit is written to the node Q1. In other words, the data of the node SN11 is written to the node Q1.

[0205] At time t7, the PMU 193 sets the signals PSE2, SCE, and RC to "L," and the recovery operation ends.

[0206] The backup circuit 402 using OS transistors is very suitable for normally-off computing because it consumes small amounts of both dynamic and static power. The CPU 400 including the CPU core 401 having the backup circuit 402 using OS transistors can be called an NoffCPU (registered trademark). The NoffCPU has a non-volatile memory, and can stop the power supply when operation is not required. Even if the flip-flop 480 is installed, it is possible to prevent almost no performance degradation of the CPU core 401 and almost no increase in dynamic power.

[0207] CPU core 401 may have multiple power domains that can be power-gated. The multiple power domains are provided with one or more power switches for controlling the input of voltage. CPU core 401 may also have one or more power domains in which power gating is not performed. For example, a power gating control circuit for controlling flip-flop 480 and power switches 491 to 493 may be provided in a power domain in which power gating is not performed.

[0208] The application of the flip-flop 480 is not limited to the CPU 400. In the CPU 400, the flip-flop 480 can be applied to a register provided in a power domain capable of power gating.

[0209] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0210] (Embodiment 4) In this embodiment, an example of a configuration of a transistor applicable to the CPU 400 and the semiconductor device 100 described in the above embodiment will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. By using this configuration, the design freedom of the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0211] FIG. 22 shows a part of a cross-sectional structure of the semiconductor device. The semiconductor device shown in FIG. 22 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 23A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 23B is a cross-sectional view of the transistor 500 in the channel width direction. For example, the transistor 500 corresponds to an OS transistor included in the memory cell 320 described in the above embodiment, that is, a transistor having an oxide semiconductor in a channel formation region. The transistor 550 corresponds to a Si transistor included in the arithmetic circuit portion 210 described in the above embodiment, that is, a transistor having silicon in a channel formation region.

[0212] The transistor 500 is an OS transistor. An OS transistor has an extremely small off-state current. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of a refresh operation of the storage node can be reduced or the refresh operation is not required, so that the power consumption of a semiconductor device can be reduced.

[0213] In FIG. 22, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0214] The transistor 550 is provided on a substrate 371. The substrate 371 is, for example, a p-type silicon substrate. The substrate 371 may be an n-type silicon substrate. The oxide layer 374 is preferably an insulating layer (also referred to as a BOX layer) formed by buried oxide in the substrate 371, for example, silicon oxide. The transistor 550 is provided on single crystal silicon provided on the substrate 371 via the oxide layer 374, that is, a so-called SOI (Silicon On Insulator) substrate.

[0215] A substrate 371 in the SOI substrate is provided with an insulator 373 functioning as an element isolation layer. The substrate 371 also has a well region 372. The well region 372 is a region to which n-type or p-type conductivity is imparted according to the conductivity type of the transistor 550. A semiconductor region 375, and low-resistance regions 376a and 376b functioning as source and drain regions are provided in the single crystal silicon in the SOI substrate. Also, a low-resistance region 376c is provided on the well region 372.

[0216] The transistor 550 can be provided overlapping a well region 372 to which an impurity element that imparts conductivity is added. The well region 372 can function as a bottom gate electrode of the transistor 550 by independently changing the potential through the low resistance region 376c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 372, the threshold voltage of the transistor 550 can be increased and the off-current can be reduced. Therefore, by applying a negative potential to the well region 372, the drain current when the potential applied to the gate electrode of the Si transistor is 0 V can be reduced. As a result, the power consumption based on the through current or the like in the arithmetic circuit unit 210 having the transistor 550 can be reduced, and the arithmetic efficiency can be improved.

[0217] The transistor 550 is preferably a so-called fin type in which a top surface of a semiconductor layer and side surfaces in a channel width direction are covered with a conductor 378 via an insulator 377. By making the transistor 550 a fin type, the effective channel width is increased, and thus the on characteristics of the transistor 550 can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, and thus the off characteristics of the transistor 550 can be improved.

[0218] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0219] The conductor 378 may function as a first gate (also called a top gate) electrode. The well region 372 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the well region 372 can be controlled via the low resistance region 376c.

[0220] The region where the channel of the semiconductor region 375 is formed, the region nearby, the low resistance region 376a which becomes the source region or drain region, the low resistance region 376b, the low resistance region 376c which is connected to the electrode which controls the potential of the well region 372, and the like preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 550 may be a HEMT by using GaAs and GaAlAs, or the like.

[0221] Well region 372, low resistance region 376a, low resistance region 376b, and low resistance region 376c include the semiconductor material applied to semiconductor region 375 as well as an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0222] The conductor 378 functioning as the gate electrode can be a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material. The conductor 378 can also be a silicide such as nickel silicide.

[0223] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0224] The low-resistance region 376a, the low-resistance region 376b, and the low-resistance region 376c may be formed by stacking another conductor, for example, a silicide such as nickel silicide. This structure can increase the conductivity of the region functioning as an electrode. In addition, in this case, an insulator functioning as a sidewall spacer (also called a sidewall insulating layer) may be provided on the side surface of the conductor 378 functioning as the gate electrode and the side surface of the insulator functioning as the gate insulating film. This structure can prevent the conductor 378 from being electrically connected to the low-resistance region 376a and the low-resistance region 376b.

[0225] An insulator 379, an insulator 381, an insulator 383, and an insulator 385 are stacked in this order to cover the transistor 550.

[0226] As insulator 379, insulator 381, insulator 383, and insulator 385, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0227] In this specification, an oxynitride refers to a material that contains more oxygen than nitrogen. For example, silicon oxynitride refers to a material that contains oxygen, nitrogen, and silicon in its composition and contains more oxygen than nitrogen. In this specification, a nitride oxide refers to a material that contains more oxygen than nitrogen. For example, aluminum nitride oxide refers to a material that contains oxygen, nitrogen, and aluminum in its composition and contains more nitrogen than oxygen.

[0228] The insulator 381 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 381 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0229] The insulator 383 is preferably a film having a barrier property that prevents diffusion of hydrogen and impurities from the substrate 371, the transistor 550, or the like to a region where the transistor 500 is provided.

[0230] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0231] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 383 is calculated as 10×10 per area of ​​the insulator 383 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0232] Note that the insulator 385 preferably has a lower dielectric constant than the insulator 383. For example, the relative dielectric constant of the insulator 385 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 385 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 383. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0233] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 379, 381, 383, and 385. The conductors 328 and 330 function as plugs or wiring. A plurality of conductors that function as plugs or wiring may be collectively assigned the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0234] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten and / or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form it from a low resistance conductive material such as aluminum and / or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0235] A wiring layer may be provided over the insulator 385 and the conductor 330. For example, in FIG. 22, the insulator 350, the insulator 352, and the insulator 354 are stacked in this order. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0236] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, like the insulator 383. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0237] Note that, for example, tantalum nitride or the like may be used as a conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0238] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 22, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0239] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, like the insulator 383. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0240] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 22, an insulator 370, an insulator 369, and an insulator 368 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 369, and the insulator 368. The conductor 376 functions as a plug or a wiring. The conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0241] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, like the insulator 383. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0242] A wiring layer may be provided over the insulator 368 and the conductor 376. For example, in FIG. 22, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0243] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 383. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0244] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0245] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0246] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region where the transistor 500 is provided, such as the substrate 371 or a region where the transistor 550 is provided. Therefore, a material similar to that of the insulator 383 can be used.

[0247] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, a film that suppresses the diffusion of hydrogen is preferably used between the transistor 500 and the transistor 550.

[0248] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0249] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0250] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 379. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be formed using a silicon oxide film and / or a silicon oxynitride film.

[0251] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0252] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0253] Above the insulator 516 is a transistor 500 .

[0254] As shown in Figures 23A and 23B, transistor 500 has a conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, an insulator 520 arranged on insulator 516 and conductor 503, an insulator 522 arranged on insulator 520, an insulator 524 arranged on insulator 522, an oxide 530a arranged on insulator 524, an oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, an insulator 580 arranged on conductor 542a and conductor 542b and having an opening formed therebetween overlapping with conductor 542a and conductor 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the formation surface of insulator 545.

[0255] 23A and 23B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a, as shown in FIG. 23A and 23B. It is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545, as shown in FIG. 23A and 23B.

[0256] In this specification and other documents, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

[0257] Note that, in the transistor 500, a two-layer structure of the oxide 530a and the oxide 530b is shown in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this structure. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0258] In addition, although the conductor 560 in the transistor 500 has a two-layer structure, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a three-or-more-layer structure. The transistor 500 shown in FIGS. 22, 23A, and 23B is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and / or driving method.

[0259] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0260] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This makes it possible to improve the switching speed of the transistor 500 and provide high frequency characteristics.

[0261] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-current can be reduced. Therefore, the drain current when the potential applied to the conductor 560 is 0 V can be reduced by applying a negative potential to the conductor 503 compared to the case where a negative potential is not applied.

[0262] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0263] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like is different from a fin type configuration and a planar type configuration. By adopting the S-channel configuration, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0264] The conductor 503 has a structure similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inside. Note that, although the transistor 500 shows a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0265] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities and / or oxygen.

[0266] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and the conductivity from decreasing.

[0267] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single layer structure.

[0268] The insulators 520, 522, and 524 function as a second gate insulating film.

[0269] Here, it is preferable that the insulator 524 in contact with the oxide 530 is an insulator containing more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and other documents, oxygen released by heating may be referred to as "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiencies (V O In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter, V OH) may function as a donor and generate an electron that is a carrier. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0270] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more than 3.0×10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0271] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O The reaction "H → Vo + H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time may combine with oxygen to become HO and be removed from the oxide 530 or the insulator in the vicinity of the oxide 530. Also, some of the hydrogen may be gettered to the conductor 542a and the conductor 542b.

[0272] In addition, the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. In addition, the pressure of the microwave treatment may be set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, for example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0273] In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0274] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O→null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0275] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0276] Since the insulator 522 has a function of suppressing diffusion of oxygen and impurities, the oxygen contained in the oxide 530 does not diffuse toward the insulator 520, which is preferable. In addition, the conductor 503 can be suppressed from reacting with the oxygen contained in the insulator 524 and / or the oxide 530.

[0277] The insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0278] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and / or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0279] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0280] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k material insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable and high dielectric constant laminate structure.

[0281] 23A and 23B, the second gate insulating film has a three-layer stack structure, which includes insulators 520, 522, and 524. However, the second gate insulating film may have a single layer, two layers, or four or more layers. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0282] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) may be used for the oxide 530.

[0283] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0284] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0285] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0286] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, the atomic ratio of element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, the atomic ratio of In to element M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0287] In addition, it is preferable that the energy of the conduction band minimum of the oxide 530a is higher than that of the oxide 530b, or, in other words, it is preferable that the electron affinity of the oxide 530a is smaller than that of the oxide 530b.

[0288] Here, at the junction between the oxide 530a and the oxide 530b, the energy level of the conduction band minimum changes gradually. In other words, it can be said that the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0289] Specifically, the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0290] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0291] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0292] 23A, the conductor 542a and the conductor 542b are shown as a single layer, but may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. A two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0293] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated with an aluminum film or copper film on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated with an aluminum film or copper film on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0294] 23A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0295] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0296] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0297] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0298] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later process. Note that when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or a material whose conductivity does not decrease significantly even when oxygen is absorbed, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0299] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. The insulator 544 can also prevent oxidation of the conductor 542a and / or the conductor 542b due to excess oxygen contained in the insulator 580.

[0300] The insulator 545 functions as a first gate insulating film. Like the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0301] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0302] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545.

[0303] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 can be suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0304] The insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film have a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a layered structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0305] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 23A and 23B, it may have a single-layer structure or a laminated structure of three or more layers.

[0306] The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 560a has a function of suppressing the diffusion of oxygen, so that it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and its conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0307] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b also functions as wiring, so it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0308] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because they can easily form an excess oxygen region in a later step.

[0309] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0310] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b, so that conductor 560 is formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0311] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0312] The insulator 574 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0313] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0314] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0315] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0316] Conductor 540a and conductor 540b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided facing each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same configuration as conductor 546 and conductor 548, which will be described later.

[0317] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0318] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0319] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 379. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0320] In addition, conductors 546, 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0321] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0322] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by an insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the insulator having a high barrier property is formed in contact with the insulator 522 or the insulator 514, which is preferable because it serves as part of the manufacturing process of the transistor 500. Note that the insulator having a high barrier property against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514, for example.

[0323] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0324] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0325] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned element (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide can also be used.

[0326] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0327] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten and / or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When the conductor 620 is formed simultaneously with other components such as a conductor, a low resistance metal material such as Cu (copper) and / or Al (aluminum) may be used.

[0328] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 379. The insulator 640 may also function as a planarizing film that covers the uneven shape thereunder.

[0329] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0330] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0331] (Embodiment 5) In this embodiment, a configuration of an integrated circuit including each component of the arithmetic processing system 1000 described in the above embodiment will be described with reference to FIGS. 24A and 24B.

[0332] Fig. 24A is an example of a schematic diagram for explaining an integrated circuit including each component of the arithmetic processing system 1000. The integrated circuit 390 shown in Fig. 24A can be formed as a single integrated circuit by integrating each circuit by forming a part of the circuit of the CPU 400 and the accelerator described as the semiconductor device 100 using OS transistors.

[0333] 24A, in a CPU 400, a backup circuit 402 can be provided in a layer having OS transistors above a CPU core 401. Also, as shown in Fig. 24A, in a semiconductor device 100, a layer 120 including OS transistors that constitute a memory circuit unit 310 can be provided above a layer 110 that includes Si transistors that constitute an arithmetic circuit unit 210. In the layer 110, drive circuits such as a write bit line drive circuit 220, a read word line drive circuit 230, and a write word line drive circuit 240 can be provided.

[0334] 24A, a control device 150, a memory device 160, and the like can be provided. As the memory device 160, in addition to SRAM and DRAM including Si transistors, NOSRAM and DOSRAM described in the above embodiment can be applied. Also, MRAM, PRAM, ReRAM, FeRAM, and the like can be used as the memory device 160.

[0335] Furthermore, in the memory device 160, a layer having OS transistors is stacked over a driver circuit provided in a layer having Si transistors, whereby memory density can be improved.

[0336] As shown in FIG. 24A, in the case of an SoC in which circuits such as a CPU 400, a semiconductor device 100, a control device 150, and a storage device 160 are tightly coupled, there is a problem of heat generation, but an OS transistor is preferable because the fluctuation of electrical characteristics due to heat is smaller than that of a Si transistor. In addition, by integrating circuits in a three-dimensional direction as shown in FIG. 24A, parasitic capacitance can be reduced compared to a stacked structure using a silicon through electrode (Through Silicon Via: TSV) or the like. Therefore, the power consumption required for charging and discharging each wiring can be reduced. As a result, the efficiency of calculation processing can be improved.

[0337] Fig. 24B shows an example of a semiconductor chip incorporating an integrated circuit 390. A semiconductor chip 391 shown in Fig. 24B has leads 392 and an integrated circuit 390. As described in Fig. 24A, the integrated circuit 390 has the various circuits shown in the above embodiments provided on one die. The integrated circuit 390 has a layered structure and is broadly divided into a layer having Si transistors (Si transistor layer 393), a wiring layer 394, and a layer having OS transistors (OS transistor layer 395). The OS transistor layer 395 can be provided by being layered on the Si transistor layer 393, which makes it easy to miniaturize the semiconductor chip 391.

[0338] 24B, a QFP (Quad Flat Package) is applied to the package of the semiconductor chip 391, but the form of the package is not limited to this. Other configuration examples include DIP (Dual In-line Package), PGA (Pin Grid Array), SOP (Small Outline Package), SSOP (Shrink Small Outline Package), TSOP (Thin-Small Outline Package), LCC (Leaded Chip Carrier), QFN (Quad Flat Non-leaded package), BGA (Ball Grid Array), FBGA (Fine pitch Ball Grid Array), DTP (Dual Tape carrier Package), QTP (Quad Tape-carrier Package), etc., which are insertion mounting types.

[0339] An arithmetic circuit and a driver circuit having Si transistors, and a memory circuit having OS transistors can all be formed in Si transistor layer 393, wiring layer 394, and OS transistor layer 395. That is, the elements constituting the above-mentioned semiconductor device can be formed in the same manufacturing process. Therefore, even if the number of constituting elements increases, there is no need to increase the manufacturing process in semiconductor chip 391 shown in FIG. 24B, and the above-mentioned semiconductor device can be incorporated at low cost.

[0340] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0341] (Embodiment 6) In this embodiment mode, an electronic device, a mobile object, and a computing system to which the integrated circuit 390 described in the above embodiment mode can be applied will be described with reference to FIGS. 25A to 28. FIG.

[0342] Fig. 25A shows an external view of an automobile as an example of a moving body. Fig. 25B shows a simplified diagram of data exchange within the automobile. The automobile 590 has a plurality of cameras 591 and the like. The automobile 590 also includes various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar.

[0343] In an automobile 590, the above-mentioned integrated circuit 390 (or a semiconductor chip 391 incorporating the above-mentioned integrated circuit 390) can be used for a camera 591 or the like. The automobile 590 processes a plurality of images obtained by the camera 591 in a plurality of imaging directions 592 using the integrated circuit 390 described in the above embodiment, and analyzes the plurality of images collectively using a host controller 594 or the like via a bus 593 or the like, thereby determining the surrounding traffic conditions, such as the presence or absence of guardrails and / or pedestrians, and performing automatic driving. The automobile 590 can also be used in a system that performs road guidance, hazard prediction, and the like.

[0344] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0345] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, a moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and a computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0346] Fig. 26A is an external view showing an example of a portable electronic device. Fig. 26B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, and the like.

[0347] In portable electronic device 595, the integrated circuit 390 can be provided on printed circuit board 596. Portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by speaker 597, camera 598, microphone 599, etc., using integrated circuit 390 described in the above embodiment. Also, the portable electronic device can be used in a system that performs voice guidance, image search, etc.

[0348] In the integrated circuit 390, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, facial recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0349] A portable game machine 1100 shown in FIG. 27A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, an operation key 1107, and the like. The housings 1101, 1102, and 1103 are removable. By attaching the connection unit 1105 provided in the housing 1101 to the housing 1108, a video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated to function as an operation unit. The integrated circuit 390 described in the above embodiment can be incorporated in a chip provided on a substrate of the housings 1102 and 1103.

[0350] 27B shows a stick-type electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The integrated circuit 390 shown in the previous embodiment can be incorporated in the controller chip 1126 of the board 1124, etc.

[0351] 27C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the integrated circuit 390 shown in the previous embodiment can be incorporated into the control circuit 2110.

[0352] The integrated circuit 390 described in the above embodiment can be used in a server that communicates with the electronic device instead of being built into the electronic device. In this case, the electronic device and the server constitute a computing system. Figure 28 shows an example of the configuration of a system 3000.

[0353] The system 3000 is configured with an electronic device 3001 and a server 3002. Communication between the electronic device 3001 and the server 3002 can be performed via an Internet line 3003.

[0354] Server 3002 has a plurality of racks 3004. A plurality of boards 3005 are provided in the plurality of racks, and integrated circuits 390 described in the above embodiment can be mounted on the boards 3005. This forms a neural network in server 3002. Server 3002 can perform neural network calculations using data input from electronic device 3001 via internet line 3003. Results of calculations by server 3002 can be transmitted to electronic device 3001 via internet line 3003 as necessary. This can reduce the calculation load on electronic device 3001.

[0355] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments. [Explanation of symbols]

[0356] 100: semiconductor device, 110: layer, 120: layer, 150: control device, 160: memory device, 193: PMU, 200: calculation block, 210: calculation circuit section, 211: calculation circuit, 220: bit line drive circuit, 230: word line drive circuit, 240: word line drive circuit, 290: calculation block array, 310: memory circuit section, 320: memory cell, 321: transistor, 322: transistor, 323: transistor, 324: capacitance

Claims

1. A plurality of operation blocks are included. The calculation block includes: The display device includes an arithmetic circuit section, a memory circuit section, a first drive circuit, a second drive circuit, and a third drive circuit, the arithmetic circuit unit includes a first transistor, the memory circuit unit includes a second transistor, the arithmetic circuit unit is electrically connected to the memory circuit unit, the arithmetic circuit unit and the memory circuit unit have overlapping regions, the first driving circuit, the second driving circuit, and the third driving circuit are electrically connected to the memory circuit unit; the arithmetic circuit unit, the first driving circuit, the second driving circuit, and the third driving circuit are provided in a first layer, the memory circuit unit is provided in a second layer, The first layer and the second layer have an overlapping region.

2. In claim 1, The first driver circuit is a semiconductor device having a function of supplying data to the memory circuit unit.

3. In claim 1 or 2, The second driver circuit is a semiconductor device having a function of controlling an operation of writing data to the memory circuit portion.

4. In any one of claims 1 to 3, The third driver circuit is a semiconductor device having a function of controlling an operation of reading data from the memory circuit unit.

5. In any one of claims 1 to 4, The arithmetic circuit unit is a semiconductor device having a function of performing product-sum operations.

6. In any one of claims 1 to 5, The memory circuit portion is a semiconductor device having a function of retaining data.

7. In claim 6, The data is weight data.

8. In any one of claims 1 to 7, The semiconductor device, wherein the first transistor includes silicon as a semiconductor in which a channel is formed.

9. In any one of claims 1 to 4, The second transistor includes an oxide semiconductor as a semiconductor in which a channel is formed.

10. In claim 9, The semiconductor device, wherein the oxide semiconductor contains at least one of indium and zinc.

11. A semiconductor device having a plurality of calculation blocks arranged in a matrix of M rows and N columns (M and N are each a natural number of 2 or more), and N first drive circuits, The N first driving circuits are arranged in respective columns, Each of the plurality of operation blocks includes: The memory device includes an arithmetic circuit unit and a memory circuit unit, the arithmetic circuit unit is electrically connected to the memory circuit unit, the arithmetic circuit unit and the memory circuit unit have overlapping regions, The memory circuit unit arranged in the e-th column (e is a natural number from 1 to N) a semiconductor device electrically connected to the first driving circuit arranged in the e-th column;

12. In claim 11, The arithmetic circuit unit is a semiconductor device having a function of performing product-sum operations.

13. In claim 11 or 12, The memory circuit portion is a semiconductor device having a function of retaining data.

14. In claim 13, The data is weight data.

15. In any one of claims 11 to 13, the memory circuit unit has a plurality of memory cells, The memory cell includes: A semiconductor device including a transistor in which a channel is formed, the semiconductor including an oxide semiconductor.

16. In any one of claims 11 to 15, The first driver circuit is a semiconductor device having a function of supplying data to the memory circuit unit.

17. In any one of claims 11 to 16, a second drive circuit extending in a column direction; The second drive circuit is A semiconductor device electrically connected to the memory circuit unit.

18. In claim 17, The second driver circuit is a semiconductor device having a function of controlling an operation of writing data to the memory circuit portion.

19. In any one of claims 11 to 18, Each of the plurality of operation blocks includes: A third drive circuit is provided. The third driving circuit is A semiconductor device electrically connected to the memory circuit unit.

20. In any one of claims 11 to 18, a third drive circuit extending in a column direction; The third driving circuit is A semiconductor device electrically connected to the memory circuit unit.

21. In claim 19 or 20, The third driver circuit is a semiconductor device having a function of controlling an operation of reading data from the memory circuit unit.

Images