Server, switching method, and switching program

Abstract

A server (10) includes: an FPGA-mounted NIC (11) on which an FPGA (111) for performing packet processing is mounted and which is connected to a system 0 vGW (15a); an NIC (12) connected to a system 1 vGW (15b); and a switching unit (132). According to a time table, the switching unit (132) switches an NIC for receiving packets to the NIC (12) by putting off a power source of the FPGA-mounted NIC (11), at a time period when power efficiency is superior in packet processing performed in the vGW (15b) compared to in packet processing performed in the FPGA (111). Furthermore, the switching unit (132) switches the NIC for receiving the packets to the FPGA-mounted NIC (11) by putting on the power source of the FPGA-mounted NIC (11) at a time period when power efficiency is superior in the packet processing performed in the FPGA (111) compared to in the packet processing performed in the vGW (15b).

Description

[Technical field]

[0001] The present invention relates to a server, a switching method, and a switching program. [Background technology]

[0002] Conventionally, there is a technology called NFV (Network Function Virtualization) that implements the functions of network devices as a VM (Virtual Machine) on a virtualization platform of a general-purpose server. NFV technology can reduce equipment costs by consolidating physical devices.

[0003] In NFV technology, servers use a CPU to run VMs and process network packets, but there is a limit to the processing performance of the CPU, so as traffic volume increases, multiple servers must be prepared, which increases equipment costs and power consumption.

[0004] To solve the above problems, a technology has been proposed in which a NIC (Network Interface Card) equipped with an FPGA (Field Programmable Gate Array) is connected to a server and packet processing that was previously performed by the CPU is offloaded to the hardware (FPGA). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Intel FPGA PAC N3000 (Intel FPGA Programmable Acceleration Card N3000), [online], [Retrieved February 15, 2022], Internet <URL:https: / / www.intel.co.jp / content / www / jp / ja / products / details / fpga / platforms / pac / n3000.html> Summary of the Invention [Problem to be solved by the invention]

[0006] The above FPGA consumes constant power regardless of the processing load, so there is a problem that the power efficiency of the server is poor when the processing load is low. For example, as shown in Figure 1, when the amount of traffic to be processed by the server is low, the power consumption of processing packets by the FPGA is higher than that of processing packets by the CPU.

[0007] Here, for example, as shown in FIG. 2, when the amount of traffic that the server must process varies greatly with time, there is a problem that power efficiency is poor when the server processes packets using an FPGA, both during periods of high traffic (period indicated by reference numeral 201) and periods of low traffic (period indicated by reference numeral 202).

[0008] Therefore, an object of the present invention is to improve power efficiency while maintaining the processing performance of a server under high load. [Means for solving the problem]

[0009] In order to solve the above-mentioned problems, the present invention is characterized by comprising a first NIC (Network Interface Card) connected to a virtual machine and equipped with an FPGA (Field Programmable Gate Array) that processes input packets addressed to the virtual machine, a second NIC that is set with the same IP address as the virtual machine and is connected to the virtual machine that processes the input packets, and a switching unit that switches the NIC that accepts the packets to the second NIC by turning off the power of the first NIC when a predetermined time period arrives during which it is more power efficient for the virtual machine to process packets than for the FPGA to process packets. Effect of the Invention

[0010] According to the present invention, it is possible to improve power efficiency while maintaining the processing performance of a server under high load. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a graph showing an example of the power consumption of a CPU and an FPGA versus the amount of traffic. [Diagram 2] FIG. 2 is a graph showing an example of the change in traffic volume over time. [Diagram 3] FIG. 3 illustrates an example of a configuration of a server. [Figure 4] FIG. 4 is a diagram showing an example of a route of user traffic when a server processes packets using an FPGA. [Diagram 5] FIG. 5 is a diagram showing an example of a route of user traffic when a server processes packets using a CPU. [Figure 6] FIG. 6 is a flowchart showing an example of a processing procedure when the server switches packet processing that has been performed by the FPGA to be performed by the CPU. [Figure 7] FIG. 7 is a flowchart showing an example of a processing procedure when a server switches packet processing from the CPU to the FPGA. [Figure 8] FIG. 8 is a diagram for explaining the FPGA of the server. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a computer that executes a switching program. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, a mode (embodiment) for carrying out the present invention will be described with reference to the drawings, but the present invention is not limited to the present embodiment.

[0013] First, an overview of the server 10 of the present embodiment will be described with reference to Figures 3 to 5. As shown in Figure 3, the server 10 includes a NIC (first NIC, FPGA-equipped NIC) 11 equipped with an FPGA 111, and a normal NIC (second NIC) 12.

[0014] A redundant virtual machine (for example, vGW (virtual gateway) 15) is connected to the FPGA-equipped NIC 11 and NIC 12. Here, of the redundant vGWs 15, the vGW 15 of system 0 is designated as vGW 15a, and the vGW 15 of system 1 is designated as vGW 15b. For example, if the vGW 15a of system 0 of company 1 becomes unable to communicate, the vGW 15b of system 1 of company 1 operates in place of vGW 15a and processes input packets. For example, the vGW 15a of system 0 is connected to the FPGA-equipped NIC 11, and the vGW 15b of system 1 is connected to the NIC 12.

[0015] The time management unit 131 manages whether a time period during which the server 10 should process packets in the FPGA 111 or in the CPU (vGW 15b) is to be used, based on the time table in the storage unit 14. In this time table, as shown in Fig. 3, time periods during which the server 10 should process packets in the FPGA 111 and time periods during which the server 10 should process packets in the CPU are set. Note that the time period during which the FPGA 111 should process packets is, for example, a time period during which the traffic volume is relatively high and it is more power efficient for the server 10 to process packets in the FPGA 111. Also, the time period during which the CPU should process packets is, for example, a time period during which the traffic volume is relatively low and it is more power efficient for the server 10 to process packets in the CPU.

[0016] Then, when a time period during which the FPGA 111 should process packets based on the above-mentioned time table arrives, the time management unit 131 instructs the switching unit 132 to process the packets based on the FPGA 111. Also, when a time period during which the CPU should process packets based on the time table arrives, the time management unit 131 instructs the switching unit 132 to process the packets based on the CPU.

[0017] The switching unit 132 switches the NIC based on an instruction from the time management unit 131. For example, when the switching unit 132 receives an instruction from the time management unit 131 to process a packet in the FPGA-equipped NIC 11, the switching unit 132 turns on the power of the FPGA-equipped NIC 11. As a result, the vGW 15 corresponding to the VIP (virtual IP address) becomes the vGW 15a, and the packet addressed to the VIP is input to the FPGA-equipped NIC 11 and processed by the FPGA 111 (see the path indicated by the solid line in FIG. 4).

[0018] On the other hand, when the switching unit 132 receives an instruction from the time management unit 131 to process the packet by the CPU, it turns off the power supply of the FPGA-equipped NIC 11 (see FIG. 5). As a result, the vGW 15 corresponding to the VIP becomes vGW 15b, and the packet addressed to the VIP is input to the NIC 12 and processed by vGW 15b (see the route indicated by the bold line in FIG. 5). That is, the packet is processed by the CPU of the server 10. Furthermore, powering off the FPGA-equipped NIC 11 reduces the power consumption of the server 10.

[0019] In this way, the server 10 causes the FPGA 111 to process packets during time periods when it is more power efficient to process packets using the FPGA 111 (e.g., time periods when traffic is high), and causes the CPU to process packets during time periods when it is more power efficient to process packets using the CPU (e.g., time periods when traffic is low). As a result, it is possible to improve the power efficiency of the server 10 while maintaining the processing performance of the server 10 under high load.

[0020] [Configuration example] 3, a configuration example of the server 10 will be described. The server 10 includes an FPGA-equipped NIC 11, a normal NIC 12, an OS 13, a time management unit 131, a switching unit 132, a storage unit 14, and redundant vGWs 15 (vGWs 15a and 15b).

[0021] The FPGA-equipped NIC 11 is a NIC equipped with an FPGA 111 that processes input packets. The FPGA-equipped NIC 11 has ports (e.g., port1, port2) that handle the input and output of packets. For example, when the FPGA-equipped NIC 11 accepts a packet input from port1, the FPGA-equipped NIC 11 processes the packet using the FPGA 111 and outputs it from port2. Of the redundant vGWs 15, the FPGA-equipped NIC 11 is connected to the vGW 15a of system 0.

[0022] NIC12 is a normal NIC, and one of the redundant vGW15 is connected to vGW15b. NIC12 has ports (e.g., port3, port4) that handle input and output of packets. For example, a packet received by NIC12 from port3 reaches vGW15b via an IF (e.g., eth2) of OS13. Then, the packet processed by vGW15b is output from port4 of NIC12 via an IF (e.g., eth3) of OS13.

[0023] The OS 13 is basic software that operates the server 10. The OS 13 provides, for example, IFs (eth0, eth1) that connect the FPGA-equipped NIC 11 and the vGW 15a, and IFs (eth2, eth3) that connect the NIC 12 and the vGW 15b.

[0024] The time management unit 131 instructs the switching unit 132 whether the packet should be processed by the FPGA 111 or the CPU, based on the time table in the storage unit 14 .

[0025] The switching unit 132 executes NIC switching based on an instruction from the time management unit 131. For example, when the switching unit 132 receives an instruction from the time management unit 131 that the FPGA 111 should process packets, the switching unit 132 turns on the power of the FPGA-equipped NIC 11. On the other hand, when the switching unit 132 receives an instruction from the time management unit 131 that the CPU should process packets, the switching unit 132 turns off the power of the FPGA-equipped NIC 11 (see FIG. 5).

[0026] The time management unit 131 and the switching unit 132 may be realized by hardware or by executing a program.

[0027] The storage unit 14 stores data to be referred to when the server 10 executes various processes. For example, the storage unit 14 stores a time table to be referred to by the time management unit 131. For example, as shown in Fig. 3, the time table sets a time period during which the server 10 executes packet processing in the FPGA 111 and a time period during which the server 10 executes packet processing in the CPU.

[0028] The time period set in the timetable for processing packets by the FPGA 111 is a time period during which packet processing by the FPGA 111 consumes less power than packet processing by the CPU. The time period is, for example, 9:00-20:00, during which the amount of traffic input to the server 10 is greater than a predetermined value.

[0029] The time set in the timetable for processing packets by the CPU is a time period during which packet processing by the CPU consumes less power than packet processing by the FPGA-equipped NIC 11. The time period is, for example, a time period other than 9:00-20:00 during which the amount of traffic input to the server 10 is equal to or less than a predetermined value.

[0030] The time periods set in the timetable for processing packets in FPGA 111 and for processing packets in the CPU are determined, for example, by the measurement results of the input traffic volume to server 10 for each time period. The time periods set in the timetable can be appropriately changed by an administrator, etc.

[0031] The vGW15 is a virtualized gateway that processes packets input via a NIC. The vGW15 has a redundant configuration. For example, as shown in FIG. 3, when the server 10 prepares a vGW15 for each of the networks of the company 1 and the company 2, a vGW15a of system 0 and a vGW15b of system 1 are prepared for each of the companies 1 and 2.

[0032] The vGW15a of the 0 system is a vGW15 that operates in a normal state. The vGW15b of the 1 system is a vGW15 that operates in place of the vGW15a when the vGW15a becomes unable to communicate. The same virtual IP address is set to the vGW15a and the vGW15b. The vGW15a and the vGW15b are virtual routers that are made redundant by, for example, VRRC (Virtual Router Redundancy Protocol), and the vGW15a operates as a master router by VRRP. Of the vGW15a and the vGW15b, the vGW15a is connected to the FPGA-equipped NIC11, and the vGW15b is connected to the NIC12.

[0033] [Example of processing procedure] Next, an example of a processing procedure of the server 10 will be described using Fig. 6 while referring to Fig. 4 and Fig. 5. First, an example of a processing procedure in the case where the server 10 switches the packet processing performed by the FPGA 111 to be performed by the CPU will be described.

[0034] [Switching method (FPGA → CPU)] The time management unit 131 of the server 10 refers to the time table, and when it detects that it is time for the CPU to process packets (Yes in S1), it outputs to the switching unit 132 an instruction to process the packets by the CPU (S2). On the other hand, if it is not yet time for the CPU to process packets (No in S1), it returns to S1.

[0035] After S2, when the switching unit 132 receives an instruction to process the packet in the CPU (S3), it links down an IF (for example, eth0 shown in FIG. 4) connected to the FPGA-equipped NIC 11 among the IFs provided by the OS 13 (S4).

[0036] After S4, the switching unit 132 confirms that the vGW 15b of the 1st system has been switched to the vGW 15 of the ACT system and that user traffic has started to flow via the vGW 15b of the 1st system (S5). For example, the switching unit 132 confirms that user traffic has started to flow via the vGW 15b based on the amount of traffic flowing through an IF (e.g., eth2 shown in FIG. 4) connected to the vGW 15b. Thereafter, the switching unit 132 turns off the power supply of the FPGA-equipped NIC 11 (S6).

[0037] As a result, the user traffic is input from the NIC 12 of the server 10, reaches the vGW 15b, is processed by the vGW 15b, and is then output via the NIC 12, as shown in FIG.

[0038] The reason why the switching unit 132 turns off the power supply of the FPGA-equipped NIC 11 after linking down the IF connected to the FPGA-equipped NIC 11 is to allow the user traffic to flow via the FPGA-equipped NIC 11 even during the waiting time until the ACT system vGW 15 switches from vGW 15a to vGW 15b. This prevents communication interruption of the user traffic.

[0039] [Switching method (CPU → FPGA)] Next, an example of a processing procedure in which the server 10 switches packet processing that has been performed by the CPU to be performed by the FPGA 111 will be described with reference to FIG. 7 as well as FIG.

[0040] The time management unit 131 of the server 10 refers to the time table, and when it detects that it is time for the FPGA 111 to process the packet (Yes in S11), it outputs to the switching unit 132 an instruction to process the packet in the FPGA 111 (S12). On the other hand, if it is not yet time for the FPGA 111 to process the packet (No in S11), it returns to S11.

[0041] After S12, when the switching unit 132 receives an instruction to process the packet in the FPGA 111 (S13), it links up an IF (e.g., eth0 shown in FIG. 4) connected to the FPGA-equipped NIC 11 among the IFs provided by the OS 13 (S14), and turns on the power supply of the FPGA-equipped NIC 11 (S15). As a result, the vGW 15 of the ACT system is switched from the vGW 15b of the 1 system to the vGW 15a of the 0 system, and user traffic starts to flow via the FPGA-equipped NIC 11. The switching unit 132 may link up the IF connected to the FPGA-equipped NIC 11 after turning on the power supply of the FPGA-equipped NIC 11.

[0042] [FPGA Details] Next, the FPGA 111 will be described in detail with reference to Fig. 8. Here, a case will be described in which, during a time period when the server 10 processes packets using the FPGA 111, user traffic flows along the path indicated by the solid line in Fig. 8, and alive monitoring packets between the vGW 15a of system 0 and the vGW 15b of system 1 flow along the path indicated by the dashed line in Fig. 8.

[0043] In such a case, the FPGA 111 outputs the packet of the vGW 15a with Destination IP=0 to eth0 of the OS 13. Also, the FPGA 111 outputs the packet of the vGW 15b with Destination IP=1 to the opposite port 1. Furthermore, when the Destination IP is other than the above, the FPGA 111 outputs to the port opposite to the input port (for example, when the input port is port 1, it outputs to port 2).

[0044] In this way, the FPGA 111 can distinguish between alive monitoring packets between the vGWs 15a and 15b and user traffic packets, and perform appropriate routing control for each packet.

[0045] In addition, during a time period when the server 10 processes packets using the CPU (i.e., the vGW 15b), for example, user traffic flows through the path shown in Fig. 5. Also, since the FPGA-equipped NIC 11 is powered off during that time period, no alive monitoring packet flows between the vGW 15a of system 0 and the vGW 15b of system 1.

[0046] According to the server 10 described above, during a time period when it is more power efficient for the FPGA-equipped NIC 11 to process packets (e.g., during a time period when the traffic volume is high), the FPGA-equipped NIC 11 processes packets, and during a time period when it is more power efficient for the CPU to process packets (e.g., during a time period when the traffic volume is low), the CPU processes packets. As a result, the power efficiency of the server 10 can be improved.

[0047] In the above embodiment, the vGW 15 connected to the FPGA-equipped NIC 11 and the NIC 12 are separate vGWs 15, but the present invention is not limited to this. For example, the FPGA-equipped NIC 11 and the NIC 12 may be connected to the same vGW 15.

[0048] [System configuration, etc.] In addition, each component of each unit shown in the figure is a functional concept, and does not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each device is not limited to that shown in the figure, and all or a part of it can be functionally or physically distributed and integrated in any unit according to various loads, usage conditions, etc. Furthermore, each processing function performed by each device can be realized in whole or in part by a CPU and a program executed by the CPU, or can be realized as hardware using wired logic.

[0049] Furthermore, among the processes described in the above embodiments, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically by a known method. In addition, the information including the processing procedures, control procedures, specific names, various data and parameters shown in the above documents and drawings can be changed arbitrarily unless otherwise specified.

[0050] [program] The time management unit 131 and the switching unit 132 can be implemented by installing a program (switching program) as package software or online software on a desired computer. For example, by making an information processing device execute the above program, the information processing device can function as the time management unit 131 and the switching unit 132. The information processing device referred to here includes mobile communication terminals such as smartphones, mobile phones, and PHS (Personal Handyphone System), and further terminals such as PDAs (Personal Digital Assistants).

[0051] 9 is a diagram showing an example of a computer that executes a switching program. The computer 1000 includes, for example, a memory 1010 and a CPU 1020. The computer 1000 also includes a hard disk drive interface 1030, a disk drive interface 1040, a serial port interface 1050, a video adapter 1060, and a network interface 1070. These components are connected by a bus 1080.

[0052] The memory 1010 includes a read only memory (ROM) 1011 and a random access memory (RAM) 1012. The ROM 1011 stores a boot program such as a basic input output system (BIOS). The hard disk drive interface 1030 is connected to a hard disk drive 1090. The disk drive interface 1040 is connected to a disk drive 1100. A removable storage medium such as a magnetic disk or an optical disk is inserted into the disk drive 1100. The serial port interface 1050 is connected to a mouse 1110 and a keyboard 1120, for example. The video adapter 1060 is connected to a display 1130, for example.

[0053] The hard disk drive 1090 stores, for example, an OS 1091, an application program 1092, a program module 1093, and program data 1094. That is, the programs that define the processes executed by the time management unit 131 and the switching unit 132 are implemented as a program module 1093 in which computer-executable codes are written. The program module 1093 is stored, for example, in the hard disk drive 1090. For example, the program module 1093 for executing processes similar to the functional configurations in the time management unit 131 and the switching unit 132 is stored in the hard disk drive 1090. The hard disk drive 1090 may be replaced by an SSD (Solid State Drive).

[0054] Data used in the processing of the above-described embodiment is stored as program data 1094 in, for example, the memory 1010 or the hard disk drive 1090. Then, the CPU 1020 reads out the program module 1093 or the program data 1094 stored in the memory 1010 or the hard disk drive 1090 into the RAM 1012 as necessary and executes them.

[0055] Note that the program module 1093 and the program data 1094 are not limited to being stored in the hard disk drive 1090, but may be stored in, for example, a removable storage medium and read by the CPU 1020 via the disk drive 1100 or the like. Alternatively, the program module 1093 and the program data 1094 may be stored in another computer connected via a network (such as a local area network (LAN) or wide area network (WAN)). The program module 1093 and the program data 1094 may then be read by the CPU 1020 from the other computer via the network interface 1070. [Explanation of symbols]

[0056] 10 Server 11 FPGA-equipped NIC (first NIC) 12 NICs (second NIC) 13 OS 14 Storage section 15(15a,15b) vGW 131 Time Management Department 132 Switching section

Claims

1. A first network interface card (NIC) connected to a virtual machine and equipped with a field programmable gate array (FPGA) for processing input packets addressed to the virtual machine; A second NIC that is set with the same IP address as the virtual machine and is connected to a virtual machine that processes input packets; a switching unit that switches a NIC that receives the packets to the second NIC by turning off a power supply of the first NIC when a predetermined time period has come when it is more power efficient for the virtual machine to process packets than for the FPGA to process packets; A server comprising:

2. The switching unit is When a predetermined time period has come in which it is more power efficient for the FPGA to process packets than for the virtual machine to process packets, a NIC that accepts the packets is switched to the first NIC by turning on a power supply for the first NIC. The server according to claim 1 .

3. The virtual machine connected to the first NIC and the virtual machine connected to the second NIC are virtual routers that are made redundant by VRRC (Virtual Router Redundancy Protocol), and the virtual machine connected to the first NIC is a master router of VRRP. The server according to claim 1 .

4. A server-implemented switching method, comprising: The server includes a first NIC (Network Interface Card) equipped with an FPGA (Field Programmable Gate Array) that is connected to a virtual machine and processes input packets addressed to the virtual machine, and a second NIC that is set with the same IP address as the virtual machine and is connected to the virtual machine that processes the input packets, a step of switching a NIC that accepts the packets to the second NIC by turning off the power supply of the first NIC when a predetermined time period has come in which it is more power efficient for the virtual machine to process the packets than for the FPGA to process the packets; A switching method comprising:

5. A computer includes a first NIC (Network Interface Card) equipped with an FPGA (Field Programmable Gate Array) that is connected to a virtual machine and processes input packets addressed to the virtual machine, and a second NIC that is set with the same IP address as the virtual machine and is connected to the virtual machine that processes the input packets, a step of switching a NIC that accepts the packets to the second NIC by turning off the power supply of the first NIC when a predetermined time period has come in which it is more power efficient for the virtual machine to process the packets than for the FPGA to process the packets; A switching program to execute the above.

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